LLDB compatibility: Send complete register definitions in target.xml #148
Description
LLDB requires that the full list of registers is provided.
For example, for rv32, this string is currently returned:
fn target_description_xml() -> Option<&'static str> {
Some(r#"<target version="1.0"><architecture>riscv:rv32</architecture></target>"#)
}This works fine with gdb (it seems to be ignore the register list), but llvm cares. To fix it, I changed it to this:
<target version="1.0">
<architecture>riscv:rv32</architecture>
<feature name="org.gnu.gdb.riscv.cpu">
<reg name="zero" bitsize="32" type="int" regnum="0"/>
<reg name="ra" bitsize="32" type="code_ptr"/>
<reg name="sp" bitsize="32" type="data_ptr"/>
<reg name="gp" bitsize="32" type="data_ptr"/>
<reg name="tp" bitsize="32" type="data_ptr"/>
<reg name="t0" bitsize="32" type="int"/>
<reg name="t1" bitsize="32" type="int"/>
<reg name="t2" bitsize="32" type="int"/>
<reg name="fp" bitsize="32" type="data_ptr"/>
// remaining registers
</feature>
</architecture>With that, lldb works out of the box; gdb is unaffected.
I think, lldb is actually within the spec to require this. See https://sourceware.org/gdb/current/onlinedocs/gdb.html/RISC_002dV-Features.html:
The ‘org.gnu.gdb.riscv.cpu’ feature is required for RISC-V targets. It should contain the registers ‘x0’ through ‘x31’, and ‘pc’. Either the architectural names (‘x0’, ‘x1’, etc) can be used, or the ABI names (‘zero’, ‘ra’, etc).
I'm working on a patch to address this.