RISC-V switch of QtMips project

[ppisa]

• Update memory model
  • User read and write methods with void pointer and variable buffer size (easier for mmap, for system calls emulation, ELF image writing to memory)
  • Use plain byte addressable backend - it allows to support big and little endian architectures easier and mix of endianness between emulated CPU and host
  • Update cache to work above new model
  • Update peripherals to work above new model, add endian switch to memory backend and frontend objects
• Introduce Address a RegisterValue types to allow 64-bit RISC-V support one day
• Move components to "src" subdirectory
• RISC-V core
  • Rename objects and file names to be more architecture neutral or switch to RISC-V names
  • Decide source of instruction encoding (QtMips used GNU binutils, C converted by Python to Python, then Python simarch )
  • Switch field names to match RISC-V ISA documents
  • Rewrite ALU to support RISC-V operations and GPR file
  • Consider floating point data path and vector unit communication with GPR
    • (Floating point data path for single data type #128)
    • Double precision
    • Vector instructions
  • Redefine signal names and InstructionFlags #27
  • Update interstage buffers/registers in machine::Core
  • instruction arguments description ArgumentDesc
  • Unit for immediate decode
  • Switch/generate RISC-V instruction description table
  • Update branch processing, switch to flush after branch, decide where to process branches (Decode or Execute after ALU)
  • Decode instruction length (Compressed code) and appropriate PC increment
  • Replace COP0 by machine registers
  • Update resolution of exceptions
  • Update unit tests
  • Update complex assembler based testcases
• Update core visualization
  • Update existing core visualization to roughly match RISC-V
  • Consider switch of core visualization to SvgScene, old one
  • Update memory view - NOTHING TO DO
  • Update register views
  • Update instruction view, what to to with 16/32 bit resync
  • DWARF mapping between instruction address and source line
• Update templates and examples
  • Add more advanced examples into repository.
  • Build examples with CMake ???
• System calls emulation update
  • Switch stream/file backends to QIODevice
  • Update serial port to QIODevice
  • Update systemcalls to QIODevice
  • Update systemcalls to RISC-V codes and parameters, get rid of delay slot
  • Rewrite mmap to utilize new memory model and map real files on Linux and Windows
• Update all documentation and teaching materials
  • Update README
  • Update B35APO pages
• Packaging and make system
  • CMake
    • Test on Linux
    • Test on Emscripten
    • Test on Windows MingW
    • Test on MacOS
  • SUSE Open Build service
  • UBUNTU Lauchpad
  • Nix
  • Guix
  • macOS (brew)
  • ??? for Window (choco?, winget?, store?, pkg)
• Advanced topics
  • Branch predictor
  • L2/Ln cache
  • MMU
  • Multicore
  • Extend cache states for MESI/MOESI
  • Visualization of coherence protocols
  • Visualization of instruction decode (fields)