Add support for PR2

.github/workflows/build.yml

@@ -49,6 +49,8 @@ jobs:
 
           cp twister-out/pt2*/zephyr/pblboot/boot/boot.default/zephyr/zephyr.hex \
              artifacts/pblboot-pt2-$VERSION.hex
+          cp twister-out/pr2*/zephyr/pblboot/boot/boot.default/zephyr/zephyr.hex \
+             artifacts/pblboot-pr2-$VERSION.hex
 
       - name: Store artifacts
         uses: actions/upload-artifact@v4

boards/coredevices/pr2/Kconfig.pr2

@@ -0,0 +1,5 @@
+# Copyright (c) 2026 Core Devices LLC
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_PR2
+	select SOC_SF32LB52JUD6

boards/coredevices/pr2/board.cmake

@@ -0,0 +1,6 @@
+# Copyright (c) 2026 Core Devices LLC
+# SPDX-License-Identifier: Apache-2.0
+
+board_runner_args(sftool "--chip=SF32LB52")
+
+include(${ZEPHYR_BASE}/boards/common/sftool.board.cmake)

boards/coredevices/pr2/board.yml

@@ -0,0 +1,9 @@
+# Copyright (c) 2026 Core Devices LLC
+# SPDX-License-Identifier: Apache-2.0
+
+board:
+  name: pr2
+  full_name: Pebble Round 2
+  vendor: coredevices
+  socs:
+    - name: sf32lb52jud6

boards/coredevices/pr2/pr2-pinctrl.dtsi

@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2026 Core Devices LLC
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/pinctrl/sf32lb52x-pinctrl.h>
+
+&pinctrl {
+	i2c1_default: i2c1_default {
+		group1 {
+			pinmux = <PA32_I2C1_SCL>, <PA33_I2C1_SDA>;
+			input-enable;
+		};
+	};
+
+	i2c2_default: i2c2_default {
+		group1 {
+			pinmux = <PA11_I2C2_SCL>, <PA10_I2C2_SDA>;
+			input-enable;
+		};
+	};
+
+	i2c3_default: i2c3_default {
+		group1 {
+			pinmux = <PA31_I2C3_SCL>, <PA30_I2C3_SDA>;
+			input-enable;
+		};
+	};
+
+	usart1_default: usart1_default {
+		group1 {
+			pinmux = <PA19_USART1_TXD>;
+		};
+
+		group2 {
+			pinmux = <PA18_USART1_RXD>;
+			input-enable;
+			bias-pull-up;
+		};
+	};
+};

boards/coredevices/pr2/pr2.dts

@@ -0,0 +1,211 @@
+/*
+ * Copyright (c) 2026 Core Devices LLC
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <sifli/sf32lb52x.dtsi>
+#include <sifli/sf32lb52x-ram012.dtsi>
+#include <zephyr/dt-bindings/dma/sf32lb52x-dma.h>
+#include <zephyr/dt-bindings/gpio/gpio.h>
+#include <zephyr/dt-bindings/i2c/i2c.h>
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+#include <zephyr/dt-bindings/regulator/npm13xx.h>
+
+#include "pr2-pinctrl.dtsi"
+
+/ {
+	model = "Core Devices Pebble Round 2";
+	compatible = "coredevices,pr2";
+
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	chosen {
+		zephyr,flash = &gd25q256e;
+		zephyr,flash-controller = &mpi2;
+		zephyr,code-partition = &code;
+		zephyr,console = &usart1;
+		zephyr,shell-uart = &usart1;
+	};
+
+	buttons {
+		compatible = "gpio-keys";
+
+		btn_back: button-back {
+			label = "BACK";
+			gpios = <&gpioa_32_44 2 GPIO_ACTIVE_HIGH>;
+			zephyr,code = <INPUT_KEY_BACK>;
+		};
+
+		btn_up: button-up {
+			label = "UP";
+			gpios = <&gpioa_32_44 3 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+			zephyr,code = <INPUT_KEY_UP>;
+		};
+
+		btn_center: button-center {
+			label = "CENTER";
+			gpios = <&gpioa_32_44 4 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+			zephyr,code = <INPUT_KEY_ENTER>;
+		};
+
+		btn_down: button-down {
+			label = "DOWN";
+			gpios = <&gpioa_32_44 5 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+			zephyr,code = <INPUT_KEY_DOWN>;
+		};
+	};
+
+	aliases {
+		sw0 = &btn_back;
+		sw1 = &btn_up;
+		watchdog0 = &wdt;
+	};
+};
+
+&cpu0 {
+	clock-frequency = <DT_FREQ_M(240)>;
+};
+
+&dmac {
+	status = "okay";
+};
+
+&gpioa_00_31 {
+	status = "okay";
+};
+
+&gpioa_32_44 {
+	status = "okay";
+};
+
+&hxt48 {
+	status = "okay";
+};
+
+&i2c1 {
+	status = "okay";
+	pinctrl-0 = <&i2c1_default>;
+	pinctrl-names = "default";
+	clock-frequency = <I2C_BITRATE_FAST>;
+};
+
+&i2c2 {
+	status = "okay";
+	pinctrl-0 = <&i2c2_default>;
+	pinctrl-names = "default";
+	clock-frequency = <I2C_BITRATE_FAST>;
+};
+
+&i2c3 {
+	status = "okay";
+	pinctrl-0 = <&i2c3_default>;
+	pinctrl-names = "default";
+	clock-frequency = <I2C_BITRATE_FAST>;
+
+	npm1300: pmic@6b {
+		compatible = "nordic,npm1300";
+		reg = <0x6b>;
+		pmic-int-pin = <1>;
+		host-int-gpios = <&gpioa_32_44 12 GPIO_ACTIVE_HIGH>;
+
+		npm1300_charger: charger {
+			compatible = "nordic,npm1300-charger";
+			term-microvolt = <4450000>;
+			term-warm-microvolt = <4000000>;
+			current-microamp = <14000>;
+			dischg-limit-microamp = <200000>;
+			vbus-limit-microamp = <500000>;
+			thermistor-ohms = <10000>;
+			thermistor-beta = <3380>;
+			charging-enable;
+			vbatlow-charge-enable;
+		};
+
+		npm1300_gpio: gpio-controller {
+			compatible = "nordic,npm1300-gpio";
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <5>;
+		};
+
+		regulators {
+			compatible = "nordic,npm1300-regulator";
+
+			npm1300_ldo1: LDO1 {
+				regulator-allowed-modes = <NPM13XX_LDSW_MODE_LDO>;
+				regulator-initial-mode = <NPM13XX_LDSW_MODE_LDO>;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+			};
+
+			npm1300_ldo2: LDO2 {
+				regulator-allowed-modes = <NPM13XX_LDSW_MODE_LDSW>;
+				regulator-initial-mode = <NPM13XX_LDSW_MODE_LDSW>;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+			};
+		};
+	};
+};
+
+&mpi2 {
+	compatible = "sifli,sf32lb-mpi-qspi-nor";
+	dmas = <&dmac 0 SF32LB52X_DMA_REQ_MPI2 SF32LB_DMA_PL_MEDIUM>;
+	sifli,lines = <4>;
+	sifli,psclr = <0>;
+	status = "okay";
+
+	gd25q256e: flash@0 {
+		compatible = "gd,gd25q256e", "jedec,qspi-nor";
+		reg = <0x0>;
+		size = <DT_SIZE_M(256)>;
+		quad-enable-requirements = "S2B1v6";
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			ptable: partition@0 {
+				label = "ptable";
+				reg = <0x0 DT_SIZE_K(64)>;
+			};
+
+			code: partition@10000 {
+				label = "code";
+				reg = <0x10000 DT_SIZE_K(32704)>;
+			};
+		};
+	};
+};
+
+&pinctrl {
+	status = "okay";
+};
+
+&rcc_clk {
+	status = "okay";
+
+	sifli,hdiv = <1>;
+	sifli,pdiv1 = <1>;
+	sifli,pdiv2 = <6>;
+
+	dll1 {
+		status = "okay";
+		clock-frequency = <DT_FREQ_M(240)>;
+	};
+};
+
+&usart1 {
+	status = "okay";
+	current-speed = <1000000>;
+	pinctrl-0 = <&usart1_default>;
+	pinctrl-names = "default";
+};
+
+&wdt {
+	status = "okay";
+};

boards/coredevices/pr2/pr2.yaml

@@ -0,0 +1,16 @@
+# Copyright (c) 2026 Core Devices LLC
+# SPDX-License-Identifier: Apache-2.0
+
+identifier: pr2
+name: Pebble-Round-2
+vendor: coredevices
+type: mcu
+arch: arm
+ram: 512
+flash: 32704
+toolchain:
+  - zephyr
+supported:
+  - uart
+  - gpio
+  - watchdog

boards/coredevices/pr2/pr2_defconfig

@@ -0,0 +1,14 @@
+# Copyright (c) 2026 Core Devices LLC
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_ARM_MPU=y
+CONFIG_HW_STACK_PROTECTION=y
+
+CONFIG_SERIAL=y
+CONFIG_GPIO=y
+
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+CONFIG_SF32LB52X_BOOTROM_FLASH_ON_DELAY_MS=100
+CONFIG_SF32LB52X_BOOTROM_FLASH_OFF_DELAY_MS=100

boot/boards/pr2.overlay

@@ -0,0 +1,71 @@
+/*
+ * Copyright (c) 2026 Core Devices LLC
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	chosen {
+		/* we are the bootloader */
+		zephyr,code-partition = &boot;
+
+		/* slots */
+		pb,slot0 = &slot0;
+		pb,slot1 = &slot1;
+		pb,prf = &prf;
+
+		/* buttons */
+		pb,btn-back = &btn_back;
+		pb,btn-up = &btn_up;
+		pb,btn-center = &btn_center;
+		pb,btn-down = &btn_down;
+
+		/* charger */
+		pb,charger = &npm1300_charger;
+
+		/* watchdog */
+		pb,wdt = &wdt;
+	};
+};
+
+&mpi2 {
+	flash@0 {
+		partitions {
+			/* define custom partition scheme */
+			/delete-node/ code@10000;
+
+			boot: partition@10000 {
+				label = "boot";
+				reg = <0x10000 DT_SIZE_K(64)>;
+			};
+
+			slot0: partition@20000 {
+				label = "slot0";
+				reg = <0x20000 DT_SIZE_K(3072)>;
+			};
+
+			slot1: partition@320000 {
+				label = "slot1";
+				reg = <0x320000 DT_SIZE_K(3072)>;
+			};
+
+			prf: partition@a20000 {
+				label = "prf";
+				reg = <0xa20000 DT_SIZE_K(576)>;
+			};
+		};
+	};
+};
+
+/* disable unused peripherals that would be automatically enabled */
+
+&i2c1 {
+	status = "disabled";
+};
+
+&i2c2 {
+	status = "disabled";
+};
+
+&npm1300_gpio {
+	status = "disabled";
+};

boot/sample.yaml

@@ -8,5 +8,6 @@ common:
   build_only: true
   integration_platforms:
     - pt2
+    - pr2
 tests:
   boot.default: {}