Problem when STM32H7 cache enabled #2643
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Hello, Do you have any expierience with such MCU configuration? I would appreciate any help with this topic. |
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Replies: 2 comments 1 reply
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Our experience is in our examples. H7's ETH can only access certain RAM regions, if descriptors or buffers are allocated in regions not accessible by the peripheral... that won't work. We don't have any plans for addressing caches nor MPU. If you are a paying customer or want to be and this is important to you, please contact Cesanta. |
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Hi, @gawelkot |
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Please do not necropost
Please see our documentation, and follow the guidelines in our tutorials.
https://mongoose.ws/articles/stm32-ethernet-and-cache/