Skip to content

UPSTREAM PR #17318: ggml-cpu: extend support for RVV floating-point kernels#264

Closed
loci-dev wants to merge 5 commits intomainfrom
upstream-PR17318-branch_riseproject-dev-riscv
Closed

UPSTREAM PR #17318: ggml-cpu: extend support for RVV floating-point kernels#264
loci-dev wants to merge 5 commits intomainfrom
upstream-PR17318-branch_riseproject-dev-riscv

Conversation

@loci-dev
Copy link
Copy Markdown

Mirrored from ggml-org/llama.cpp#17318

This PR extends the existing RISC-V Vector (RVV) floating-point support introduced introduced in (PR# 15075), adding new kernels.

Summary

  • Adds a BF16 RVV Flag to ggml-cpu/CMakeLists.txt to enable the zvfbfwma extension
  • Adds 6 new kernels for floating-point operations.

Newly Added Kernels

  • ggml_vec_dot_bf16
  • ggml_vec_mad_f16
  • ggml_vec_scale_f16
  • ggml_vec_dot_f16_unroll
  • ggml_cpu_bf16_to_fp32
  • ggml_cpu_fp16_to_fp32

Testing

Kernels were functionally tested on QEMU for VLENs (128-bit, 256-bit, 512-bit and 1024-bit) for a range of input sizes.

@loci-dev loci-dev force-pushed the main branch 2 times, most recently from e32d8e6 to 3071a9f Compare November 20, 2025 20:09
@stojanai stojanai closed this Nov 20, 2025
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Labels

None yet

Projects

None yet

Development

Successfully merging this pull request may close these issues.

3 participants