Tried to fix formatting issues in github pages in the README.

docs/AIEDesignPatterns.md

@@ -5,7 +5,7 @@ This document is an introduction to using the AIE dialect in practice and provid
 
 ## Using AIE Cores
 
-[Core Example](https://github.com/Xilinx/mlir-aie/test/unit_tests/03_sync_with_locks/aie.mlir)
+[Core Example](https://github.com/Xilinx/mlir-aie/tree/main/test/unit_tests/03_sync_with_locks/aie.mlir)
 
 We can use the AIE Cores as below to perform some operations
 
@@ -30,7 +30,7 @@ Perform some operations on the buffer in the core
 ```
 
 ## Single-buffered Communication
-[Single-buffer DMA example](https://github.com/Xilinx/mlir-aie/test/unit_tests/05_tiledma/aie.mlir)
+[Single-buffer DMA example](https://github.com/Xilinx/mlir-aie/tree/main/test/unit_tests/05_tiledma/aie.mlir)
 
 Define the AIE tiles you want to communicate between. Here Tile (7,1) will be the source and (7,2) the destination.
 
@@ -102,7 +102,7 @@ At the end, we release the lock back in state 0. This allows for the memory to r
 
 ## Double-buffered Communication
 
-[Double-buffer DMA example](https://github.com/Xilinx/mlir-aie/test/unit_tests/17_shim_dma_with_core/aie.mlir)
+[Double-buffer DMA example](https://github.com/Xilinx/mlir-aie/tree/main/test/unit_tests/17_shim_dma_with_core/aie.mlir)
 
 This example uses the same setup as the previous. For Tile (7,2) we can define an additional lock and buffer and change the buffers to be half the size:
 ```
@@ -154,7 +154,7 @@ We can use the core in a similar fashion, using the two locks to perform operati
 
 ## Controlling from the ARM Processor
 
-[Controlling From ARM](https://github.com/Xilinx/mlir-aie/test/unit_tests/17_shim_dma_with_core/aie.mlir)
+[Controlling From ARM](https://github.com/Xilinx/mlir-aie/tree/main/test/unit_tests/17_shim_dma_with_core/aie.mlir)
 
 We can perform some operations from the ARM processor and configure the lock to start the transfer. Here is a simple example where we write to a buffer, and begin the data transfer all from the host code.
 
@@ -216,7 +216,7 @@ XAieTile_LockRelease(&(TileInst[7][1]), 0, 1, 0); // Release lock
 This allows the data transfer to begin
 
 ## Static DDR Configuration
-[Static DDR](https://github.com/Xilinx/mlir-aie/test/unit_tests/17_shim_dma_with_core/aie.mlir)
+[Static DDR](https://github.com/Xilinx/mlir-aie/tree/main/test/unit_tests/17_shim_dma_with_core/aie.mlir)
 
 To read/write from DDR, we declare an external buffer with a location and size
 ```

docs/README.md

@@ -17,6 +17,7 @@ Generated code documentation
 Tutorials
 - [AIE Design Patterns](AIEDesignPatterns)
 - [AIE Routing](AIERouting)
+
 -----
 
 <p align="center">Copyright&copy; 2019-2021 Xilinx</p>