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11 changes: 11 additions & 0 deletions include/aie/Dialect/AIE/IR/AIEAttrs.td
Original file line number Diff line number Diff line change
Expand Up @@ -97,6 +97,17 @@ def AIEArch: I32EnumAttr<"AIEArch", "AIE Architecture",
let cppNamespace = "xilinx::AIE";
}

def AIETileType: I32EnumAttr<"AIETileType", "Type of AIE Tile",
[
I32EnumAttrCase<"CoreTile", 0>,
I32EnumAttrCase<"MemTile", 1>,
I32EnumAttrCase<"ShimNOCTile", 2>,
I32EnumAttrCase<"ShimPLTile", 3>,
]> {

let cppNamespace = "xilinx::AIE";
}

def AIEDevice: I32EnumAttr<"AIEDevice", "AIE Device",
[
I32EnumAttrCase<"xcvc1902", 1>,
Expand Down
122 changes: 79 additions & 43 deletions include/aie/Dialect/AIE/IR/AIEInterfaces.td
Original file line number Diff line number Diff line change
Expand Up @@ -28,14 +28,10 @@ def HasValidDMAChannels : NativeOpTrait<"HasValidDMAChannels"> {
string cppNamespace = "::xilinx::AIE";
}

def PredIsCoreTile : CPred<"xilinx::AIE::getTargetModel(&$_op).isCoreTile(llvm::cast<xilinx::AIE::TileElement>($_op).getTileID().col,"
"llvm::cast<xilinx::AIE::TileElement>($_op).getTileID().row)">;
def PredIsMemTile : CPred<"xilinx::AIE::getTargetModel(&$_op).isMemTile(llvm::cast<xilinx::AIE::TileElement>($_op).getTileID().col,"
"llvm::cast<xilinx::AIE::TileElement>($_op).getTileID().row)">;
def PredIsShimNOCTile : CPred<"xilinx::AIE::getTargetModel(&$_op).isShimNOCTile(llvm::cast<xilinx::AIE::TileElement>($_op).getTileID().col,"
"llvm::cast<xilinx::AIE::TileElement>($_op).getTileID().row)">;
def PredIsShimPLTile : CPred<"xilinx::AIE::getTargetModel(&$_op).isShimPLTile(llvm::cast<xilinx::AIE::TileElement>($_op).getTileID().col,"
"llvm::cast<xilinx::AIE::TileElement>($_op).getTileID().row)">;
def PredIsCoreTile : CPred<"llvm::cast<xilinx::AIE::TileElement>($_op).getTileLike().isCoreTile()">;
def PredIsMemTile : CPred<"llvm::cast<xilinx::AIE::TileElement>($_op).getTileLike().isMemTile()">;
def PredIsShimNOCTile : CPred<"llvm::cast<xilinx::AIE::TileElement>($_op).getTileLike().isShimNOCTile()">;
def PredIsShimPLTile : CPred<"llvm::cast<xilinx::AIE::TileElement>($_op).getTileLike().isShimPLTile()">;

def IsCoreTile : PredOpTrait<"op exists in a core tile", PredIsCoreTile>;
def IsMemTile : PredOpTrait<"op exists in a MemTile", PredIsMemTile>;
Expand All @@ -48,6 +44,48 @@ def IsFlowEndPoint : NativeOpTrait<"IsFlowEndPoint"> {
string cppNamespace = "::xilinx::AIE";
}

def TileLike : OpInterface<"TileLike"> {
let description = [{
Interface for operations that represent an AIE tile (logical or physical).
}];
let cppNamespace = "::xilinx::AIE";
let methods = [
InterfaceMethod<[{Return the true hardware tile type.}],
"xilinx::AIE::AIETileType", "getTileType", (ins)
>,
InterfaceMethod<[{Return the optional column index.}],
"std::optional<int>", "tryGetCol", (ins)
>,
InterfaceMethod<[{Return the optional row index.}],
"std::optional<int>", "tryGetRow", (ins)
>,
InterfaceMethod<[{}], "bool", "isCoreTile", (ins), [{}], [{
return $_op.getTileType() == xilinx::AIE::AIETileType::CoreTile;
}]>,
InterfaceMethod<[{}], "bool", "isMemTile", (ins), [{}], [{
return $_op.getTileType() == xilinx::AIE::AIETileType::MemTile;
}]>,
InterfaceMethod<[{}], "bool", "isShimNOCTile", (ins), [{}], [{
return $_op.getTileType() == xilinx::AIE::AIETileType::ShimNOCTile;
}]>,
InterfaceMethod<[{}], "bool", "isShimPLTile", (ins), [{}], [{
return $_op.getTileType() == xilinx::AIE::AIETileType::ShimPLTile;
}]>,
InterfaceMethod<[{}], "bool", "isShimNOCorPLTile", (ins), [{}], [{
return $_op.isShimNOCTile() || $_op.isShimPLTile();
}]>,
InterfaceMethod<[{}], "bool", "isShimTile", (ins), [{}], [{
return $_op.isShimNOCTile() || $_op.isShimPLTile();
}]>,
InterfaceMethod<[{Return the number of source connections for a wire bundle.}],
"size_t", "getNumSourceConnections", (ins "xilinx::AIE::WireBundle":$bundle)
>,
InterfaceMethod<[{Return the number of dest connections for a wire bundle.}],
"size_t", "getNumDestConnections", (ins "xilinx::AIE::WireBundle":$bundle)
>,
];
}

def TileElement : OpInterface<"TileElement", [
DeclareOpInterfaceMethods<OpAsmOpInterface>,
]> {
Expand All @@ -56,49 +94,48 @@ def TileElement : OpInterface<"TileElement", [
}];
let cppNamespace = "::xilinx::AIE";
let methods = [
InterfaceMethod<[{
Return the tile operand value.
}],
"mlir::Value", "getTile", (ins )
InterfaceMethod<[{Return the tile operand value.}],
"mlir::Value", "getTile", (ins)
>,
InterfaceMethod<[{
Return the location of the Tile where the element is located.
}],
"xilinx::AIE::TileID", "getTileID", (ins ),
/*methodBody=*/[{}],
/*defaultImpl=*/[{
ConcreteOp op = llvm::cast<ConcreteOp>(this->getOperation());
return op.getTileOp().getTileID();
InterfaceMethod<[{Return the TileLike interface for this element's tile.}],
"TileLike", "getTileLike", (ins), [{}], [{
return llvm::dyn_cast<TileLike>($_op.getTile().getDefiningOp());
}]
>,
InterfaceMethod<[{
Return column.
}],
"int", "colIndex", (ins),
/*methodBody=*/[{}],
/*defaultImpl=*/[{
return $_op.getTileID().col;
InterfaceMethod<[{Return the column index of this element's tile. Asserts if unplaced.}],
"int", "colIndex", (ins), [{}], [{
std::optional<int> col = $_op.getTileLike().tryGetCol();
assert(col.has_value() && "TileElement called colIndex() on an unplaced tile.");
return *col;
}]
>,
InterfaceMethod<[{
Return row.
}],
"int", "rowIndex", (ins),
/*methodBody=*/[{}],
/*defaultImpl=*/[{
return $_op.getTileID().row;
InterfaceMethod<[{Return the row index of this element's tile. Asserts if unplaced.}],
"int", "rowIndex", (ins), [{}], [{
std::optional<int> row = $_op.getTileLike().tryGetRow();
assert(row.has_value() && "TileElement called rowIndex() on an unplaced tile.");
return *row;
}]
>,
InterfaceMethod<[{Return the TileID of this element's tile.}],
"TileID", "getTileID", (ins), [{}], [{
return TileID{$_op.colIndex(), $_op.rowIndex()};
}]
>
];

let extraClassDeclaration = [{
TileOp getTileOp();
}];

let extraTraitClassDeclaration = [{
void getAsmResultNames(
llvm::function_ref<void(mlir::Value, llvm::StringRef)> setNameFn) {
ConcreteOp op = llvm::cast<ConcreteOp>(this->getOperation());
std::string nameWithoutDialect =
op.getOperationName().str().substr(op.getOperationName().find('.') + 1);
setNameFn(op.getResult(), nameWithoutDialect + "_" +
std::to_string(getTileID().col) + "_" +
std::to_string(getTileID().row));
void getAsmResultNames(::mlir::OpAsmSetValueNameFn setNameFn) {
std::optional<int> col = $_op.getTileLike().tryGetCol();
std::optional<int> row = $_op.getTileLike().tryGetRow();
if (col && row) {
llvm::StringRef opName = $_op.getOperation()->getName().stripDialect();
std::string name = (opName + "_" + llvm::Twine(*col) + "_" + llvm::Twine(*row)).str();
setNameFn($_op.getResult(), name);
}
}
}];
}
Expand All @@ -109,7 +146,6 @@ def Interconnect : OpInterface<"Interconnect", [TileElement]> {
enabling them to host flows for routing.
}];
let cppNamespace = "::xilinx::AIE";

let methods = [
InterfaceMethod<[{}],
"mlir::Region &", "getConnections", (ins )
Expand Down
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