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@SkillSurf

SkillSurf

Empowering Sri Lankans to be industry and life‑ready.

SkillSurf

Skill Surf, founded by alumni from the Dept. of Electronics and Telecommunication Engineering, University of Moratuwa, focuses on building an ecosystem to empower all our learners to be industry and life-ready. The organization focuses on narrowing the gap between theoretical education and practical, industry-relevant skills, particularly in a fast-changing technological landscape. Skill Surf provides specialized bootcamps in technology areas like the Internet of Things (IoT), processor and chip design, and AI, meeting the increasing demands of Sri Lanka's growing tech industry. Its role extends to enhancing the national economy by equipping professionals with vital tech skills and helping to bridge the skills gap.

  • Empowerment through Education: Enabling learning enthusiasts to acquire essential technical skills in high-demand areas
  • Bridging the Skills Gap: Addressing the mismatch between traditional educational offerings and the practical demands of the modern tech industry.
  • Fostering a Community of Tech Enthusiasts: Building a community of skilled professionals passionate about technology and innovation.
  • Lifelong Learning and Continuous Improvement: Enabling continuous learning to keep pace with the rapidly evolving tech landscape.

SkillSurf Portfolio



 View Skill Surf Portfolio 


Roadmap

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  1. systemverilog systemverilog Public

    SystemVerilog for ASIC/FPGA Design & Simulation, with Synopsys Tool Flow

    Tcl 54 17

  2. introduction_qc introduction_qc Public

    Introduction to Quantum Computing Free One-Day Workshop

    Mathematica 4 1

  3. introduction_genAI introduction_genAI Public

    Introduction to GenAI Free One-Day Workshop

    Jupyter Notebook 20 3

  4. art_of_aicd art_of_aicd Public

    The Art of Analog IC Design Free One Day Workshop organized by SkillSurf.

    HTML 1

  5. ttsky25_se_opamp ttsky25_se_opamp Public

    Template for Operational Amplifier Design submission for Tiny Tapeout SKY130 (ChipFoundry) shuttles

    Verilog 3

  6. cmos-pll-ihp-sg13g2 cmos-pll-ihp-sg13g2 Public

    A charge-pump (CP) based Phase Locked Loop (PLL) using IHP SG13G2 130nm technology.

    Jupyter Notebook 3

Repositories

Showing 10 of 19 repositories
  • frac-n-pll-vco-smacd_2026 Public

    A 2.4GHz Type-II ∆Σ Fractional-N Phase Locked Loop (PLL) with a Type IV Cross-Coupled Differential LC Voltage-Controlled Oscillator (VCO) for Wifi/Bluetooth Applications (UNIC-CASS program by IEEE CASS)

    SkillSurf/frac-n-pll-vco-smacd_2026’s past year of commit activity
    Jupyter Notebook 3 0 10 0 Updated Apr 9, 2026
  • os-ina-pso-smacd_2026 Public

    Design of an Area Optimized Low-Power Low-Noise CMOS Instrumentation Amplifier in SKY130 using Hybrid Particle Swarm Optimization

    SkillSurf/os-ina-pso-smacd_2026’s past year of commit activity
    Jupyter Notebook 2 MIT 0 0 0 Updated Apr 8, 2026
  • .github Public
    SkillSurf/.github’s past year of commit activity
    0 0 0 0 Updated Apr 7, 2026
  • systemverilog Public

    SystemVerilog for ASIC/FPGA Design & Simulation, with Synopsys Tool Flow

    SkillSurf/systemverilog’s past year of commit activity
    Tcl 54 MIT 17 0 0 Updated Feb 27, 2026
  • art_of_aicd Public

    The Art of Analog IC Design Free One Day Workshop organized by SkillSurf.

    SkillSurf/art_of_aicd’s past year of commit activity
    HTML 0 MIT 1 0 1 Updated Jan 26, 2026
  • intro_comparch Public

    Hands-on Introduction to Computer Architecture with RISC‑V

    SkillSurf/intro_comparch’s past year of commit activity
    SystemVerilog 0 0 0 0 Updated Nov 17, 2025
  • ttsky25_se_opamp Public

    Template for Operational Amplifier Design submission for Tiny Tapeout SKY130 (ChipFoundry) shuttles

    SkillSurf/ttsky25_se_opamp’s past year of commit activity
    Verilog 3 Apache-2.0 0 0 0 Updated Nov 12, 2025
  • ttsky25_se_opamps Public

    TTSKY25b Low-power Single-ended Op-Amp tapeout from AICD Contest

    SkillSurf/ttsky25_se_opamps’s past year of commit activity
    Verilog 2 Apache-2.0 0 0 0 Updated Nov 10, 2025
  • cmos-pll-ihp-sg13g2 Public

    A charge-pump (CP) based Phase Locked Loop (PLL) using IHP SG13G2 130nm technology.

    SkillSurf/cmos-pll-ihp-sg13g2’s past year of commit activity
    Jupyter Notebook 3 MIT 0 0 0 Updated Sep 1, 2025
  • sg13g2_asic_flow Public Forked from iic-jku/SG13G2_ASIC-Design-Template

    SG13G2 ASIC flow design template

    SkillSurf/sg13g2_asic_flow’s past year of commit activity
    Python 1 8 0 0 Updated Apr 9, 2025

People

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