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fix(cmsis): add missing opening parenthesis for bitmask and fix malformed comments #6

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d3026cc
fix(mp21x/drivers/usb): missing opening parenthesis in USB_OTG_GCCFG_…
7086cmd Feb 17, 2026
781e367
fix: comment
7086cmd Feb 17, 2026
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10 changes: 5 additions & 5 deletions Drivers/CMSIS/Device/ST/STM32MP2xx/Include/stm32mp211axx_ca35.h
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Expand Up @@ -6694,11 +6694,11 @@ typedef struct

/********* Bit definition for CA35SSC_LPI_TSGEN_NTS_CR_WC1 register *********/
#define CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSREQ_Pos (8U)
#define CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSREQ_Msk (0x1UL << CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSREQ_Pos) *!< 0x00000100 */
#define CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSREQ CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSREQ_Msk *!< */
#define CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSREQ_Msk (0x1UL << CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSREQ_Pos) /*!< 0x00000100 */
#define CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSREQ CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSREQ_Msk /*!< */
#define CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSACK_Pos (9U)
#define CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSACK_Msk (0x1UL << CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSACK_Pos) *!< 0x00000200 */
#define CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSACK CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSACK_Msk *!< */
#define CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSACK_Msk (0x1UL << CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSACK_Pos) /*!< 0x00000200 */
#define CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSACK CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSACK_Msk /*!< */

/********* Bit definition for CA35SSC_LPI_TSGEN_NTS_CR_WT1 register *********/
#define CA35SSC_LPI_TSGEN_NTS_CR_WT1_TS_CSYSREQ_Pos (8U)
Expand Down Expand Up @@ -43238,7 +43238,7 @@ typedef struct
#define USB_OTG_GCCFG_FSVPLUS_Msk (0x1UL << USB_OTG_GCCFG_FSVPLUS_Pos) /*!< 0x00000002 */
#define USB_OTG_GCCFG_FSVPLUS USB_OTG_GCCFG_FSVPLUS_Msk /*!< Single-Ended DP2 indicator DP voltage level */
#define USB_OTG_GCCFG_FSVMINUS_Pos (2U)
#define USB_OTG_GCCFG_FSVMINUS_Msk 0x1UL << USB_OTG_GCCFG_FSVMINUS_Pos) /*!< 0x00000004 */
#define USB_OTG_GCCFG_FSVMINUS_Msk (0x1UL << USB_OTG_GCCFG_FSVMINUS_Pos) /*!< 0x00000004 */
#define USB_OTG_GCCFG_FSVMINUS USB_OTG_GCCFG_FSVMINUS_Msk /*!< Single-Ended DM2 indicator DM voltage level */
#define USB_OTG_GCCFG_SESSVLD_Pos (3U)
#define USB_OTG_GCCFG_SESSVLD_Msk (0x1UL << USB_OTG_GCCFG_SESSVLD_Pos) /*!< 0x00000008 */
Expand Down
2 changes: 1 addition & 1 deletion Drivers/CMSIS/Device/ST/STM32MP2xx/Include/stm32mp211axx_cm33.h
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Expand Up @@ -45014,7 +45014,7 @@ typedef struct
#define USB_OTG_GCCFG_FSVPLUS_Msk (0x1UL << USB_OTG_GCCFG_FSVPLUS_Pos) /*!< 0x00000002 */
#define USB_OTG_GCCFG_FSVPLUS USB_OTG_GCCFG_FSVPLUS_Msk /*!< Single-Ended DP2 indicator DP voltage level */
#define USB_OTG_GCCFG_FSVMINUS_Pos (2U)
#define USB_OTG_GCCFG_FSVMINUS_Msk 0x1UL << USB_OTG_GCCFG_FSVMINUS_Pos) /*!< 0x00000004 */
#define USB_OTG_GCCFG_FSVMINUS_Msk (0x1UL << USB_OTG_GCCFG_FSVMINUS_Pos) /*!< 0x00000004 */
#define USB_OTG_GCCFG_FSVMINUS USB_OTG_GCCFG_FSVMINUS_Msk /*!< Single-Ended DM2 indicator DM voltage level */
#define USB_OTG_GCCFG_SESSVLD_Pos (3U)
#define USB_OTG_GCCFG_SESSVLD_Msk (0x1UL << USB_OTG_GCCFG_SESSVLD_Pos) /*!< 0x00000008 */
Expand Down
10 changes: 5 additions & 5 deletions Drivers/CMSIS/Device/ST/STM32MP2xx/Include/stm32mp211cxx_ca35.h
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Expand Up @@ -6866,11 +6866,11 @@ typedef struct

/********* Bit definition for CA35SSC_LPI_TSGEN_NTS_CR_WC1 register *********/
#define CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSREQ_Pos (8U)
#define CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSREQ_Msk (0x1UL << CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSREQ_Pos) *!< 0x00000100 */
#define CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSREQ CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSREQ_Msk *!< */
#define CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSREQ_Msk (0x1UL << CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSREQ_Pos) /*!< 0x00000100 */
#define CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSREQ CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSREQ_Msk /*!< */
#define CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSACK_Pos (9U)
#define CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSACK_Msk (0x1UL << CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSACK_Pos) *!< 0x00000200 */
#define CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSACK CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSACK_Msk *!< */
#define CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSACK_Msk (0x1UL << CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSACK_Pos) /*!< 0x00000200 */
#define CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSACK CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSACK_Msk /*!< */

/********* Bit definition for CA35SSC_LPI_TSGEN_NTS_CR_WT1 register *********/
#define CA35SSC_LPI_TSGEN_NTS_CR_WT1_TS_CSYSREQ_Pos (8U)
Expand Down Expand Up @@ -44500,7 +44500,7 @@ typedef struct
#define USB_OTG_GCCFG_FSVPLUS_Msk (0x1UL << USB_OTG_GCCFG_FSVPLUS_Pos) /*!< 0x00000002 */
#define USB_OTG_GCCFG_FSVPLUS USB_OTG_GCCFG_FSVPLUS_Msk /*!< Single-Ended DP2 indicator DP voltage level */
#define USB_OTG_GCCFG_FSVMINUS_Pos (2U)
#define USB_OTG_GCCFG_FSVMINUS_Msk 0x1UL << USB_OTG_GCCFG_FSVMINUS_Pos) /*!< 0x00000004 */
#define USB_OTG_GCCFG_FSVMINUS_Msk (0x1UL << USB_OTG_GCCFG_FSVMINUS_Pos) /*!< 0x00000004 */
#define USB_OTG_GCCFG_FSVMINUS USB_OTG_GCCFG_FSVMINUS_Msk /*!< Single-Ended DM2 indicator DM voltage level */
#define USB_OTG_GCCFG_SESSVLD_Pos (3U)
#define USB_OTG_GCCFG_SESSVLD_Msk (0x1UL << USB_OTG_GCCFG_SESSVLD_Pos) /*!< 0x00000008 */
Expand Down
2 changes: 1 addition & 1 deletion Drivers/CMSIS/Device/ST/STM32MP2xx/Include/stm32mp211cxx_cm33.h
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Expand Up @@ -46380,7 +46380,7 @@ typedef struct
#define USB_OTG_GCCFG_FSVPLUS_Msk (0x1UL << USB_OTG_GCCFG_FSVPLUS_Pos) /*!< 0x00000002 */
#define USB_OTG_GCCFG_FSVPLUS USB_OTG_GCCFG_FSVPLUS_Msk /*!< Single-Ended DP2 indicator DP voltage level */
#define USB_OTG_GCCFG_FSVMINUS_Pos (2U)
#define USB_OTG_GCCFG_FSVMINUS_Msk 0x1UL << USB_OTG_GCCFG_FSVMINUS_Pos) /*!< 0x00000004 */
#define USB_OTG_GCCFG_FSVMINUS_Msk (0x1UL << USB_OTG_GCCFG_FSVMINUS_Pos) /*!< 0x00000004 */
#define USB_OTG_GCCFG_FSVMINUS USB_OTG_GCCFG_FSVMINUS_Msk /*!< Single-Ended DM2 indicator DM voltage level */
#define USB_OTG_GCCFG_SESSVLD_Pos (3U)
#define USB_OTG_GCCFG_SESSVLD_Msk (0x1UL << USB_OTG_GCCFG_SESSVLD_Pos) /*!< 0x00000008 */
Expand Down
10 changes: 5 additions & 5 deletions Drivers/CMSIS/Device/ST/STM32MP2xx/Include/stm32mp211dxx_ca35.h
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Expand Up @@ -6694,11 +6694,11 @@ typedef struct

/********* Bit definition for CA35SSC_LPI_TSGEN_NTS_CR_WC1 register *********/
#define CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSREQ_Pos (8U)
#define CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSREQ_Msk (0x1UL << CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSREQ_Pos) *!< 0x00000100 */
#define CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSREQ CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSREQ_Msk *!< */
#define CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSREQ_Msk (0x1UL << CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSREQ_Pos) /*!< 0x00000100 */
#define CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSREQ CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSREQ_Msk /*!< */
#define CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSACK_Pos (9U)
#define CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSACK_Msk (0x1UL << CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSACK_Pos) *!< 0x00000200 */
#define CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSACK CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSACK_Msk *!< */
#define CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSACK_Msk (0x1UL << CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSACK_Pos) /*!< 0x00000200 */
#define CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSACK CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSACK_Msk /*!< */

/********* Bit definition for CA35SSC_LPI_TSGEN_NTS_CR_WT1 register *********/
#define CA35SSC_LPI_TSGEN_NTS_CR_WT1_TS_CSYSREQ_Pos (8U)
Expand Down Expand Up @@ -43238,7 +43238,7 @@ typedef struct
#define USB_OTG_GCCFG_FSVPLUS_Msk (0x1UL << USB_OTG_GCCFG_FSVPLUS_Pos) /*!< 0x00000002 */
#define USB_OTG_GCCFG_FSVPLUS USB_OTG_GCCFG_FSVPLUS_Msk /*!< Single-Ended DP2 indicator DP voltage level */
#define USB_OTG_GCCFG_FSVMINUS_Pos (2U)
#define USB_OTG_GCCFG_FSVMINUS_Msk 0x1UL << USB_OTG_GCCFG_FSVMINUS_Pos) /*!< 0x00000004 */
#define USB_OTG_GCCFG_FSVMINUS_Msk (0x1UL << USB_OTG_GCCFG_FSVMINUS_Pos) /*!< 0x00000004 */
#define USB_OTG_GCCFG_FSVMINUS USB_OTG_GCCFG_FSVMINUS_Msk /*!< Single-Ended DM2 indicator DM voltage level */
#define USB_OTG_GCCFG_SESSVLD_Pos (3U)
#define USB_OTG_GCCFG_SESSVLD_Msk (0x1UL << USB_OTG_GCCFG_SESSVLD_Pos) /*!< 0x00000008 */
Expand Down
2 changes: 1 addition & 1 deletion Drivers/CMSIS/Device/ST/STM32MP2xx/Include/stm32mp211dxx_cm33.h
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Expand Up @@ -45014,7 +45014,7 @@ typedef struct
#define USB_OTG_GCCFG_FSVPLUS_Msk (0x1UL << USB_OTG_GCCFG_FSVPLUS_Pos) /*!< 0x00000002 */
#define USB_OTG_GCCFG_FSVPLUS USB_OTG_GCCFG_FSVPLUS_Msk /*!< Single-Ended DP2 indicator DP voltage level */
#define USB_OTG_GCCFG_FSVMINUS_Pos (2U)
#define USB_OTG_GCCFG_FSVMINUS_Msk 0x1UL << USB_OTG_GCCFG_FSVMINUS_Pos) /*!< 0x00000004 */
#define USB_OTG_GCCFG_FSVMINUS_Msk (0x1UL << USB_OTG_GCCFG_FSVMINUS_Pos) /*!< 0x00000004 */
#define USB_OTG_GCCFG_FSVMINUS USB_OTG_GCCFG_FSVMINUS_Msk /*!< Single-Ended DM2 indicator DM voltage level */
#define USB_OTG_GCCFG_SESSVLD_Pos (3U)
#define USB_OTG_GCCFG_SESSVLD_Msk (0x1UL << USB_OTG_GCCFG_SESSVLD_Pos) /*!< 0x00000008 */
Expand Down
10 changes: 5 additions & 5 deletions Drivers/CMSIS/Device/ST/STM32MP2xx/Include/stm32mp211fxx_ca35.h
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Expand Up @@ -6866,11 +6866,11 @@ typedef struct

/********* Bit definition for CA35SSC_LPI_TSGEN_NTS_CR_WC1 register *********/
#define CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSREQ_Pos (8U)
#define CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSREQ_Msk (0x1UL << CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSREQ_Pos) *!< 0x00000100 */
#define CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSREQ CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSREQ_Msk *!< */
#define CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSREQ_Msk (0x1UL << CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSREQ_Pos) /*!< 0x00000100 */
#define CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSREQ CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSREQ_Msk /*!< */
#define CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSACK_Pos (9U)
#define CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSACK_Msk (0x1UL << CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSACK_Pos) *!< 0x00000200 */
#define CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSACK CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSACK_Msk *!< */
#define CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSACK_Msk (0x1UL << CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSACK_Pos) /*!< 0x00000200 */
#define CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSACK CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSACK_Msk /*!< */

/********* Bit definition for CA35SSC_LPI_TSGEN_NTS_CR_WT1 register *********/
#define CA35SSC_LPI_TSGEN_NTS_CR_WT1_TS_CSYSREQ_Pos (8U)
Expand Down Expand Up @@ -44500,7 +44500,7 @@ typedef struct
#define USB_OTG_GCCFG_FSVPLUS_Msk (0x1UL << USB_OTG_GCCFG_FSVPLUS_Pos) /*!< 0x00000002 */
#define USB_OTG_GCCFG_FSVPLUS USB_OTG_GCCFG_FSVPLUS_Msk /*!< Single-Ended DP2 indicator DP voltage level */
#define USB_OTG_GCCFG_FSVMINUS_Pos (2U)
#define USB_OTG_GCCFG_FSVMINUS_Msk 0x1UL << USB_OTG_GCCFG_FSVMINUS_Pos) /*!< 0x00000004 */
#define USB_OTG_GCCFG_FSVMINUS_Msk (0x1UL << USB_OTG_GCCFG_FSVMINUS_Pos) /*!< 0x00000004 */
#define USB_OTG_GCCFG_FSVMINUS USB_OTG_GCCFG_FSVMINUS_Msk /*!< Single-Ended DM2 indicator DM voltage level */
#define USB_OTG_GCCFG_SESSVLD_Pos (3U)
#define USB_OTG_GCCFG_SESSVLD_Msk (0x1UL << USB_OTG_GCCFG_SESSVLD_Pos) /*!< 0x00000008 */
Expand Down
2 changes: 1 addition & 1 deletion Drivers/CMSIS/Device/ST/STM32MP2xx/Include/stm32mp211fxx_cm33.h
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Expand Up @@ -46380,7 +46380,7 @@ typedef struct
#define USB_OTG_GCCFG_FSVPLUS_Msk (0x1UL << USB_OTG_GCCFG_FSVPLUS_Pos) /*!< 0x00000002 */
#define USB_OTG_GCCFG_FSVPLUS USB_OTG_GCCFG_FSVPLUS_Msk /*!< Single-Ended DP2 indicator DP voltage level */
#define USB_OTG_GCCFG_FSVMINUS_Pos (2U)
#define USB_OTG_GCCFG_FSVMINUS_Msk 0x1UL << USB_OTG_GCCFG_FSVMINUS_Pos) /*!< 0x00000004 */
#define USB_OTG_GCCFG_FSVMINUS_Msk (0x1UL << USB_OTG_GCCFG_FSVMINUS_Pos) /*!< 0x00000004 */
#define USB_OTG_GCCFG_FSVMINUS USB_OTG_GCCFG_FSVMINUS_Msk /*!< Single-Ended DM2 indicator DM voltage level */
#define USB_OTG_GCCFG_SESSVLD_Pos (3U)
#define USB_OTG_GCCFG_SESSVLD_Msk (0x1UL << USB_OTG_GCCFG_SESSVLD_Pos) /*!< 0x00000008 */
Expand Down
10 changes: 5 additions & 5 deletions Drivers/CMSIS/Device/ST/STM32MP2xx/Include/stm32mp213axx_ca35.h
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Expand Up @@ -6803,11 +6803,11 @@ typedef struct

/********* Bit definition for CA35SSC_LPI_TSGEN_NTS_CR_WC1 register *********/
#define CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSREQ_Pos (8U)
#define CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSREQ_Msk (0x1UL << CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSREQ_Pos) *!< 0x00000100 */
#define CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSREQ CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSREQ_Msk *!< */
#define CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSREQ_Msk (0x1UL << CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSREQ_Pos) /*!< 0x00000100 */
#define CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSREQ CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSREQ_Msk /*!< */
#define CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSACK_Pos (9U)
#define CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSACK_Msk (0x1UL << CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSACK_Pos) *!< 0x00000200 */
#define CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSACK CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSACK_Msk *!< */
#define CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSACK_Msk (0x1UL << CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSACK_Pos) /*!< 0x00000200 */
#define CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSACK CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSACK_Msk /*!< */

/********* Bit definition for CA35SSC_LPI_TSGEN_NTS_CR_WT1 register *********/
#define CA35SSC_LPI_TSGEN_NTS_CR_WT1_TS_CSYSREQ_Pos (8U)
Expand Down Expand Up @@ -44785,7 +44785,7 @@ typedef struct
#define USB_OTG_GCCFG_FSVPLUS_Msk (0x1UL << USB_OTG_GCCFG_FSVPLUS_Pos) /*!< 0x00000002 */
#define USB_OTG_GCCFG_FSVPLUS USB_OTG_GCCFG_FSVPLUS_Msk /*!< Single-Ended DP2 indicator DP voltage level */
#define USB_OTG_GCCFG_FSVMINUS_Pos (2U)
#define USB_OTG_GCCFG_FSVMINUS_Msk 0x1UL << USB_OTG_GCCFG_FSVMINUS_Pos) /*!< 0x00000004 */
#define USB_OTG_GCCFG_FSVMINUS_Msk (0x1UL << USB_OTG_GCCFG_FSVMINUS_Pos) /*!< 0x00000004 */
#define USB_OTG_GCCFG_FSVMINUS USB_OTG_GCCFG_FSVMINUS_Msk /*!< Single-Ended DM2 indicator DM voltage level */
#define USB_OTG_GCCFG_SESSVLD_Pos (3U)
#define USB_OTG_GCCFG_SESSVLD_Msk (0x1UL << USB_OTG_GCCFG_SESSVLD_Pos) /*!< 0x00000008 */
Expand Down
2 changes: 1 addition & 1 deletion Drivers/CMSIS/Device/ST/STM32MP2xx/Include/stm32mp213axx_cm33.h
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Expand Up @@ -46591,7 +46591,7 @@ typedef struct
#define USB_OTG_GCCFG_FSVPLUS_Msk (0x1UL << USB_OTG_GCCFG_FSVPLUS_Pos) /*!< 0x00000002 */
#define USB_OTG_GCCFG_FSVPLUS USB_OTG_GCCFG_FSVPLUS_Msk /*!< Single-Ended DP2 indicator DP voltage level */
#define USB_OTG_GCCFG_FSVMINUS_Pos (2U)
#define USB_OTG_GCCFG_FSVMINUS_Msk 0x1UL << USB_OTG_GCCFG_FSVMINUS_Pos) /*!< 0x00000004 */
#define USB_OTG_GCCFG_FSVMINUS_Msk (0x1UL << USB_OTG_GCCFG_FSVMINUS_Pos) /*!< 0x00000004 */
#define USB_OTG_GCCFG_FSVMINUS USB_OTG_GCCFG_FSVMINUS_Msk /*!< Single-Ended DM2 indicator DM voltage level */
#define USB_OTG_GCCFG_SESSVLD_Pos (3U)
#define USB_OTG_GCCFG_SESSVLD_Msk (0x1UL << USB_OTG_GCCFG_SESSVLD_Pos) /*!< 0x00000008 */
Expand Down
10 changes: 5 additions & 5 deletions Drivers/CMSIS/Device/ST/STM32MP2xx/Include/stm32mp213cxx_ca35.h
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Expand Up @@ -6975,11 +6975,11 @@ typedef struct

/********* Bit definition for CA35SSC_LPI_TSGEN_NTS_CR_WC1 register *********/
#define CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSREQ_Pos (8U)
#define CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSREQ_Msk (0x1UL << CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSREQ_Pos) *!< 0x00000100 */
#define CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSREQ CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSREQ_Msk *!< */
#define CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSREQ_Msk (0x1UL << CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSREQ_Pos) /*!< 0x00000100 */
#define CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSREQ CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSREQ_Msk /*!< */
#define CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSACK_Pos (9U)
#define CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSACK_Msk (0x1UL << CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSACK_Pos) *!< 0x00000200 */
#define CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSACK CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSACK_Msk *!< */
#define CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSACK_Msk (0x1UL << CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSACK_Pos) /*!< 0x00000200 */
#define CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSACK CA35SSC_LPI_TSGEN_NTS_CR_WC1_TS_CSYSACK_Msk /*!< */

/********* Bit definition for CA35SSC_LPI_TSGEN_NTS_CR_WT1 register *********/
#define CA35SSC_LPI_TSGEN_NTS_CR_WT1_TS_CSYSREQ_Pos (8U)
Expand Down Expand Up @@ -46047,7 +46047,7 @@ typedef struct
#define USB_OTG_GCCFG_FSVPLUS_Msk (0x1UL << USB_OTG_GCCFG_FSVPLUS_Pos) /*!< 0x00000002 */
#define USB_OTG_GCCFG_FSVPLUS USB_OTG_GCCFG_FSVPLUS_Msk /*!< Single-Ended DP2 indicator DP voltage level */
#define USB_OTG_GCCFG_FSVMINUS_Pos (2U)
#define USB_OTG_GCCFG_FSVMINUS_Msk 0x1UL << USB_OTG_GCCFG_FSVMINUS_Pos) /*!< 0x00000004 */
#define USB_OTG_GCCFG_FSVMINUS_Msk (0x1UL << USB_OTG_GCCFG_FSVMINUS_Pos) /*!< 0x00000004 */
#define USB_OTG_GCCFG_FSVMINUS USB_OTG_GCCFG_FSVMINUS_Msk /*!< Single-Ended DM2 indicator DM voltage level */
#define USB_OTG_GCCFG_SESSVLD_Pos (3U)
#define USB_OTG_GCCFG_SESSVLD_Msk (0x1UL << USB_OTG_GCCFG_SESSVLD_Pos) /*!< 0x00000008 */
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2 changes: 1 addition & 1 deletion Drivers/CMSIS/Device/ST/STM32MP2xx/Include/stm32mp213cxx_cm33.h
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Original file line number Diff line number Diff line change
Expand Up @@ -47957,7 +47957,7 @@ typedef struct
#define USB_OTG_GCCFG_FSVPLUS_Msk (0x1UL << USB_OTG_GCCFG_FSVPLUS_Pos) /*!< 0x00000002 */
#define USB_OTG_GCCFG_FSVPLUS USB_OTG_GCCFG_FSVPLUS_Msk /*!< Single-Ended DP2 indicator DP voltage level */
#define USB_OTG_GCCFG_FSVMINUS_Pos (2U)
#define USB_OTG_GCCFG_FSVMINUS_Msk 0x1UL << USB_OTG_GCCFG_FSVMINUS_Pos) /*!< 0x00000004 */
#define USB_OTG_GCCFG_FSVMINUS_Msk (0x1UL << USB_OTG_GCCFG_FSVMINUS_Pos) /*!< 0x00000004 */
#define USB_OTG_GCCFG_FSVMINUS USB_OTG_GCCFG_FSVMINUS_Msk /*!< Single-Ended DM2 indicator DM voltage level */
#define USB_OTG_GCCFG_SESSVLD_Pos (3U)
#define USB_OTG_GCCFG_SESSVLD_Msk (0x1UL << USB_OTG_GCCFG_SESSVLD_Pos) /*!< 0x00000008 */
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