Add RV32M extension support

[5iri]

• Add MUL, MULH, MULHSU, MULHU, DIV, DIVU, REM, REMU instructions to the ALU and decoder
• Add sim/factorial.c system test that exercises all M-extension operations, with volatile operands to prevent GCC from constant-folding them at -O1
• Add unit tests for all M-extension ALU operations including edge cases (div-by-zero, signed overflow)

[Copilot]

Pull request overview

Adds RV32M (integer multiply/divide) instruction support across the RTL and expands the verification suite to cover decoder/ALU behavior and an end-to-end program.

Changes:

• Add RV32M instruction IDs and decode support (MUL/MULH/MULHSU/MULHU/DIV/DIVU/REM/REMU).
• Implement RV32M operations in the ALU, including divide-by-zero and overflow handling.
• Extend unit tests and add a new factorial-based system test intended to exercise M-extension operations.

Reviewed changes

Copilot reviewed 8 out of 8 changed files in this pull request and generated 8 comments.

Show a summary per file

File	Description
rtl/include/instr_defines.vh	Adds instruction ID constants for RV32M ops.
rtl/core_modules/decoder.v	Decodes funct7/funct3 combinations for RV32M R-type instructions.
rtl/core_modules/alu.v	Implements RV32M multiply/divide/remainder semantics and adds a FORMAL vs non-FORMAL split.
tests/unit_tests/test_decoder_gcc.py	Updates assembler march to include m and adds decoder test vectors for RV32M instructions; adjusts sim env.
tests/unit_tests/test_alu.py	Adds RV32M ALU unit tests (including div-by-zero and overflow) and adjusts sim env.
tests/system_tests/test_fibonacci.py	Adds additional runtime logging in the simulation loop.
tests/system_tests/test_factorial.py	Adds new system test that compiles/runs factorial.c and monitors memory-mapped outputs.
sim/factorial.c	Adds factorial program intended to exercise all RV32M operations.

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