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Replace separate memory modules with single unified memory module #22

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8994e8f
Replace separate memory modules with single unified memory module
Feb 12, 2026
e20fd80
fixed memory access
Feb 12, 2026
1e3b6d9
adding suggested changes
Feb 13, 2026
52e4c7d
code cleanup
spr4bhu Feb 22, 2026
e2ab0a6
made requested changes
spr4bhu Feb 26, 2026
c9d885e
fix unified memory naming, instruction bounds check, and hex load size
spr4bhu Mar 13, 2026
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86 changes: 0 additions & 86 deletions rtl/data_mem.v
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2 changes: 1 addition & 1 deletion rtl/include/memory_map.vh
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Original file line number Diff line number Diff line change
Expand Up @@ -49,7 +49,7 @@
`define UART_BAUD 32'h2000000C // Baud rate divisor

// Memory access helper macros
`define IS_INSTR_MEM(addr) ((addr) <= `INSTR_MEM_SIZE)
`define IS_INSTR_MEM(addr) ((addr) <= `INSTR_MEM_END)
`define IS_TIMER_MEM(addr) ((addr) >= `TIMER_BASE && (addr) <= `TIMER_END)
`define IS_DATA_MEM(addr) ((addr) >= `DATA_MEM_BASE && (addr) <= `DATA_MEM_END)
`define IS_PERIPH_MEM(addr) ((addr) >= `PERIPH_BASE && (addr) <= `PERIPH_END)
Expand Down
126 changes: 0 additions & 126 deletions rtl/instr_mem.v
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18 changes: 10 additions & 8 deletions rtl/riscv_cpu.v
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Original file line number Diff line number Diff line change
Expand Up @@ -23,7 +23,7 @@ module riscv_cpu (
wire [31:0] pc_inst0_out;
wire pc_inst0_j_signal;
wire [31:0] pc_inst0_jump;
wire stall_pipeline; // For load-use hazards
wire pipeline_stall; // For load-use hazards
// Branch handling: use EX stage jump signal/address
assign pc_inst0_j_signal = ex_inst0_jump_signal_out;
assign pc_inst0_jump = ex_inst0_jump_addr_out;
Expand All @@ -32,7 +32,7 @@ module riscv_cpu (
.rst(rst),
.j_signal(pc_inst0_j_signal),
.jump(pc_inst0_jump),
.stall(stall_pipeline), // Stall on load-use hazard
.stall(pipeline_stall), // Stall on load-use hazard
.out(pc_inst0_out)
);

Expand All @@ -46,12 +46,16 @@ module riscv_cpu (
wire branch_flush;
assign branch_flush = ex_inst0_jump_signal_out; // Flush IF/ID if branch taken
// If branch taken, flush IF/ID by setting instruction to 0 (NOP)
wire [31:0] instruction_to_if_id;
assign instruction_to_if_id = branch_flush ? 32'h00000013 : module_instr_in;
wire if_id_stall;
assign if_id_stall = pipeline_stall && !branch_flush;
IF_ID if_id_inst0 (
.clk(clk),
.rst(rst),
.pc_in(pc_inst0_out),
.instruction_in(branch_flush ? 32'h13 : module_instr_in),
.stall(stall_pipeline), // Stall on load-use hazard
.instruction_in(instruction_to_if_id),
.stall(if_id_stall),
.pc_out(if_id_pc_out),
.instruction_out(if_id_instr_out)
);
Expand Down Expand Up @@ -89,7 +93,7 @@ module riscv_cpu (
.instr_id_ex(id_ex_inst0_instr_id_out),
.rd_ex(id_ex_inst0_rd_addr_out),
.rd_valid_ex(id_ex_inst0_rd_valid_out),
.stall_pipeline(stall_pipeline)
.stall_pipeline(pipeline_stall)
);

// Instantiate Register File
Expand Down Expand Up @@ -151,7 +155,7 @@ module riscv_cpu (
.pc_in(if_id_pc_out),
.rs1_value_in(rf_inst0_rs1_value_out),
.rs2_value_in(rf_inst0_rs2_value_out),
.stall(pipeline_flush || stall_pipeline), // Use combined flush
.stall(pipeline_flush || pipeline_stall), // Use combined flush
.rs1_valid_out(id_ex_inst0_rs1_valid_out),
.rs2_valid_out(id_ex_inst0_rs2_valid_out),
.rd_valid_out(id_ex_inst0_rd_valid_out),
Expand Down Expand Up @@ -455,6 +459,4 @@ module riscv_cpu (
.wr_en_out(wb_inst0_wr_en_out)
);

// Write Back Stage

endmodule
59 changes: 31 additions & 28 deletions rtl/top.v
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Original file line number Diff line number Diff line change
Expand Up @@ -29,7 +29,6 @@ module top (
wire [31:0] data_mem_addr;
wire [3:0] cpu_write_byte_enable; // Write byte enables
wire [2:0] cpu_load_type; // Load type
wire [31:0] instr_read_data;

// Timer module wires
wire [31:0] timer_read_data;
Expand Down Expand Up @@ -57,16 +56,16 @@ module top (

// Multiplex read data based on address
assign mem_read_data = timer_access ? timer_read_data :
data_mem_access ? data_mem_read_data :
data_mem_access ? unified_mem_read_data :
uart_access ? uart_read_data :
instr_mem_access ? instr_read_data : 32'h00000000;
instr_mem_access ? unified_mem_read_data : 32'h00000000;

// Debug outputs
assign pc_debug = cpu_pc_out;
assign instr_debug = instr_to_cpu;

// Data memory read data (separate wire for clarity)
wire [31:0] data_mem_read_data;
wire [31:0] unified_mem_read_data;

// Instantiate the RISC-V CPU core
riscv_cpu cpu_inst (
Expand All @@ -87,33 +86,37 @@ module top (
.module_load_type(cpu_load_type)
);

// Instantiate instruction memory
instr_mem #(
.DATA_WIDTH(32),
.ADDR_WIDTH(32),
.MEM_SIZE(131072) // 512KB / 4 bytes = 128K words
) instr_mem_inst (
.instr_addr(cpu_pc_out),
.instr_addr_p2(data_mem_addr),
.load_type(cpu_load_type),
.instr(instr_to_cpu),
.instr_p2(instr_read_data)
);
// Address translation for unified memory
wire [31:0] instr_addr;
wire [31:0] data_addr;
wire data_we;
wire data_re;

// Instantiate data memory
data_mem #(
.DATA_WIDTH(32),
assign instr_addr = cpu_pc_out;
assign data_addr = instr_mem_access ? (data_mem_addr - `INSTR_MEM_BASE) :
(data_mem_addr - `DATA_MEM_BASE + `INSTR_MEM_SIZE);
assign data_we = cpu_mem_write_en && (data_mem_access || instr_mem_access);
assign data_re = cpu_mem_read_en && (data_mem_access || instr_mem_access);

// Unified memory size covers both instruction and data regions
localparam UNIFIED_MEM_SIZE = `INSTR_MEM_SIZE + `DATA_MEM_SIZE;

// Instantiate unified memory (parameterized like data_mem / instr_mem on main)
unified_memory #(
.ADDR_WIDTH(32),
.MEM_SIZE(1048576) // 1MB in bytes
) data_mem_inst (
.DATA_WIDTH(32),
.MEM_SIZE(UNIFIED_MEM_SIZE)
) unified_mem_inst (
.clk(clk),
.wr_en(cpu_mem_write_en && data_mem_access),
.rd_en(cpu_mem_read_en && data_mem_access),
.write_byte_enable(cpu_write_byte_enable),
.load_type(cpu_load_type),
.addr(data_mem_addr - `DATA_MEM_BASE),
.wr_data(cpu_mem_write_data),
.rd_data_out(data_mem_read_data)
.addr_instr(instr_addr),
.instr_out(instr_to_cpu),
.addr_data(data_addr),
.write_data(cpu_mem_write_data),
.read_data(unified_mem_read_data),
.write_enable(data_we),
.byte_enable(cpu_write_byte_enable),
.read_enable(data_re),
.load_type(cpu_load_type)
);

// Instantiate timer module
Expand Down
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