|
| 1 | +/* |
| 2 | + * Copyright (C) 2018 Eistec AB |
| 3 | + * |
| 4 | + * This file is subject to the terms and conditions of the GNU Lesser |
| 5 | + * General Public License v2.1. See the file LICENSE in the top level |
| 6 | + * directory for more details. |
| 7 | + * |
| 8 | + */ |
| 9 | + |
| 10 | +/** |
| 11 | + * @ingroup drivers_ds3234 |
| 12 | + * @{ |
| 13 | + * |
| 14 | + * @file |
| 15 | + * @brief Driver for the DS3234 Extremely Accurate SPI Bus RTC with |
| 16 | + * Integrated Crystal and SRAM, from Maxim |
| 17 | + * |
| 18 | + * @author Joakim Nohlgård <[email protected]> |
| 19 | + * @} |
| 20 | + */ |
| 21 | + |
| 22 | +#include <stdint.h> |
| 23 | +#include <errno.h> |
| 24 | +#include "ds3234.h" |
| 25 | +#include "ds3234_regs.h" |
| 26 | + |
| 27 | +#define ENABLE_DEBUG (0) |
| 28 | +#include "debug.h" |
| 29 | + |
| 30 | +/* SPI command byte parameters */ |
| 31 | +#define DS3234_CMD_READ (0x00) |
| 32 | +#define DS3234_CMD_WRITE (0x80) |
| 33 | + |
| 34 | + |
| 35 | +/** |
| 36 | + * @brief Read one or more registers from the sensor |
| 37 | + * |
| 38 | + * @param[in] dev device descriptor |
| 39 | + * @param[in] addr register address |
| 40 | + * @param[in] len number of bytes to read |
| 41 | + * @param[out] buf destination buffer |
| 42 | + */ |
| 43 | +static void ds3234_read_reg(const ds3234_params_t *dev, uint8_t addr, size_t len, uint8_t *buf) |
| 44 | +{ |
| 45 | + uint8_t command = DS3234_CMD_READ | addr; |
| 46 | + /* Acquire exclusive access to the bus. */ |
| 47 | + spi_acquire(dev->spi, dev->cs, SPI_MODE_3, dev->clk); |
| 48 | + /* Perform the transaction */ |
| 49 | + spi_transfer_regs(dev->spi, dev->cs, command, NULL, buf, len); |
| 50 | + /* Release the bus for other threads. */ |
| 51 | + spi_release(dev->spi); |
| 52 | +} |
| 53 | + |
| 54 | +/** |
| 55 | + * @brief Write a register value to the sensor |
| 56 | + * |
| 57 | + * @param[in] dev device descriptor |
| 58 | + * @param[in] addr register address |
| 59 | + * @param[in] len register size |
| 60 | + * @param[in] buf source buffer |
| 61 | + */ |
| 62 | +static void ds3234_write_reg(const ds3234_params_t *dev, uint8_t addr, size_t len, const uint8_t *buf) |
| 63 | +{ |
| 64 | + uint8_t command = DS3234_CMD_WRITE | addr; |
| 65 | + /* Acquire exclusive access to the bus. */ |
| 66 | + spi_acquire(dev->spi, dev->cs, SPI_MODE_3, dev->clk); |
| 67 | + /* Perform the transaction */ |
| 68 | + spi_transfer_regs(dev->spi, dev->cs, command, buf, NULL, len); |
| 69 | + /* Release the bus for other threads. */ |
| 70 | + spi_release(dev->spi); |
| 71 | +} |
| 72 | + |
| 73 | +int ds3234_pps_init(const ds3234_params_t *dev) |
| 74 | +{ |
| 75 | + /* initialize CS pin */ |
| 76 | + int res = spi_init_cs(dev->spi, dev->cs); |
| 77 | + if (res < 0) { |
| 78 | + return DS3234_NO_SPI; |
| 79 | + } |
| 80 | + DEBUG("ds3234: init on SPI_DEV(%u)\n", dev->spi); |
| 81 | + |
| 82 | + if (ENABLE_DEBUG) { |
| 83 | + for (int k = 0; k <= 0x19; ++k) { |
| 84 | + uint8_t dbg_reg = 0; |
| 85 | + ds3234_read_reg(dev, k, 1, &dbg_reg); |
| 86 | + DEBUG("%2x: %2x\n", k, dbg_reg); |
| 87 | + } |
| 88 | + } |
| 89 | + uint8_t reg = 0; |
| 90 | + ds3234_read_reg(dev, DS323X_REG_CONTROL, 1, ®); |
| 91 | + |
| 92 | + /* set reg to a non-zero known value to check if device is present */ |
| 93 | + reg |= DS323X_REG_CONTROL_RS1_MASK; |
| 94 | + |
| 95 | + ds3234_write_reg(dev, DS323X_REG_CONTROL, 1, ®); |
| 96 | + uint8_t readback = 0; |
| 97 | + ds3234_read_reg(dev, DS323X_REG_CONTROL, 1, &readback); |
| 98 | + if (reg != readback) { |
| 99 | + DEBUG("ds3234: readback mismatch: expected %u, actual %u\n", (unsigned)reg, (unsigned)readback); |
| 100 | + return DS3234_NO_DEV; |
| 101 | + } |
| 102 | + |
| 103 | + /* The control register is configured to: |
| 104 | + * - Enable the oscillator |
| 105 | + * - Enable an square wave output on the SQW pin |
| 106 | + * - Sets the square wave frequency to 1 Hz |
| 107 | + */ |
| 108 | + reg &= ~(DS323X_REG_CONTROL_EOSC_MASK | DS323X_REG_CONTROL_INTCN_MASK | |
| 109 | + DS323X_REG_CONTROL_RS1_MASK | DS323X_REG_CONTROL_RS2_MASK); |
| 110 | + ds3234_write_reg(dev, DS323X_REG_CONTROL, 1, ®); |
| 111 | + |
| 112 | + return DS3234_OK; |
| 113 | +} |
0 commit comments