[TRTLLM-9831][perf] Use TMA.RED to improve effective memory bandwidth

[sherry-1001]

Summary by CodeRabbit

Release Notes

• New Features

  • Added block reduction optimization path for GEMM kernel operations, enabling improved performance for certain computation scenarios.

• Refactor

  • Enhanced kernel implementation with block reduction support across multiple data types (BF16, FP32, FP16), including updated memory layout handling and epilogue processing.

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Description

The performance of REDG.128bit is highly sensitive to the data distribution—more precisely, to the address distribution and contention pattern. In contrast, UBLKRED/BLKRED consolidate many fine‑grained REDG operations into regular, coarse‑grained bulk accesses, making performance more stable with much smaller variance.
UBLKRED can gain 50% performance improvement in some cases, so we use UBLKRED defaultly for finalized fusion kernel

Test Coverage

TensorRT-LLM/tests/unittest/_torch/thop/parallel/test_cute_dsl_moe.py

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[coderabbitai]

📝 Walkthrough

Walkthrough

A block-reduction (blkred) code path is introduced to a GEMM kernel, controlled by a new use_blkred parameter. Changes include extended kernel signatures, epilogue logic for block-reduce operations, memory layout adjustments, and new block-reduce utility functions (bf16, fp16, fp32 variants).

Changes

Cohort / File(s)	Summary
Kernel Custom Ops Integration tensorrt_llm/_torch/custom_ops/cute_dsl_custom_ops.py	Enables use_blkred=True in GEMM kernel invocation within finalize fusion path.
Block-Reduction Kernel Implementation tensorrt_llm/_torch/cute_dsl_kernels/blackwell/blockscaled_contiguous_grouped_gemm_finalize_fusion.py	Introduces optional block-reduction path controlled by use_blkred parameter. Extends kernel __init__, _compute_stages, and _setup_attributes signatures. Adds epilogue shared-memory copy/partition logic (epilog_smem_copy_and_partition), conditional epilogue accumulation routing, block-reduce utility invocations, and updated memory layout handling for block-reduce (c_smem_layout_staged). Modifies SharedStorage to conditionally include shared C buffer.
Block-Reduction Utility Operators tensorrt_llm/_torch/cute_dsl_kernels/blackwell/utils.py	Introduces three new DSL user-op blocks: blk_reduce_bf16, blk_reduce_fp32, blk_reduce_fp16. Each wraps inline CUDA assembly with CP-reduce intrinsics for vectorized reduction across global and shared memory.

Estimated code review effort

🎯 3 (Moderate) | ⏱️ ~25 minutes

🚥 Pre-merge checks | ✅ 2 | ❌ 1

❌ Failed checks (1 warning)

Check name	Status	Explanation	Resolution
Docstring Coverage	⚠️ Warning	Docstring coverage is 61.54% which is insufficient. The required threshold is 80.00%.	Write docstrings for the functions missing them to satisfy the coverage threshold.

✅ Passed checks (2 passed)

Check name	Status	Explanation
Title check	✅ Passed	The title clearly summarizes the main change: using TMA.RED (UBLKRED/BLKRED) to improve effective memory bandwidth in the finalized fusion kernel.
Description check	✅ Passed	The description includes key sections: the problem (REDG.128bit sensitivity), the solution (UBLKRED/BLKRED), and test coverage. However, it lacks detailed explanation of what was changed and why the specific approach was chosen.

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✨ Finishing touches

• 📝 Generate docstrings

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[coderabbitai]

Actionable comments posted: 1

🤖 Fix all issues with AI agents

In
`@tensorrt_llm/_torch/cute_dsl_kernels/blackwell/blockscaled_contiguous_grouped_gemm_finalize_fusion.py`:
- Around line 538-547: The computed C shared-memory sizing in _compute_stages is
inconsistent with c_smem_layout_staged: instead of using swizzled_pad = 16 //
(out_dtype.width // 8) (which underestimates bytes for FP32), compute the staged
C stride using the same formula as c_smem_layout_staged (i.e., use
cta_tile_shape_mnk[1] + 8 for the C stage stride/width) and derive C bytes from
that stride and out_dtype.width; update _compute_stages and the other affected
locations (the blocks around where c_smem_layout_staged is used and the
occurrences you noted) to use cta_tile_shape_mnk[1] + 8 consistently so A/B
stage counts and SMEM capacity calculations match the layout and avoid
underestimation for FP32.

[kaiyux]

/bot run

[tensorrt-cicd]

PR_Github #33528 [ run ] triggered by Bot. Commit: 18de6bf

[tensorrt-cicd]

PR_Github #33528 [ run ] completed with state SUCCESS. Commit: 18de6bf
/LLM/main/L0_MergeRequest_PR pipeline #25864 completed with status: 'FAILURE'

⚠️ Action Required:

• Please check the failed tests and fix your PR
• If you cannot view the failures, ask the CI triggerer to share details
• Once fixed, request an NVIDIA team member to trigger CI again

[syuoni]

/bot run --disable-fail-fast

[tensorrt-cicd]

PR_Github #33612 [ run ] triggered by Bot. Commit: 18de6bf

[tensorrt-cicd]

PR_Github #33612 [ run ] completed with state SUCCESS. Commit: 18de6bf
/LLM/main/L0_MergeRequest_PR pipeline #25930 completed with status: 'FAILURE'

⚠️ Action Required:

• Please check the failed tests and fix your PR
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[sherry-1001]

/bot run --disable-fail-fast

[tensorrt-cicd]

PR_Github #33673 [ run ] triggered by Bot. Commit: 731d020

[tensorrt-cicd]

PR_Github #33673 [ run ] completed with state SUCCESS. Commit: 731d020
/LLM/main/L0_MergeRequest_PR pipeline #25977 completed with status: 'SUCCESS'