Multiple pin conflict fixes for AVR 644 and 1284 chips

[descipher]

Description

This PR addresses a pin conflict issue due to a removed flag for setting AVR_SS_PIN 4 on init and it now is always set high.
There are multiple pin conflicts with both ATMEGA644 and ATMEGA1284Ps. There is also a serious safety issue with the fact that it is set high in the HAL init for some boards with a heater on PIN 4.

Conflicted boards are:

ANET,ATMEGA1284P,FAN_PIN 4
AZTEEG,ATMEGA1284P,FAN_PIN 4
GEN3+,ATMEGA644,FAN_PIN 4
GEN6,ATMEGA644,E0_STEP_PIN 4
GEN7,ATMEGA644,HEATER_0_PIN 4
MELZI_ALL,ATMEGA1284P,FAN_PIN 4
OMCA,ATMEGA644,FAN_PIN 4
SANGUINOLOLU,ATMEGA1284P,FAN_PIN 4
SETHI,ATMEGA644,HEATER_0_PIN 4
STB,ATMEGA644,,FAN_PIN 4

Requirements

N/A

Benefits

Safety, proper pin init states.

Configurations

Any Atmega644 or Atmega1284P listed above.

Related Issues

#23418

[thinkyhead]

Looks like this PR was begun with an older commit. I have merged bugfix into it to reduce it only to the actual changes. I've left in a single difference, using the macros for the timer 0 case, which is on the one hand cosmetic, but also implies that the code would be more or less the same without treating timer 0 as a special case.

Also… Rebased and squashed.

[thinkyhead]

I can check the datasheet, but remind me why the q element in this timer is 0 (A) and not 1 (B)…

#ifdef TCCR0A
  case TIMER0B:   // Protected timer, but allow setting the duty cycle on OCR0B for pin D4 only
    return Timer({ { &TCCR0A, nullptr, nullptr }, { (uint16_t*)&OCR0B, nullptr, nullptr }, nullptr, 0, 0, true, true });
#endif

[descipher]

I can check the datasheet, but remind me why the q element in this timer is 0 (A) and not 1 (B)…

#ifdef TCCR0A
  case TIMER0B:   // Protected timer, but allow setting the duty cycle on OCR0B for pin D4 only
    return Timer({ { &TCCR0A, nullptr, nullptr }, { (uint16_t*)&OCR0B, nullptr, nullptr }, nullptr, 0, 0, true, true });
#endif

We only used the bool flags in the original code. The q was ignored.

[descipher]

Ok, some additional testing is in order, thanks for the review and sorry about the missed upstream sync.

[descipher]

Passed quality checks, full 2+ hour print performed.