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[Backport to 15] Add SPV_INTEL_16bit_atomics extension (#3424)
This continues #3343 and reflects specification update, including extension renaming. Specification: intel/llvm#20009
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13 files changed

+173
-25
lines changed

13 files changed

+173
-25
lines changed

‎include/LLVMSPIRVExtensions.inc‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -78,6 +78,6 @@ EXT(SPV_INTEL_bfloat16_arithmetic)
7878
EXT(SPV_INTEL_ternary_bitwise_function)
7979
EXT(SPV_INTEL_int4)
8080
EXT(SPV_INTEL_function_variants)
81-
EXT(SPV_INTEL_shader_atomic_bfloat16)
81+
EXT(SPV_INTEL_16bit_atomics)
8282
EXT(SPV_INTEL_predicated_io)
8383
EXT(SPV_INTEL_sigmoid)

‎lib/SPIRV/libSPIRV/SPIRVEnum.h‎

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -218,6 +218,16 @@ template <> inline void SPIRVMap<SPIRVCapabilityKind, SPIRVCapVec>::init() {
218218
{CapabilityInt4TypeINTEL, CapabilityCooperativeMatrixKHR});
219219
ADD_VEC_INIT(internal::CapabilityBFloat16ArithmeticINTEL,
220220
{CapabilityBFloat16TypeKHR});
221+
ADD_VEC_INIT(internal::CapabilityAtomicInt16CompareExchangeINTEL,
222+
{CapabilityInt16});
223+
ADD_VEC_INIT(internal::CapabilityInt16AtomicsINTEL,
224+
{internal::CapabilityAtomicInt16CompareExchangeINTEL});
225+
ADD_VEC_INIT(internal::CapabilityAtomicBFloat16LoadStoreINTEL,
226+
{CapabilityBFloat16TypeKHR});
227+
ADD_VEC_INIT(internal::CapabilityAtomicBFloat16AddINTEL,
228+
{CapabilityBFloat16TypeKHR});
229+
ADD_VEC_INIT(internal::CapabilityAtomicBFloat16MinMaxINTEL,
230+
{CapabilityBFloat16TypeKHR});
221231
}
222232

223233
template <> inline void SPIRVMap<SPIRVExecutionModelKind, SPIRVCapVec>::init() {

‎lib/SPIRV/libSPIRV/SPIRVInstruction.h‎

Lines changed: 34 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -2831,8 +2831,16 @@ class SPIRVAtomicInstBase : public SPIRVInstTemplateBase {
28312831
// Besides, OpAtomicCompareExchangeWeak, OpAtomicFlagTestAndSet and
28322832
// OpAtomicFlagClear instructions require the "kernel" capability. But this
28332833
// capability should be added by setting the OpenCL memory model.
2834-
if (hasType() && getType()->isTypeInt(64))
2835-
return {CapabilityInt64Atomics};
2834+
if (hasType()) {
2835+
if (getType()->isTypeInt(64))
2836+
return {CapabilityInt64Atomics};
2837+
if (getType()->isTypeInt(16) &&
2838+
Module->isAllowedToUseExtension(
2839+
ExtensionID::SPV_INTEL_16bit_atomics)) {
2840+
Module->addExtension(ExtensionID::SPV_INTEL_16bit_atomics);
2841+
return {internal::CapabilityInt16AtomicsINTEL};
2842+
}
2843+
}
28362844
return {};
28372845
}
28382846

@@ -2846,7 +2854,24 @@ class SPIRVAtomicInstBase : public SPIRVInstTemplateBase {
28462854
}
28472855
};
28482856

2849-
class SPIRVAtomicStoreInst : public SPIRVAtomicInstBase {
2857+
// This specialization will handle smaller set of compare-and-swap instructions
2858+
// that require only one capability. The instructions are: OpAtomicLoad,
2859+
// OpAtomicStore, OpAtomicExchange, OpAtomicCompareExchange and
2860+
// OpAtomicCompareExchangeWeak.
2861+
class SPIRVAtomicCompareExchangeInstructions : public SPIRVAtomicInstBase {
2862+
public:
2863+
SPIRVCapVec getRequiredCapability() const override {
2864+
if (hasType() && getType()->isTypeInt(16) &&
2865+
this->getModule()->isAllowedToUseExtension(
2866+
ExtensionID::SPV_INTEL_16bit_atomics)) {
2867+
Module->addExtension(ExtensionID::SPV_INTEL_16bit_atomics);
2868+
return {internal::CapabilityAtomicInt16CompareExchangeINTEL};
2869+
}
2870+
return SPIRVAtomicInstBase::getRequiredCapability();
2871+
}
2872+
};
2873+
2874+
class SPIRVAtomicStoreInst : public SPIRVAtomicCompareExchangeInstructions {
28502875
public:
28512876
// Overriding the following method because of 'const'-related
28522877
// issues with overriding getRequiredCapability(). TODO: Resolve.
@@ -2863,7 +2888,7 @@ class SPIRVAtomicFAddEXTInst : public SPIRVAtomicInstBase {
28632888
llvm::Optional<ExtensionID> getRequiredExtension() const override {
28642889
assert(hasType());
28652890
if (getType()->isTypeFloat(16, FPEncodingBFloat16KHR))
2866-
return ExtensionID::SPV_INTEL_shader_atomic_bfloat16;
2891+
Module->addExtension(ExtensionID::SPV_INTEL_16bit_atomics);
28672892
if (getType()->isTypeFloat(16))
28682893
return ExtensionID::SPV_EXT_shader_atomic_float16_add;
28692894
return ExtensionID::SPV_EXT_shader_atomic_float_add;
@@ -2888,7 +2913,7 @@ class SPIRVAtomicFMinMaxEXTBase : public SPIRVAtomicInstBase {
28882913
public:
28892914
llvm::Optional<ExtensionID> getRequiredExtension() const override {
28902915
if (getType()->isTypeFloat(16, FPEncodingBFloat16KHR))
2891-
return ExtensionID::SPV_INTEL_shader_atomic_bfloat16;
2916+
Module->addExtension(ExtensionID::SPV_INTEL_16bit_atomics);
28922917
return ExtensionID::SPV_EXT_shader_atomic_float_min_max;
28932918
}
28942919

@@ -2912,10 +2937,6 @@ class SPIRVAtomicFMinMaxEXTBase : public SPIRVAtomicInstBase {
29122937
// Atomic builtins
29132938
_SPIRV_OP(AtomicFlagTestAndSet, true, 6)
29142939
_SPIRV_OP(AtomicFlagClear, false, 4)
2915-
_SPIRV_OP(AtomicLoad, true, 6)
2916-
_SPIRV_OP(AtomicExchange, true, 7)
2917-
_SPIRV_OP(AtomicCompareExchange, true, 9)
2918-
_SPIRV_OP(AtomicCompareExchangeWeak, true, 9)
29192940
_SPIRV_OP(AtomicIIncrement, true, 6)
29202941
_SPIRV_OP(AtomicIDecrement, true, 6)
29212942
_SPIRV_OP(AtomicIAdd, true, 7)
@@ -2932,7 +2953,11 @@ _SPIRV_OP(MemoryBarrier, false, 3)
29322953
#define _SPIRV_OP(x, BaseClass, ...) \
29332954
typedef SPIRVInstTemplate<SPIRV##BaseClass, Op##x, __VA_ARGS__> SPIRV##x;
29342955
// Specialized atomic builtins
2956+
_SPIRV_OP(AtomicLoad, AtomicCompareExchangeInstructions, true, 6)
29352957
_SPIRV_OP(AtomicStore, AtomicStoreInst, false, 5)
2958+
_SPIRV_OP(AtomicExchange, AtomicCompareExchangeInstructions, true, 7)
2959+
_SPIRV_OP(AtomicCompareExchange, AtomicCompareExchangeInstructions, true, 9)
2960+
_SPIRV_OP(AtomicCompareExchangeWeak, AtomicCompareExchangeInstructions, true, 9)
29362961
_SPIRV_OP(AtomicFAddEXT, AtomicFAddEXTInst, true, 7)
29372962
_SPIRV_OP(AtomicFMinEXT, AtomicFMinMaxEXTBase, true, 7)
29382963
_SPIRV_OP(AtomicFMaxEXT, AtomicFMinMaxEXTBase, true, 7)

‎lib/SPIRV/libSPIRV/SPIRVNameMapEnum.h‎

Lines changed: 8 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -603,9 +603,6 @@ template <> inline void SPIRVMap<Capability, std::string>::init() {
603603
add(CapabilityLongCompositesINTEL, "LongCompositesINTEL");
604604
add(CapabilityOptNoneEXT, "OptNoneEXT");
605605
add(CapabilityAtomicFloat16AddEXT, "AtomicFloat16AddEXT");
606-
add(internal::CapabilityAtomicBFloat16AddINTEL, "AtomicBFloat16AddINTEL");
607-
add(internal::CapabilityAtomicBFloat16MinMaxINTEL,
608-
"AtomicBFloat16MinMaxINTEL");
609606
add(CapabilityDebugInfoModuleINTEL, "DebugInfoModuleINTEL");
610607
add(CapabilitySplitBarrierINTEL, "SplitBarrierINTEL");
611608
add(CapabilityGlobalVariableFPGADecorationsINTEL,
@@ -657,6 +654,14 @@ template <> inline void SPIRVMap<Capability, std::string>::init() {
657654
add(internal::CapabilityBFloat16ArithmeticINTEL, "BFloat16ArithmeticINTEL");
658655
add(internal::CapabilityPredicatedIOINTEL, "PredicatedIOINTEL");
659656
add(internal::CapabilitySigmoidINTEL, "SigmoidINTEL");
657+
add(internal::CapabilityAtomicBFloat16AddINTEL, "AtomicBFloat16AddINTEL");
658+
add(internal::CapabilityAtomicBFloat16MinMaxINTEL,
659+
"AtomicBFloat16MinMaxINTEL");
660+
add(internal::CapabilityAtomicInt16CompareExchangeINTEL,
661+
"AtomicInt16CompareExchangeINTEL");
662+
add(internal::CapabilityInt16AtomicsINTEL, "Int16AtomicsINTEL");
663+
add(internal::CapabilityAtomicBFloat16LoadStoreINTEL,
664+
"AtomicBFloat16LoadStoreINTEL");
660665
}
661666
SPIRV_DEF_NAMEMAP(Capability, SPIRVCapabilityNameMap)
662667

‎lib/SPIRV/libSPIRV/spirv_internal.hpp‎

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -117,6 +117,9 @@ enum InternalCapability {
117117
ICapabilityAtomicBFloat16AddINTEL = 6255,
118118
ICapabilityAtomicBFloat16MinMaxINTEL = 6256,
119119
ICapabilityPredicatedIOINTEL = 6257,
120+
ICapabilityAtomicInt16CompareExchangeINTEL = 6260,
121+
ICapabilityInt16AtomicsINTEL = 6261,
122+
ICapabilityAtomicBFloat16LoadStoreINTEL = 6262,
120123
ICapabilityCooperativeMatrixPrefetchINTEL = 6411,
121124
ICapabilityComplexFloatMulDivINTEL = 6414,
122125
ICapabilityTensorFloat32RoundingINTEL = 6425,
@@ -278,6 +281,12 @@ constexpr Capability CapabilityGlobalVariableDecorationsINTEL =
278281
static_cast<Capability>(ICapGlobalVariableDecorationsINTEL);
279282
constexpr Capability CapabilityBFloat16ArithmeticINTEL =
280283
static_cast<Capability>(ICapabilityBFloat16ArithmeticINTEL);
284+
constexpr Capability CapabilityAtomicInt16CompareExchangeINTEL =
285+
static_cast<Capability>(ICapabilityAtomicInt16CompareExchangeINTEL);
286+
constexpr Capability CapabilityInt16AtomicsINTEL =
287+
static_cast<Capability>(ICapabilityInt16AtomicsINTEL);
288+
constexpr Capability CapabilityAtomicBFloat16LoadStoreINTEL =
289+
static_cast<Capability>(ICapabilityAtomicBFloat16LoadStoreINTEL);
281290

282291
constexpr Decoration DecorationMathOpDSPModeINTEL =
283292
static_cast<Decoration>(IDecMathOpDSPModeINTEL);

test/extensions/INTEL/SPV_INTEL_shader_atomic_bfloat16/AtomicFAddEXT.ll renamed to test/extensions/INTEL/SPV_INTEL_16bit_atomics/AtomicFAddEXT.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
; RUN: llvm-as %s -o %t.bc
2-
; RUN: llvm-spirv %t.bc --spirv-ext=+SPV_INTEL_shader_atomic_bfloat16,+SPV_KHR_bfloat16 -o %t.spv
2+
; RUN: llvm-spirv %t.bc --spirv-ext=+SPV_INTEL_16bit_atomics,+SPV_KHR_bfloat16,+SPV_EXT_shader_atomic_float_add -o %t.spv
33
; RUN: llvm-spirv -to-text %t.spv -o %t.spt
44
; RUN: FileCheck < %t.spt %s --check-prefix=CHECK-SPIRV
55

@@ -11,7 +11,7 @@ target triple = "spir64-unknown-unknown"
1111

1212
; CHECK-SPIRV-DAG: Capability AtomicBFloat16AddINTEL
1313
; CHECK-SPIRV-DAG: Capability BFloat16TypeKHR
14-
; CHECK-SPIRV-DAG: Extension "SPV_INTEL_shader_atomic_bfloat16"
14+
; CHECK-SPIRV-DAG: Extension "SPV_INTEL_16bit_atomics"
1515
; CHECK-SPIRV-DAG: Extension "SPV_KHR_bfloat16"
1616

1717
; CHECK-SPIRV: TypeFloat [[BFLOAT:[0-9]+]] 16 0

test/extensions/INTEL/SPV_INTEL_shader_atomic_bfloat16/AtomicFMaxEXT.ll renamed to test/extensions/INTEL/SPV_INTEL_16bit_atomics/AtomicFMaxEXT.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
; RUN: llvm-as %s -o %t.bc
2-
; RUN: llvm-spirv %t.bc --spirv-ext=+SPV_INTEL_shader_atomic_bfloat16,+SPV_KHR_bfloat16 -o %t.spv
2+
; RUN: llvm-spirv %t.bc --spirv-ext=+SPV_INTEL_16bit_atomics,+SPV_KHR_bfloat16,+SPV_EXT_shader_atomic_float_min_max -o %t.spv
33
; RUN: llvm-spirv -to-text %t.spv -o %t.spt
44
; RUN: FileCheck < %t.spt %s --check-prefix=CHECK-SPIRV
55

@@ -11,7 +11,7 @@ target triple = "spir64-unknown-unknown"
1111

1212
; CHECK-SPIRV-DAG: Capability AtomicBFloat16MinMaxINTEL
1313
; CHECK-SPIRV-DAG: Capability BFloat16TypeKHR
14-
; CHECK-SPIRV-DAG: Extension "SPV_INTEL_shader_atomic_bfloat16"
14+
; CHECK-SPIRV-DAG: Extension "SPV_INTEL_16bit_atomics"
1515
; CHECK-SPIRV-DAG: Extension "SPV_KHR_bfloat16"
1616

1717
; CHECK-SPIRV: TypeFloat [[BFLOAT:[0-9]+]] 16 0

test/extensions/INTEL/SPV_INTEL_shader_atomic_bfloat16/AtomicFMinEXT.ll renamed to test/extensions/INTEL/SPV_INTEL_16bit_atomics/AtomicFMinEXT.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
; RUN: llvm-as %s -o %t.bc
2-
; RUN: llvm-spirv %t.bc --spirv-ext=+SPV_INTEL_shader_atomic_bfloat16,+SPV_KHR_bfloat16 -o %t.spv
2+
; RUN: llvm-spirv %t.bc --spirv-ext=+SPV_INTEL_16bit_atomics,+SPV_KHR_bfloat16,+SPV_EXT_shader_atomic_float_min_max -o %t.spv
33
; RUN: llvm-spirv -to-text %t.spv -o %t.spt
44
; RUN: FileCheck < %t.spt %s --check-prefix=CHECK-SPIRV
55

@@ -11,7 +11,7 @@ target triple = "spir64-unknown-unknown"
1111

1212
; CHECK-SPIRV-DAG: Capability AtomicBFloat16MinMaxINTEL
1313
; CHECK-SPIRV-DAG: Capability BFloat16TypeKHR
14-
; CHECK-SPIRV-DAG: Extension "SPV_INTEL_shader_atomic_bfloat16"
14+
; CHECK-SPIRV-DAG: Extension "SPV_INTEL_16bit_atomics"
1515
; CHECK-SPIRV-DAG: Extension "SPV_KHR_bfloat16"
1616

1717
; CHECK-SPIRV: TypeFloat [[BFLOAT:[0-9]+]] 16 0

‎test/extensions/INTEL/SPV_INTEL_16bit_atomics/AtomicInt16CompareExchangeCapability.ll‎

Lines changed: 55 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,55 @@
1+
; RUN: llvm-as %s -o %t.bc
2+
; RUN: llvm-spirv %t.bc -o %t.spv --spirv-ext=+SPV_INTEL_16bit_atomics
3+
; RUN: llvm-spirv -to-text %t.spv -o %t.spt
4+
; RUN: FileCheck < %t.spt %s --check-prefix=CHECK-SPIRV
5+
6+
; RUN: llvm-spirv -r --spirv-target-env=CL2.0 %t.spv -o %t.rev.bc
7+
; RUN: llvm-dis %t.rev.bc
8+
; RUN: FileCheck < %t.rev.ll %s --check-prefixes=CHECK-LLVM
9+
10+
; Check that without extension we don't use its capabilities - there is no
11+
; limitation on using i16 with atomic instruction in the core specification.
12+
; RUN: llvm-spirv %t.bc -o %t.noext.spv
13+
; RUN: spirv-val %t.noext.spv
14+
; RUN: llvm-spirv -to-text %t.noext.spv -o %t.noext.spt
15+
; RUN: FileCheck < %t.noext.spt %s --check-prefix=CHECK-SPIRV-NOEXT
16+
17+
; CHECK-SPIRV: Capability Int16
18+
; CHECK-SPIRV: Capability AtomicInt16CompareExchangeINTEL
19+
; CHECK-SPIRV-NOT: Capability Int16AtomicsINTEL
20+
; CHECK-SPIRV: Extension "SPV_INTEL_16bit_atomics"
21+
22+
; CHECK-SPIRV-NOEXT: Capability Int16
23+
; CHECK-SPIRV-NOEXT-NOT: Capability AtomicInt16CompareExchangeINTEL
24+
; CHECK-SPIRV-NOEXT-NOT: Capability Int16AtomicsINTEL
25+
; CHECK-SPIRV-NOEXT-NOT: Extension "SPV_INTEL_16bit_atomics"
26+
27+
; CHECK-SPIRV-DAG: Constant [[#]] [[#DeviceScope:]] 1
28+
; CHECK-SPIRV-DAG: Constant [[#]] [[#Release:]] 4
29+
; CHECK-SPIRV-DAG: Constant [[#]] [[#SequentiallyConsistent:]] 16
30+
; CHECK-SPIRV-DAG: Constant [[#]] [[#Acquire:]] 2
31+
32+
; CHECK-LLVM: call spir_func void @_Z21atomic_store_explicitPU3AS4VU7_Atomicss12memory_order12memory_scope
33+
; CHECK-LLVM: call spir_func i16 @_Z20atomic_load_explicitPU3AS4VU7_Atomics12memory_order12memory_scope
34+
; CHECK-LLVM: call spir_func i16 @_Z24atomic_exchange_explicitPU3AS4VU7_Atomicss12memory_order12memory_scope
35+
; CHECK-LLVM: call spir_func i1 @_Z39atomic_compare_exchange_strong_explicitPU3AS4VU7_AtomicsPU3AS4ss12memory_orderS4_12memory_scope
36+
37+
target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024"
38+
target triple = "spir64"
39+
40+
@ui = common dso_local addrspace(1) global i16 0, align 4
41+
; Function Attrs: nounwind
42+
define dso_local spir_func void @test() {
43+
entry:
44+
; CHECK-SPIRV: Variable [[#]] [[#PTR:]] 7
45+
%0 = alloca i16
46+
; CHECK-SPIRV: AtomicStore [[#PTR]] [[#DeviceScope]] [[#Release]] [[#]]
47+
store atomic i16 0, ptr %0 release, align 4
48+
; CHECK-SPIRV: AtomicLoad [[#]] [[#]] [[#PTR]] [[#DeviceScope]] [[#Acquire]]
49+
%1 = load atomic i16, ptr %0 acquire, align 4
50+
; CHECK-SPIRV: AtomicExchange [[#]] [[#]] [[#]] [[#DeviceScope]] [[#]] {{.+}}
51+
%2 = atomicrmw xchg ptr addrspace(1) @ui, i16 42 acq_rel
52+
; CHECK-SPIRV: AtomicCompareExchange [[#]] [[#]] [[#]] [[#DeviceScope]] [[#SequentiallyConsistent]] [[#Acquire]] {{.+}}
53+
%3 = cmpxchg ptr %0, i16 128, i16 456 seq_cst acquire
54+
ret void
55+
}

‎test/extensions/INTEL/SPV_INTEL_16bit_atomics/Int16AtomicsINTEL.ll‎

Lines changed: 44 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,44 @@
1+
; RUN: llvm-as %s -o %t.bc
2+
; RUN: llvm-spirv %t.bc -o %t.spv --spirv-ext=+SPV_INTEL_16bit_atomics
3+
; RUN: llvm-spirv -to-text %t.spv -o %t.spt
4+
; RUN: FileCheck < %t.spt %s --check-prefix=CHECK-SPIRV
5+
6+
; RUN: llvm-spirv -r --spirv-target-env=CL2.0 %t.spv -o %t.rev.bc
7+
; RUN: llvm-dis %t.rev.bc
8+
; RUN: FileCheck < %t.rev.ll %s --check-prefixes=CHECK-LLVM
9+
10+
; RUN: llvm-spirv -r --spirv-target-env="SPV-IR" %t.spv -o %t.rev.bc
11+
; RUN: llvm-dis %t.rev.bc
12+
; RUN: FileCheck < %t.rev.ll %s --check-prefixes=CHECK-LLVM-SPV-IR
13+
14+
; Check that without extension we don't use its capabilities - there is no
15+
; limitation on using i16 with atomic instruction in the core specification.
16+
; RUN: llvm-spirv %t.bc -o %t.noext.spv
17+
; RUN: spirv-val %t.noext.spv
18+
; RUN: llvm-spirv -to-text %t.noext.spv -o %t.noext.spt
19+
; RUN: FileCheck < %t.noext.spt %s --check-prefix=CHECK-SPIRV-NOEXT
20+
21+
; CHECK-SPIRV: Capability Int16
22+
; CHECK-SPIRV: Capability AtomicInt16CompareExchangeINTEL
23+
; CHECK-SPIRV: Capability Int16AtomicsINTEL
24+
; CHECK-SPIRV: Extension "SPV_INTEL_16bit_atomics"
25+
; CHECK-SPIRV: AtomicOr
26+
27+
; CHECK-SPIRV-NOEXT: Capability Int16
28+
; CHECK-SPIRV-NOEXT-NOT: Capability AtomicInt16CompareExchangeINTEL
29+
; CHECK-SPIRV-NOEXT-NOT: Capability Int16AtomicsINTEL
30+
; CHECK-SPIRV-NOEXT-NOT: Extension "SPV_INTEL_16bit_atomics"
31+
32+
; CHECK-LLVM: call spir_func i16 @_Z24atomic_fetch_or_explicitPU3AS4VU7_Atomicss12memory_order12memory_scope
33+
; CHECK-LLVM-SPV-IR: call spir_func i16 @_Z16__spirv_AtomicOrPU3AS1siis
34+
35+
target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024"
36+
target triple = "spir64"
37+
38+
@ui = common dso_local addrspace(1) global i16 0, align 4
39+
40+
define dso_local spir_func void @test() {
41+
entry:
42+
%0 = atomicrmw or ptr addrspace(1) @ui, i16 42 release
43+
ret void
44+
}

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