Bump LLVM version to 6.0.0

deps/Versions.make

@@ -1,4 +1,4 @@
-LLVM_VER = 3.9.1
+LLVM_VER = 6.0.0
 PCRE_VER = 10.30
 DSFMT_VER = 2.2.3
 LAPACK_VER = 3.5.0

deps/checksums/cfe-6.0.0.src.tar.xz/md5

@@ -0,0 +1 @@
+121b3896cb0c7765d690acc5d9495d24

deps/checksums/cfe-6.0.0.src.tar.xz/sha512

@@ -0,0 +1 @@
+e886dd27448503bbfc7fd4f68eb089c19b2f2be4f0e5b26d3df253833f60b91d70b472a6b530063386e2252075b110ce9f5942800feddf6c34b94a75cf7bd5c6

deps/checksums/compiler-rt-6.0.0.src.tar.xz/md5

@@ -0,0 +1 @@
+ba6368e894b5528e527d86a69d8533c6

deps/checksums/compiler-rt-6.0.0.src.tar.xz/sha512

@@ -0,0 +1 @@
+717bed116ef43ebb2e18daf6fb737472edf57564947f53fe6368d3bbb080f63e986c0d1b94dbd087be998196ad7be54f4361854f8eb5214600b82449ba02c9c1

deps/checksums/llvm-6.0.0.src.tar.xz/md5

@@ -0,0 +1 @@
+788a11a35fa62eb008019b37187d09d2

deps/checksums/llvm-6.0.0.src.tar.xz/sha512

@@ -0,0 +1 @@
+a71fdd5ddc46f01327ad891cfcc198febdbe10769c57f14d8a4fb7d514621ee4080e1a641200d3353c16a16731d390270499ec6cd3dc98fadc570f3eb6b52b8c

deps/llvm.mk

@@ -511,9 +511,20 @@ $(eval $(call LLVM_PATCH,llvm-D34078-vectorize-fdiv))
 $(eval $(call LLVM_PATCH,llvm-5.0-NVPTX-addrspaces)) # NVPTX
 $(eval $(call LLVM_PATCH,llvm-4.0.0-D37576-NVPTX-sm_70)) # NVPTX, Remove for 6.0
 $(eval $(call LLVM_PATCH,llvm-D38765-gvn_5.0)) # Remove for 6.0
-$(eval $(call LLVM_PATCH,llvm-D42262-jumpthreading-not-i1))
+$(eval $(call LLVM_PATCH,llvm-D42262-jumpthreading-not-i1)) # remove for 7.0
 $(eval $(call LLVM_PATCH,llvm-PPC-addrspaces)) # PPC
 $(eval $(call LLVM_PATCH,llvm-PR36292-5.0)) # PPC fixes #26249, remove for 6.0
+else ifeq ($(LLVM_VER_SHORT),6.0)
+$(eval $(call LLVM_PATCH,llvm-D27629-AArch64-large_model_4.0))
+$(eval $(call LLVM_PATCH,llvm-D34078-vectorize-fdiv))
+$(eval $(call LLVM_PATCH,llvm-6.0-NVPTX-addrspaces)) # NVPTX
+$(eval $(call LLVM_PATCH,llvm-D42262-jumpthreading-not-i1)) # remove for 7.0
+$(eval $(call LLVM_PATCH,llvm-PPC-addrspaces)) # remove for 7.0
+$(eval $(call LLVM_PATCH,llvm-D42260)) # remove for 7.0 (probably)
+$(eval $(call LLVM_PATCH,llvm-rL326843-missing-header)) # remove for 7.0
+$(eval $(call LLVM_PATCH,llvm-6.0-r327540)) # remove for 7.0
+$(eval $(call LLVM_PATCH,llvm-6.0.0_D27296-libssp)) # remove for 7.0
+$(eval $(call LLVM_PATCH,llvm-6.0-D44650))
 endif # LLVM_VER
 
 # Remove hardcoded OS X requirements in compilter-rt cmake build

deps/patches/llvm-6.0-D44650.patch

@@ -0,0 +1,13 @@
+Index: tools/llvm-cfi-verify/CMakeLists.txt
+===================================================================
+--- a/tools/llvm-cfi-verify/CMakeLists.txt
++++ b/tools/llvm-cfi-verify/CMakeLists.txt
+@@ -11,7 +11,7 @@
+   Symbolize
+   )
+
+-add_llvm_tool(llvm-cfi-verify
++add_llvm_tool(llvm-cfi-verify DISABLE_LLVM_LINK_LLVM_DYLIB
+   llvm-cfi-verify.cpp)
+
+ add_subdirectory(lib)

deps/patches/llvm-6.0-NVPTX-addrspaces.patch

@@ -0,0 +1,32 @@
+diff --git a/lib/Target/NVPTX/NVPTXISelLowering.cpp b/lib/Target/NVPTX/NVPTXISelLowering.cpp
+index f1e4251a44b..73d49f5d7e4 100644
+--- a/lib/Target/NVPTX/NVPTXISelLowering.cpp
++++ b/lib/Target/NVPTX/NVPTXISelLowering.cpp
+@@ -1248,6 +1248,14 @@ SDValue NVPTXTargetLowering::getSqrtEstimate(SDValue Operand, SelectionDAG &DAG,
+   }
+ }
+
++bool NVPTXTargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
++                                               unsigned DestAS) const {
++  assert(SrcAS != DestAS && "Expected different address spaces!");
++
++  return (SrcAS  == ADDRESS_SPACE_GENERIC || SrcAS  > ADDRESS_SPACE_LOCAL) &&
++         (DestAS == ADDRESS_SPACE_GENERIC || DestAS > ADDRESS_SPACE_LOCAL);
++}
++
+ SDValue
+ NVPTXTargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
+   SDLoc dl(Op);
+diff --git a/lib/Target/NVPTX/NVPTXISelLowering.h b/lib/Target/NVPTX/NVPTXISelLowering.h
+index ef04a8573d4..68a9a7195c4 100644
+--- a/lib/Target/NVPTX/NVPTXISelLowering.h
++++ b/lib/Target/NVPTX/NVPTXISelLowering.h
+@@ -443,6 +443,8 @@ public:
+                                const NVPTXSubtarget &STI);
+   SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
+
++  bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override;
++
+   SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
+
+   const char *getTargetNodeName(unsigned Opcode) const override;

deps/patches/llvm-6.0-r327540.patch

@@ -0,0 +1,79 @@
+From 2671f80b2d151c9a87a4a93860f8a6b98db57aad Mon Sep 17 00:00:00 2001
+From: Craig Topper <[email protected]>
+Date: Wed, 14 Mar 2018 17:57:19 +0000
+Subject: [PATCH] [X86] Add back fast-isel code for handling i8 shifts.
+
+I removed this in r316797 because the coverage report showed no coverage and I thought it should have been handled by the auto generated table. I now see that there is code that bypasses the table if the shift amount is out of bounds.
+
+This adds back the code. We'll codegen out of bounds i8 shifts to effectively (amount & 0x1f). The 0x1f is a strange quirk of x86 that shift amounts are always masked to 5-bits(except 64-bits). So if the masked value is still out bounds the result will be 0.
+
+Fixes PR36731.
+
+git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327540 91177308-0d34-0410-b5e6-96231b3b80d8
+---
+ lib/Target/X86/X86FastISel.cpp      | 21 ++++++++++++++-------
+ test/CodeGen/X86/fast-isel-shift.ll | 12 ++++++++++++
+ 2 files changed, 26 insertions(+), 7 deletions(-)
+
+diff --git a/lib/Target/X86/X86FastISel.cpp b/lib/Target/X86/X86FastISel.cpp
+index 7e88304ae19..943022585a1 100644
+--- a/lib/Target/X86/X86FastISel.cpp
++++ b/lib/Target/X86/X86FastISel.cpp
+@@ -1789,9 +1789,16 @@ bool X86FastISel::X86SelectBranch(const Instruction *I) {
+ bool X86FastISel::X86SelectShift(const Instruction *I) {
+   unsigned CReg = 0, OpReg = 0;
+   const TargetRegisterClass *RC = nullptr;
+-  assert(!I->getType()->isIntegerTy(8) &&
+-         "i8 shifts should be handled by autogenerated table");
+-  if (I->getType()->isIntegerTy(16)) {
++  if (I->getType()->isIntegerTy(8)) {
++    CReg = X86::CL;
++    RC = &X86::GR8RegClass;
++    switch (I->getOpcode()) {
++    case Instruction::LShr: OpReg = X86::SHR8rCL; break;
++    case Instruction::AShr: OpReg = X86::SAR8rCL; break;
++    case Instruction::Shl:  OpReg = X86::SHL8rCL; break;
++    default: return false;
++    }
++  } else if (I->getType()->isIntegerTy(16)) {
+     CReg = X86::CX;
+     RC = &X86::GR16RegClass;
+     switch (I->getOpcode()) {
+@@ -1836,10 +1843,10 @@ bool X86FastISel::X86SelectShift(const Instruction *I) {
+
+   // The shift instruction uses X86::CL. If we defined a super-register
+   // of X86::CL, emit a subreg KILL to precisely describe what we're doing here.
+-  assert(CReg != X86::CL && "CReg should be a super register of CL");
+-  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
+-          TII.get(TargetOpcode::KILL), X86::CL)
+-    .addReg(CReg, RegState::Kill);
++  if (CReg != X86::CL)
++    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
++            TII.get(TargetOpcode::KILL), X86::CL)
++      .addReg(CReg, RegState::Kill);
+
+   unsigned ResultReg = createResultReg(RC);
+   BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(OpReg), ResultReg)
+diff --git a/test/CodeGen/X86/fast-isel-shift.ll b/test/CodeGen/X86/fast-isel-shift.ll
+index 3699b7ba4bf..4dc56f351f5 100644
+--- a/test/CodeGen/X86/fast-isel-shift.ll
++++ b/test/CodeGen/X86/fast-isel-shift.ll
+@@ -381,3 +381,15 @@ define i64 @ashr_imm4_i64(i64 %a) {
+   %c = ashr i64 %a, 4
+   ret i64 %c
+ }
++
++; Make sure we don't crash on out of bounds i8 shifts.
++define i8 @PR36731(i8 %a) {
++; CHECK-LABEL: PR36731:
++; CHECK:       ## %bb.0:
++; CHECK-NEXT:    movb $255, %cl
++; CHECK-NEXT:    shlb %cl, %dil
++; CHECK-NEXT:    movl %edi, %eax
++; CHECK-NEXT:    retq
++  %b = shl i8 %a, -1
++  ret i8 %b
++}
+-- 
+2.16.2
+

deps/patches/llvm-6.0.0_D27296-libssp.patch

@@ -0,0 +1,35 @@
+Index: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
+===================================================================
+--- a/lib/Target/X86/X86ISelLowering.cpp
++++ b/lib/Target/X86/X86ISelLowering.cpp
+@@ -2098,7 +2098,8 @@
+
+ void X86TargetLowering::insertSSPDeclarations(Module &M) const {
+   // MSVC CRT provides functionalities for stack protection.
+-  if (Subtarget.getTargetTriple().isOSMSVCRT()) {
++  if (Subtarget.getTargetTriple().isWindowsMSVCEnvironment() ||
++      Subtarget.getTargetTriple().isWindowsItaniumEnvironment()) {
+     // MSVC CRT has a global variable holding security cookie.
+     M.getOrInsertGlobal("__security_cookie",
+                         Type::getInt8PtrTy(M.getContext()));
+@@ -2120,15 +2121,19 @@
+
+ Value *X86TargetLowering::getSDagStackGuard(const Module &M) const {
+   // MSVC CRT has a global variable holding security cookie.
+-  if (Subtarget.getTargetTriple().isOSMSVCRT())
++  if (Subtarget.getTargetTriple().isWindowsMSVCEnvironment() ||
++      Subtarget.getTargetTriple().isWindowsItaniumEnvironment()) {
+     return M.getGlobalVariable("__security_cookie");
++  }
+   return TargetLowering::getSDagStackGuard(M);
+ }
+
+ Value *X86TargetLowering::getSSPStackGuardCheck(const Module &M) const {
+   // MSVC CRT has a function to validate security cookie.
+-  if (Subtarget.getTargetTriple().isOSMSVCRT())
++  if (Subtarget.getTargetTriple().isWindowsMSVCEnvironment() ||
++      Subtarget.getTargetTriple().isWindowsItaniumEnvironment()) {
+     return M.getFunction("__security_check_cookie");
++  }
+   return TargetLowering::getSSPStackGuardCheck(M);
+ }

deps/patches/llvm-D42260.patch

@@ -0,0 +1,161 @@
+From affdc737e799481828ec327d9ee7ead64bdb7ba2 Mon Sep 17 00:00:00 2001
+From: Keno Fischer <[email protected]>
+Date: Sat, 10 Mar 2018 17:24:31 -0500
+Subject: [PATCH] [JumpThreading] Don't select an edge that we know we can't
+ thread
+
+Summary:
+In r312664 (D36404), JumpThreading stopped threading edges into
+loop headers. Unfortunately, I observed a significant performance
+regression as a result of this change. Upon further investigation,
+the problematic pattern looked something like this (after
+many high level optimizations):
+
+```
+while (true) {
+    bool cond = ...;
+    if (!cond) {
+        <body>
+    }
+    if (cond)
+        break;
+}
+```
+
+Now, naturally we want jump threading to essentially eliminate the
+second if check and hook up the edges appropriately. However, the
+above mentioned change, prevented it from doing this because it would
+have to thread an edge into the loop header.
+
+Upon further investigation, what is happening is that since both branches
+are threadable, JumpThreading picks one of them at arbitrarily. In my
+case, because of the way that the IR ended up, it tended to pick
+the one to the loop header, bailing out immediately after. However,
+if it had picked the one to the exit block, everything would have
+worked out fine (because the only remaining branch would then be folded,
+not thraded which is acceptable).
+
+Thus, to fix this problem, we can simply eliminate loop headers from
+consideration as possible threading targets earlier, to make sure that
+if there are multiple eligible branches, we can still thread one of
+the ones that don't target a loop header.
+
+Reviewers: hfinkel, kparzysz, haicheng, bmakam
+
+Subscribers: vchuravy, brzycki, mcrosier, llvm-commits
+
+Differential Revision: https://reviews.llvm.org/D42260
+---
+ lib/Transforms/Scalar/JumpThreading.cpp      | 15 +++++-
+ test/Transforms/JumpThreading/header-succ.ll | 72 ++++++++++++++++++++++++++++
+ 2 files changed, 86 insertions(+), 1 deletion(-)
+ create mode 100644 test/Transforms/JumpThreading/header-succ.ll
+
+diff --git a/lib/Transforms/Scalar/JumpThreading.cpp b/lib/Transforms/Scalar/JumpThreading.cpp
+index 141c9938bf8..ccca37ce116 100644
+--- a/lib/Transforms/Scalar/JumpThreading.cpp
++++ b/lib/Transforms/Scalar/JumpThreading.cpp
+@@ -1629,8 +1629,21 @@ bool JumpThreadingPass::ProcessThreadableEdges(Value *Cond, BasicBlock *BB,
+   // threadable destination (the common case) we can avoid this.
+   BasicBlock *MostPopularDest = OnlyDest;
+
+-  if (MostPopularDest == MultipleDestSentinel)
++  if (MostPopularDest == MultipleDestSentinel) {
++    // Remove any loop headers from the Dest list, ThreadEdge conservatively
++    // won't process them, but we might have other destination that are eligible
++    // and we still want to process.
++    erase_if(PredToDestList,
++             [&](const std::pair<BasicBlock *, BasicBlock *> &PredToDest) {
++               return LoopHeaders.count(PredToDest.second) != 0;
++             });
++
++    if (PredToDestList.empty()) {
++      return false;
++    }
++
+     MostPopularDest = FindMostPopularDest(BB, PredToDestList);
++  }
+
+   // Now that we know what the most popular destination is, factor all
+   // predecessors that will jump to it into a single predecessor.
+diff --git a/test/Transforms/JumpThreading/header-succ.ll b/test/Transforms/JumpThreading/header-succ.ll
+new file mode 100644
+index 00000000000..1e65e737d4a
+--- /dev/null
++++ b/test/Transforms/JumpThreading/header-succ.ll
+@@ -0,0 +1,72 @@
++; RUN: opt -S -jump-threading < %s | FileCheck %s
++
++; Check that the heuristic for avoiding accidental introduction of irreducible
++; loops doesn't also prevent us from threading simple constructs where this
++; isn't a problem.
++
++declare void @opaque_body()
++
++define void @jump_threading_loopheader() {
++; CHECK-LABEL: @jump_threading_loopheader
++top:
++    br label %entry
++
++entry:
++    %ind = phi i32 [0, %top], [%nextind, %latch]
++    %nextind = add i32 %ind, 1
++    %cmp = icmp ule i32 %ind, 10
++; CHECK: br i1 %cmp, label %latch, label %exit
++    br i1 %cmp, label %body, label %latch
++
++body:
++    call void @opaque_body()
++; CHECK: br label %entry
++    br label %latch
++
++latch:
++    %cond = phi i2 [1, %entry], [2, %body]
++    switch i2 %cond, label %unreach [
++        i2 2, label %entry
++        i2 1, label %exit
++    ]
++
++unreach:
++    unreachable
++
++exit:
++    ret void
++}
++
++; We also need to check the opposite order of the branches, in the switch
++; instruction because jump-threading relies on that to decide which edge to
++; try to thread first
++define void @jump_threading_loopheader2() {
++; CHECK-LABEL: @jump_threading_loopheader2
++top:
++    br label %entry
++
++entry:
++    %ind = phi i32 [0, %top], [%nextind, %latch]
++    %nextind = add i32 %ind, 1
++    %cmp = icmp ule i32 %ind, 10
++; CHECK: br i1 %cmp, label %latch, label %exit
++    br i1 %cmp, label %body, label %latch
++
++body:
++    call void @opaque_body()
++; CHECK: br label %entry
++    br label %latch
++
++latch:
++    %cond = phi i2 [1, %entry], [2, %body]
++    switch i2 %cond, label %unreach [
++        i2 2, label %entry
++        i2 1, label %exit
++    ]
++
++unreach:
++    unreachable
++
++exit:
++    ret void
++}
+-- 
+2.16.2
+