Learn to design synthesizable digital systems in FPGAs using ONLY free tools #verilog #icestorm #lattice #Linux
GioCC/open-fpga-verilog-tutorial
Folders and files
| Name | Name | Last commit date | ||
|---|---|---|---|---|
Repository files navigation
Releases
No releases published
Languages
- Verilog 49.6%
- Makefile 20.7%
- SystemVerilog 18.2%
- Rocq Prover 5.7%
- Python 5.4%
- Assembly 0.4%