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Merged
dr-orlovsky merged 4 commits into from
Jul 12, 2023
Merged

Test registers memory allocation #94

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158c7b0
regs: add constant ALL enumerating reg types
dr-orlovsky Jul 9, 2023
d62d419
regs: add constant ALL enumerating all reg indexes
dr-orlovsky Jul 9, 2023
a8c46cc
regs: fix Debug implementation for displaying large-size float registers
dr-orlovsky Jul 9, 2023
b9fb593
regs: test memory allocation
dr-orlovsky Jul 9, 2023
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72 changes: 67 additions & 5 deletions src/reg/core_regs.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -27,7 +27,7 @@ use alloc::vec::Vec;
use core::fmt::{self, Debug, Formatter};

use amplify::hex::ToHex;
use amplify::num::apfloat::ieee;
use amplify::num::apfloat::{ieee, Float};
use amplify::num::{u1024, u256, u512};
use half::bf16;

Expand Down Expand Up @@ -599,15 +599,33 @@ impl Debug for CoreRegs {
}
for i in 0..32 {
if let Some(v) = self.f80[i] {
write!(f, "{}f80{}[{}{:02}{}]={}{}{}\n\t\t", reg, eq, reset, i, eq, val, v, reset)?;
write!(
f,
"{}f80{}[{}{:02}{}]={}{}{}\n\t\t",
reg,
eq,
reset,
i,
eq,
val,
v.to_bits(),
reset
)?;
}
}
for i in 0..32 {
if let Some(v) = self.f128[i] {
write!(
f,
"{}f128{}[{}{:02}{}]={}{}{}\n\t\t",
reg, eq, reset, i, eq, val, v, reset
reg,
eq,
reset,
i,
eq,
val,
v.to_bits(),
reset
)?;
}
}
Expand All @@ -616,7 +634,14 @@ impl Debug for CoreRegs {
write!(
f,
"{}f256{}[{}{:02}{}]={}{}{}\n\t\t",
reg, eq, reset, i, eq, val, v, reset
reg,
eq,
reset,
i,
eq,
val,
v.to_bits(),
reset
)?;
}
}
Expand All @@ -625,7 +650,7 @@ impl Debug for CoreRegs {
let v = Number::from(v);
write!(
f,
"{}f512{}[{}{:02}{}]={}{}{}\n\t\t",
"{}f512{}[{}{:02}{}]={}{:x}{}\n\t\t",
reg, eq, reset, i, eq, val, v, reset
)?;
}
Expand Down Expand Up @@ -746,3 +771,40 @@ impl Debug for CoreRegs {
Ok(())
}
}

#[cfg(test)]
mod test {
use amplify::num::u4;

use super::*;

// Checks that we do not overflow the stack if using all registers
#[test]
fn init_all() {
let mut regs = CoreRegs::new();

for reg in RegA::ALL {
for idx in Reg32::ALL {
regs.set(reg, idx, u8::from(idx));
}
}

for reg in RegF::ALL {
for idx in Reg32::ALL {
regs.set(reg, idx, u8::from(idx));
}
}

for reg in RegR::ALL {
for idx in Reg32::ALL {
regs.set(reg, idx, u8::from(idx));
}
}

for idx in 0u8..16 {
regs.set_s(u4::with(idx), Some(ByteStr::with(format!("string index {idx}"))));
}

eprintln!("{regs:#?}");
}
}
36 changes: 36 additions & 0 deletions src/reg/families.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -105,6 +105,18 @@ impl NumericRegister for RegA {
}

impl RegA {
/// Set of all A registers
pub const ALL: [RegA; 8] = [
RegA::A8,
RegA::A16,
RegA::A32,
RegA::A64,
RegA::A128,
RegA::A256,
RegA::A512,
RegA::A1024,
];

/// Constructs [`RegA`] object for a provided requirement for register bit size
pub fn with(bits: u16) -> Option<Self> {
Some(match bits {
Expand Down Expand Up @@ -328,6 +340,18 @@ impl NumericRegister for RegF {
}

impl RegF {
/// Set of all F registers
pub const ALL: [RegF; 8] = [
RegF::F16B,
RegF::F16,
RegF::F32,
RegF::F64,
RegF::F80,
RegF::F128,
RegF::F256,
RegF::F512,
];

/// Constructs [`RegF`] object for a provided requirement for register bit size
pub fn with(bits: u16, use_bfloat16: bool) -> Option<Self> {
Some(match bits {
Expand Down Expand Up @@ -445,6 +469,18 @@ impl NumericRegister for RegR {
}

impl RegR {
/// Set of all R registers
pub const ALL: [RegR; 8] = [
RegR::R128,
RegR::R160,
RegR::R256,
RegR::R512,
RegR::R1024,
RegR::R2048,
RegR::R4096,
RegR::R8192,
];

/// Constructs [`RegR`] object for a provided requirement for register bit size
#[inline]
pub fn with(bits: u16) -> Option<Self> {
Expand Down
72 changes: 72 additions & 0 deletions src/reg/indexes.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -164,6 +164,42 @@ pub enum Reg32 {
}

impl Reg32 {
/// Constant enumerating all register indexes.
pub const ALL: [Reg32; 32] = [
Reg32::Reg0,
Reg32::Reg1,
Reg32::Reg2,
Reg32::Reg3,
Reg32::Reg4,
Reg32::Reg5,
Reg32::Reg6,
Reg32::Reg7,
Reg32::Reg8,
Reg32::Reg9,
Reg32::Reg10,
Reg32::Reg11,
Reg32::Reg12,
Reg32::Reg13,
Reg32::Reg14,
Reg32::Reg15,
Reg32::Reg16,
Reg32::Reg17,
Reg32::Reg18,
Reg32::Reg19,
Reg32::Reg20,
Reg32::Reg21,
Reg32::Reg22,
Reg32::Reg23,
Reg32::Reg24,
Reg32::Reg25,
Reg32::Reg26,
Reg32::Reg27,
Reg32::Reg28,
Reg32::Reg29,
Reg32::Reg30,
Reg32::Reg31,
];

/// Returns `usize` representation of the register index
#[inline]
pub fn to_usize(self) -> usize { self as u8 as usize }
Expand Down Expand Up @@ -311,6 +347,28 @@ pub enum Reg16 {
Reg15 = 15,
}

impl Reg16 {
/// Constant enumerating all register indexes.
pub const ALL: [Reg16; 16] = [
Reg16::Reg0,
Reg16::Reg1,
Reg16::Reg2,
Reg16::Reg3,
Reg16::Reg4,
Reg16::Reg5,
Reg16::Reg6,
Reg16::Reg7,
Reg16::Reg8,
Reg16::Reg9,
Reg16::Reg10,
Reg16::Reg11,
Reg16::Reg12,
Reg16::Reg13,
Reg16::Reg14,
Reg16::Reg15,
];
}

impl Register for Reg16 {
#[inline]
fn description() -> &'static str { "4-bit register index" }
Expand Down Expand Up @@ -408,6 +466,20 @@ pub enum Reg8 {
Reg7 = 7,
}

impl Reg8 {
/// Constant enumerating all register indexes.
pub const ALL: [Reg8; 8] = [
Reg8::Reg0,
Reg8::Reg1,
Reg8::Reg2,
Reg8::Reg3,
Reg8::Reg4,
Reg8::Reg5,
Reg8::Reg6,
Reg8::Reg7,
];
}

impl Register for Reg8 {
#[inline]
fn description() -> &'static str { "3-bit register index" }
Expand Down