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Merged
dr-orlovsky merged 5 commits into from
Jun 26, 2023
Merged

Revert mnemonic #12

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d7278e0
Revert "destination first"
6293 Jun 22, 2023
4ed7d1f
revert mnemonic on macro
6293 Jun 22, 2023
9604fc3
add tests on BytesOp::Con
6293 Jun 21, 2023
1df0618
add tests on BytesOp::Find
6293 Jun 21, 2023
5de7ed3
add tests on BytesOp::Rev
6293 Jun 24, 2023
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26 changes: 13 additions & 13 deletions examples/asm.rs
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Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -34,7 +34,7 @@ fn main() {
lt.r f64[5],f64[9] ;
gt r160[5],r256[9] ;
lt r160[5],r256[9] ;
eq.e a8[5],a8[9] ;
eq.e a8[5],a8[9] ;
eq.n r160[5],r160[9] ;
eq.e f64[19],f64[29] ;
ifn a32[31] ;
Expand Down Expand Up @@ -63,21 +63,21 @@ fn main() {
abs f128[11] ;
and a32[5],a32[6],a32[5] ;
xor r128[5],r128[6],r128[5] ;
shr.u a256[12],a16[2] ;
shr.s a256[12],a16[2] ;
shl r256[24],a16[22] ;
shr r256[24],a16[22] ;
scr r256[24],a16[22] ;
scl r256[24],a16[22] ;
shr.u a16[2],a256[12] ;
shr.s a16[2],a256[12] ;
shl a16[22],r256[24] ;
shr a16[22],r256[24] ;
scr a16[22],r256[24] ;
scl a16[22],r256[24] ;
rev a512[28] ;
ripemd r160[7],s16[9] ;
sha2 r256[2],s16[19] ;
secpgen r512[1],r256[1] ;
ripemd s16[9],r160[7] ;
sha2 s16[19],r256[2] ;
secpgen r256[1],r512[1] ;
dup r512[1],r512[22] ;
spy a512[1],r512[22] ;
secpmul r512[1],r256[1],r512[2] ;
secpadd r512[1],r512[22] ;
secpneg r512[3],r512[1] ;
secpmul r256[1],r512[1],r512[2] ;
secpadd r512[22],r512[1] ;
secpneg r512[1],r512[3] ;
ifz a16[8] ;
jif 190 ;
call 56 @ alu07EnUZgFtu28sWqqH3womkTopXCkgAGsCLvLnYvNcPLRt ;
Expand Down
114 changes: 68 additions & 46 deletions src/macros.rs
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Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -108,6 +108,10 @@ macro_rules! aluasm_inner {
$code.push($crate::instr!{ $op . $flag $( $arg [ $idx ] ),+ });
$crate::aluasm_inner! { $code => $( $tt )* }
};
{ $code:ident => $op:ident $arglit:literal, $arg:ident [ $idx:literal ] ; $($tt:tt)* } => {
$code.push($crate::instr!{ $op $arglit , $arg [ $idx ] });
$crate::aluasm_inner! { $code => $( $tt )* }
};
{ $code:ident => $op:ident $arg:ident [ $idx:literal ] , $arglit:literal ; $($tt:tt)* } => {
$code.push($crate::instr!{ $op $arg [ $idx ] , $arglit });
$crate::aluasm_inner! { $code => $( $tt )* }
Expand Down Expand Up @@ -159,7 +163,7 @@ macro_rules! instr {
))
};

(extr $regr:ident[$regr_idx:literal],s16[$idx:literal],a16[$offset_idx:literal]) => {
(extr s16[$idx:literal], $regr:ident[$regr_idx:literal],a16[$offset_idx:literal]) => {
Instr::Bytes(BytesOp::Extr(
RegS::from($idx),
$crate::_reg_ty!(Reg, $regr),
Expand Down Expand Up @@ -188,20 +192,38 @@ macro_rules! instr {
ExtendFlag::Fail,
))
}};
(len $rega:ident[$rega_idx:literal],s16[$s_idx:literal]) => {{
(len s16[$s_idx:literal], $rega:ident[$rega_idx:literal]) => {{
Instr::Bytes(BytesOp::Len(
RegS::from($s_idx),
$crate::_reg_tya!(Reg, $rega),
$crate::_reg_idx!($rega_idx),
))
}};
(cnt a16[$dst_idx:literal],s16[$s_idx:literal],a8[$byte_idx:literal]) => {{
(cnt s16[$s_idx:literal],a8[$byte_idx:literal],a16[$dst_idx:literal]) => {{
Instr::Bytes(BytesOp::Cnt(
RegS::from($s_idx),
$crate::_reg_idx16!($byte_idx),
$crate::_reg_idx16!($dst_idx),
))
}};
(
con s16[$src1_idx:literal],s16[$src2_idx:literal],a16[$frag_idx:literal],a16[$offset_dst_idx:literal],a16[$len_dst_idx:literal]
) => {{
Instr::Bytes(BytesOp::Con(
RegS::from($src1_idx),
RegS::from($src2_idx),
$crate::_reg_idx!($frag_idx),
$crate::_reg_idx!($offset_dst_idx),
$crate::_reg_idx!($len_dst_idx),
))
}};
(find s16[$str_idx:literal],s16[$fragment_idx:literal],a16[$should_be_0:literal]) => {{
assert_eq!(0, $should_be_0);
Instr::Bytes(BytesOp::Find(RegS::from($str_idx), RegS::from($fragment_idx)))
}};
(rev s16[$src_idx:literal],s16[$dst_idx:literal]) => {{
Instr::Bytes(BytesOp::Rev(RegS::from($src_idx), RegS::from($dst_idx)))
}};
(put $reg:ident[$idx:literal], $val:literal) => {{
let s = stringify!($val);
let mut num = s.parse::<MaybeNumber>().expect(&format!("invalid number literal `{}`", s));
Expand Down Expand Up @@ -231,7 +253,7 @@ macro_rules! instr {
$crate::_reg_idx!($idx2),
))
}};
(mov $dst_reg:ident[$dst_idx:literal], $src_reg:ident[$src_idx:literal]) => {{
(mov $src_reg:ident[$src_idx:literal], $dst_reg:ident[$dst_idx:literal]) => {{
if $crate::_reg_ty!(Reg, $src_reg) != $crate::_reg_ty!(Reg, $dst_reg) {
panic!("Move operation must be performed between registers of the same type");
}
Expand All @@ -241,7 +263,7 @@ macro_rules! instr {
$crate::_reg_idx!($dst_idx),
))
}};
(dup $dst_reg:ident[$dst_idx:literal], $src_reg:ident[$src_idx:literal]) => {{
(dup $src_reg:ident[$src_idx:literal], $dst_reg:ident[$dst_idx:literal]) => {{
if $crate::_reg_ty!(Reg, $src_reg) != $crate::_reg_ty!(Reg, $dst_reg) {
panic!("Dup operation must be performed between registers of the same type");
}
Expand All @@ -251,7 +273,7 @@ macro_rules! instr {
$crate::_reg_idx!($dst_idx),
))
}};
(cpy $dst_reg:ident[$dst_idx:literal], $src_reg:ident[$src_idx:literal]) => {{
(cpy $src_reg:ident[$src_idx:literal], $dst_reg:ident[$dst_idx:literal]) => {{
if $crate::_reg_ty!(Reg, $src_reg) != $crate::_reg_ty!(Reg, $dst_reg) {
panic!("Copy operation must be performed between registers of the same type");
}
Expand All @@ -262,7 +284,7 @@ macro_rules! instr {
$crate::_reg_idx!($dst_idx),
))
}};
(cnv $dst_reg:ident[$dst_idx:literal], $src_reg:ident[$src_idx:literal]) => {{
(cnv $src_reg:ident[$src_idx:literal], $dst_reg:ident[$dst_idx:literal]) => {{
match ($crate::_reg_block!($src_reg), $crate::_reg_block!($dst_reg)) {
(RegBlockAFR::A, RegBlockAFR::F) => Instr::Move(MoveOp::CnvAF(
$crate::_reg_tya!(Reg, $src_reg),
Expand Down Expand Up @@ -291,7 +313,7 @@ macro_rules! instr {
(_, _) => panic!("Conversion operation between unsupported register types"),
}
}};
(spy $dst_reg:ident[$dst_idx:literal], $src_reg:ident[$src_idx:literal]) => {{
(spy $src_reg:ident[$src_idx:literal], $dst_reg:ident[$dst_idx:literal]) => {{
match ($crate::_reg_block!($src_reg), $crate::_reg_block!($dst_reg)) {
(RegBlockAFR::A, RegBlockAFR::R) => Instr::Move(MoveOp::SpyAR(
$crate::_reg_tya!(Reg, $src_reg),
Expand Down Expand Up @@ -523,7 +545,7 @@ macro_rules! instr {
Instr::Cmp(CmpOp::StInv)
};

(add. $flag:ident $dst_reg:ident[$dst_idx:literal], $reg1:ident[$idx1:literal]) => {
(add. $flag:ident $reg1:ident[$idx1:literal], $dst_reg:ident[$dst_idx:literal]) => {
match ($crate::_reg_block!($reg1), $crate::_reg_block!($dst_reg)) {
(RegBlockAFR::A, RegBlockAFR::A) => Instr::Arithmetic(ArithmeticOp::AddA(
$crate::_int_flags!($flag),
Expand All @@ -544,7 +566,7 @@ macro_rules! instr {
(_, _) => panic!("addition must be performed between registers of the same type"),
}
};
(sub. $flag:ident $dst_reg:ident[$dst_idx:literal], $reg1:ident[$idx1:literal]) => {
(sub. $flag:ident $reg1:ident[$idx1:literal], $dst_reg:ident[$dst_idx:literal]) => {
match ($crate::_reg_block!($reg1), $crate::_reg_block!($dst_reg)) {
(RegBlockAFR::A, RegBlockAFR::A) => Instr::Arithmetic(ArithmeticOp::SubA(
$crate::_int_flags!($flag),
Expand All @@ -565,7 +587,7 @@ macro_rules! instr {
(_, _) => panic!("subtraction must be performed between registers of the same type"),
}
};
(mul. $flag:ident $dst_reg:ident[$dst_idx:literal], $reg1:ident[$idx1:literal]) => {
(mul. $flag:ident $reg1:ident[$idx1:literal], $dst_reg:ident[$dst_idx:literal]) => {
match ($crate::_reg_block!($reg1), $crate::_reg_block!($dst_reg)) {
(RegBlockAFR::A, RegBlockAFR::A) => Instr::Arithmetic(ArithmeticOp::MulA(
$crate::_int_flags!($flag),
Expand All @@ -586,7 +608,7 @@ macro_rules! instr {
(_, _) => panic!("multiplication must be performed between registers of the same type"),
}
};
(div. $flag:ident $dst_reg:ident[$dst_idx:literal], $reg1:ident[$idx1:literal]) => {
(div. $flag:ident $reg1:ident[$idx1:literal], $dst_reg:ident[$dst_idx:literal]) => {
match ($crate::_reg_block!($reg1), $crate::_reg_block!($dst_reg)) {
(RegBlockAFR::A, RegBlockAFR::A) => Instr::Arithmetic(ArithmeticOp::DivA(
$crate::_int_flags!($flag),
Expand All @@ -607,7 +629,7 @@ macro_rules! instr {
(_, _) => panic!("division must be performed between registers of the same type"),
}
};
(rem $dst_reg:ident[$dst_idx:literal], $reg1:ident[$idx1:literal]) => {
(rem $reg1:ident[$idx1:literal], $dst_reg:ident[$dst_idx:literal]) => {
if $crate::_reg_block!($reg1) != RegBlockAFR::A
|| $crate::_reg_block!($dst_reg) != RegBlockAFR::A
{
Expand Down Expand Up @@ -664,9 +686,9 @@ macro_rules! instr {

(
and
$dst_reg:ident[$dst_idx:literal],
$reg1:ident[$idx1:literal],
$reg2:ident[$idx2:literal]
$reg2:ident[$idx2:literal],
$dst_reg:ident[$dst_idx:literal]
) => {
if $crate::_reg_ty!(Reg, $reg1) != $crate::_reg_ty!(Reg, $reg2)
|| $crate::_reg_ty!(Reg, $reg2) != $crate::_reg_ty!(Reg, $dst_reg)
Expand All @@ -686,7 +708,7 @@ macro_rules! instr {
}
};
(
or $dst_reg:ident[$dst_idx:literal], $reg2:ident[$idx2:literal], $reg1:ident[$idx1:literal]
or $reg1:ident[$idx1:literal], $reg2:ident[$idx2:literal], $dst_reg:ident[$dst_idx:literal]
) => {
if $crate::_reg_ty!(Reg, $reg1) != $crate::_reg_ty!(Reg, $reg2)
|| $crate::_reg_ty!(Reg, $reg2) != $crate::_reg_ty!(Reg, $dst_reg)
Expand All @@ -707,9 +729,9 @@ macro_rules! instr {
};
(
xor
$dst_reg:ident[$dst_idx:literal],
$reg1:ident[$idx1:literal],
$reg2:ident[$idx2:literal],
$reg1:ident[$idx1:literal]
$dst_reg:ident[$dst_idx:literal]
) => {
if $crate::_reg_ty!(Reg, $reg1) != $crate::_reg_ty!(Reg, $reg2)
|| $crate::_reg_ty!(Reg, $reg2) != $crate::_reg_ty!(Reg, $dst_reg)
Expand All @@ -730,52 +752,52 @@ macro_rules! instr {
};
(shl $reg1:ident[$idx1:literal], $reg2:ident[$idx2:literal]) => {
Instr::Bitwise(BitwiseOp::Shl(
$crate::_reg_tya2!(Reg, $reg2),
$crate::_reg_idx!($idx2),
$crate::_reg_ty!(Reg, $reg1).into(),
$crate::_reg_tya2!(Reg, $reg1),
$crate::_reg_idx!($idx1),
$crate::_reg_ty!(Reg, $reg2).into(),
$crate::_reg_idx!($idx2),
))
};
(shr.u $reg1:ident[$idx1:literal], $reg2:ident[$idx2:literal]) => {
Instr::Bitwise(BitwiseOp::ShrA(
SignFlag::Unsigned,
$crate::_reg_tya2!(Reg, $reg2),
$crate::_reg_idx16!($idx2),
$crate::_reg_ty!(Reg, $reg1),
$crate::_reg_idx!($idx1),
$crate::_reg_tya2!(Reg, $reg1),
$crate::_reg_idx16!($idx1),
$crate::_reg_ty!(Reg, $reg2),
$crate::_reg_idx!($idx2),
))
};
(shr.s $reg1:ident[$idx1:literal], $reg2:ident[$idx2:literal]) => {
Instr::Bitwise(BitwiseOp::ShrA(
SignFlag::Signed,
$crate::_reg_tya2!(Reg, $reg2),
$crate::_reg_idx16!($idx2),
$crate::_reg_ty!(Reg, $reg1),
$crate::_reg_idx!($idx1),
$crate::_reg_tya2!(Reg, $reg1),
$crate::_reg_idx16!($idx1),
$crate::_reg_ty!(Reg, $reg2),
$crate::_reg_idx!($idx2),
))
};
(shr $reg1:ident[$idx1:literal], $reg2:ident[$idx2:literal]) => {
Instr::Bitwise(BitwiseOp::ShrR(
$crate::_reg_tya2!(Reg, $reg2),
$crate::_reg_idx!($idx2),
$crate::_reg_ty!(Reg, $reg1),
$crate::_reg_tya2!(Reg, $reg1),
$crate::_reg_idx!($idx1),
$crate::_reg_ty!(Reg, $reg2),
$crate::_reg_idx!($idx2),
))
};
(scl $reg1:ident[$idx1:literal], $reg2:ident[$idx2:literal]) => {
Instr::Bitwise(BitwiseOp::Scl(
$crate::_reg_tya2!(Reg, $reg2),
$crate::_reg_idx!($idx2),
$crate::_reg_ty!(Reg, $reg1).into(),
$crate::_reg_tya2!(Reg, $reg1),
$crate::_reg_idx!($idx1),
$crate::_reg_ty!(Reg, $reg2).into(),
$crate::_reg_idx!($idx2),
))
};
(scr $reg1:ident[$idx1:literal], $reg2:ident[$idx2:literal]) => {
Instr::Bitwise(BitwiseOp::Scr(
$crate::_reg_tya2!(Reg, $reg2),
$crate::_reg_idx!($idx2),
$crate::_reg_ty!(Reg, $reg1).into(),
$crate::_reg_tya2!(Reg, $reg1),
$crate::_reg_idx!($idx1),
$crate::_reg_ty!(Reg, $reg2).into(),
$crate::_reg_idx!($idx2),
))
};
(rev $reg:ident[$idx:literal]) => {
Expand All @@ -792,17 +814,17 @@ macro_rules! instr {
}
};

(ripemd r160[$idx2:literal],s16[$idx1:literal]) => {
(ripemd s16[$idx1:literal],r160[$idx2:literal]) => {
Instr::Digest(DigestOp::Ripemd(RegS::from($idx1), $crate::_reg_idx16!($idx2)))
};
(sha2 r256[$idx2:literal],s16[$idx1:literal]) => {
(sha2 s16[$idx1:literal],r256[$idx2:literal]) => {
Instr::Digest(DigestOp::Sha256(RegS::from($idx1), $crate::_reg_idx16!($idx2)))
};
(sha2 r512[$idx2:literal],s16[$idx1:literal]) => {
(sha2 s16[$idx1:literal],r512[$idx2:literal]) => {
Instr::Digest(DigestOp::Sha512(RegS::from($idx1), $crate::_reg_idx16!($idx2)))
};

(secpgen $reg2:ident[$idx2:literal], $reg1:ident[$idx1:literal]) => {
(secpgen $reg1:ident[$idx1:literal], $reg2:ident[$idx2:literal]) => {
if $crate::_reg_block!($reg1) != RegBlockAFR::R
|| $crate::_reg_block!($reg2) != RegBlockAFR::R
{
Expand All @@ -813,9 +835,9 @@ macro_rules! instr {
};
(
secpmul
$dst_reg:ident[$dst_idx:literal],
$scalar_reg:ident[$scalar_idx:literal],
$src_reg:ident[$src_idx:literal]
$src_reg:ident[$src_idx:literal],
$dst_reg:ident[$dst_idx:literal]
) => {
if $crate::_reg_ty!(Reg, $src_reg) != $crate::_reg_ty!(Reg, $dst_reg) {
panic!("ecmul instruction can be used only with registers of the same type");
Expand All @@ -828,7 +850,7 @@ macro_rules! instr {
))
}
};
(secpadd $reg2:ident[$idx2:literal], $reg1:ident[$idx1:literal]) => {
(secpadd $reg1:ident[$idx1:literal], $reg2:ident[$idx2:literal]) => {
if $crate::_reg_block!($reg1) != RegBlockAFR::R
|| $crate::_reg_block!($reg2) != RegBlockAFR::R
{
Expand All @@ -837,7 +859,7 @@ macro_rules! instr {
Instr::Secp256k1(Secp256k1Op::Add($crate::_reg_idx!($idx1), $crate::_reg_idx8!($idx2)))
}
};
(secpneg $reg2:ident[$idx2:literal], $reg1:ident[$idx1:literal]) => {
(secpneg $reg1:ident[$idx1:literal], $reg2:ident[$idx2:literal]) => {
if $crate::_reg_block!($reg1) != RegBlockAFR::R
|| $crate::_reg_block!($reg2) != RegBlockAFR::R
{
Expand Down
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