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[TTI] Use Register in isLoadFromStackSlot and isStoreToStackSlot [nfc] (llvm#80339)
1 parent acec641 commit 3ff7cae

37 files changed

+95
-95
lines changed

‎llvm/include/llvm/CodeGen/TargetInstrInfo.h‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -269,7 +269,7 @@ class TargetInstrInfo : public MCInstrInfo {
269269
/// the destination along with the FrameIndex of the loaded stack slot. If
270270
/// not, return 0. This predicate must return 0 if the instruction has
271271
/// any side effects other than loading from the stack slot.
272-
virtual unsigned isLoadFromStackSlot(const MachineInstr &MI,
272+
virtual Register isLoadFromStackSlot(const MachineInstr &MI,
273273
int &FrameIndex) const {
274274
return 0;
275275
}
@@ -278,7 +278,7 @@ class TargetInstrInfo : public MCInstrInfo {
278278
/// bytes loaded from the stack. This must be implemented if a backend
279279
/// supports partial stack slot spills/loads to further disambiguate
280280
/// what the load does.
281-
virtual unsigned isLoadFromStackSlot(const MachineInstr &MI,
281+
virtual Register isLoadFromStackSlot(const MachineInstr &MI,
282282
int &FrameIndex,
283283
unsigned &MemBytes) const {
284284
MemBytes = 0;
@@ -287,7 +287,7 @@ class TargetInstrInfo : public MCInstrInfo {
287287

288288
/// Check for post-frame ptr elimination stack locations as well.
289289
/// This uses a heuristic so it isn't reliable for correctness.
290-
virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI,
290+
virtual Register isLoadFromStackSlotPostFE(const MachineInstr &MI,
291291
int &FrameIndex) const {
292292
return 0;
293293
}
@@ -307,7 +307,7 @@ class TargetInstrInfo : public MCInstrInfo {
307307
/// the source reg along with the FrameIndex of the loaded stack slot. If
308308
/// not, return 0. This predicate must return 0 if the instruction has
309309
/// any side effects other than storing to the stack slot.
310-
virtual unsigned isStoreToStackSlot(const MachineInstr &MI,
310+
virtual Register isStoreToStackSlot(const MachineInstr &MI,
311311
int &FrameIndex) const {
312312
return 0;
313313
}
@@ -316,7 +316,7 @@ class TargetInstrInfo : public MCInstrInfo {
316316
/// bytes stored to the stack. This must be implemented if a backend
317317
/// supports partial stack slot spills/loads to further disambiguate
318318
/// what the store does.
319-
virtual unsigned isStoreToStackSlot(const MachineInstr &MI,
319+
virtual Register isStoreToStackSlot(const MachineInstr &MI,
320320
int &FrameIndex,
321321
unsigned &MemBytes) const {
322322
MemBytes = 0;
@@ -325,7 +325,7 @@ class TargetInstrInfo : public MCInstrInfo {
325325

326326
/// Check for post-frame ptr elimination stack locations as well.
327327
/// This uses a heuristic, so it isn't reliable for correctness.
328-
virtual unsigned isStoreToStackSlotPostFE(const MachineInstr &MI,
328+
virtual Register isStoreToStackSlotPostFE(const MachineInstr &MI,
329329
int &FrameIndex) const {
330330
return 0;
331331
}

‎llvm/lib/Target/AArch64/AArch64InstrInfo.cpp‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2186,7 +2186,7 @@ bool AArch64InstrInfo::isFPRCopy(const MachineInstr &MI) {
21862186
return false;
21872187
}
21882188

2189-
unsigned AArch64InstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
2189+
Register AArch64InstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
21902190
int &FrameIndex) const {
21912191
switch (MI.getOpcode()) {
21922192
default:
@@ -2210,7 +2210,7 @@ unsigned AArch64InstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
22102210
return 0;
22112211
}
22122212

2213-
unsigned AArch64InstrInfo::isStoreToStackSlot(const MachineInstr &MI,
2213+
Register AArch64InstrInfo::isStoreToStackSlot(const MachineInstr &MI,
22142214
int &FrameIndex) const {
22152215
switch (MI.getOpcode()) {
22162216
default:

‎llvm/lib/Target/AArch64/AArch64InstrInfo.h‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -56,9 +56,9 @@ class AArch64InstrInfo final : public AArch64GenInstrInfo {
5656
areMemAccessesTriviallyDisjoint(const MachineInstr &MIa,
5757
const MachineInstr &MIb) const override;
5858

59-
unsigned isLoadFromStackSlot(const MachineInstr &MI,
59+
Register isLoadFromStackSlot(const MachineInstr &MI,
6060
int &FrameIndex) const override;
61-
unsigned isStoreToStackSlot(const MachineInstr &MI,
61+
Register isStoreToStackSlot(const MachineInstr &MI,
6262
int &FrameIndex) const override;
6363

6464
/// Does this instruction set its full destination register to zero?

‎llvm/lib/Target/AMDGPU/SIInstrInfo.cpp‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -8526,7 +8526,7 @@ unsigned SIInstrInfo::isSGPRStackAccess(const MachineInstr &MI,
85268526
return getNamedOperand(MI, AMDGPU::OpName::data)->getReg();
85278527
}
85288528

8529-
unsigned SIInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
8529+
Register SIInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
85308530
int &FrameIndex) const {
85318531
if (!MI.mayLoad())
85328532
return Register();
@@ -8540,7 +8540,7 @@ unsigned SIInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
85408540
return Register();
85418541
}
85428542

8543-
unsigned SIInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
8543+
Register SIInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
85448544
int &FrameIndex) const {
85458545
if (!MI.mayStore())
85468546
return Register();

‎llvm/lib/Target/AMDGPU/SIInstrInfo.h‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1213,9 +1213,9 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
12131213
unsigned isStackAccess(const MachineInstr &MI, int &FrameIndex) const;
12141214
unsigned isSGPRStackAccess(const MachineInstr &MI, int &FrameIndex) const;
12151215

1216-
unsigned isLoadFromStackSlot(const MachineInstr &MI,
1216+
Register isLoadFromStackSlot(const MachineInstr &MI,
12171217
int &FrameIndex) const override;
1218-
unsigned isStoreToStackSlot(const MachineInstr &MI,
1218+
Register isStoreToStackSlot(const MachineInstr &MI,
12191219
int &FrameIndex) const override;
12201220

12211221
unsigned getInstBundleSize(const MachineInstr &MI) const;

‎llvm/lib/Target/ARC/ARCInstrInfo.cpp‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -65,7 +65,7 @@ static bool isStore(int Opcode) {
6565
/// the destination along with the FrameIndex of the loaded stack slot. If
6666
/// not, return 0. This predicate must return 0 if the instruction has
6767
/// any side effects other than loading from the stack slot.
68-
unsigned ARCInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
68+
Register ARCInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
6969
int &FrameIndex) const {
7070
int Opcode = MI.getOpcode();
7171
if (isLoad(Opcode)) {
@@ -84,7 +84,7 @@ unsigned ARCInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
8484
/// the source reg along with the FrameIndex of the loaded stack slot. If
8585
/// not, return 0. This predicate must return 0 if the instruction has
8686
/// any side effects other than storing to the stack slot.
87-
unsigned ARCInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
87+
Register ARCInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
8888
int &FrameIndex) const {
8989
int Opcode = MI.getOpcode();
9090
if (isStore(Opcode)) {

‎llvm/lib/Target/ARC/ARCInstrInfo.h‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -37,15 +37,15 @@ class ARCInstrInfo : public ARCGenInstrInfo {
3737
/// the destination along with the FrameIndex of the loaded stack slot. If
3838
/// not, return 0. This predicate must return 0 if the instruction has
3939
/// any side effects other than loading from the stack slot.
40-
unsigned isLoadFromStackSlot(const MachineInstr &MI,
40+
Register isLoadFromStackSlot(const MachineInstr &MI,
4141
int &FrameIndex) const override;
4242

4343
/// If the specified machine instruction is a direct
4444
/// store to a stack slot, return the virtual or physical register number of
4545
/// the source reg along with the FrameIndex of the loaded stack slot. If
4646
/// not, return 0. This predicate must return 0 if the instruction has
4747
/// any side effects other than storing to the stack slot.
48-
unsigned isStoreToStackSlot(const MachineInstr &MI,
48+
Register isStoreToStackSlot(const MachineInstr &MI,
4949
int &FrameIndex) const override;
5050

5151
unsigned getInstSizeInBytes(const MachineInstr &MI) const override;

‎llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1304,7 +1304,7 @@ void ARMBaseInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
13041304
}
13051305
}
13061306

1307-
unsigned ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
1307+
Register ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
13081308
int &FrameIndex) const {
13091309
switch (MI.getOpcode()) {
13101310
default: break;
@@ -1356,7 +1356,7 @@ unsigned ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
13561356
return 0;
13571357
}
13581358

1359-
unsigned ARMBaseInstrInfo::isStoreToStackSlotPostFE(const MachineInstr &MI,
1359+
Register ARMBaseInstrInfo::isStoreToStackSlotPostFE(const MachineInstr &MI,
13601360
int &FrameIndex) const {
13611361
SmallVector<const MachineMemOperand *, 1> Accesses;
13621362
if (MI.mayStore() && hasStoreToStackSlot(MI, Accesses) &&
@@ -1555,7 +1555,7 @@ void ARMBaseInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
15551555
}
15561556
}
15571557

1558-
unsigned ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
1558+
Register ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
15591559
int &FrameIndex) const {
15601560
switch (MI.getOpcode()) {
15611561
default: break;
@@ -1613,7 +1613,7 @@ unsigned ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
16131613
return 0;
16141614
}
16151615

1616-
unsigned ARMBaseInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr &MI,
1616+
Register ARMBaseInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr &MI,
16171617
int &FrameIndex) const {
16181618
SmallVector<const MachineMemOperand *, 1> Accesses;
16191619
if (MI.mayLoad() && hasLoadFromStackSlot(MI, Accesses) &&

‎llvm/lib/Target/ARM/ARMBaseInstrInfo.h‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -186,13 +186,13 @@ class ARMBaseInstrInfo : public ARMGenInstrInfo {
186186
///
187187
unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
188188

189-
unsigned isLoadFromStackSlot(const MachineInstr &MI,
189+
Register isLoadFromStackSlot(const MachineInstr &MI,
190190
int &FrameIndex) const override;
191-
unsigned isStoreToStackSlot(const MachineInstr &MI,
191+
Register isStoreToStackSlot(const MachineInstr &MI,
192192
int &FrameIndex) const override;
193-
unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI,
193+
Register isLoadFromStackSlotPostFE(const MachineInstr &MI,
194194
int &FrameIndex) const override;
195-
unsigned isStoreToStackSlotPostFE(const MachineInstr &MI,
195+
Register isStoreToStackSlotPostFE(const MachineInstr &MI,
196196
int &FrameIndex) const override;
197197

198198
void copyToCPSR(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,

‎llvm/lib/Target/AVR/AVRInstrInfo.cpp‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -91,7 +91,7 @@ void AVRInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
9191
}
9292
}
9393

94-
unsigned AVRInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
94+
Register AVRInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
9595
int &FrameIndex) const {
9696
switch (MI.getOpcode()) {
9797
case AVR::LDDRdPtrQ:
@@ -110,7 +110,7 @@ unsigned AVRInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
110110
return 0;
111111
}
112112

113-
unsigned AVRInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
113+
Register AVRInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
114114
int &FrameIndex) const {
115115
switch (MI.getOpcode()) {
116116
case AVR::STDPtrQRr:

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