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drm/radeon: fix display tiling setup on SI
Apply the same logic as CI to SI for setting up the display tiling parameters. The num banks may vary per tiling index just like CI. Bugs: https://bugs.freedesktop.org/show_bug.cgi?id=71488 https://bugs.freedesktop.org/show_bug.cgi?id=73946 https://bugs.freedesktop.org/show_bug.cgi?id=74927 Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
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drivers/gpu/drm/radeon/atombios_crtc.c

Lines changed: 7 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1176,7 +1176,7 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
11761176
evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split);
11771177

11781178
/* Set NUM_BANKS. */
1179-
if (rdev->family >= CHIP_BONAIRE) {
1179+
if (rdev->family >= CHIP_TAHITI) {
11801180
unsigned tileb, index, num_banks, tile_split_bytes;
11811181

11821182
/* Calculate the macrotile mode index. */
@@ -1194,13 +1194,14 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
11941194
return -EINVAL;
11951195
}
11961196

1197-
num_banks = (rdev->config.cik.macrotile_mode_array[index] >> 6) & 0x3;
1197+
if (rdev->family >= CHIP_BONAIRE)
1198+
num_banks = (rdev->config.cik.macrotile_mode_array[index] >> 6) & 0x3;
1199+
else
1200+
num_banks = (rdev->config.si.tile_mode_array[index] >> 20) & 0x3;
11981201
fb_format |= EVERGREEN_GRPH_NUM_BANKS(num_banks);
11991202
} else {
1200-
/* SI and older. */
1201-
if (rdev->family >= CHIP_TAHITI)
1202-
tmp = rdev->config.si.tile_config;
1203-
else if (rdev->family >= CHIP_CAYMAN)
1203+
/* NI and older. */
1204+
if (rdev->family >= CHIP_CAYMAN)
12041205
tmp = rdev->config.cayman.tile_config;
12051206
else
12061207
tmp = rdev->config.evergreen.tile_config;

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