@@ -68,6 +68,52 @@ void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common)
6868 complete (& common -> free );
6969}
7070
71+ static u64 qp_allowed_event_types (void )
72+ {
73+ u64 mask ;
74+
75+ mask = BIT (MLX5_EVENT_TYPE_PATH_MIG ) |
76+ BIT (MLX5_EVENT_TYPE_COMM_EST ) |
77+ BIT (MLX5_EVENT_TYPE_SQ_DRAINED ) |
78+ BIT (MLX5_EVENT_TYPE_SRQ_LAST_WQE ) |
79+ BIT (MLX5_EVENT_TYPE_WQ_CATAS_ERROR ) |
80+ BIT (MLX5_EVENT_TYPE_PATH_MIG_FAILED ) |
81+ BIT (MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR ) |
82+ BIT (MLX5_EVENT_TYPE_WQ_ACCESS_ERROR );
83+
84+ return mask ;
85+ }
86+
87+ static u64 rq_allowed_event_types (void )
88+ {
89+ u64 mask ;
90+
91+ mask = BIT (MLX5_EVENT_TYPE_SRQ_LAST_WQE ) |
92+ BIT (MLX5_EVENT_TYPE_WQ_CATAS_ERROR );
93+
94+ return mask ;
95+ }
96+
97+ static u64 sq_allowed_event_types (void )
98+ {
99+ return BIT (MLX5_EVENT_TYPE_WQ_CATAS_ERROR );
100+ }
101+
102+ static bool is_event_type_allowed (int rsc_type , int event_type )
103+ {
104+ switch (rsc_type ) {
105+ case MLX5_EVENT_QUEUE_TYPE_QP :
106+ return BIT (event_type ) & qp_allowed_event_types ();
107+ case MLX5_EVENT_QUEUE_TYPE_RQ :
108+ return BIT (event_type ) & rq_allowed_event_types ();
109+ case MLX5_EVENT_QUEUE_TYPE_SQ :
110+ return BIT (event_type ) & sq_allowed_event_types ();
111+ default :
112+ WARN (1 , "Event arrived for unknown resource type" );
113+ return false;
114+ }
115+ }
116+
71117void mlx5_rsc_event (struct mlx5_core_dev * dev , u32 rsn , int event_type )
72118{
73119 struct mlx5_core_rsc_common * common = mlx5_get_rsc (dev , rsn );
@@ -76,6 +122,12 @@ void mlx5_rsc_event(struct mlx5_core_dev *dev, u32 rsn, int event_type)
76122 if (!common )
77123 return ;
78124
125+ if (!is_event_type_allowed ((rsn >> MLX5_USER_INDEX_LEN ), event_type )) {
126+ mlx5_core_warn (dev , "event 0x%.2x is not allowed on resource 0x%.8x\n" ,
127+ event_type , rsn );
128+ return ;
129+ }
130+
79131 switch (common -> res ) {
80132 case MLX5_RES_QP :
81133 case MLX5_RES_RQ :
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