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li041li041
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Separate lock-free fields from Zone and make fields private
2 parents 16431e1 + 21acef7 commit 1a9da8a

34 files changed

Lines changed: 435 additions & 272 deletions

‎src/arch/aarch64/cpu.rs‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -274,7 +274,7 @@ pub fn get_target_cpu(_irq: usize, zone_id: usize) -> usize {
274274
find_zone(zone_id)
275275
.unwrap()
276276
.read()
277-
.cpu_set
277+
.cpu_set()
278278
.first_cpu()
279279
.unwrap()
280280
}

‎src/arch/aarch64/hypercall.rs‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -30,7 +30,7 @@ impl<'a> HyperCall<'a> {
3030
// ipa->hpa->hva
3131
let hpa = unsafe {
3232
zone.read()
33-
.gpm
33+
.gpm()
3434
.page_table_query(ivc_info_ipa as _)
3535
.unwrap()
3636
.0

‎src/arch/aarch64/ivc.rs‎

Lines changed: 13 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -151,16 +151,20 @@ impl From<&HvIvcConfig> for IvcRecord {
151151

152152
impl Zone {
153153
pub fn ivc_init(&mut self, ivc_configs: &[HvIvcConfig]) {
154+
let mut inner = self.write();
154155
for ivc_config in ivc_configs {
155156
// is_new is ok to remove
156-
if let Ok((_, start_paddr)) = insert_ivc_record(ivc_config, self.id as _) {
157+
if let Ok((_, start_paddr)) = insert_ivc_record(ivc_config, self.id() as _) {
157158
info!(
158159
"ivc init: zone {}'s shared mem begins at {:x}, ipa is {:x}",
159-
self.id, start_paddr, ivc_config.shared_mem_ipa
160+
self.id(),
161+
start_paddr,
162+
ivc_config.shared_mem_ipa
160163
);
161164
let rw_sec_size: usize = ivc_config.rw_sec_size as usize;
162165
let out_sec_size: usize = ivc_config.out_sec_size as usize;
163-
self.gpm
166+
inner
167+
.gpm_mut()
164168
.insert(MemoryRegion::new_with_offset_mapper(
165169
ivc_config.shared_mem_ipa as _,
166170
start_paddr,
@@ -174,7 +178,8 @@ impl Zone {
174178
} else {
175179
MemFlags::READ
176180
};
177-
self.gpm
181+
inner
182+
.gpm_mut()
178183
.insert(MemoryRegion::new_with_offset_mapper(
179184
ivc_config.shared_mem_ipa as usize + rw_sec_size + i * out_sec_size,
180185
start_paddr + rw_sec_size + i * out_sec_size,
@@ -183,7 +188,7 @@ impl Zone {
183188
))
184189
.unwrap();
185190
}
186-
self.mmio_region_register(
191+
inner.mmio_region_register(
187192
ivc_config.control_table_ipa as _,
188193
PAGE_SIZE,
189194
mmio_ivc_handler,
@@ -193,7 +198,9 @@ impl Zone {
193198
return;
194199
}
195200
}
196-
IVC_INFOS.lock().insert(self.id, IvcInfo::from(ivc_configs));
201+
IVC_INFOS
202+
.lock()
203+
.insert(self.id(), IvcInfo::from(ivc_configs));
197204
}
198205
}
199206

‎src/arch/aarch64/trap.rs‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -390,10 +390,10 @@ fn handle_psci_smc(
390390
PsciFnId::PSCI_CPU_ON_32 | PsciFnId::PSCI_CPU_ON_64 => psci_emulate_cpu_on(regs),
391391
PsciFnId::PSCI_SYSTEM_OFF => {
392392
let zone = this_zone();
393-
let zone_id = zone.read().id;
393+
let zone_id = zone.id();
394394
let is_root = is_this_root_zone();
395395

396-
for cpu_id in zone.read().cpu_set.iter_except(this_cpu_data().id) {
396+
for cpu_id in zone.read().cpu_set().iter_except(this_cpu_data().id) {
397397
let target_cpu = get_cpu_data(cpu_id);
398398
let _lock = target_cpu.ctrl_lock.lock();
399399
target_cpu.zone = None;

‎src/arch/aarch64/zone.rs‎

Lines changed: 25 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -26,6 +26,7 @@ use crate::{
2626

2727
impl Zone {
2828
pub fn pt_init(&mut self, mem_regions: &[HvConfigMemoryRegion]) -> HvResult {
29+
let mut inner = self.write();
2930
// The first memory region is used to map the guest physical memory.
3031

3132
for mem_region in mem_regions.iter() {
@@ -35,29 +36,41 @@ impl Zone {
3536
}
3637
match mem_region.mem_type {
3738
MEM_TYPE_RAM | MEM_TYPE_IO => {
38-
self.gpm.insert(MemoryRegion::new_with_offset_mapper(
39-
mem_region.virtual_start as GuestPhysAddr,
40-
mem_region.physical_start as HostPhysAddr,
41-
mem_region.size as _,
42-
flags,
43-
))?
39+
inner
40+
.gpm_mut()
41+
.insert(MemoryRegion::new_with_offset_mapper(
42+
mem_region.virtual_start as GuestPhysAddr,
43+
mem_region.physical_start as HostPhysAddr,
44+
mem_region.size as _,
45+
flags,
46+
))?
4447
}
4548
MEM_TYPE_VIRTIO => {
46-
self.mmio_region_register(
49+
inner.mmio_region_register(
4750
mem_region.physical_start as _,
4851
mem_region.size as _,
4952
mmio_virtio_handler,
5053
mem_region.physical_start as _,
5154
);
5255
}
5356
_ => {
54-
// hvisor-tool will check memory type. So only root linux can reach here.
55-
panic!("Unsupported memory type: {}", mem_region.mem_type)
57+
// hvisor-tool should check memory type in advance.
58+
if self.id() == 0 {
59+
panic!("Unsupported memory type: {}", mem_region.mem_type);
60+
}
61+
return hv_result_err!(
62+
EINVAL,
63+
format!(
64+
"zone {} has unsupported memory type: {}",
65+
self.id(),
66+
mem_region.mem_type
67+
)
68+
);
5669
}
5770
}
5871
}
5972

60-
info!("VM stage 2 memory set: {:#x?}", self.gpm);
73+
info!("VM stage 2 memory set: {:#x?}", inner.gpm());
6174
Ok(())
6275
}
6376

@@ -66,10 +79,11 @@ impl Zone {
6679
mem_regions: &[HvConfigMemoryRegion],
6780
hv_config: &HvArchZoneConfig,
6881
) -> HvResult {
82+
let mut inner = self.write();
6983
// Create a new stage 2 page table for iommu.
7084
// Only map the memory regions that are possible to be accessed by devices as DMA buffer.
7185

72-
let pt = self.iommu_pt.as_mut().unwrap();
86+
let pt = inner.iommu_pt_mut().unwrap();
7387
let flags = MemFlags::READ | MemFlags::WRITE;
7488
for mem_region in mem_regions.iter() {
7589
match mem_region.mem_type {

‎src/arch/loongarch64/cpu.rs‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -169,7 +169,7 @@ pub fn get_target_cpu(irq: usize, zone_id: usize) -> usize {
169169
find_zone(zone_id)
170170
.unwrap()
171171
.read()
172-
.cpu_set
172+
.cpu_set()
173173
.first_cpu()
174174
.unwrap()
175175
}

‎src/arch/loongarch64/trap.rs‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -608,14 +608,14 @@ pub fn _vcpu_return(ctx: usize) {
608608
} else {
609609
// since LVZ use GID=0 for hypervisor TLB, we cannot use zone id 0 here
610610
// so we add it by 1 - wheatfox
611-
vm_id = z.unwrap().read().id + 1;
611+
vm_id = z.unwrap().id() + 1;
612612
}
613613
gstat::set_gid(vm_id);
614614
gstat::set_pgm(true);
615615
trace!(
616616
"loongarch64: _vcpu_return: set hardware Guest ID to {} for zone {}",
617617
vm_id,
618-
z.unwrap().read().id
618+
z.unwrap().id()
619619
);
620620
// Configure guest TLB control
621621
gtlbc::set_use_tgid(true);

‎src/arch/loongarch64/zone.rs‎

Lines changed: 39 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -40,39 +40,46 @@ use spin::Mutex;
4040

4141
impl Zone {
4242
pub fn pt_init(&mut self, mem_regions: &[HvConfigMemoryRegion]) -> HvResult {
43+
let mut inner = self.write();
4344
// use the new zone config type of init
4445
for region in mem_regions {
4546
trace!("loongarch64: pt_init: process region: {:#x?}", region);
4647
let mem_type = region.mem_type;
4748
match mem_type {
4849
MEM_TYPE_RAM => {
49-
self.gpm.insert(MemoryRegion::new_with_offset_mapper(
50-
region.virtual_start as GuestPhysAddr,
51-
region.physical_start as HostPhysAddr,
52-
region.size as _,
53-
MemFlags::READ | MemFlags::WRITE | MemFlags::EXECUTE,
54-
))?;
50+
inner
51+
.gpm_mut()
52+
.insert(MemoryRegion::new_with_offset_mapper(
53+
region.virtual_start as GuestPhysAddr,
54+
region.physical_start as HostPhysAddr,
55+
region.size as _,
56+
MemFlags::READ | MemFlags::WRITE | MemFlags::EXECUTE,
57+
))?;
5558
}
5659
MEM_TYPE_IO => {
57-
self.gpm.insert(MemoryRegion::new_with_offset_mapper(
58-
region.virtual_start as GuestPhysAddr,
59-
region.physical_start as HostPhysAddr,
60-
region.size as _,
61-
MemFlags::READ | MemFlags::WRITE | MemFlags::IO,
62-
))?;
60+
inner
61+
.gpm_mut()
62+
.insert(MemoryRegion::new_with_offset_mapper(
63+
region.virtual_start as GuestPhysAddr,
64+
region.physical_start as HostPhysAddr,
65+
region.size as _,
66+
MemFlags::READ | MemFlags::WRITE | MemFlags::IO,
67+
))?;
6368
}
6469
MEM_TYPE_VIRTIO => {
6570
info!(
6671
"loongarch64: pt_init: register virtio mmio region: {:#x?}",
6772
region
6873
);
69-
self.gpm.insert(MemoryRegion::new_with_offset_mapper(
70-
region.virtual_start as GuestPhysAddr,
71-
region.physical_start as HostPhysAddr,
72-
PAGE_SIZE, // since we only need 0x200 size for virtio mmio, but the minimal size is PAGE_SIZE
73-
MemFlags::USER, // we use the USER as a hint flag for invalidating this stage-2 PTE
74-
))?;
75-
self.mmio_region_register(
74+
inner
75+
.gpm_mut()
76+
.insert(MemoryRegion::new_with_offset_mapper(
77+
region.virtual_start as GuestPhysAddr,
78+
region.physical_start as HostPhysAddr,
79+
PAGE_SIZE, // since we only need 0x200 size for virtio mmio, but the minimal size is PAGE_SIZE
80+
MemFlags::USER, // we use the USER as a hint flag for invalidating this stage-2 PTE
81+
))?;
82+
inner.mmio_region_register(
7683
region.physical_start as _,
7784
region.size as _,
7885
mmio_virtio_handler,
@@ -92,14 +99,14 @@ impl Zone {
9299
// 3. chip configuration
93100

94101
info!("loongarch64: pt_init: add mmio handler for 0x1fe0_xxxx mmio region");
95-
self.mmio_region_register(0x1fe0_0000, 0x3000, loongarch_generic_mmio_handler, 0x1234);
102+
inner.mmio_region_register(0x1fe0_0000, 0x3000, loongarch_generic_mmio_handler, 0x1234);
96103

97-
info!("zone stage-2 memory set: {:#x?}", self.gpm);
104+
info!("zone stage-2 memory set: {:#x?}", inner.gpm());
98105
unsafe {
99106
// test the page table by querying the first page
100107
if mem_regions.len() > 0 {
101-
let r = self
102-
.gpm
108+
let r = inner
109+
.gpm()
103110
.page_table_query(mem_regions[0].virtual_start as GuestPhysAddr);
104111
debug!("query 0x{:x}: {:#x?}", mem_regions[0].virtual_start, r);
105112
// check whether the first page is mapped
@@ -674,13 +681,15 @@ pub fn loongarch_generic_mmio_handler(mmio: &mut MMIOAccess, arg: usize) -> HvRe
674681

675682
impl Zone {
676683
pub fn page_table_emergency(&mut self, vaddr: usize, size: usize) -> HvResult {
677-
self.gpm.insert(MemoryRegion::new_with_offset_mapper(
678-
vaddr as GuestPhysAddr,
679-
vaddr as HostPhysAddr,
680-
size as _,
681-
MemFlags::READ | MemFlags::WRITE | MemFlags::IO,
682-
))?;
683-
self.gpm.delete(vaddr as GuestPhysAddr, size)
684+
self.write()
685+
.gpm_mut()
686+
.insert(MemoryRegion::new_with_offset_mapper(
687+
vaddr as GuestPhysAddr,
688+
vaddr as HostPhysAddr,
689+
size as _,
690+
MemFlags::READ | MemFlags::WRITE | MemFlags::IO,
691+
))?;
692+
self.write().gpm_mut().delete(vaddr as GuestPhysAddr, size)
684693
}
685694

686695
pub fn arch_zone_pre_configuration(&mut self, config: &HvZoneConfig) -> HvResult {

‎src/arch/riscv64/cpu.rs‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -247,7 +247,7 @@ pub fn get_target_cpu(_irq: usize, zone_id: usize) -> usize {
247247
find_zone(zone_id)
248248
.unwrap()
249249
.read()
250-
.cpu_set
250+
.cpu_set()
251251
.first_cpu()
252252
.unwrap()
253253
}

‎src/arch/riscv64/zone.rs‎

Lines changed: 11 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -22,6 +22,7 @@ use crate::{
2222
};
2323
impl Zone {
2424
pub fn pt_init(&mut self, mem_regions: &[HvConfigMemoryRegion]) -> HvResult {
25+
let mut inner = self.write();
2526
for mem_region in mem_regions.iter() {
2627
let mut flags = MemFlags::READ | MemFlags::WRITE;
2728
// Note: in riscv, base flags are D/A/G/U/W/X, some mem attributes are embedded in the PMA.
@@ -31,15 +32,17 @@ impl Zone {
3132
}
3233
match mem_region.mem_type {
3334
MEM_TYPE_RAM | MEM_TYPE_IO => {
34-
self.gpm.insert(MemoryRegion::new_with_offset_mapper(
35-
mem_region.virtual_start as GuestPhysAddr,
36-
mem_region.physical_start as HostPhysAddr,
37-
mem_region.size as _,
38-
flags,
39-
))?
35+
inner
36+
.gpm_mut()
37+
.insert(MemoryRegion::new_with_offset_mapper(
38+
mem_region.virtual_start as GuestPhysAddr,
39+
mem_region.physical_start as HostPhysAddr,
40+
mem_region.size as _,
41+
flags,
42+
))?
4043
}
4144
MEM_TYPE_VIRTIO => {
42-
self.mmio_region_register(
45+
inner.mmio_region_register(
4346
mem_region.physical_start as _,
4447
mem_region.size as _,
4548
mmio_virtio_handler,
@@ -51,7 +54,7 @@ impl Zone {
5154
}
5255
}
5356
}
54-
info!("VM stage 2 memory set: {:#x?}", self.gpm);
57+
info!("VM stage 2 memory set: {:#x?}", inner.gpm());
5558
Ok(())
5659
}
5760

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