From ced534b927160fface0345a1f1e5ed9e241be82c Mon Sep 17 00:00:00 2001 From: sanmalho Date: Fri, 12 Nov 2021 12:24:53 -0500 Subject: [PATCH 1/3] Fixes to support minigraph generation for linecards in a VoQ Chassis PR# 4479 added support for minigraph generation for packet based chassis. However, this broke the generated minigraph for linecards in a VoQ chassis. There were two issues in the minigraph generated with PR #4479: - In Cpg - Missing BGPRouterDeclaration section for remote asics - -ASIC<#> - For multi-asic linecard, missing BGPRouterDeclaraion section for my asics - ASIC<#> - In Dpg, we are missing the DeviceDataPlaneInfo for my asics in a multi-asic linecard - This is generated in template_dpg_asic, which is dependent on asic_topo_config. For voq_chassis, asic_topo_config is empty dictionary - as the iBGP connections depend on the what linecards are present in the chassis, and also what asics are on each linecard. To fix the above issues: - create an almost empty asic topology file for our multi-asic linecard with slot0. - In config_sonic_basedon_testbed.yml, when dealing with voq switch_type, before running through the Jinja2 templates, change slot0 in the asic_topo_config to the slot_num that is defined in the inventory. Below is the asic topology for our multi-asic linecard Nokia_IXR7250e_36x400G card (in vars/topo_Nokia_IXR7250e_36x400G.yml) that I prototyped with: slot0: ASIC0: topology: NEIGH_ASIC: configuration_properties: common: asic_type: FrontEnd configuration: ASIC1: topology: NEIGH_ASIC: configuration_properties: common: asic_type: FrontEnd configuration: --- ansible/config_sonic_basedon_testbed.yml | 11 ++++ ansible/library/topo_facts.py | 3 +- ansible/templates/minigraph_cpg.j2 | 57 ++++++++------------ ansible/vars/topo_Nokia-IXR7250E-36x400G.yml | 16 ++++++ 4 files changed, 51 insertions(+), 36 deletions(-) create mode 100644 ansible/vars/topo_Nokia-IXR7250E-36x400G.yml diff --git a/ansible/config_sonic_basedon_testbed.yml b/ansible/config_sonic_basedon_testbed.yml index c035c6f7aea..3acb0fc6b19 100644 --- a/ansible/config_sonic_basedon_testbed.yml +++ b/ansible/config_sonic_basedon_testbed.yml @@ -235,6 +235,17 @@ - "ports" when: front_panel_asic_ifnames != [] + - block: + - name: Create new dictionary for my slot + set_fact: + new_asic_topo_config : "{{ new_asic_topo_config | default( { slot_num : asic_topo_config.slot0 }) }}" + + - name: set asic_topo_config to new dictionary + set_fact: + asic_topo_config: "{{ new_asic_topo_config }}" + + when: switch_type is defined and switch_type == 'voq' and slot_num is defined and asic_topo_config|length > 0 + - name: create minigraph file in ansible minigraph folder template: src=templates/minigraph_template.j2 dest=minigraph/{{ inventory_hostname}}.{{ topo }}.xml diff --git a/ansible/library/topo_facts.py b/ansible/library/topo_facts.py index 00462542b65..f0f055a8fb1 100644 --- a/ansible/library/topo_facts.py +++ b/ansible/library/topo_facts.py @@ -84,6 +84,8 @@ def __init__(self): def parse_topo_defintion(self, topo_definition, po_map, dut_num, neigh_type='VMs'): vmconfig = dict() + if topo_definition['topology'][neigh_type] is None: + return vmconfig for vm in topo_definition['topology'][neigh_type]: vmconfig[vm] = dict() vmconfig[vm]['intfs'] = [[] for i in range(dut_num)] @@ -105,7 +107,6 @@ def parse_topo_defintion(self, topo_definition, po_map, dut_num, neigh_type='VMs for asic_intf in topo_definition['topology'][neigh_type][vm]['asic_intfs']: vmconfig[vm]['asic_intfs'][dut_index].append(asic_intf) - # physical interface if 'configuration' in topo_definition: if 'interfaces' in topo_definition['configuration'][vm]: diff --git a/ansible/templates/minigraph_cpg.j2 b/ansible/templates/minigraph_cpg.j2 index ac5857e74f1..c26735d4437 100644 --- a/ansible/templates/minigraph_cpg.j2 +++ b/ansible/templates/minigraph_cpg.j2 @@ -1,4 +1,4 @@ - + {% if card_type is not defined or card_type != 'supervisor' %} @@ -216,6 +216,21 @@ {% endif %} {% endfor %} +{% if switch_type is defined and switch_type == 'voq' %} +{% set asic_id = asic.split('ASIC')[1]|int %} +{% for a_linecard in all_loopback4096 %} +{% for idx in range(all_loopback4096[a_linecard]|length) %} +{% if loopback4096_ip[asic_id] != all_loopback4096[a_linecard][idx] %} + +
{{ all_inbands[a_linecard][idx] }}
+ + + + +{% endif %} +{% endfor %} +{% endfor %} +{% else %} {% for neigh_asic in asic_config['neigh_asic'] %} {% if neigh_asic in asic_config['neigh_asic'] and asic_config['neigh_asic'][neigh_asic]['peer_ipv4'][0] %} @@ -226,56 +241,28 @@ {% endif %} {% endfor %} +{% endif %} {% endfor %} +{% endif %} {% if switch_type is defined and (switch_type == 'voq' or switch_type == 'chassis-packet') %} {% for a_linecard in all_loopback4096 %} {% if a_linecard != inventory_hostname %} {% for idx in range(all_loopback4096[a_linecard]|length) %} {{ vm_topo_config['dut_asn'] }} +{% if switch_type == 'voq' %} + {{ chassis_ibgp_peers[all_inbands[a_linecard][idx].split('/')[0]] }} +{% else %} {{ chassis_ibgp_peers[all_loopback4096[a_linecard][idx].split('/')[0]] }} +{% endif %} {% endfor %} {% endif %} {% endfor %} -{% if num_asics > 1 %} -{% for asic_id in range(num_asics) %} -{% set asic_name = "ASIC" + asic_id|string %} - - {{ vm_topo_config['dut_asn'] }} - {{ asic_name }} - -{% for index in range( vms_number) %} -{% if vms[index] in vm_asic_ifnames and vm_asic_ifnames[vms[index]][0].split('-')[1] == asic_name %} - -
{{ vm_topo_config['vm'][vms[index]]['peer_ipv4'][dut_index|int] }}
- - - - -{% endif %} -{% endfor %} -{% for a_linecard in all_loopback4096 %} -{% for idx in range(all_loopback4096[a_linecard]|length) %} -{% if loopback4096_ip[asic_id] != all_loopback4096[a_linecard][idx] %} - -
{{ all_loopback4096[a_linecard][idx] }}
- - - - -{% endif %} -{% endfor %} -{% endfor %} - - -{% endfor %} -{% endif %} -{% endif %} {% endif %} {% endif %} diff --git a/ansible/vars/topo_Nokia-IXR7250E-36x400G.yml b/ansible/vars/topo_Nokia-IXR7250E-36x400G.yml new file mode 100644 index 00000000000..a3a459c097c --- /dev/null +++ b/ansible/vars/topo_Nokia-IXR7250E-36x400G.yml @@ -0,0 +1,16 @@ +slot0: + ASIC0: + topology: + NEIGH_ASIC: + configuration_properties: + common: + asic_type: FrontEnd + configuration: + + ASIC1: + topology: + NEIGH_ASIC: + configuration_properties: + common: + asic_type: FrontEnd + configuration: From e27fc235058e58a1221ba454f66b0172ec81a41f Mon Sep 17 00:00:00 2001 From: sanmalho Date: Mon, 15 Nov 2021 15:57:46 -0500 Subject: [PATCH 2/3] Make all port channels names padded with one zero In minigraph_dpg_asic.j2 we are making port channel names be zero padded with upto 2 zeros with 'zfill(2)' - example: PortChannel02 However, in minigraph_dpg.j2, the padded is upto 4 zeros with 'zfill(4)' - example: PortChannel0002 This causes mismatch in the minigraph for the port channels in the host DeviceDataPlaneInfo vs asic DeviceDataPlaneInfo. Fix is to use 'zfill(2)' in minigraph_dpg.j2 as well, instead of 'zfill(4)'. --- ansible/templates/minigraph_dpg.j2 | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/ansible/templates/minigraph_dpg.j2 b/ansible/templates/minigraph_dpg.j2 index 1354f719c61..8a6b012c6ec 100644 --- a/ansible/templates/minigraph_dpg.j2 +++ b/ansible/templates/minigraph_dpg.j2 @@ -108,7 +108,7 @@ {% if 'port-channel' in vm_topo_config['vm'][vms[index]]['ip_intf'][dut_index|int]|lower %} {% set port_channel_intf=';'.join(intf_names[vms[index]]) %} - PortChannel{{ ((index+1)|string).zfill(4) }} + PortChannel{{ ((index+1)|string).zfill(2) }} {{ port_channel_intf }} @@ -171,7 +171,7 @@ {% if 'port-channel' in vm_topo_config['vm'][vms[index]]['ip_intf'][dut_index|int]|lower %} - PortChannel{{ ((index+1) |string).zfill(4) }} + PortChannel{{ ((index+1) |string).zfill(2) }} {% else %} {{ port_alias[vm_topo_config['vm'][vms[index]]['interface_indexes'][dut_index|int][0]] }} {% endif %} @@ -180,7 +180,7 @@ {% if 'port-channel' in vm_topo_config['vm'][vms[index]]['ip_intf'][dut_index|int]|lower %} - PortChannel{{ ((index+1) |string).zfill(4) }} + PortChannel{{ ((index+1) |string).zfill(2) }} {% else %} {{ port_alias[vm_topo_config['vm'][vms[index]]['interface_indexes'][dut_index|int][0]] }} {% endif %} @@ -242,7 +242,7 @@ {%- set acl_intfs = [] -%} {%- for index in range(vms_number) %} {% if 'port-channel' in vm_topo_config['vm'][vms[index]]['ip_intf'][dut_index|int]|lower %} -{% set a_intf = 'PortChannel' + ((index+1) |string).zfill(4) %} +{% set a_intf = 'PortChannel' + ((index+1) |string).zfill(2) %} {{- acl_intfs.append(a_intf) -}} {% endif %} {% endfor %} From e1a8ddffe9b87885a4b9da53309feae0c00a2026 Mon Sep 17 00:00:00 2001 From: sanmalho Date: Wed, 24 Nov 2021 17:56:43 -0500 Subject: [PATCH 3/3] Revert "Make all port channels names padded with one zero" This reverts commit e27fc235058e58a1221ba454f66b0172ec81a41f. --- ansible/templates/minigraph_dpg.j2 | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/ansible/templates/minigraph_dpg.j2 b/ansible/templates/minigraph_dpg.j2 index 8a6b012c6ec..1354f719c61 100644 --- a/ansible/templates/minigraph_dpg.j2 +++ b/ansible/templates/minigraph_dpg.j2 @@ -108,7 +108,7 @@ {% if 'port-channel' in vm_topo_config['vm'][vms[index]]['ip_intf'][dut_index|int]|lower %} {% set port_channel_intf=';'.join(intf_names[vms[index]]) %} - PortChannel{{ ((index+1)|string).zfill(2) }} + PortChannel{{ ((index+1)|string).zfill(4) }} {{ port_channel_intf }} @@ -171,7 +171,7 @@ {% if 'port-channel' in vm_topo_config['vm'][vms[index]]['ip_intf'][dut_index|int]|lower %} - PortChannel{{ ((index+1) |string).zfill(2) }} + PortChannel{{ ((index+1) |string).zfill(4) }} {% else %} {{ port_alias[vm_topo_config['vm'][vms[index]]['interface_indexes'][dut_index|int][0]] }} {% endif %} @@ -180,7 +180,7 @@ {% if 'port-channel' in vm_topo_config['vm'][vms[index]]['ip_intf'][dut_index|int]|lower %} - PortChannel{{ ((index+1) |string).zfill(2) }} + PortChannel{{ ((index+1) |string).zfill(4) }} {% else %} {{ port_alias[vm_topo_config['vm'][vms[index]]['interface_indexes'][dut_index|int][0]] }} {% endif %} @@ -242,7 +242,7 @@ {%- set acl_intfs = [] -%} {%- for index in range(vms_number) %} {% if 'port-channel' in vm_topo_config['vm'][vms[index]]['ip_intf'][dut_index|int]|lower %} -{% set a_intf = 'PortChannel' + ((index+1) |string).zfill(2) %} +{% set a_intf = 'PortChannel' + ((index+1) |string).zfill(4) %} {{- acl_intfs.append(a_intf) -}} {% endif %} {% endfor %}