[chassis] [single-asic] Generate correct minigraph for single-asic card (#7797)

* Update port_alias.py to support single-asic

Author: wenyiz2021

ansible/library/port_alias.py

@@ -169,8 +169,10 @@ def get_portmap(self, asic_id=None, include_internal=False,
                         aliasmap[alias] = name
                         if role == "Ext" and (asic_name_index != -1) and (len(mapping) > asic_name_index):
                             asicifname = mapping[asic_name_index]
-                            front_panel_asic_ifnames[alias] = asicifname
-                            front_panel_asic_id[alias] = "ASIC0" if asic_id is None else "ASIC" + str(asic_id)
+                            # we only want following ASIC info in minigraph for multi-asic
+                            if asic_id is not None:
+                                front_panel_asic_ifnames[alias] = asicifname
+                                front_panel_asic_id[alias] = "ASIC" + str(asic_id)
                     if (asic_name_index != -1) and (len(mapping) > asic_name_index):
                         asicifname = mapping[asic_name_index]
                         asic_if_names.append(asicifname)