|
236 | 236 | u'MMU_THDM_MCQE_QUEUE_OFFSET_PIPE0.mmu_xpe0', u'ING_SNAT.ipipe0', |
237 | 237 | u'MMU_THDM_MCQE_QUEUE_OFFSET_B_PIPE1.mmu_xpe0', u'MMU_THDU_OFFSET_QGROUP_PIPE3.mmu_xpe0', |
238 | 238 | u'ING_VP_VLAN_MEMBERSHIP.ipipe0', u'MMU_THDU_CONFIG_PORT_PIPE3.mmu_xpe0', u'FP_GLOBAL_MASK_TCAM.ipipe0', |
| 239 | + ], |
| 240 | + 'th3' : [ |
| 241 | + # cannot pass |
| 242 | + u'L3_DEFIP_TCAM_LEVEL1.ipipe0', |
| 243 | + u'MATCH_LOGICAL_TABLE_SELECT_PIPE7.ipipe0', |
| 244 | + u'EXACT_MATCH_LOGICAL_TABLE_SELECT_PIPE7.ipipe0', |
| 245 | + u'MMU_QSCH_L2_WEIGHT_MEM_PIPE7.mmu_eb0', |
| 246 | + u'L3_ENTRY_ONLY_SINGLE.ipipe0', |
| 247 | + u'IFP_LOGICAL_TABLE_SELECT_PIPE6.ipipe0', |
| 248 | + u'MMU_QSCH_L2_WEIGHT_MEM_PIPE3.mmu_eb0', |
| 249 | + u'IFP_LOGICAL_TABLE_SELECT_PIPE0.ipipe0', |
| 250 | + u'L3_ENTRY_SINGLE.ipipe0', |
| 251 | + u'L2_ENTRY.ipipe0', |
| 252 | + u'EXACT_MATCH_LOGICAL_TABLE_SELECT_PIPE6.ipipe0', |
| 253 | + u'EXACT_MATCH_LOGICAL_TABLE_SELECT_PIPE0.ipipe0', |
| 254 | + u'L3_DEFIP_ALPM_LEVEL3.ipipe0', |
| 255 | + u'L3_ENTRY_DOUBLE.ipipe0', |
| 256 | + u'L3_TUNNEL_QUAD.ipipe0', |
| 257 | + u'L3_DEFIP_PAIR_LEVEL1.ipipe0', |
| 258 | + u'EXACT_MATCH_LOGICAL_TABLE_SELECT.ipipe0', |
| 259 | + u'EXACT_MATCH_LOGICAL_TABLE_SELECT_PIPE3.ipipe0', |
| 260 | + u'EXACT_MATCH_LOGICAL_TABLE_SELECT_PIPE1.ipipe0', |
| 261 | + u'L3_ENTRY_ONLY_DOUBLE.ipipe0', |
| 262 | + u'MMU_QSCH_L2_WEIGHT_MEM_PIPE0.mmu_eb0', |
| 263 | + u'L3_DEFIP_ALPM_LEVEL2.ipipe0', |
| 264 | + u'EGR_IP_TUNNEL_IPV6.epipe0', |
| 265 | + u'EXACT_MATCH_ECC.ipipe0', |
| 266 | + u'IFP_LOGICAL_TABLE_SELECT_PIPE3.ipipe0', |
| 267 | + u'EXACT_MATCH_LOGICAL_TABLE_SELECT_PIPE5.ipipe0', |
| 268 | + u'L3_DEFIP_ALPM_LEVEL3_SINGLE.ipipe0', |
| 269 | + u'IFP_LOGICAL_TABLE_SELECT.ipipe0', |
| 270 | + u'MMU_QSCH_L2_WEIGHT_MEM_PIPE5.mmu_eb0', |
| 271 | + u'IFP_LOGICAL_TABLE_SELECT_PIPE2.ipipe0', |
| 272 | + u'EXACT_MATCH_LOGICAL_TABLE_SELECT_PIPE2.ipipe0', |
| 273 | + u'L3_ENTRY_QUAD.ipipe0', |
| 274 | + u'IFP_LOGICAL_TABLE_SELECT_PIPE1.ipipe0', |
| 275 | + u'EGR_IP_TUNNEL_MPLS.epipe0', |
| 276 | + u'IFP_LOGICAL_TABLE_SELECT_PIPE5.ipipe0', |
| 277 | + u'MMU_QSCH_L2_WEIGHT_MEM_PIPE4.mmu_eb0', |
| 278 | + u'L2_USER_ENTRY.ipipe0', |
| 279 | + u'MMU_QSCH_L2_WEIGHT_MEM_PIPE6.mmu_eb0', |
| 280 | + u'MY_STATION_TCAM.ipipe0', |
| 281 | + u'IFP_LOGICAL_TABLE_SELECT_PIPE4.ipipe0', |
| 282 | + u'L3_DEFIP_LEVEL1.ipipe0' , |
| 283 | + u'MMU_QSCH_L2_WEIGHT_MEM_PIPE2.mmu_eb0', |
| 284 | + u'L3_DEFIP_ALPM_LEVEL2_SINGLE.ipipe0', |
| 285 | + u'L3_TUNNEL_DOUBLE.ipipe0', |
| 286 | + u'L3_ENTRY_ONLY_QUAD.ipipe0', |
| 287 | + u'IFP_LOGICAL_TABLE_SELECT_PIPE7.ipipe0', |
| 288 | + u'MMU_QSCH_L2_WEIGHT_MEM_PIPE1.mmu_eb0', |
| 289 | + u'MPLS_ENTRY_SINGLE.ipipe0', |
| 290 | + u'CPU_COS_MAP.ipipe0', |
| 291 | + u'L3_TUNNEL_SINGLE.ipipe0', |
| 292 | + u'L3_DEFIP_ALPM_LEVEL2_HIT_ONLY.ipipe0', |
| 293 | + u'L2_ENTRY_ONLY_SINGLE.ipipe0', |
| 294 | + u'L3_DEFIP_LEVEL1_HIT_ONLY.ipipe0', |
| 295 | + u'EXACT_MATCH_LOGICAL_TABLE_SELECT_PIPE4.ipipe0', |
| 296 | + u'L3_DEFIP_ALPM_LEVEL3_HIT_ONLY.ipipe0' |
| 297 | + |
| 298 | + ] |
| 299 | + |
239 | 300 | ] |
240 | 301 | } |
241 | 302 |
|
@@ -273,6 +334,8 @@ def get_asic_name(): |
273 | 334 | asic = "td2" |
274 | 335 | elif "Broadcom Limited Device b870" in output: |
275 | 336 | asic = "td3" |
| 337 | + elif "Broadcom Limited Device b980" in output: |
| 338 | + asic = "th3" |
276 | 339 |
|
277 | 340 | return asic |
278 | 341 |
|
|
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