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Shuotian Cheng
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[topology]: Fix t1-64-lag topology device link base indices (#414)
This piece of information is used in the LLDP test. Signed-off-by: Shu0T1an ChenG <shuche@microsoft.com>
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ansible/templates/topo/t1-64-lag.j2

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -324,35 +324,35 @@
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<ElementType>DeviceInterfaceLink</ElementType>
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<EndDevice>{{ inventory_hostname }}</EndDevice>
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<EndPort>{{ port_alias[32+index*8+2] }}</EndPort>
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<StartDevice>ARISTA{{ '%02d' % (index+1) }}T0</StartDevice>
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<StartDevice>ARISTA{{ '%02d' % (index*5+1) }}T0</StartDevice>
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<StartPort>Ethernet1</StartPort>
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</DeviceLinkBase>
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<DeviceLinkBase>
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<ElementType>DeviceInterfaceLink</ElementType>
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<EndDevice>{{ inventory_hostname }}</EndDevice>
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<EndPort>{{ port_alias[32+index*8+2] }}</EndPort>
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<StartDevice>ARISTA{{ '%02d' % (index+1) }}T0</StartDevice>
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<EndPort>{{ port_alias[32+index*8+4] }}</EndPort>
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<StartDevice>ARISTA{{ '%02d' % (index*5+2) }}T0</StartDevice>
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<StartPort>Ethernet1</StartPort>
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</DeviceLinkBase>
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<DeviceLinkBase>
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<ElementType>DeviceInterfaceLink</ElementType>
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<EndDevice>{{ inventory_hostname }}</EndDevice>
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<EndPort>{{ port_alias[32+index*8+5] }}</EndPort>
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<StartDevice>ARISTA{{ '%02d' % (index+1) }}T0</StartDevice>
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<StartDevice>ARISTA{{ '%02d' % (index*5+3) }}T0</StartDevice>
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<StartPort>Ethernet1</StartPort>
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</DeviceLinkBase>
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<DeviceLinkBase>
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<ElementType>DeviceInterfaceLink</ElementType>
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<EndDevice>{{ inventory_hostname }}</EndDevice>
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<EndPort>{{ port_alias[32+index*8+6] }}</EndPort>
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<StartDevice>ARISTA{{ '%02d' % (index+1) }}T0</StartDevice>
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<StartDevice>ARISTA{{ '%02d' % (index*5+4) }}T0</StartDevice>
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<StartPort>Ethernet1</StartPort>
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</DeviceLinkBase>
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<DeviceLinkBase>
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<ElementType>DeviceInterfaceLink</ElementType>
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<EndDevice>{{ inventory_hostname }}</EndDevice>
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<EndPort>{{ port_alias[32+index*8+7] }}</EndPort>
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<StartDevice>ARISTA{{ '%02d' % (index+1) }}T0</StartDevice>
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<StartDevice>ARISTA{{ '%02d' % (index*5+5) }}T0</StartDevice>
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<StartPort>Ethernet1</StartPort>
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</DeviceLinkBase>
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{% endfor %}

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