From 60068b85e418e7ee61c44f4165a5d8626ebd0f9e Mon Sep 17 00:00:00 2001 From: Roy Wen Date: Tue, 30 Sep 2025 15:29:31 -0400 Subject: [PATCH 01/13] add device dir for nh-5010 --- .../BALANCED/buffers.json.j2 | 2 + .../BALANCED/buffers_defaults_t2.j2 | 47 + .../BALANCED/pg_profile_lookup.ini | 17 + .../NH-5010-F-O32-C32/BALANCED/qos.json.j2 | 4 + .../NH-5010-F-O32-C32/agera2.bcm | 801 + .../NH-5010-F-O32-C32/buffer_ports.j2 | 6 + .../NH-5010-F-O32-C32/buffers.json.j2 | 2 + .../NH-5010-F-O32-C32/buffers_defaults_t2.j2 | 52 + .../NH-5010-F-O32-C32/context_config.json | 98 + .../NH-5010-F-O32-C32/gearbox_config.json | 438 + .../NH-5010-F-O32-C32/hwsku.json | 334 + .../NH-5010-F-O32-C32/nh5010-default.bcm | 2260 ++ .../NH-5010-F-O32-C32/phy0_config.json | 59 + .../NH-5010-F-O32-C32/phy10_config.json | 59 + .../NH-5010-F-O32-C32/phy11_config.json | 59 + .../NH-5010-F-O32-C32/phy12_config.json | 59 + .../NH-5010-F-O32-C32/phy13_config.json | 59 + .../NH-5010-F-O32-C32/phy14_config.json | 59 + .../NH-5010-F-O32-C32/phy15_config.json | 59 + .../NH-5010-F-O32-C32/phy1_config.json | 59 + .../NH-5010-F-O32-C32/phy2_config.json | 59 + .../NH-5010-F-O32-C32/phy3_config.json | 59 + .../NH-5010-F-O32-C32/phy4_config.json | 59 + .../NH-5010-F-O32-C32/phy5_config.json | 59 + .../NH-5010-F-O32-C32/phy6_config.json | 59 + .../NH-5010-F-O32-C32/phy7_config.json | 59 + .../NH-5010-F-O32-C32/phy8_config.json | 59 + .../NH-5010-F-O32-C32/phy9_config.json | 59 + .../NH-5010-F-O32-C32/port_config.ini | 68 + .../NH-5010-F-O32-C32/psai.profile | 1 + .../NH-5010-F-O32-C32/qos.json.j2 | 172 + .../NH-5010-F-O32-C32/sai.profile | 2 + .../NH-5010-F-O64/BALANCED/buffers.json.j2 | 2 + .../BALANCED/buffers_defaults_t2.j2 | 47 + .../BALANCED/pg_profile_lookup.ini | 17 + .../NH-5010-F-O64/BALANCED/qos.json.j2 | 4 + .../NH-5010-F-O64/agera2.bcm | 801 + .../NH-5010-F-O64/buffer_ports.j2 | 6 + .../NH-5010-F-O64/buffers.json.j2 | 2 + .../NH-5010-F-O64/buffers_defaults_t2.j2 | 52 + .../NH-5010-F-O64/context_config.json | 98 + .../NH-5010-F-O64/gearbox_config.json | 438 + .../NH-5010-F-O64/hwsku.json | 334 + .../NH-5010-F-O64/media_settings.json | 1284 ++ .../NH-5010-F-O64/nh5010-default.bcm | 2260 ++ .../NH-5010-F-O64/phy0_config.json | 59 + .../NH-5010-F-O64/phy10_config.json | 59 + .../NH-5010-F-O64/phy11_config.json | 59 + .../NH-5010-F-O64/phy12_config.json | 59 + .../NH-5010-F-O64/phy13_config.json | 59 + .../NH-5010-F-O64/phy14_config.json | 59 + .../NH-5010-F-O64/phy15_config.json | 59 + .../NH-5010-F-O64/phy1_config.json | 59 + .../NH-5010-F-O64/phy2_config.json | 59 + .../NH-5010-F-O64/phy3_config.json | 59 + .../NH-5010-F-O64/phy4_config.json | 59 + .../NH-5010-F-O64/phy5_config.json | 59 + .../NH-5010-F-O64/phy6_config.json | 59 + .../NH-5010-F-O64/phy7_config.json | 59 + .../NH-5010-F-O64/phy8_config.json | 59 + .../NH-5010-F-O64/phy9_config.json | 59 + .../NH-5010-F-O64/port_config.ini | 68 + .../NH-5010-F-O64/psai.profile | 1 + .../NH-5010-F-O64/qos.json.j2 | 172 + .../NH-5010-F-O64/sai.profile | 2 + .../x86_64-nexthop_5010-r0/default_sku | 1 + .../x86_64-nexthop_5010-r0/gbsyncd.ini | 1 + .../x86_64-nexthop_5010-r0/installer.conf | 1 + .../pcie-variables.yaml | 41 + .../nexthop/x86_64-nexthop_5010-r0/pcie.yaml | 1 + .../x86_64-nexthop_5010-r0/pcie.yaml.j2 | 141 + .../pddf/pd-plugin.json | 78 + .../pddf/pddf-device.json | 3 + .../pddf/pddf-device.json.j2 | 16953 ++++++++++++++++ .../x86_64-nexthop_5010-r0/pddf_support | 0 .../x86_64-nexthop_5010-r0/platform.json | 921 + .../x86_64-nexthop_5010-r0/platform_asic | 1 + .../platform_components.json | 15 + .../x86_64-nexthop_5010-r0/platform_env.conf | 4 + .../plugins/led_control.py | 9 + .../pmon_daemon_control.json | 5 + .../system_health_monitoring_config.json | 14 + .../thermal_policy.json | 101 + 83 files changed, 30070 insertions(+) create mode 100644 device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/BALANCED/buffers.json.j2 create mode 100644 device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/BALANCED/buffers_defaults_t2.j2 create mode 100644 device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/BALANCED/pg_profile_lookup.ini create mode 100644 device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/BALANCED/qos.json.j2 create mode 100644 device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/agera2.bcm create mode 100644 device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/buffer_ports.j2 create mode 100644 device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/buffers.json.j2 create mode 100644 device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/buffers_defaults_t2.j2 create mode 100644 device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/context_config.json create mode 100644 device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/gearbox_config.json create mode 100644 device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/hwsku.json create mode 100644 device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/nh5010-default.bcm create mode 100644 device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/phy0_config.json create mode 100644 device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/phy10_config.json create mode 100644 device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/phy11_config.json create mode 100644 device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/phy12_config.json create mode 100644 device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/phy13_config.json create mode 100644 device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/phy14_config.json create mode 100644 device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/phy15_config.json create mode 100644 device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/phy1_config.json create mode 100644 device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/phy2_config.json create mode 100644 device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/phy3_config.json create mode 100644 device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/phy4_config.json create mode 100644 device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/phy5_config.json create mode 100644 device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/phy6_config.json create mode 100644 device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/phy7_config.json create mode 100644 device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/phy8_config.json create mode 100644 device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/phy9_config.json create mode 100644 device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/port_config.ini create mode 100644 device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/psai.profile create mode 100644 device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/qos.json.j2 create mode 100644 device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/sai.profile create mode 100644 device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/BALANCED/buffers.json.j2 create mode 100644 device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/BALANCED/buffers_defaults_t2.j2 create mode 100644 device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/BALANCED/pg_profile_lookup.ini create mode 100644 device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/BALANCED/qos.json.j2 create mode 100644 device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/agera2.bcm create mode 100644 device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/buffer_ports.j2 create mode 100644 device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/buffers.json.j2 create mode 100644 device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/buffers_defaults_t2.j2 create mode 100644 device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/context_config.json create mode 100644 device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/gearbox_config.json create mode 100644 device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/hwsku.json create mode 100644 device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/media_settings.json create mode 100644 device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/nh5010-default.bcm create mode 100644 device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/phy0_config.json create mode 100644 device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/phy10_config.json create mode 100644 device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/phy11_config.json create mode 100644 device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/phy12_config.json create mode 100644 device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/phy13_config.json create mode 100644 device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/phy14_config.json create mode 100644 device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/phy15_config.json create mode 100644 device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/phy1_config.json create mode 100644 device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/phy2_config.json create mode 100644 device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/phy3_config.json create mode 100644 device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/phy4_config.json create mode 100644 device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/phy5_config.json create mode 100644 device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/phy6_config.json create mode 100644 device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/phy7_config.json create mode 100644 device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/phy8_config.json create mode 100644 device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/phy9_config.json create mode 100644 device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/port_config.ini create mode 100644 device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/psai.profile create mode 100644 device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/qos.json.j2 create mode 100644 device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/sai.profile create mode 100644 device/nexthop/x86_64-nexthop_5010-r0/default_sku create mode 100644 device/nexthop/x86_64-nexthop_5010-r0/gbsyncd.ini create mode 100644 device/nexthop/x86_64-nexthop_5010-r0/installer.conf create mode 100644 device/nexthop/x86_64-nexthop_5010-r0/pcie-variables.yaml create mode 100644 device/nexthop/x86_64-nexthop_5010-r0/pcie.yaml create mode 100644 device/nexthop/x86_64-nexthop_5010-r0/pcie.yaml.j2 create mode 100644 device/nexthop/x86_64-nexthop_5010-r0/pddf/pd-plugin.json create mode 100644 device/nexthop/x86_64-nexthop_5010-r0/pddf/pddf-device.json create mode 100644 device/nexthop/x86_64-nexthop_5010-r0/pddf/pddf-device.json.j2 create mode 100644 device/nexthop/x86_64-nexthop_5010-r0/pddf_support create mode 100644 device/nexthop/x86_64-nexthop_5010-r0/platform.json create mode 100644 device/nexthop/x86_64-nexthop_5010-r0/platform_asic create mode 100644 device/nexthop/x86_64-nexthop_5010-r0/platform_components.json create mode 100644 device/nexthop/x86_64-nexthop_5010-r0/platform_env.conf create mode 100644 device/nexthop/x86_64-nexthop_5010-r0/plugins/led_control.py create mode 100644 device/nexthop/x86_64-nexthop_5010-r0/pmon_daemon_control.json create mode 100644 device/nexthop/x86_64-nexthop_5010-r0/system_health_monitoring_config.json create mode 100644 device/nexthop/x86_64-nexthop_5010-r0/thermal_policy.json diff --git a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/BALANCED/buffers.json.j2 b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/BALANCED/buffers.json.j2 new file mode 100644 index 00000000000..f34a844f4a8 --- /dev/null +++ b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/BALANCED/buffers.json.j2 @@ -0,0 +1,2 @@ +{%- set default_topo = 't2' %} +{%- include 'buffers_config.j2' %} diff --git a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/BALANCED/buffers_defaults_t2.j2 b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/BALANCED/buffers_defaults_t2.j2 new file mode 100644 index 00000000000..b13d888689d --- /dev/null +++ b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/BALANCED/buffers_defaults_t2.j2 @@ -0,0 +1,47 @@ +{%- set default_cable = '300m' %} + +{%- set ports2cable = { + 'torrouter_server' : '300m', + 'leafrouter_torrouter' : '300m', + 'spinerouter_leafrouter' : '300m', + 'regionalhub_spinerouter': '300m', + 'aznghub_spinerouter' : '300m' + } +-%} + +{%- macro generate_port_lists(PORT_ALL) %} + {# Generate list of ports #} + {%- for port_idx in range(0,256,8) %} + {%- if PORT_ALL.append("Ethernet%d" % (port_idx)) %}{%- endif %} + {%- endfor %} +{%- endmacro %} + +{%- macro generate_buffer_pool_and_profiles() %} + "BUFFER_POOL": { + "ingress_lossless_pool": { + "size": "56441610000", + "type": "both", + "mode": "dynamic", + "xoff": "2822080500" + } + }, + "BUFFER_PROFILE": { + "ingress_lossy_profile": { + "pool":"ingress_lossless_pool", + "size":"0", + "xon_offset": "0", + "dynamic_th":"0" + }, + "egress_lossless_profile": { + "pool":"ingress_lossless_pool", + "size":"0", + "dynamic_th":"-1" + }, + "egress_lossy_profile": { + "pool":"ingress_lossless_pool", + "size":"0", + "dynamic_th":"-4" + } + }, +{%- endmacro %} + diff --git a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/BALANCED/pg_profile_lookup.ini b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/BALANCED/pg_profile_lookup.ini new file mode 100644 index 00000000000..a417a9558d0 --- /dev/null +++ b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/BALANCED/pg_profile_lookup.ini @@ -0,0 +1,17 @@ +# PG lossless profiles. +# speed cable size xon xoff threshold xon_offset +25000 5m 18796 0 612140 0 3556 +25000 40m 18796 0 612140 0 3556 +25000 300m 18796 0 612140 0 3556 +100000 5m 18796 0 612140 0 3556 +100000 40m 18796 0 612140 0 3556 +100000 300m 18796 0 612140 0 3556 +200000 5m 18796 0 612140 0 3556 +200000 40m 18796 0 612140 0 3556 +200000 300m 18796 0 612140 0 3556 +400000 5m 18796 0 612140 0 3556 +400000 40m 18796 0 612140 0 3556 +400000 300m 18796 0 612140 0 3556 +800000 5m 18796 0 612140 0 3556 +800000 40m 18796 0 612140 0 3556 +800000 300m 18796 0 612140 0 3556 diff --git a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/BALANCED/qos.json.j2 b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/BALANCED/qos.json.j2 new file mode 100644 index 00000000000..af1c4dfb256 --- /dev/null +++ b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/BALANCED/qos.json.j2 @@ -0,0 +1,4 @@ +{%- macro generate_global_dscp_to_tc_map() %} +{# This is an empty macro since the global DSCP_TO_TC map is not required #} +{%- endmacro %} +{%- include 'qos_config.j2' %} diff --git a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/agera2.bcm b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/agera2.bcm new file mode 100644 index 00000000000..3a72ef15df2 --- /dev/null +++ b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/agera2.bcm @@ -0,0 +1,801 @@ +### PHY CONFIGURATION FILE +### Please refer to config_file_format.txt in the top level folder for configuration file format + +### PHY CONFIGURATIONS +phy_init_config_chip_id:9 = 85361 +phy_init_mode:9 = 0 +phy_init_config_ref_clk:9 = 312000000 + +### LANE CONFIGURATIONS +#---------------------------------------------------------------------------------------------------------------- +# Lane_Property : Global_Lane = PHY_ID, IF_Side, Local_Lane, Tx_Lane_Map, Rx_Lane_Map, Tx_Polarity, Rx_Polarity +#---------------------------------------------------------------------------------------------------------------- +# Line side lanes: +phy_lane_property : 288 = 9, 0, 0, 3, 3, 0, 0 +phy_lane_property : 289 = 9, 0, 1, 4, 4, 0, 1 +phy_lane_property : 290 = 9, 0, 2, 5, 5, 0, 0 +phy_lane_property : 291 = 9, 0, 3, 2, 2, 1, 1 +phy_lane_property : 292 = 9, 0, 4, 1, 1, 1, 0 +phy_lane_property : 293 = 9, 0, 5, 6, 6, 0, 1 +phy_lane_property : 294 = 9, 0, 6, 7, 7, 0, 0 +phy_lane_property : 295 = 9, 0, 7, 0, 0, 1, 1 +phy_lane_property : 296 = 9, 0, 8, D, D, 0, 0 +phy_lane_property : 297 = 9, 0, 9, A, A, 0, 1 +phy_lane_property : 298 = 9, 0, 10, B, B, 0, 0 +phy_lane_property : 299 = 9, 0, 11, C, C, 0, 1 +phy_lane_property : 300 = 9, 0, 12, F, F, 0, 0 +phy_lane_property : 301 = 9, 0, 13, 8, 8, 0, 1 +phy_lane_property : 302 = 9, 0, 14, 9, 9, 0, 0 +phy_lane_property : 303 = 9, 0, 15, E, E, 0, 1 + + +# System side lanes: +phy_lane_property : 304 = 9, 1, 4, 0, 0, 0, 0 # UNUSED +phy_lane_property : 305 = 9, 1, 5, 1, 1, 0, 0 # UNUSED +phy_lane_property : 306 = 9, 1, 6, 2, 2, 0, 0 # UNUSED +phy_lane_property : 307 = 9, 1, 7, 3, 3, 0, 0 # UNUSED +phy_lane_property : 308 = 9, 1, 0, 4, 4, 0, 0 +phy_lane_property : 309 = 9, 1, 1, 5, 5, 0, 0 +phy_lane_property : 310 = 9, 1, 2, 6, 6, 0, 0 +phy_lane_property : 311 = 9, 1, 3, 7, 7, 0, 0 +phy_lane_property : 312 = 9, 1, 8, 8, 8, 0, 0 +phy_lane_property : 313 = 9, 1, 9, 9, 9, 0, 0 +phy_lane_property : 314 = 9, 1, 10, A, A, 0, 0 +phy_lane_property : 315 = 9, 1, 11, B, B, 0, 0 +phy_lane_property : 316 = 9, 1, 12, C, C, 0, 0 # UNUSED +phy_lane_property : 317 = 9, 1, 13, D, D, 0, 0 # UNUSED +phy_lane_property : 318 = 9, 1, 14, E, E, 0, 0 # UNUSED +phy_lane_property : 319 = 9, 1, 15, F, F, 0, 0 # UNUSED + +#---------------------------------------------------------------------------------------------------------------- +### PHY CONFIGURATION FILE +### Please refer to config_file_format.txt in the top level folder for configuration file format + +### PHY CONFIGURATIONS +phy_init_config_chip_id:8 = 85361 +phy_init_mode:8 = 0 +phy_init_config_ref_clk:8 = 312000000 + +### LANE CONFIGURATIONS +#---------------------------------------------------------------------------------------------------------------- +# Lane_Property : Global_Lane = PHY_ID, IF_Side, Local_Lane, Tx_Lane_Map, Rx_Lane_Map, Tx_Polarity, Rx_Polarity +#---------------------------------------------------------------------------------------------------------------- +# Line side lanes: +phy_lane_property : 256 = 8, 0, 0, 3, 3, 0, 0 +phy_lane_property : 257 = 8, 0, 1, 4, 4, 0, 1 +phy_lane_property : 258 = 8, 0, 2, 5, 5, 0, 0 +phy_lane_property : 259 = 8, 0, 3, 2, 2, 1, 1 +phy_lane_property : 260 = 8, 0, 4, 1, 1, 1, 0 +phy_lane_property : 261 = 8, 0, 5, 6, 6, 0, 1 +phy_lane_property : 262 = 8, 0, 6, 7, 7, 0, 0 +phy_lane_property : 263 = 8, 0, 7, 0, 0, 1, 1 +phy_lane_property : 264 = 8, 0, 8, D, D, 0, 0 +phy_lane_property : 265 = 8, 0, 9, A, A, 0, 1 +phy_lane_property : 266 = 8, 0, 10, B, B, 0, 0 +phy_lane_property : 267 = 8, 0, 11, C, C, 0, 1 +phy_lane_property : 268 = 8, 0, 12, F, F, 0, 0 +phy_lane_property : 269 = 8, 0, 13, 8, 8, 0, 1 +phy_lane_property : 270 = 8, 0, 14, 9, 9, 0, 0 +phy_lane_property : 271 = 8, 0, 15, E, E, 0, 1 + + +# System side lanes: +phy_lane_property : 272 = 8, 1, 4, 0, 0, 0, 0 # UNUSED +phy_lane_property : 273 = 8, 1, 5, 1, 1, 0, 0 # UNUSED +phy_lane_property : 274 = 8, 1, 6, 2, 2, 0, 0 # UNUSED +phy_lane_property : 275 = 8, 1, 7, 3, 3, 0, 0 # UNUSED +phy_lane_property : 276 = 8, 1, 0, 4, 4, 0, 0 +phy_lane_property : 277 = 8, 1, 1, 5, 5, 0, 0 +phy_lane_property : 278 = 8, 1, 2, 6, 6, 0, 0 +phy_lane_property : 279 = 8, 1, 3, 7, 7, 0, 0 +phy_lane_property : 280 = 8, 1, 8, 8, 8, 0, 0 +phy_lane_property : 281 = 8, 1, 9, 9, 9, 0, 0 +phy_lane_property : 282 = 8, 1, 10, A, A, 0, 0 +phy_lane_property : 283 = 8, 1, 11, B, B, 0, 0 +phy_lane_property : 284 = 8, 1, 12, C, C, 0, 0 # UNUSED +phy_lane_property : 285 = 8, 1, 13, D, D, 0, 0 # UNUSED +phy_lane_property : 286 = 8, 1, 14, E, E, 0, 0 # UNUSED +phy_lane_property : 287 = 8, 1, 15, F, F, 0, 0 # UNUSED + +#---------------------------------------------------------------------------------------------------------------- +### PHY CONFIGURATION FILE +### Please refer to config_file_format.txt in the top level folder for configuration file format + +### PHY CONFIGURATIONS +phy_init_config_chip_id:10 = 85361 +phy_init_mode:10 = 0 +phy_init_config_ref_clk:10 = 312000000 + +### LANE CONFIGURATIONS +#---------------------------------------------------------------------------------------------------------------- +# Lane_Property : Global_Lane = PHY_ID, IF_Side, Local_Lane, Tx_Lane_Map, Rx_Lane_Map, Tx_Polarity, Rx_Polarity +#---------------------------------------------------------------------------------------------------------------- +# Line side lanes: +phy_lane_property : 320 = 10, 0, 0, 3, 3, 0, 0 +phy_lane_property : 321 = 10, 0, 1, 4, 4, 0, 1 +phy_lane_property : 322 = 10, 0, 2, 5, 5, 0, 0 +phy_lane_property : 323 = 10, 0, 3, 2, 2, 1, 1 +phy_lane_property : 324 = 10, 0, 4, 1, 1, 1, 0 +phy_lane_property : 325 = 10, 0, 5, 6, 6, 0, 1 +phy_lane_property : 326 = 10, 0, 6, 7, 7, 0, 0 +phy_lane_property : 327 = 10, 0, 7, 0, 0, 1, 1 +phy_lane_property : 328 = 10, 0, 8, D, D, 0, 0 +phy_lane_property : 329 = 10, 0, 9, A, A, 0, 1 +phy_lane_property : 330 = 10, 0, 10, B, B, 0, 0 +phy_lane_property : 331 = 10, 0, 11, C, C, 0, 1 +phy_lane_property : 332 = 10, 0, 12, F, F, 0, 0 +phy_lane_property : 333 = 10, 0, 13, 8, 8, 0, 1 +phy_lane_property : 334 = 10, 0, 14, 9, 9, 0, 0 +phy_lane_property : 335 = 10, 0, 15, E, E, 0, 1 + + +# System side lanes: +phy_lane_property : 336 = 10, 1, 4, 0, 0, 0, 0 # UNUSED +phy_lane_property : 337 = 10, 1, 5, 1, 1, 0, 0 # UNUSED +phy_lane_property : 338 = 10, 1, 6, 2, 2, 0, 0 # UNUSED +phy_lane_property : 339 = 10, 1, 7, 3, 3, 0, 0 # UNUSED +phy_lane_property : 340 = 10, 1, 0, 4, 4, 0, 0 +phy_lane_property : 341 = 10, 1, 1, 5, 5, 0, 0 +phy_lane_property : 342 = 10, 1, 2, 6, 6, 0, 0 +phy_lane_property : 343 = 10, 1, 3, 7, 7, 0, 0 +phy_lane_property : 344 = 10, 1, 8, 8, 8, 0, 0 +phy_lane_property : 345 = 10, 1, 9, 9, 9, 0, 0 +phy_lane_property : 346 = 10, 1, 10, A, A, 0, 0 +phy_lane_property : 347 = 10, 1, 11, B, B, 0, 0 +phy_lane_property : 348 = 10, 1, 12, C, C, 0, 0 # UNUSED +phy_lane_property : 349 = 10, 1, 13, D, D, 0, 0 # UNUSED +phy_lane_property : 350 = 10, 1, 14, E, E, 0, 0 # UNUSED +phy_lane_property : 351 = 10, 1, 15, F, F, 0, 0 # UNUSED + +#---------------------------------------------------------------------------------------------------------------- +### PHY CONFIGURATION FILE +### Please refer to config_file_format.txt in the top level folder for configuration file format + +### PHY CONFIGURATIONS +phy_init_config_chip_id:11 = 85361 +phy_init_mode:11 = 0 +phy_init_config_ref_clk:11 = 312000000 + +### LANE CONFIGURATIONS +#---------------------------------------------------------------------------------------------------------------- +# Lane_Property : Global_Lane = PHY_ID, IF_Side, Local_Lane, Tx_Lane_Map, Rx_Lane_Map, Tx_Polarity, Rx_Polarity +#---------------------------------------------------------------------------------------------------------------- +# Line side lanes: +phy_lane_property : 352 = 11, 0, 0, 3, 3, 0, 0 +phy_lane_property : 353 = 11, 0, 1, 4, 4, 0, 1 +phy_lane_property : 354 = 11, 0, 2, 5, 5, 0, 0 +phy_lane_property : 355 = 11, 0, 3, 2, 2, 1, 1 +phy_lane_property : 356 = 11, 0, 4, 1, 1, 1, 0 +phy_lane_property : 357 = 11, 0, 5, 6, 6, 0, 1 +phy_lane_property : 358 = 11, 0, 6, 7, 7, 0, 0 +phy_lane_property : 359 = 11, 0, 7, 0, 0, 1, 1 +phy_lane_property : 360 = 11, 0, 8, D, D, 0, 0 +phy_lane_property : 361 = 11, 0, 9, A, A, 0, 1 +phy_lane_property : 362 = 11, 0, 10, B, B, 0, 0 +phy_lane_property : 363 = 11, 0, 11, C, C, 0, 1 +phy_lane_property : 364 = 11, 0, 12, F, F, 0, 0 +phy_lane_property : 365 = 11, 0, 13, 8, 8, 0, 1 +phy_lane_property : 366 = 11, 0, 14, 9, 9, 0, 0 +phy_lane_property : 367 = 11, 0, 15, E, E, 0, 1 + + +# System side lanes: +phy_lane_property : 368 = 11, 1, 4, 0, 0, 0, 0 # UNUSED +phy_lane_property : 369 = 11, 1, 5, 1, 1, 0, 0 # UNUSED +phy_lane_property : 370 = 11, 1, 6, 2, 2, 0, 0 # UNUSED +phy_lane_property : 371 = 11, 1, 7, 3, 3, 0, 0 # UNUSED +phy_lane_property : 372 = 11, 1, 0, 4, 4, 0, 0 +phy_lane_property : 373 = 11, 1, 1, 5, 5, 0, 0 +phy_lane_property : 374 = 11, 1, 2, 6, 6, 0, 0 +phy_lane_property : 375 = 11, 1, 3, 7, 7, 0, 0 +phy_lane_property : 376 = 11, 1, 8, 8, 8, 0, 0 +phy_lane_property : 377 = 11, 1, 9, 9, 9, 0, 0 +phy_lane_property : 378 = 11, 1, 10, A, A, 0, 0 +phy_lane_property : 379 = 11, 1, 11, B, B, 0, 0 +phy_lane_property : 380 = 11, 1, 12, C, C, 0, 0 # UNUSED +phy_lane_property : 381 = 11, 1, 13, D, D, 0, 0 # UNUSED +phy_lane_property : 382 = 11, 1, 14, E, E, 0, 0 # UNUSED +phy_lane_property : 383 = 11, 1, 15, F, F, 0, 0 # UNUSED + +#---------------------------------------------------------------------------------------------------------------- +### PHY CONFIGURATION FILE +### Please refer to config_file_format.txt in the top level folder for configuration file format + +### PHY CONFIGURATIONS +phy_init_config_chip_id:12 = 85361 +phy_init_mode:12 = 0 +phy_init_config_ref_clk:12 = 312000000 + +### LANE CONFIGURATIONS +#---------------------------------------------------------------------------------------------------------------- +# Lane_Property : Global_Lane = PHY_ID, IF_Side, Local_Lane, Tx_Lane_Map, Rx_Lane_Map, Tx_Polarity, Rx_Polarity +#---------------------------------------------------------------------------------------------------------------- +# Line side lanes: +phy_lane_property : 384 = 12, 0, 0, 3, 3, 0, 0 +phy_lane_property : 385 = 12, 0, 1, 4, 4, 0, 1 +phy_lane_property : 386 = 12, 0, 2, 5, 5, 0, 0 +phy_lane_property : 387 = 12, 0, 3, 2, 2, 1, 1 +phy_lane_property : 388 = 12, 0, 4, 1, 1, 1, 0 +phy_lane_property : 389 = 12, 0, 5, 6, 6, 0, 1 +phy_lane_property : 390 = 12, 0, 6, 7, 7, 0, 0 +phy_lane_property : 391 = 12, 0, 7, 0, 0, 1, 1 +phy_lane_property : 392 = 12, 0, 8, D, D, 0, 0 +phy_lane_property : 393 = 12, 0, 9, A, A, 0, 1 +phy_lane_property : 394 = 12, 0, 10, B, B, 0, 0 +phy_lane_property : 395 = 12, 0, 11, C, C, 0, 1 +phy_lane_property : 396 = 12, 0, 12, F, F, 0, 0 +phy_lane_property : 397 = 12, 0, 13, 8, 8, 0, 1 +phy_lane_property : 398 = 12, 0, 14, 9, 9, 0, 0 +phy_lane_property : 399 = 12, 0, 15, E, E, 0, 1 + + +# System side lanes: +phy_lane_property : 400 = 12, 1, 4, 0, 0, 0, 0 # UNUSED +phy_lane_property : 401 = 12, 1, 5, 1, 1, 0, 0 # UNUSED +phy_lane_property : 402 = 12, 1, 6, 2, 2, 0, 0 # UNUSED +phy_lane_property : 403 = 12, 1, 7, 3, 3, 0, 0 # UNUSED +phy_lane_property : 404 = 12, 1, 0, 4, 4, 0, 0 +phy_lane_property : 405 = 12, 1, 1, 5, 5, 0, 0 +phy_lane_property : 406 = 12, 1, 2, 6, 6, 0, 0 +phy_lane_property : 407 = 12, 1, 3, 7, 7, 0, 0 +phy_lane_property : 408 = 12, 1, 8, 8, 8, 0, 0 +phy_lane_property : 409 = 12, 1, 9, 9, 9, 0, 0 +phy_lane_property : 410 = 12, 1, 10, A, A, 0, 0 +phy_lane_property : 411 = 12, 1, 11, B, B, 0, 0 +phy_lane_property : 412 = 12, 1, 12, C, C, 0, 0 # UNUSED +phy_lane_property : 413 = 12, 1, 13, D, D, 0, 0 # UNUSED +phy_lane_property : 414 = 12, 1, 14, E, E, 0, 0 # UNUSED +phy_lane_property : 415 = 12, 1, 15, F, F, 0, 0 # UNUSED + +#---------------------------------------------------------------------------------------------------------------- +### PHY CONFIGURATION FILE +### Please refer to config_file_format.txt in the top level folder for configuration file format + +### PHY CONFIGURATIONS +phy_init_config_chip_id:13 = 85361 +phy_init_mode:13 = 0 +phy_init_config_ref_clk:13 = 312000000 + +### LANE CONFIGURATIONS +#---------------------------------------------------------------------------------------------------------------- +# Lane_Property : Global_Lane = PHY_ID, IF_Side, Local_Lane, Tx_Lane_Map, Rx_Lane_Map, Tx_Polarity, Rx_Polarity +#---------------------------------------------------------------------------------------------------------------- +# Line side lanes: +phy_lane_property : 416 = 13, 0, 0, 3, 3, 0, 0 +phy_lane_property : 417 = 13, 0, 1, 4, 4, 0, 1 +phy_lane_property : 418 = 13, 0, 2, 5, 5, 0, 0 +phy_lane_property : 419 = 13, 0, 3, 2, 2, 1, 1 +phy_lane_property : 420 = 13, 0, 4, 1, 1, 1, 0 +phy_lane_property : 421 = 13, 0, 5, 6, 6, 0, 1 +phy_lane_property : 422 = 13, 0, 6, 7, 7, 0, 0 +phy_lane_property : 423 = 13, 0, 7, 0, 0, 1, 1 +phy_lane_property : 424 = 13, 0, 8, D, D, 0, 0 +phy_lane_property : 425 = 13, 0, 9, A, A, 0, 1 +phy_lane_property : 426 = 13, 0, 10, B, B, 0, 0 +phy_lane_property : 427 = 13, 0, 11, C, C, 0, 1 +phy_lane_property : 428 = 13, 0, 12, F, F, 0, 0 +phy_lane_property : 429 = 13, 0, 13, 8, 8, 0, 1 +phy_lane_property : 430 = 13, 0, 14, 9, 9, 0, 0 +phy_lane_property : 431 = 13, 0, 15, E, E, 0, 1 + + +# System side lanes: +phy_lane_property : 432 = 13, 1, 4, 0, 0, 0, 0 # UNUSED +phy_lane_property : 433 = 13, 1, 5, 1, 1, 0, 0 # UNUSED +phy_lane_property : 434 = 13, 1, 6, 2, 2, 0, 0 # UNUSED +phy_lane_property : 435 = 13, 1, 7, 3, 3, 0, 0 # UNUSED +phy_lane_property : 436 = 13, 1, 0, 4, 4, 0, 0 +phy_lane_property : 437 = 13, 1, 1, 5, 5, 0, 0 +phy_lane_property : 438 = 13, 1, 2, 6, 6, 0, 0 +phy_lane_property : 439 = 13, 1, 3, 7, 7, 0, 0 +phy_lane_property : 440 = 13, 1, 8, 8, 8, 0, 0 +phy_lane_property : 441 = 13, 1, 9, 9, 9, 0, 0 +phy_lane_property : 442 = 13, 1, 10, A, A, 0, 0 +phy_lane_property : 443 = 13, 1, 11, B, B, 0, 0 +phy_lane_property : 444 = 13, 1, 12, C, C, 0, 0 # UNUSED +phy_lane_property : 445 = 13, 1, 13, D, D, 0, 0 # UNUSED +phy_lane_property : 446 = 13, 1, 14, E, E, 0, 0 # UNUSED +phy_lane_property : 447 = 13, 1, 15, F, F, 0, 0 # UNUSED + +#---------------------------------------------------------------------------------------------------------------- +### PHY CONFIGURATION FILE +### Please refer to config_file_format.txt in the top level folder for configuration file format + +### PHY CONFIGURATIONS +phy_init_config_chip_id:14 = 85361 +phy_init_mode:14 = 0 +phy_init_config_ref_clk:14 = 312000000 + +### LANE CONFIGURATIONS +#---------------------------------------------------------------------------------------------------------------- +# Lane_Property : Global_Lane = PHY_ID, IF_Side, Local_Lane, Tx_Lane_Map, Rx_Lane_Map, Tx_Polarity, Rx_Polarity +#---------------------------------------------------------------------------------------------------------------- +# Line side lanes: +phy_lane_property : 448 = 14, 0, 0, 3, 3, 0, 0 +phy_lane_property : 449 = 14, 0, 1, 4, 4, 0, 1 +phy_lane_property : 450 = 14, 0, 2, 5, 5, 0, 0 +phy_lane_property : 451 = 14, 0, 3, 2, 2, 1, 1 +phy_lane_property : 452 = 14, 0, 4, 1, 1, 1, 0 +phy_lane_property : 453 = 14, 0, 5, 6, 6, 0, 1 +phy_lane_property : 454 = 14, 0, 6, 7, 7, 0, 0 +phy_lane_property : 455 = 14, 0, 7, 0, 0, 1, 1 +phy_lane_property : 456 = 14, 0, 8, D, D, 0, 0 +phy_lane_property : 457 = 14, 0, 9, A, A, 0, 1 +phy_lane_property : 458 = 14, 0, 10, B, B, 0, 0 +phy_lane_property : 459 = 14, 0, 11, C, C, 0, 1 +phy_lane_property : 460 = 14, 0, 12, F, F, 0, 0 +phy_lane_property : 461 = 14, 0, 13, 8, 8, 0, 1 +phy_lane_property : 462 = 14, 0, 14, 9, 9, 0, 0 +phy_lane_property : 463 = 14, 0, 15, E, E, 0, 1 + + +# System side lanes: +phy_lane_property : 464 = 14, 1, 4, 0, 0, 0, 0 # UNUSED +phy_lane_property : 465 = 14, 1, 5, 1, 1, 0, 0 # UNUSED +phy_lane_property : 466 = 14, 1, 6, 2, 2, 0, 0 # UNUSED +phy_lane_property : 467 = 14, 1, 7, 3, 3, 0, 0 # UNUSED +phy_lane_property : 468 = 14, 1, 0, 4, 4, 0, 0 +phy_lane_property : 469 = 14, 1, 1, 5, 5, 0, 0 +phy_lane_property : 470 = 14, 1, 2, 6, 6, 0, 0 +phy_lane_property : 471 = 14, 1, 3, 7, 7, 0, 0 +phy_lane_property : 472 = 14, 1, 8, 8, 8, 0, 0 +phy_lane_property : 473 = 14, 1, 9, 9, 9, 0, 0 +phy_lane_property : 474 = 14, 1, 10, A, A, 0, 0 +phy_lane_property : 475 = 14, 1, 11, B, B, 0, 0 +phy_lane_property : 476 = 14, 1, 12, C, C, 0, 0 # UNUSED +phy_lane_property : 477 = 14, 1, 13, D, D, 0, 0 # UNUSED +phy_lane_property : 478 = 14, 1, 14, E, E, 0, 0 # UNUSED +phy_lane_property : 479 = 14, 1, 15, F, F, 0, 0 # UNUSED + +#---------------------------------------------------------------------------------------------------------------- +### PHY CONFIGURATION FILE +### Please refer to config_file_format.txt in the top level folder for configuration file format + +### PHY CONFIGURATIONS +phy_init_config_chip_id:15 = 85361 +phy_init_mode:15 = 0 +phy_init_config_ref_clk:15 = 312000000 + +### LANE CONFIGURATIONS +#---------------------------------------------------------------------------------------------------------------- +# Lane_Property : Global_Lane = PHY_ID, IF_Side, Local_Lane, Tx_Lane_Map, Rx_Lane_Map, Tx_Polarity, Rx_Polarity +#---------------------------------------------------------------------------------------------------------------- +# Line side lanes: +phy_lane_property : 480 = 15, 0, 0, 3, 3, 0, 0 +phy_lane_property : 481 = 15, 0, 1, 4, 4, 0, 1 +phy_lane_property : 482 = 15, 0, 2, 5, 5, 0, 0 +phy_lane_property : 483 = 15, 0, 3, 2, 2, 1, 1 +phy_lane_property : 484 = 15, 0, 4, 1, 1, 1, 0 +phy_lane_property : 485 = 15, 0, 5, 6, 6, 0, 1 +phy_lane_property : 486 = 15, 0, 6, 7, 7, 0, 0 +phy_lane_property : 487 = 15, 0, 7, 0, 0, 1, 1 +phy_lane_property : 488 = 15, 0, 8, D, D, 0, 0 +phy_lane_property : 489 = 15, 0, 9, A, A, 0, 1 +phy_lane_property : 490 = 15, 0, 10, B, B, 0, 0 +phy_lane_property : 491 = 15, 0, 11, C, C, 0, 1 +phy_lane_property : 492 = 15, 0, 12, F, F, 0, 0 +phy_lane_property : 493 = 15, 0, 13, 8, 8, 0, 1 +phy_lane_property : 494 = 15, 0, 14, 9, 9, 0, 0 +phy_lane_property : 495 = 15, 0, 15, E, E, 0, 1 + + +# System side lanes: +phy_lane_property : 496 = 15, 1, 4, 0, 0, 0, 0 # UNUSED +phy_lane_property : 497 = 15, 1, 5, 1, 1, 0, 0 # UNUSED +phy_lane_property : 498 = 15, 1, 6, 2, 2, 0, 0 # UNUSED +phy_lane_property : 499 = 15, 1, 7, 3, 3, 0, 0 # UNUSED +phy_lane_property : 500 = 15, 1, 0, 4, 4, 0, 0 +phy_lane_property : 501 = 15, 1, 1, 5, 5, 0, 0 +phy_lane_property : 502 = 15, 1, 2, 6, 6, 0, 0 +phy_lane_property : 503 = 15, 1, 3, 7, 7, 0, 0 +phy_lane_property : 504 = 15, 1, 8, 8, 8, 0, 0 +phy_lane_property : 505 = 15, 1, 9, 9, 9, 0, 0 +phy_lane_property : 506 = 15, 1, 10, A, A, 0, 0 +phy_lane_property : 507 = 15, 1, 11, B, B, 0, 0 +phy_lane_property : 508 = 15, 1, 12, C, C, 0, 0 # UNUSED +phy_lane_property : 509 = 15, 1, 13, D, D, 0, 0 # UNUSED +phy_lane_property : 510 = 15, 1, 14, E, E, 0, 0 # UNUSED +phy_lane_property : 511 = 15, 1, 15, F, F, 0, 0 # UNUSED + +#---------------------------------------------------------------------------------------------------------------- +### PHY CONFIGURATION FILE +### Please refer to config_file_format.txt in the top level folder for configuration file format + +### PHY CONFIGURATIONS +phy_init_config_chip_id:0 = 85361 +phy_init_mode:0 = 0 +phy_init_config_ref_clk:0 = 312000000 + +### LANE CONFIGURATIONS +#---------------------------------------------------------------------------------------------------------------- +# Lane_Property : Global_Lane = PHY_ID, IF_Side, Local_Lane, Tx_Lane_Map, Rx_Lane_Map, Tx_Polarity, Rx_Polarity +#---------------------------------------------------------------------------------------------------------------- +# Line side lanes: +phy_lane_property : 0 = 0, 0, 0, 3, 3, 0, 0 +phy_lane_property : 1 = 0, 0, 1, 4, 4, 0, 1 +phy_lane_property : 2 = 0, 0, 2, 5, 5, 0, 0 +phy_lane_property : 3 = 0, 0, 3, 2, 2, 1, 1 +phy_lane_property : 4 = 0, 0, 4, 1, 1, 1, 0 +phy_lane_property : 5 = 0, 0, 5, 6, 6, 0, 1 +phy_lane_property : 6 = 0, 0, 6, 7, 7, 0, 0 +phy_lane_property : 7 = 0, 0, 7, 0, 0, 1, 1 +phy_lane_property : 8 = 0, 0, 8, D, D, 0, 0 +phy_lane_property : 9 = 0, 0, 9, A, A, 0, 1 +phy_lane_property : 10 = 0, 0, 10, B, B, 0, 0 +phy_lane_property : 11 = 0, 0, 11, C, C, 0, 1 +phy_lane_property : 12 = 0, 0, 12, F, F, 0, 0 +phy_lane_property : 13 = 0, 0, 13, 8, 8, 0, 1 +phy_lane_property : 14 = 0, 0, 14, 9, 9, 0, 0 +phy_lane_property : 15 = 0, 0, 15, E, E, 0, 1 + + +# System side lanes: +phy_lane_property : 16 = 0, 1, 4, 0, 0, 0, 0 # UNUSED +phy_lane_property : 17 = 0, 1, 5, 1, 1, 0, 0 # UNUSED +phy_lane_property : 18 = 0, 1, 6, 2, 2, 0, 0 # UNUSED +phy_lane_property : 19 = 0, 1, 7, 3, 3, 0, 0 # UNUSED +phy_lane_property : 20 = 0, 1, 0, 4, 4, 0, 0 +phy_lane_property : 21 = 0, 1, 1, 5, 5, 0, 0 +phy_lane_property : 22 = 0, 1, 2, 6, 6, 0, 0 +phy_lane_property : 23 = 0, 1, 3, 7, 7, 0, 0 +phy_lane_property : 24 = 0, 1, 8, 8, 8, 0, 0 +phy_lane_property : 25 = 0, 1, 9, 9, 9, 0, 0 +phy_lane_property : 26 = 0, 1, 10, A, A, 0, 0 +phy_lane_property : 27 = 0, 1, 11, B, B, 0, 0 +phy_lane_property : 28 = 0, 1, 12, C, C, 0, 0 # UNUSED +phy_lane_property : 29 = 0, 1, 13, D, D, 0, 0 # UNUSED +phy_lane_property : 30 = 0, 1, 14, E, E, 0, 0 # UNUSED +phy_lane_property : 31 = 0, 1, 15, F, F, 0, 0 # UNUSED + +#---------------------------------------------------------------------------------------------------------------- +### PHY CONFIGURATION FILE +### Please refer to config_file_format.txt in the top level folder for configuration file format + +### PHY CONFIGURATIONS +phy_init_config_chip_id:1 = 85361 +phy_init_mode:1 = 0 +phy_init_config_ref_clk:1 = 312000000 + +### LANE CONFIGURATIONS +#---------------------------------------------------------------------------------------------------------------- +# Lane_Property : Global_Lane = PHY_ID, IF_Side, Local_Lane, Tx_Lane_Map, Rx_Lane_Map, Tx_Polarity, Rx_Polarity +#---------------------------------------------------------------------------------------------------------------- +# Line side lanes: +phy_lane_property : 32 = 1, 0, 0, 3, 3, 0, 0 +phy_lane_property : 33 = 1, 0, 1, 4, 4, 0, 1 +phy_lane_property : 34 = 1, 0, 2, 5, 5, 0, 0 +phy_lane_property : 35 = 1, 0, 3, 2, 2, 1, 1 +phy_lane_property : 36 = 1, 0, 4, 1, 1, 1, 0 +phy_lane_property : 37 = 1, 0, 5, 6, 6, 0, 1 +phy_lane_property : 38 = 1, 0, 6, 7, 7, 0, 0 +phy_lane_property : 39 = 1, 0, 7, 0, 0, 1, 1 +phy_lane_property : 40 = 1, 0, 8, D, D, 0, 0 +phy_lane_property : 41 = 1, 0, 9, A, A, 0, 1 +phy_lane_property : 42 = 1, 0, 10, B, B, 0, 0 +phy_lane_property : 43 = 1, 0, 11, C, C, 0, 1 +phy_lane_property : 44 = 1, 0, 12, F, F, 0, 0 +phy_lane_property : 45 = 1, 0, 13, 8, 8, 0, 1 +phy_lane_property : 46 = 1, 0, 14, 9, 9, 0, 0 +phy_lane_property : 47 = 1, 0, 15, E, E, 0, 1 + + +# System side lanes: +phy_lane_property : 48 = 1, 1, 4, 0, 0, 0, 0 # UNUSED +phy_lane_property : 49 = 1, 1, 5, 1, 1, 0, 0 # UNUSED +phy_lane_property : 50 = 1, 1, 6, 2, 2, 0, 0 # UNUSED +phy_lane_property : 51 = 1, 1, 7, 3, 3, 0, 0 # UNUSED +phy_lane_property : 52 = 1, 1, 0, 4, 4, 0, 0 +phy_lane_property : 53 = 1, 1, 1, 5, 5, 0, 0 +phy_lane_property : 54 = 1, 1, 2, 6, 6, 0, 0 +phy_lane_property : 55 = 1, 1, 3, 7, 7, 0, 0 +phy_lane_property : 56 = 1, 1, 8, 8, 8, 0, 0 +phy_lane_property : 57 = 1, 1, 9, 9, 9, 0, 0 +phy_lane_property : 58 = 1, 1, 10, A, A, 0, 0 +phy_lane_property : 59 = 1, 1, 11, B, B, 0, 0 +phy_lane_property : 60 = 1, 1, 12, C, C, 0, 0 # UNUSED +phy_lane_property : 61 = 1, 1, 13, D, D, 0, 0 # UNUSED +phy_lane_property : 62 = 1, 1, 14, E, E, 0, 0 # UNUSED +phy_lane_property : 63 = 1, 1, 15, F, F, 0, 0 # UNUSED + +#---------------------------------------------------------------------------------------------------------------- +### PHY CONFIGURATION FILE +### Please refer to config_file_format.txt in the top level folder for configuration file format + +### PHY CONFIGURATIONS +phy_init_config_chip_id:2 = 85361 +phy_init_mode:2 = 0 +phy_init_config_ref_clk:2 = 312000000 + +### LANE CONFIGURATIONS +#---------------------------------------------------------------------------------------------------------------- +# Lane_Property : Global_Lane = PHY_ID, IF_Side, Local_Lane, Tx_Lane_Map, Rx_Lane_Map, Tx_Polarity, Rx_Polarity +#---------------------------------------------------------------------------------------------------------------- +# Line side lanes: +phy_lane_property : 64 = 2, 0, 0, 3, 3, 0, 0 +phy_lane_property : 65 = 2, 0, 1, 4, 4, 0, 1 +phy_lane_property : 66 = 2, 0, 2, 5, 5, 0, 0 +phy_lane_property : 67 = 2, 0, 3, 2, 2, 1, 1 +phy_lane_property : 68 = 2, 0, 4, 1, 1, 1, 0 +phy_lane_property : 69 = 2, 0, 5, 6, 6, 0, 1 +phy_lane_property : 70 = 2, 0, 6, 7, 7, 0, 0 +phy_lane_property : 71 = 2, 0, 7, 0, 0, 1, 1 +phy_lane_property : 72 = 2, 0, 8, D, D, 0, 0 +phy_lane_property : 73 = 2, 0, 9, A, A, 0, 1 +phy_lane_property : 74 = 2, 0, 10, B, B, 0, 0 +phy_lane_property : 75 = 2, 0, 11, C, C, 0, 1 +phy_lane_property : 76 = 2, 0, 12, F, F, 0, 0 +phy_lane_property : 77 = 2, 0, 13, 8, 8, 0, 1 +phy_lane_property : 78 = 2, 0, 14, 9, 9, 0, 0 +phy_lane_property : 79 = 2, 0, 15, E, E, 0, 1 + + +# System side lanes: +phy_lane_property : 80 = 2, 1, 4, 0, 0, 0, 0 # UNUSED +phy_lane_property : 81 = 2, 1, 5, 1, 1, 0, 0 # UNUSED +phy_lane_property : 82 = 2, 1, 6, 2, 2, 0, 0 # UNUSED +phy_lane_property : 83 = 2, 1, 7, 3, 3, 0, 0 # UNUSED +phy_lane_property : 84 = 2, 1, 0, 4, 4, 0, 0 +phy_lane_property : 85 = 2, 1, 1, 5, 5, 0, 0 +phy_lane_property : 86 = 2, 1, 2, 6, 6, 0, 0 +phy_lane_property : 87 = 2, 1, 3, 7, 7, 0, 0 +phy_lane_property : 88 = 2, 1, 8, 8, 8, 0, 0 +phy_lane_property : 89 = 2, 1, 9, 9, 9, 0, 0 +phy_lane_property : 90 = 2, 1, 10, A, A, 0, 0 +phy_lane_property : 91 = 2, 1, 11, B, B, 0, 0 +phy_lane_property : 92 = 2, 1, 12, C, C, 0, 0 # UNUSED +phy_lane_property : 93 = 2, 1, 13, D, D, 0, 0 # UNUSED +phy_lane_property : 94 = 2, 1, 14, E, E, 0, 0 # UNUSED +phy_lane_property : 95 = 2, 1, 15, F, F, 0, 0 # UNUSED + +#---------------------------------------------------------------------------------------------------------------- +### PHY CONFIGURATION FILE +### Please refer to config_file_format.txt in the top level folder for configuration file format + +### PHY CONFIGURATIONS +phy_init_config_chip_id:3 = 85361 +phy_init_mode:3 = 0 +phy_init_config_ref_clk:3 = 312000000 + +### LANE CONFIGURATIONS +#---------------------------------------------------------------------------------------------------------------- +# Lane_Property : Global_Lane = PHY_ID, IF_Side, Local_Lane, Tx_Lane_Map, Rx_Lane_Map, Tx_Polarity, Rx_Polarity +#---------------------------------------------------------------------------------------------------------------- +# Line side lanes: +phy_lane_property : 96 = 3, 0, 0, 3, 3, 0, 0 +phy_lane_property : 97 = 3, 0, 1, 4, 4, 0, 1 +phy_lane_property : 98 = 3, 0, 2, 5, 5, 0, 0 +phy_lane_property : 99 = 3, 0, 3, 2, 2, 1, 1 +phy_lane_property : 100 = 3, 0, 4, 1, 1, 1, 0 +phy_lane_property : 101 = 3, 0, 5, 6, 6, 0, 1 +phy_lane_property : 102 = 3, 0, 6, 7, 7, 0, 0 +phy_lane_property : 103 = 3, 0, 7, 0, 0, 1, 1 +phy_lane_property : 104 = 3, 0, 8, D, D, 0, 0 +phy_lane_property : 105 = 3, 0, 9, A, A, 0, 1 +phy_lane_property : 106 = 3, 0, 10, B, B, 0, 0 +phy_lane_property : 107 = 3, 0, 11, C, C, 0, 1 +phy_lane_property : 108 = 3, 0, 12, F, F, 0, 0 +phy_lane_property : 109 = 3, 0, 13, 8, 8, 0, 1 +phy_lane_property : 110 = 3, 0, 14, 9, 9, 0, 0 +phy_lane_property : 111 = 3, 0, 15, E, E, 0, 1 + + +# System side lanes: +phy_lane_property : 112 = 3, 1, 4, 0, 0, 0, 0 # UNUSED +phy_lane_property : 113 = 3, 1, 5, 1, 1, 0, 0 # UNUSED +phy_lane_property : 114 = 3, 1, 6, 2, 2, 0, 0 # UNUSED +phy_lane_property : 115 = 3, 1, 7, 3, 3, 0, 0 # UNUSED +phy_lane_property : 116 = 3, 1, 0, 4, 4, 0, 0 +phy_lane_property : 117 = 3, 1, 1, 5, 5, 0, 0 +phy_lane_property : 118 = 3, 1, 2, 6, 6, 0, 0 +phy_lane_property : 119 = 3, 1, 3, 7, 7, 0, 0 +phy_lane_property : 120 = 3, 1, 8, 8, 8, 0, 0 +phy_lane_property : 121 = 3, 1, 9, 9, 9, 0, 0 +phy_lane_property : 122 = 3, 1, 10, A, A, 0, 0 +phy_lane_property : 123 = 3, 1, 11, B, B, 0, 0 +phy_lane_property : 124 = 3, 1, 12, C, C, 0, 0 # UNUSED +phy_lane_property : 125 = 3, 1, 13, D, D, 0, 0 # UNUSED +phy_lane_property : 126 = 3, 1, 14, E, E, 0, 0 # UNUSED +phy_lane_property : 127 = 3, 1, 15, F, F, 0, 0 # UNUSED + +#---------------------------------------------------------------------------------------------------------------- +### PHY CONFIGURATION FILE +### Please refer to config_file_format.txt in the top level folder for configuration file format + +### PHY CONFIGURATIONS +phy_init_config_chip_id:4 = 85361 +phy_init_mode:4 = 0 +phy_init_config_ref_clk:4 = 312000000 + +### LANE CONFIGURATIONS +#---------------------------------------------------------------------------------------------------------------- +# Lane_Property : Global_Lane = PHY_ID, IF_Side, Local_Lane, Tx_Lane_Map, Rx_Lane_Map, Tx_Polarity, Rx_Polarity +#---------------------------------------------------------------------------------------------------------------- +# Line side lanes: +phy_lane_property : 128 = 4, 0, 0, 3, 3, 0, 0 +phy_lane_property : 129 = 4, 0, 1, 4, 4, 0, 1 +phy_lane_property : 130 = 4, 0, 2, 5, 5, 0, 0 +phy_lane_property : 131 = 4, 0, 3, 2, 2, 1, 1 +phy_lane_property : 132 = 4, 0, 4, 1, 1, 1, 0 +phy_lane_property : 133 = 4, 0, 5, 6, 6, 0, 1 +phy_lane_property : 134 = 4, 0, 6, 7, 7, 0, 0 +phy_lane_property : 135 = 4, 0, 7, 0, 0, 1, 1 +phy_lane_property : 136 = 4, 0, 8, D, D, 0, 0 +phy_lane_property : 137 = 4, 0, 9, A, A, 0, 1 +phy_lane_property : 138 = 4, 0, 10, B, B, 0, 0 +phy_lane_property : 139 = 4, 0, 11, C, C, 0, 1 +phy_lane_property : 140 = 4, 0, 12, F, F, 0, 0 +phy_lane_property : 141 = 4, 0, 13, 8, 8, 0, 1 +phy_lane_property : 142 = 4, 0, 14, 9, 9, 0, 0 +phy_lane_property : 143 = 4, 0, 15, E, E, 0, 1 + + +# System side lanes: +phy_lane_property : 144 = 4, 1, 4, 0, 0, 0, 0 # UNUSED +phy_lane_property : 145 = 4, 1, 5, 1, 1, 0, 0 # UNUSED +phy_lane_property : 146 = 4, 1, 6, 2, 2, 0, 0 # UNUSED +phy_lane_property : 147 = 4, 1, 7, 3, 3, 0, 0 # UNUSED +phy_lane_property : 148 = 4, 1, 0, 4, 4, 0, 0 +phy_lane_property : 149 = 4, 1, 1, 5, 5, 0, 0 +phy_lane_property : 150 = 4, 1, 2, 6, 6, 0, 0 +phy_lane_property : 151 = 4, 1, 3, 7, 7, 0, 0 +phy_lane_property : 152 = 4, 1, 8, 8, 8, 0, 0 +phy_lane_property : 153 = 4, 1, 9, 9, 9, 0, 0 +phy_lane_property : 154 = 4, 1, 10, A, A, 0, 0 +phy_lane_property : 155 = 4, 1, 11, B, B, 0, 0 +phy_lane_property : 156 = 4, 1, 12, C, C, 0, 0 # UNUSED +phy_lane_property : 157 = 4, 1, 13, D, D, 0, 0 # UNUSED +phy_lane_property : 158 = 4, 1, 14, E, E, 0, 0 # UNUSED +phy_lane_property : 159 = 4, 1, 15, F, F, 0, 0 # UNUSED + +#---------------------------------------------------------------------------------------------------------------- +### PHY CONFIGURATION FILE +### Please refer to config_file_format.txt in the top level folder for configuration file format + +### PHY CONFIGURATIONS +phy_init_config_chip_id:5 = 85361 +phy_init_mode:5 = 0 +phy_init_config_ref_clk:5 = 312000000 + +### LANE CONFIGURATIONS +#---------------------------------------------------------------------------------------------------------------- +# Lane_Property : Global_Lane = PHY_ID, IF_Side, Local_Lane, Tx_Lane_Map, Rx_Lane_Map, Tx_Polarity, Rx_Polarity +#---------------------------------------------------------------------------------------------------------------- +# Line side lanes: +phy_lane_property : 160 = 5, 0, 0, 3, 3, 0, 0 +phy_lane_property : 161 = 5, 0, 1, 4, 4, 0, 1 +phy_lane_property : 162 = 5, 0, 2, 5, 5, 0, 0 +phy_lane_property : 163 = 5, 0, 3, 2, 2, 1, 1 +phy_lane_property : 164 = 5, 0, 4, 1, 1, 1, 0 +phy_lane_property : 165 = 5, 0, 5, 6, 6, 0, 1 +phy_lane_property : 166 = 5, 0, 6, 7, 7, 0, 0 +phy_lane_property : 167 = 5, 0, 7, 0, 0, 1, 1 +phy_lane_property : 168 = 5, 0, 8, D, D, 0, 0 +phy_lane_property : 169 = 5, 0, 9, A, A, 0, 1 +phy_lane_property : 170 = 5, 0, 10, B, B, 0, 0 +phy_lane_property : 171 = 5, 0, 11, C, C, 0, 1 +phy_lane_property : 172 = 5, 0, 12, F, F, 0, 0 +phy_lane_property : 173 = 5, 0, 13, 8, 8, 0, 1 +phy_lane_property : 174 = 5, 0, 14, 9, 9, 0, 0 +phy_lane_property : 175 = 5, 0, 15, E, E, 0, 1 + + +# System side lanes: +phy_lane_property : 176 = 5, 1, 4, 0, 0, 0, 0 # UNUSED +phy_lane_property : 177 = 5, 1, 5, 1, 1, 0, 0 # UNUSED +phy_lane_property : 178 = 5, 1, 6, 2, 2, 0, 0 # UNUSED +phy_lane_property : 179 = 5, 1, 7, 3, 3, 0, 0 # UNUSED +phy_lane_property : 180 = 5, 1, 0, 4, 4, 0, 0 +phy_lane_property : 181 = 5, 1, 1, 5, 5, 0, 0 +phy_lane_property : 182 = 5, 1, 2, 6, 6, 0, 0 +phy_lane_property : 183 = 5, 1, 3, 7, 7, 0, 0 +phy_lane_property : 184 = 5, 1, 8, 8, 8, 0, 0 +phy_lane_property : 185 = 5, 1, 9, 9, 9, 0, 0 +phy_lane_property : 186 = 5, 1, 10, A, A, 0, 0 +phy_lane_property : 187 = 5, 1, 11, B, B, 0, 0 +phy_lane_property : 188 = 5, 1, 12, C, C, 0, 0 # UNUSED +phy_lane_property : 189 = 5, 1, 13, D, D, 0, 0 # UNUSED +phy_lane_property : 190 = 5, 1, 14, E, E, 0, 0 # UNUSED +phy_lane_property : 191 = 5, 1, 15, F, F, 0, 0 # UNUSED + +#---------------------------------------------------------------------------------------------------------------- +### PHY CONFIGURATION FILE +### Please refer to config_file_format.txt in the top level folder for configuration file format + +### PHY CONFIGURATIONS +phy_init_config_chip_id:6 = 85361 +phy_init_mode:6 = 0 +phy_init_config_ref_clk:6 = 312000000 + +### LANE CONFIGURATIONS +#---------------------------------------------------------------------------------------------------------------- +# Lane_Property : Global_Lane = PHY_ID, IF_Side, Local_Lane, Tx_Lane_Map, Rx_Lane_Map, Tx_Polarity, Rx_Polarity +#---------------------------------------------------------------------------------------------------------------- +# Line side lanes: +phy_lane_property : 192 = 6, 0, 0, 3, 3, 0, 0 +phy_lane_property : 193 = 6, 0, 1, 4, 4, 0, 1 +phy_lane_property : 194 = 6, 0, 2, 5, 5, 0, 0 +phy_lane_property : 195 = 6, 0, 3, 2, 2, 1, 1 +phy_lane_property : 196 = 6, 0, 4, 1, 1, 1, 0 +phy_lane_property : 197 = 6, 0, 5, 6, 6, 0, 1 +phy_lane_property : 198 = 6, 0, 6, 7, 7, 0, 0 +phy_lane_property : 199 = 6, 0, 7, 0, 0, 1, 1 +phy_lane_property : 200 = 6, 0, 8, D, D, 0, 0 +phy_lane_property : 201 = 6, 0, 9, A, A, 0, 1 +phy_lane_property : 202 = 6, 0, 10, B, B, 0, 0 +phy_lane_property : 203 = 6, 0, 11, C, C, 0, 1 +phy_lane_property : 204 = 6, 0, 12, F, F, 0, 0 +phy_lane_property : 205 = 6, 0, 13, 8, 8, 0, 1 +phy_lane_property : 206 = 6, 0, 14, 9, 9, 0, 0 +phy_lane_property : 207 = 6, 0, 15, E, E, 0, 1 + + +# System side lanes: +phy_lane_property : 208 = 6, 1, 4, 0, 0, 0, 0 # UNUSED +phy_lane_property : 209 = 6, 1, 5, 1, 1, 0, 0 # UNUSED +phy_lane_property : 210 = 6, 1, 6, 2, 2, 0, 0 # UNUSED +phy_lane_property : 211 = 6, 1, 7, 3, 3, 0, 0 # UNUSED +phy_lane_property : 212 = 6, 1, 0, 4, 4, 0, 0 +phy_lane_property : 213 = 6, 1, 1, 5, 5, 0, 0 +phy_lane_property : 214 = 6, 1, 2, 6, 6, 0, 0 +phy_lane_property : 215 = 6, 1, 3, 7, 7, 0, 0 +phy_lane_property : 216 = 6, 1, 8, 8, 8, 0, 0 +phy_lane_property : 217 = 6, 1, 9, 9, 9, 0, 0 +phy_lane_property : 218 = 6, 1, 10, A, A, 0, 0 +phy_lane_property : 219 = 6, 1, 11, B, B, 0, 0 +phy_lane_property : 220 = 6, 1, 12, C, C, 0, 0 # UNUSED +phy_lane_property : 221 = 6, 1, 13, D, D, 0, 0 # UNUSED +phy_lane_property : 222 = 6, 1, 14, E, E, 0, 0 # UNUSED +phy_lane_property : 223 = 6, 1, 15, F, F, 0, 0 # UNUSED + +#---------------------------------------------------------------------------------------------------------------- +### PHY CONFIGURATION FILE +### Please refer to config_file_format.txt in the top level folder for configuration file format + +### PHY CONFIGURATIONS +phy_init_config_chip_id:7 = 85361 +phy_init_mode:7 = 0 +phy_init_config_ref_clk:7 = 312000000 + +### LANE CONFIGURATIONS +#---------------------------------------------------------------------------------------------------------------- +# Lane_Property : Global_Lane = PHY_ID, IF_Side, Local_Lane, Tx_Lane_Map, Rx_Lane_Map, Tx_Polarity, Rx_Polarity +#---------------------------------------------------------------------------------------------------------------- +# Line side lanes: +phy_lane_property : 224 = 7, 0, 0, 3, 3, 0, 0 +phy_lane_property : 225 = 7, 0, 1, 4, 4, 0, 1 +phy_lane_property : 226 = 7, 0, 2, 5, 5, 0, 0 +phy_lane_property : 227 = 7, 0, 3, 2, 2, 1, 1 +phy_lane_property : 228 = 7, 0, 4, 1, 1, 1, 0 +phy_lane_property : 229 = 7, 0, 5, 6, 6, 0, 1 +phy_lane_property : 230 = 7, 0, 6, 7, 7, 0, 0 +phy_lane_property : 231 = 7, 0, 7, 0, 0, 1, 1 +phy_lane_property : 232 = 7, 0, 8, D, D, 0, 0 +phy_lane_property : 233 = 7, 0, 9, A, A, 0, 1 +phy_lane_property : 234 = 7, 0, 10, B, B, 0, 0 +phy_lane_property : 235 = 7, 0, 11, C, C, 0, 1 +phy_lane_property : 236 = 7, 0, 12, F, F, 0, 0 +phy_lane_property : 237 = 7, 0, 13, 8, 8, 0, 1 +phy_lane_property : 238 = 7, 0, 14, 9, 9, 0, 0 +phy_lane_property : 239 = 7, 0, 15, E, E, 0, 1 + + +# System side lanes: +phy_lane_property : 240 = 7, 1, 4, 0, 0, 0, 0 # UNUSED +phy_lane_property : 241 = 7, 1, 5, 1, 1, 0, 0 # UNUSED +phy_lane_property : 242 = 7, 1, 6, 2, 2, 0, 0 # UNUSED +phy_lane_property : 243 = 7, 1, 7, 3, 3, 0, 0 # UNUSED +phy_lane_property : 244 = 7, 1, 0, 4, 4, 0, 0 +phy_lane_property : 245 = 7, 1, 1, 5, 5, 0, 0 +phy_lane_property : 246 = 7, 1, 2, 6, 6, 0, 0 +phy_lane_property : 247 = 7, 1, 3, 7, 7, 0, 0 +phy_lane_property : 248 = 7, 1, 8, 8, 8, 0, 0 +phy_lane_property : 249 = 7, 1, 9, 9, 9, 0, 0 +phy_lane_property : 250 = 7, 1, 10, A, A, 0, 0 +phy_lane_property : 251 = 7, 1, 11, B, B, 0, 0 +phy_lane_property : 252 = 7, 1, 12, C, C, 0, 0 # UNUSED +phy_lane_property : 253 = 7, 1, 13, D, D, 0, 0 # UNUSED +phy_lane_property : 254 = 7, 1, 14, E, E, 0, 0 # UNUSED +phy_lane_property : 255 = 7, 1, 15, F, F, 0, 0 # UNUSED + +#---------------------------------------------------------------------------------------------------------------- + diff --git a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/buffer_ports.j2 b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/buffer_ports.j2 new file mode 100644 index 00000000000..b69a14551aa --- /dev/null +++ b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/buffer_ports.j2 @@ -0,0 +1,6 @@ +{%- macro generate_port_lists(PORT_ALL) %} + {# Generate list of ports #} + {%- for port_idx in range(128, 260, 4) %} + {%- if PORT_ALL.append("Ethernet%d" % (port_idx)) %}{%- endif %} + {%- endfor %} +{%- endmacro %} diff --git a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/buffers.json.j2 b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/buffers.json.j2 new file mode 100644 index 00000000000..f34a844f4a8 --- /dev/null +++ b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/buffers.json.j2 @@ -0,0 +1,2 @@ +{%- set default_topo = 't2' %} +{%- include 'buffers_config.j2' %} diff --git a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/buffers_defaults_t2.j2 b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/buffers_defaults_t2.j2 new file mode 100644 index 00000000000..2cf7dca105c --- /dev/null +++ b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/buffers_defaults_t2.j2 @@ -0,0 +1,52 @@ +{%- set default_cable = '300m' %} + +{%- include 'buffer_ports.j2' %} + +{%- macro generate_port_lists(PORT_ALL) %} + {# Generate list of ports #} + {%- for port_idx in range(0,256,8) %} + {%- if PORT_ALL.append("Ethernet%d" % (port_idx)) %}{%- endif %} + {%- endfor %} +{%- endmacro %} + +{%- macro generate_buffer_pool_and_profiles() %} + "BUFFER_POOL": { + "ingress_pool": { + "size": "56441610000", + "type": "both", + "mode": "dynamic" + } + }, + "BUFFER_PROFILE": { + "ingress_lossy_profile": { + "pool":"ingress_pool", + "size":"0", + "dynamic_th":"3" + }, + "egress_lossy_profile": { + "pool":"ingress_pool", + "size":"0", + "dynamic_th":"3" + } + }, +{%- endmacro %} + +{%- macro generate_pg_profils(port_names_active) %} + "BUFFER_PG": { +{% for port in port_names_active.split(',') %} + "{{ port }}|0-7": { + "profile" : "ingress_lossy_profile" + }{% if not loop.last %},{% endif %} +{% endfor %} + }, +{%- endmacro %} + +{% macro generate_queue_buffers(port_names_active) %} + "BUFFER_QUEUE": { +{% for port in port_names_active.split(',') %} + "{{ port }}|0-7": { + "profile" : "egress_lossy_profile" + }{% if not loop.last %},{% endif %} +{% endfor %} + } +{% endmacro %} diff --git a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/context_config.json b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/context_config.json new file mode 100644 index 00000000000..e5e8c1f4768 --- /dev/null +++ b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/context_config.json @@ -0,0 +1,98 @@ +{ + "CONTEXTS": [ + { + "guid": 0, + "name": "sw0", + "dbAsic": "ASIC_DB", + "dbCounters": "COUNTERS_DB", + "dbFlex": "FLEX_COUNTER_DB", + "dbState": "STATE_DB", + "zmq_enable": false, + "zmq_endpoint": "tcp://127.0.0.1:5555", + "zmq_ntf_endpoint": "tcp://127.0.0.1:5556", + "switches": [ + { + "index": 0, + "hwinfo": "" + } + ] + }, + { + "guid": 1, + "name": "phy", + "dbAsic": "GB_ASIC_DB", + "dbCounters": "GB_COUNTERS_DB", + "dbFlex": "GB_FLEX_COUNTER_DB", + "dbState": "STATE_DB", + "zmq_enable": false, + "zmq_endpoint": "tcp://127.0.0.1:5565", + "zmq_ntf_endpoint": "tcp://127.0.0.1:5566", + "switches": [ + { + "index": 9, + "hwinfo": "9" + }, + { + "index": 8, + "hwinfo": "8" + }, + { + "index": 10, + "hwinfo": "10" + }, + { + "index": 11, + "hwinfo": "11" + }, + { + "index": 12, + "hwinfo": "12" + }, + { + "index": 13, + "hwinfo": "13" + }, + { + "index": 14, + "hwinfo": "14" + }, + { + "index": 15, + "hwinfo": "15" + }, + { + "index": 0, + "hwinfo": "0" + }, + { + "index": 1, + "hwinfo": "1" + }, + { + "index": 2, + "hwinfo": "2" + }, + { + "index": 3, + "hwinfo": "3" + }, + { + "index": 4, + "hwinfo": "4" + }, + { + "index": 5, + "hwinfo": "5" + }, + { + "index": 6, + "hwinfo": "6" + }, + { + "index": 7, + "hwinfo": "7" + } + ] + } + ] +} \ No newline at end of file diff --git a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/gearbox_config.json b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/gearbox_config.json new file mode 100644 index 00000000000..9003187a182 --- /dev/null +++ b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/gearbox_config.json @@ -0,0 +1,438 @@ +{ + "phys": [ + { + "phy_id": 0, + "name": "phy0", + "address": "2031617", + "lib_name": "libsai.so", + "firmware_path": "", + "config_file": "/usr/share/sonic/hwsku/phy0_config.json", + "sai_init_config_file": "", + "phy_access": "mdio", + "bus_id": 0, + "context_id": 1, + "hwinfo": "0" + }, + { + "phy_id": 1, + "name": "phy1", + "address": "2031616", + "lib_name": "libsai.so", + "firmware_path": "", + "config_file": "/usr/share/sonic/hwsku/phy1_config.json", + "sai_init_config_file": "", + "phy_access": "mdio", + "bus_id": 0, + "context_id": 1, + "hwinfo": "1" + }, + { + "phy_id": 2, + "name": "phy2", + "address": "2031619", + "lib_name": "libsai.so", + "firmware_path": "", + "config_file": "/usr/share/sonic/hwsku/phy2_config.json", + "sai_init_config_file": "", + "phy_access": "mdio", + "bus_id": 0, + "context_id": 1, + "hwinfo": "2" + }, + { + "phy_id": 3, + "name": "phy3", + "address": "2031618", + "lib_name": "libsai.so", + "firmware_path": "", + "config_file": "/usr/share/sonic/hwsku/phy3_config.json", + "sai_init_config_file": "", + "phy_access": "mdio", + "bus_id": 0, + "context_id": 1, + "hwinfo": "3" + }, + { + "phy_id": 4, + "name": "phy4", + "address": "2031621", + "lib_name": "libsai.so", + "firmware_path": "", + "config_file": "/usr/share/sonic/hwsku/phy4_config.json", + "sai_init_config_file": "", + "phy_access": "mdio", + "bus_id": 0, + "context_id": 1, + "hwinfo": "4" + }, + { + "phy_id": 5, + "name": "phy5", + "address": "2031620", + "lib_name": "libsai.so", + "firmware_path": "", + "config_file": "/usr/share/sonic/hwsku/phy5_config.json", + "sai_init_config_file": "", + "phy_access": "mdio", + "bus_id": 0, + "context_id": 1, + "hwinfo": "5" + }, + { + "phy_id": 6, + "name": "phy6", + "address": "2031623", + "lib_name": "libsai.so", + "firmware_path": "", + "config_file": "/usr/share/sonic/hwsku/phy6_config.json", + "sai_init_config_file": "", + "phy_access": "mdio", + "bus_id": 0, + "context_id": 1, + "hwinfo": "6" + }, + { + "phy_id": 7, + "name": "phy7", + "address": "2031622", + "lib_name": "libsai.so", + "firmware_path": "", + "config_file": "/usr/share/sonic/hwsku/phy7_config.json", + "sai_init_config_file": "", + "phy_access": "mdio", + "bus_id": 0, + "context_id": 1, + "hwinfo": "7" + }, + { + "phy_id": 8, + "name": "phy8", + "address": "2031625", + "lib_name": "libsai.so", + "firmware_path": "", + "config_file": "/usr/share/sonic/hwsku/phy8_config.json", + "sai_init_config_file": "", + "phy_access": "mdio", + "bus_id": 0, + "context_id": 1, + "hwinfo": "8" + }, + { + "phy_id": 9, + "name": "phy9", + "address": "2031624", + "lib_name": "libsai.so", + "firmware_path": "", + "config_file": "/usr/share/sonic/hwsku/phy9_config.json", + "sai_init_config_file": "", + "phy_access": "mdio", + "bus_id": 0, + "context_id": 1, + "hwinfo": "9" + }, + { + "phy_id": 10, + "name": "phy10", + "address": "2031626", + "lib_name": "libsai.so", + "firmware_path": "", + "config_file": "/usr/share/sonic/hwsku/phy10_config.json", + "sai_init_config_file": "", + "phy_access": "mdio", + "bus_id": 0, + "context_id": 1, + "hwinfo": "10" + }, + { + "phy_id": 11, + "name": "phy11", + "address": "2031627", + "lib_name": "libsai.so", + "firmware_path": "", + "config_file": "/usr/share/sonic/hwsku/phy11_config.json", + "sai_init_config_file": "", + "phy_access": "mdio", + "bus_id": 0, + "context_id": 1, + "hwinfo": "11" + }, + { + "phy_id": 12, + "name": "phy12", + "address": "2031628", + "lib_name": "libsai.so", + "firmware_path": "", + "config_file": "/usr/share/sonic/hwsku/phy12_config.json", + "sai_init_config_file": "", + "phy_access": "mdio", + "bus_id": 0, + "context_id": 1, + "hwinfo": "12" + }, + { + "phy_id": 13, + "name": "phy13", + "address": "2031629", + "lib_name": "libsai.so", + "firmware_path": "", + "config_file": "/usr/share/sonic/hwsku/phy13_config.json", + "sai_init_config_file": "", + "phy_access": "mdio", + "bus_id": 0, + "context_id": 1, + "hwinfo": "13" + }, + { + "phy_id": 14, + "name": "phy14", + "address": "2031630", + "lib_name": "libsai.so", + "firmware_path": "", + "config_file": "/usr/share/sonic/hwsku/phy14_config.json", + "sai_init_config_file": "", + "phy_access": "mdio", + "bus_id": 0, + "context_id": 1, + "hwinfo": "14" + }, + { + "phy_id": 15, + "name": "phy15", + "address": "2031631", + "lib_name": "libsai.so", + "firmware_path": "", + "config_file": "/usr/share/sonic/hwsku/phy15_config.json", + "sai_init_config_file": "", + "phy_access": "mdio", + "bus_id": 0, + "context_id": 1, + "hwinfo": "15" + } + ], + "interfaces": [ + { + "name": "Ethernet0", + "index": 1, + "phy_id": 0, + "system_lanes": [20,21,22,23], + "line_lanes": [0,1,2,3] + }, + { + "name": "Ethernet4", + "index": 2, + "phy_id": 0, + "system_lanes": [24,25,26,27], + "line_lanes": [8,9,10,11] + }, + { + "name": "Ethernet8", + "index": 3, + "phy_id": 1, + "system_lanes": [52,53,54,55], + "line_lanes": [32,33,34,35] + }, + { + "name": "Ethernet12", + "index": 4, + "phy_id": 1, + "system_lanes": [56,57,58,59], + "line_lanes": [40,41,42,43] + }, + { + "name": "Ethernet16", + "index": 5, + "phy_id": 2, + "system_lanes": [84,85,86,87], + "line_lanes": [64,65,66,67] + }, + { + "name": "Ethernet20", + "index": 6, + "phy_id": 2, + "system_lanes": [88,89,90,91], + "line_lanes": [72,73,74,75] + }, + { + "name": "Ethernet24", + "index": 7, + "phy_id": 3, + "system_lanes": [116,117,118,119], + "line_lanes": [96,97,98,99] + }, + { + "name": "Ethernet28", + "index": 8, + "phy_id": 3, + "system_lanes": [120,121,122,123], + "line_lanes": [104,105,106,107] + }, + { + "name": "Ethernet32", + "index": 9, + "phy_id": 4, + "system_lanes": [148,149,150,151], + "line_lanes": [128,129,130,131] + }, + { + "name": "Ethernet36", + "index": 10, + "phy_id": 4, + "system_lanes": [152,153,154,155], + "line_lanes": [136,137,138,139] + }, + { + "name": "Ethernet40", + "index": 11, + "phy_id": 5, + "system_lanes": [180,181,182,183], + "line_lanes": [160,161,162,163] + }, + { + "name": "Ethernet44", + "index": 12, + "phy_id": 5, + "system_lanes": [184,185,186,187], + "line_lanes": [168,169,170,171] + }, + { + "name": "Ethernet48", + "index": 13, + "phy_id": 6, + "system_lanes": [212,213,214,215], + "line_lanes": [192,193,194,195] + }, + { + "name": "Ethernet52", + "index": 14, + "phy_id": 6, + "system_lanes": [216,217,218,219], + "line_lanes": [200,201,202,203] + }, + { + "name": "Ethernet56", + "index": 15, + "phy_id": 7, + "system_lanes": [244,245,246,247], + "line_lanes": [224,225,226,227] + }, + { + "name": "Ethernet60", + "index": 16, + "phy_id": 7, + "system_lanes": [248,249,250,251], + "line_lanes": [232,233,234,235] + }, + { + "name": "Ethernet64", + "index": 17, + "phy_id": 8, + "system_lanes": [276,277,278,279], + "line_lanes": [256,257,258,259] + }, + { + "name": "Ethernet68", + "index": 18, + "phy_id": 8, + "system_lanes": [280,281,282,283], + "line_lanes": [264,265,266,267] + }, + { + "name": "Ethernet72", + "index": 19, + "phy_id": 9, + "system_lanes": [308,309,310,311], + "line_lanes": [288,289,290,291] + }, + { + "name": "Ethernet76", + "index": 20, + "phy_id": 9, + "system_lanes": [312,313,314,315], + "line_lanes": [296,297,298,299] + }, + { + "name": "Ethernet80", + "index": 21, + "phy_id": 10, + "system_lanes": [340,341,342,343], + "line_lanes": [320,321,322,323] + }, + { + "name": "Ethernet84", + "index": 22, + "phy_id": 10, + "system_lanes": [344,345,346,347], + "line_lanes": [328,329,330,331] + }, + { + "name": "Ethernet88", + "index": 23, + "phy_id": 11, + "system_lanes": [372,373,374,375], + "line_lanes": [352,353,354,355] + }, + { + "name": "Ethernet92", + "index": 24, + "phy_id": 11, + "system_lanes": [376,377,378,379], + "line_lanes": [360,361,362,363] + }, + { + "name": "Ethernet96", + "index": 25, + "phy_id": 12, + "system_lanes": [404,405,406,407], + "line_lanes": [384,385,386,387] + }, + { + "name": "Ethernet100", + "index": 26, + "phy_id": 12, + "system_lanes": [408,409,410,411], + "line_lanes": [392,393,394,395] + }, + { + "name": "Ethernet104", + "index": 27, + "phy_id": 13, + "system_lanes": [436,437,438,439], + "line_lanes": [416,417,418,419] + }, + { + "name": "Ethernet108", + "index": 28, + "phy_id": 13, + "system_lanes": [440,441,442,443], + "line_lanes": [424,425,426,427] + }, + { + "name": "Ethernet112", + "index": 29, + "phy_id": 14, + "system_lanes": [468,469,470,471], + "line_lanes": [448,449,450,451] + }, + { + "name": "Ethernet116", + "index": 30, + "phy_id": 14, + "system_lanes": [472,473,474,475], + "line_lanes": [456,457,458,459] + }, + { + "name": "Ethernet120", + "index": 31, + "phy_id": 15, + "system_lanes": [500,501,502,503], + "line_lanes": [480,481,482,483] + }, + { + "name": "Ethernet124", + "index": 32, + "phy_id": 15, + "system_lanes": [504,505,506,507], + "line_lanes": [488,489,490,491] + } + ] +} \ No newline at end of file diff --git a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/hwsku.json b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/hwsku.json new file mode 100644 index 00000000000..dd80f4d42f8 --- /dev/null +++ b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/hwsku.json @@ -0,0 +1,334 @@ +{ + "interfaces": { + "Ethernet0": { + "autoneg": "off", + "default_brkout_mode": "1x100G", + "fec": "rs" + }, + "Ethernet4": { + "autoneg": "off", + "default_brkout_mode": "1x100G", + "fec": "rs" + }, + "Ethernet8": { + "autoneg": "off", + "default_brkout_mode": "1x100G", + "fec": "rs" + }, + "Ethernet12": { + "autoneg": "off", + "default_brkout_mode": "1x100G", + "fec": "rs" + }, + "Ethernet16": { + "autoneg": "off", + "default_brkout_mode": "1x100G", + "fec": "rs" + }, + "Ethernet20": { + "autoneg": "off", + "default_brkout_mode": "1x100G", + "fec": "rs" + }, + "Ethernet24": { + "autoneg": "off", + "default_brkout_mode": "1x100G", + "fec": "rs" + }, + "Ethernet28": { + "autoneg": "off", + "default_brkout_mode": "1x100G", + "fec": "rs" + }, + "Ethernet32": { + "autoneg": "off", + "default_brkout_mode": "1x100G", + "fec": "rs" + }, + "Ethernet36": { + "autoneg": "off", + "default_brkout_mode": "1x100G", + "fec": "rs" + }, + "Ethernet40": { + "autoneg": "off", + "default_brkout_mode": "1x100G", + "fec": "rs" + }, + "Ethernet44": { + "autoneg": "off", + "default_brkout_mode": "1x100G", + "fec": "rs" + }, + "Ethernet48": { + "autoneg": "off", + "default_brkout_mode": "1x100G", + "fec": "rs" + }, + "Ethernet52": { + "autoneg": "off", + "default_brkout_mode": "1x100G", + "fec": "rs" + }, + "Ethernet56": { + "autoneg": "off", + "default_brkout_mode": "1x100G", + "fec": "rs" + }, + "Ethernet60": { + "autoneg": "off", + "default_brkout_mode": "1x100G", + "fec": "rs" + }, + "Ethernet64": { + "autoneg": "off", + "default_brkout_mode": "1x100G", + "fec": "rs" + }, + "Ethernet68": { + "autoneg": "off", + "default_brkout_mode": "1x100G", + "fec": "rs" + }, + "Ethernet72": { + "autoneg": "off", + "default_brkout_mode": "1x100G", + "fec": "rs" + }, + "Ethernet76": { + "autoneg": "off", + "default_brkout_mode": "1x100G", + "fec": "rs" + }, + "Ethernet80": { + "autoneg": "off", + "default_brkout_mode": "1x100G", + "fec": "rs" + }, + "Ethernet84": { + "autoneg": "off", + "default_brkout_mode": "1x100G", + "fec": "rs" + }, + "Ethernet88": { + "autoneg": "off", + "default_brkout_mode": "1x100G", + "fec": "rs" + }, + "Ethernet92": { + "autoneg": "off", + "default_brkout_mode": "1x100G", + "fec": "rs" + }, + "Ethernet96": { + "autoneg": "off", + "default_brkout_mode": "1x100G", + "fec": "rs" + }, + "Ethernet100": { + "autoneg": "off", + "default_brkout_mode": "1x100G", + "fec": "rs" + }, + "Ethernet104": { + "autoneg": "off", + "default_brkout_mode": "1x100G", + "fec": "rs" + }, + "Ethernet108": { + "autoneg": "off", + "default_brkout_mode": "1x100G", + "fec": "rs" + }, + "Ethernet112": { + "autoneg": "off", + "default_brkout_mode": "1x100G", + "fec": "rs" + }, + "Ethernet116": { + "autoneg": "off", + "default_brkout_mode": "1x100G", + "fec": "rs" + }, + "Ethernet120": { + "autoneg": "off", + "default_brkout_mode": "1x100G", + "fec": "rs" + }, + "Ethernet124": { + "autoneg": "off", + "default_brkout_mode": "1x100G", + "fec": "rs" + }, + "Ethernet128": { + "autoneg": "off", + "default_brkout_mode": "1x400G", + "fec": "rs" + }, + "Ethernet132": { + "autoneg": "off", + "default_brkout_mode": "1x400G", + "fec": "rs" + }, + "Ethernet136": { + "autoneg": "off", + "default_brkout_mode": "1x400G", + "fec": "rs" + }, + "Ethernet140": { + "autoneg": "off", + "default_brkout_mode": "1x400G", + "fec": "rs" + }, + "Ethernet144": { + "autoneg": "off", + "default_brkout_mode": "1x400G", + "fec": "rs" + }, + "Ethernet148": { + "autoneg": "off", + "default_brkout_mode": "1x400G", + "fec": "rs" + }, + "Ethernet152": { + "autoneg": "off", + "default_brkout_mode": "1x400G", + "fec": "rs" + }, + "Ethernet156": { + "autoneg": "off", + "default_brkout_mode": "1x400G", + "fec": "rs" + }, + "Ethernet160": { + "autoneg": "off", + "default_brkout_mode": "1x400G", + "fec": "rs" + }, + "Ethernet164": { + "autoneg": "off", + "default_brkout_mode": "1x400G", + "fec": "rs" + }, + "Ethernet168": { + "autoneg": "off", + "default_brkout_mode": "1x400G", + "fec": "rs" + }, + "Ethernet172": { + "autoneg": "off", + "default_brkout_mode": "1x400G", + "fec": "rs" + }, + "Ethernet176": { + "autoneg": "off", + "default_brkout_mode": "1x400G", + "fec": "rs" + }, + "Ethernet180": { + "autoneg": "off", + "default_brkout_mode": "1x400G", + "fec": "rs" + }, + "Ethernet184": { + "autoneg": "off", + "default_brkout_mode": "1x400G", + "fec": "rs" + }, + "Ethernet188": { + "autoneg": "off", + "default_brkout_mode": "1x400G", + "fec": "rs" + }, + "Ethernet192": { + "autoneg": "off", + "default_brkout_mode": "1x400G", + "fec": "rs" + }, + "Ethernet196": { + "autoneg": "off", + "default_brkout_mode": "1x400G", + "fec": "rs" + }, + "Ethernet200": { + "autoneg": "off", + "default_brkout_mode": "1x400G", + "fec": "rs" + }, + "Ethernet204": { + "autoneg": "off", + "default_brkout_mode": "1x400G", + "fec": "rs" + }, + "Ethernet208": { + "autoneg": "off", + "default_brkout_mode": "1x400G", + "fec": "rs" + }, + "Ethernet212": { + "autoneg": "off", + "default_brkout_mode": "1x400G", + "fec": "rs" + }, + "Ethernet216": { + "autoneg": "off", + "default_brkout_mode": "1x400G", + "fec": "rs" + }, + "Ethernet220": { + "autoneg": "off", + "default_brkout_mode": "1x400G", + "fec": "rs" + }, + "Ethernet224": { + "autoneg": "off", + "default_brkout_mode": "1x400G", + "fec": "rs" + }, + "Ethernet228": { + "autoneg": "off", + "default_brkout_mode": "1x400G", + "fec": "rs" + }, + "Ethernet232": { + "autoneg": "off", + "default_brkout_mode": "1x400G", + "fec": "rs" + }, + "Ethernet236": { + "autoneg": "off", + "default_brkout_mode": "1x400G", + "fec": "rs" + }, + "Ethernet240": { + "autoneg": "off", + "default_brkout_mode": "1x400G", + "fec": "rs" + }, + "Ethernet244": { + "autoneg": "off", + "default_brkout_mode": "1x400G", + "fec": "rs" + }, + "Ethernet248": { + "autoneg": "off", + "default_brkout_mode": "1x400G", + "fec": "rs" + }, + "Ethernet252": { + "autoneg": "off", + "default_brkout_mode": "1x400G", + "fec": "rs" + }, + "Ethernet256": { + "autoneg": "off", + "default_brkout_mode": "1x100G", + "fec": "rs" + }, + "Ethernet260": { + "autoneg": "off", + "default_brkout_mode": "1x100G", + "fec": "rs" + } + } +} \ No newline at end of file diff --git a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/nh5010-default.bcm b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/nh5010-default.bcm new file mode 100644 index 00000000000..522d09de224 --- /dev/null +++ b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/nh5010-default.bcm @@ -0,0 +1,2260 @@ +# ---------------------------------------------------------------------------------------------------- +# core_0 +# ---------------------------------------------------------------------------------------------------- +ucode_port_185.BCM8887X=CDGE4_0:core_0.1 +tm_port_header_type_out_185.BCM8887X=ETH +ucode_port_189.BCM8887X=CDGE4_1:core_0.5 +tm_port_header_type_out_189.BCM8887X=ETH + +# core 0 lane0 +lane_to_serdes_map_nif_lane0.BCM8887X=rx6:tx7 +phy_rx_polarity_flip_phy0.BCM8887X=0 +phy_tx_polarity_flip_phy0.BCM8887X=1 +serdes_tx_taps_0.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 0 lane1 +lane_to_serdes_map_nif_lane1.BCM8887X=rx4:tx3 +phy_rx_polarity_flip_phy1.BCM8887X=0 +phy_tx_polarity_flip_phy1.BCM8887X=1 +serdes_tx_taps_1.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 0 lane2 +lane_to_serdes_map_nif_lane2.BCM8887X=rx7:tx1 +phy_rx_polarity_flip_phy2.BCM8887X=0 +phy_tx_polarity_flip_phy2.BCM8887X=0 +serdes_tx_taps_2.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 0 lane3 +lane_to_serdes_map_nif_lane3.BCM8887X=rx5:tx2 +phy_rx_polarity_flip_phy3.BCM8887X=0 +phy_tx_polarity_flip_phy3.BCM8887X=1 +serdes_tx_taps_3.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 0 lane4 +lane_to_serdes_map_nif_lane4.BCM8887X=rx2:tx0 +phy_rx_polarity_flip_phy4.BCM8887X=0 +phy_tx_polarity_flip_phy4.BCM8887X=0 +serdes_tx_taps_4.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 0 lane5 +lane_to_serdes_map_nif_lane5.BCM8887X=rx3:tx6 +phy_rx_polarity_flip_phy5.BCM8887X=1 +phy_tx_polarity_flip_phy5.BCM8887X=1 +serdes_tx_taps_5.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 0 lane6 +lane_to_serdes_map_nif_lane6.BCM8887X=rx0:tx4 +phy_rx_polarity_flip_phy6.BCM8887X=0 +phy_tx_polarity_flip_phy6.BCM8887X=0 +serdes_tx_taps_6.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 0 lane7 +lane_to_serdes_map_nif_lane7.BCM8887X=rx1:tx5 +phy_rx_polarity_flip_phy7.BCM8887X=0 +phy_tx_polarity_flip_phy7.BCM8887X=0 +serdes_tx_taps_7.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + + +# ---------------------------------------------------------------------------------------------------- +# core_1 +# ---------------------------------------------------------------------------------------------------- +ucode_port_177.BCM8887X=CDGE4_2:core_0.9 +tm_port_header_type_out_177.BCM8887X=ETH +ucode_port_181.BCM8887X=CDGE4_3:core_0.13 +tm_port_header_type_out_181.BCM8887X=ETH + +# core 1 lane8 +lane_to_serdes_map_nif_lane8.BCM8887X=rx10:tx8 +phy_rx_polarity_flip_phy8.BCM8887X=0 +phy_tx_polarity_flip_phy8.BCM8887X=0 +serdes_tx_taps_8.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 1 lane9 +lane_to_serdes_map_nif_lane9.BCM8887X=rx11:tx14 +phy_rx_polarity_flip_phy9.BCM8887X=1 +phy_tx_polarity_flip_phy9.BCM8887X=1 +serdes_tx_taps_9.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 1 lane10 +lane_to_serdes_map_nif_lane10.BCM8887X=rx8:tx12 +phy_rx_polarity_flip_phy10.BCM8887X=1 +phy_tx_polarity_flip_phy10.BCM8887X=0 +serdes_tx_taps_10.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 1 lane11 +lane_to_serdes_map_nif_lane11.BCM8887X=rx9:tx13 +phy_rx_polarity_flip_phy11.BCM8887X=0 +phy_tx_polarity_flip_phy11.BCM8887X=0 +serdes_tx_taps_11.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 1 lane12 +lane_to_serdes_map_nif_lane12.BCM8887X=rx14:tx15 +phy_rx_polarity_flip_phy12.BCM8887X=0 +phy_tx_polarity_flip_phy12.BCM8887X=1 +serdes_tx_taps_12.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 1 lane13 +lane_to_serdes_map_nif_lane13.BCM8887X=rx12:tx11 +phy_rx_polarity_flip_phy13.BCM8887X=0 +phy_tx_polarity_flip_phy13.BCM8887X=1 +serdes_tx_taps_13.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 1 lane14 +lane_to_serdes_map_nif_lane14.BCM8887X=rx15:tx9 +phy_rx_polarity_flip_phy14.BCM8887X=0 +phy_tx_polarity_flip_phy14.BCM8887X=0 +serdes_tx_taps_14.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 1 lane15 +lane_to_serdes_map_nif_lane15.BCM8887X=rx13:tx10 +phy_rx_polarity_flip_phy15.BCM8887X=0 +phy_tx_polarity_flip_phy15.BCM8887X=1 +serdes_tx_taps_15.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + + +# ---------------------------------------------------------------------------------------------------- +# core_2 +# ---------------------------------------------------------------------------------------------------- +ucode_port_169.BCM8887X=CDGE4_4:core_0.17 +tm_port_header_type_out_169.BCM8887X=ETH +ucode_port_173.BCM8887X=CDGE4_5:core_0.21 +tm_port_header_type_out_173.BCM8887X=ETH + +# core 2 lane16 +lane_to_serdes_map_nif_lane16.BCM8887X=rx18:tx16 +phy_rx_polarity_flip_phy16.BCM8887X=0 +phy_tx_polarity_flip_phy16.BCM8887X=0 +serdes_tx_taps_16.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 2 lane17 +lane_to_serdes_map_nif_lane17.BCM8887X=rx19:tx22 +phy_rx_polarity_flip_phy17.BCM8887X=1 +phy_tx_polarity_flip_phy17.BCM8887X=1 +serdes_tx_taps_17.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 2 lane18 +lane_to_serdes_map_nif_lane18.BCM8887X=rx16:tx20 +phy_rx_polarity_flip_phy18.BCM8887X=0 +phy_tx_polarity_flip_phy18.BCM8887X=0 +serdes_tx_taps_18.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 2 lane19 +lane_to_serdes_map_nif_lane19.BCM8887X=rx17:tx21 +phy_rx_polarity_flip_phy19.BCM8887X=0 +phy_tx_polarity_flip_phy19.BCM8887X=0 +serdes_tx_taps_19.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 2 lane20 +lane_to_serdes_map_nif_lane20.BCM8887X=rx22:tx23 +phy_rx_polarity_flip_phy20.BCM8887X=0 +phy_tx_polarity_flip_phy20.BCM8887X=1 +serdes_tx_taps_20.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 2 lane21 +lane_to_serdes_map_nif_lane21.BCM8887X=rx20:tx19 +phy_rx_polarity_flip_phy21.BCM8887X=0 +phy_tx_polarity_flip_phy21.BCM8887X=1 +serdes_tx_taps_21.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 2 lane22 +lane_to_serdes_map_nif_lane22.BCM8887X=rx23:tx17 +phy_rx_polarity_flip_phy22.BCM8887X=0 +phy_tx_polarity_flip_phy22.BCM8887X=0 +serdes_tx_taps_22.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 2 lane23 +lane_to_serdes_map_nif_lane23.BCM8887X=rx21:tx18 +phy_rx_polarity_flip_phy23.BCM8887X=0 +phy_tx_polarity_flip_phy23.BCM8887X=1 +serdes_tx_taps_23.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + + +# ---------------------------------------------------------------------------------------------------- +# core_3 +# ---------------------------------------------------------------------------------------------------- +ucode_port_161.BCM8887X=CDGE4_6:core_0.25 +tm_port_header_type_out_161.BCM8887X=ETH +ucode_port_165.BCM8887X=CDGE4_7:core_0.29 +tm_port_header_type_out_165.BCM8887X=ETH + +# core 3 lane24 +lane_to_serdes_map_nif_lane24.BCM8887X=rx26:tx26 +phy_rx_polarity_flip_phy24.BCM8887X=1 +phy_tx_polarity_flip_phy24.BCM8887X=0 +serdes_tx_taps_24.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 3 lane25 +lane_to_serdes_map_nif_lane25.BCM8887X=rx27:tx25 +phy_rx_polarity_flip_phy25.BCM8887X=0 +phy_tx_polarity_flip_phy25.BCM8887X=1 +serdes_tx_taps_25.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 3 lane26 +lane_to_serdes_map_nif_lane26.BCM8887X=rx28:tx31 +phy_rx_polarity_flip_phy26.BCM8887X=0 +phy_tx_polarity_flip_phy26.BCM8887X=0 +serdes_tx_taps_26.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 3 lane27 +lane_to_serdes_map_nif_lane27.BCM8887X=rx30:tx24 +phy_rx_polarity_flip_phy27.BCM8887X=1 +phy_tx_polarity_flip_phy27.BCM8887X=0 +serdes_tx_taps_27.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 3 lane28 +lane_to_serdes_map_nif_lane28.BCM8887X=rx29:tx28 +phy_rx_polarity_flip_phy28.BCM8887X=1 +phy_tx_polarity_flip_phy28.BCM8887X=1 +serdes_tx_taps_28.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 3 lane29 +lane_to_serdes_map_nif_lane29.BCM8887X=rx31:tx27 +phy_rx_polarity_flip_phy29.BCM8887X=0 +phy_tx_polarity_flip_phy29.BCM8887X=1 +serdes_tx_taps_29.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 3 lane30 +lane_to_serdes_map_nif_lane30.BCM8887X=rx24:tx30 +phy_rx_polarity_flip_phy30.BCM8887X=0 +phy_tx_polarity_flip_phy30.BCM8887X=1 +serdes_tx_taps_30.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 3 lane31 +lane_to_serdes_map_nif_lane31.BCM8887X=rx25:tx29 +phy_rx_polarity_flip_phy31.BCM8887X=0 +phy_tx_polarity_flip_phy31.BCM8887X=1 +serdes_tx_taps_31.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + + +# ---------------------------------------------------------------------------------------------------- +# core_4 +# ---------------------------------------------------------------------------------------------------- +ucode_port_57.BCM8887X=CGE8:core_1.1 +tm_port_header_type_out_57.BCM8887X=ETH +ucode_port_61.BCM8887X=CGE9:core_1.5 +tm_port_header_type_out_61.BCM8887X=ETH + +# core 4 lane32 +lane_to_serdes_map_nif_lane32.BCM8887X=rx35:tx39 +phy_rx_polarity_flip_phy32.BCM8887X=1 +phy_tx_polarity_flip_phy32.BCM8887X=0 +serdes_tx_taps_32.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 4 lane33 +lane_to_serdes_map_nif_lane33.BCM8887X=rx34:tx35 +phy_rx_polarity_flip_phy33.BCM8887X=0 +phy_tx_polarity_flip_phy33.BCM8887X=0 +serdes_tx_taps_33.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 4 lane34 +lane_to_serdes_map_nif_lane34.BCM8887X=rx37:tx34 +phy_rx_polarity_flip_phy34.BCM8887X=1 +phy_tx_polarity_flip_phy34.BCM8887X=0 +serdes_tx_taps_34.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 4 lane35 +lane_to_serdes_map_nif_lane35.BCM8887X=rx39:tx33 +phy_rx_polarity_flip_phy35.BCM8887X=1 +phy_tx_polarity_flip_phy35.BCM8887X=1 +serdes_tx_taps_35.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 4 lane36 +lane_to_serdes_map_nif_lane36.BCM8887X=rx33:tx36 +phy_rx_polarity_flip_phy36.BCM8887X=1 +phy_tx_polarity_flip_phy36.BCM8887X=0 +serdes_tx_taps_36.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 4 lane37 +lane_to_serdes_map_nif_lane37.BCM8887X=rx32:tx37 +phy_rx_polarity_flip_phy37.BCM8887X=0 +phy_tx_polarity_flip_phy37.BCM8887X=1 +serdes_tx_taps_37.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 4 lane38 +lane_to_serdes_map_nif_lane38.BCM8887X=rx36:tx38 +phy_rx_polarity_flip_phy38.BCM8887X=0 +phy_tx_polarity_flip_phy38.BCM8887X=0 +serdes_tx_taps_38.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 4 lane39 +lane_to_serdes_map_nif_lane39.BCM8887X=rx38:tx32 +phy_rx_polarity_flip_phy39.BCM8887X=0 +phy_tx_polarity_flip_phy39.BCM8887X=1 +serdes_tx_taps_39.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + + +# ---------------------------------------------------------------------------------------------------- +# core_5 +# ---------------------------------------------------------------------------------------------------- +ucode_port_49.BCM8887X=CGE10:core_1.9 +tm_port_header_type_out_49.BCM8887X=ETH +ucode_port_53.BCM8887X=CGE11:core_1.13 +tm_port_header_type_out_53.BCM8887X=ETH + +# core 5 lane40 +lane_to_serdes_map_nif_lane40.BCM8887X=rx43:tx47 +phy_rx_polarity_flip_phy40.BCM8887X=1 +phy_tx_polarity_flip_phy40.BCM8887X=0 +serdes_tx_taps_40.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 5 lane41 +lane_to_serdes_map_nif_lane41.BCM8887X=rx42:tx43 +phy_rx_polarity_flip_phy41.BCM8887X=0 +phy_tx_polarity_flip_phy41.BCM8887X=0 +serdes_tx_taps_41.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 5 lane42 +lane_to_serdes_map_nif_lane42.BCM8887X=rx45:tx42 +phy_rx_polarity_flip_phy42.BCM8887X=1 +phy_tx_polarity_flip_phy42.BCM8887X=0 +serdes_tx_taps_42.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 5 lane43 +lane_to_serdes_map_nif_lane43.BCM8887X=rx47:tx41 +phy_rx_polarity_flip_phy43.BCM8887X=1 +phy_tx_polarity_flip_phy43.BCM8887X=1 +serdes_tx_taps_43.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 5 lane44 +lane_to_serdes_map_nif_lane44.BCM8887X=rx41:tx44 +phy_rx_polarity_flip_phy44.BCM8887X=1 +phy_tx_polarity_flip_phy44.BCM8887X=0 +serdes_tx_taps_44.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 5 lane45 +lane_to_serdes_map_nif_lane45.BCM8887X=rx40:tx45 +phy_rx_polarity_flip_phy45.BCM8887X=0 +phy_tx_polarity_flip_phy45.BCM8887X=1 +serdes_tx_taps_45.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 5 lane46 +lane_to_serdes_map_nif_lane46.BCM8887X=rx44:tx46 +phy_rx_polarity_flip_phy46.BCM8887X=0 +phy_tx_polarity_flip_phy46.BCM8887X=0 +serdes_tx_taps_46.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 5 lane47 +lane_to_serdes_map_nif_lane47.BCM8887X=rx46:tx40 +phy_rx_polarity_flip_phy47.BCM8887X=0 +phy_tx_polarity_flip_phy47.BCM8887X=1 +serdes_tx_taps_47.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + + +# ---------------------------------------------------------------------------------------------------- +# core_6 +# ---------------------------------------------------------------------------------------------------- +ucode_port_41.BCM8887X=CGE12:core_1.17 +tm_port_header_type_out_41.BCM8887X=ETH +ucode_port_45.BCM8887X=CGE13:core_1.21 +tm_port_header_type_out_45.BCM8887X=ETH + +# core 6 lane48 +lane_to_serdes_map_nif_lane48.BCM8887X=rx51:tx55 +phy_rx_polarity_flip_phy48.BCM8887X=1 +phy_tx_polarity_flip_phy48.BCM8887X=0 +serdes_tx_taps_48.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 6 lane49 +lane_to_serdes_map_nif_lane49.BCM8887X=rx50:tx51 +phy_rx_polarity_flip_phy49.BCM8887X=0 +phy_tx_polarity_flip_phy49.BCM8887X=0 +serdes_tx_taps_49.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 6 lane50 +lane_to_serdes_map_nif_lane50.BCM8887X=rx53:tx50 +phy_rx_polarity_flip_phy50.BCM8887X=1 +phy_tx_polarity_flip_phy50.BCM8887X=0 +serdes_tx_taps_50.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 6 lane51 +lane_to_serdes_map_nif_lane51.BCM8887X=rx55:tx49 +phy_rx_polarity_flip_phy51.BCM8887X=1 +phy_tx_polarity_flip_phy51.BCM8887X=1 +serdes_tx_taps_51.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 6 lane52 +lane_to_serdes_map_nif_lane52.BCM8887X=rx49:tx52 +phy_rx_polarity_flip_phy52.BCM8887X=1 +phy_tx_polarity_flip_phy52.BCM8887X=0 +serdes_tx_taps_52.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 6 lane53 +lane_to_serdes_map_nif_lane53.BCM8887X=rx48:tx53 +phy_rx_polarity_flip_phy53.BCM8887X=0 +phy_tx_polarity_flip_phy53.BCM8887X=1 +serdes_tx_taps_53.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 6 lane54 +lane_to_serdes_map_nif_lane54.BCM8887X=rx52:tx54 +phy_rx_polarity_flip_phy54.BCM8887X=0 +phy_tx_polarity_flip_phy54.BCM8887X=0 +serdes_tx_taps_54.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 6 lane55 +lane_to_serdes_map_nif_lane55.BCM8887X=rx54:tx48 +phy_rx_polarity_flip_phy55.BCM8887X=0 +phy_tx_polarity_flip_phy55.BCM8887X=1 +serdes_tx_taps_55.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + + +# ---------------------------------------------------------------------------------------------------- +# core_7 +# ---------------------------------------------------------------------------------------------------- +ucode_port_33.BCM8887X=CGE14:core_1.25 +tm_port_header_type_out_33.BCM8887X=ETH +ucode_port_37.BCM8887X=CGE15:core_1.29 +tm_port_header_type_out_37.BCM8887X=ETH + +# core 7 lane56 +lane_to_serdes_map_nif_lane56.BCM8887X=rx58:tx59 +phy_rx_polarity_flip_phy56.BCM8887X=1 +phy_tx_polarity_flip_phy56.BCM8887X=1 +serdes_tx_taps_56.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 7 lane57 +lane_to_serdes_map_nif_lane57.BCM8887X=rx59:tx61 +phy_rx_polarity_flip_phy57.BCM8887X=0 +phy_tx_polarity_flip_phy57.BCM8887X=1 +serdes_tx_taps_57.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 7 lane58 +lane_to_serdes_map_nif_lane58.BCM8887X=rx60:tx60 +phy_rx_polarity_flip_phy58.BCM8887X=0 +phy_tx_polarity_flip_phy58.BCM8887X=1 +serdes_tx_taps_58.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 7 lane59 +lane_to_serdes_map_nif_lane59.BCM8887X=rx62:tx56 +phy_rx_polarity_flip_phy59.BCM8887X=1 +phy_tx_polarity_flip_phy59.BCM8887X=1 +serdes_tx_taps_59.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 7 lane60 +lane_to_serdes_map_nif_lane60.BCM8887X=rx56:tx62 +phy_rx_polarity_flip_phy60.BCM8887X=0 +phy_tx_polarity_flip_phy60.BCM8887X=0 +serdes_tx_taps_60.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 7 lane61 +lane_to_serdes_map_nif_lane61.BCM8887X=rx57:tx58 +phy_rx_polarity_flip_phy61.BCM8887X=0 +phy_tx_polarity_flip_phy61.BCM8887X=0 +serdes_tx_taps_61.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 7 lane62 +lane_to_serdes_map_nif_lane62.BCM8887X=rx63:tx63 +phy_rx_polarity_flip_phy62.BCM8887X=0 +phy_tx_polarity_flip_phy62.BCM8887X=1 +serdes_tx_taps_62.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 7 lane63 +lane_to_serdes_map_nif_lane63.BCM8887X=rx61:tx57 +phy_rx_polarity_flip_phy63.BCM8887X=0 +phy_tx_polarity_flip_phy63.BCM8887X=1 +serdes_tx_taps_63.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + + +# ---------------------------------------------------------------------------------------------------- +# core_8 +# ---------------------------------------------------------------------------------------------------- +ucode_port_129.BCM8887X=CDGE4_16:core_2.1 +tm_port_header_type_out_129.BCM8887X=ETH +ucode_port_133.BCM8887X=CDGE4_17:core_2.5 +tm_port_header_type_out_133.BCM8887X=ETH + +# core 8 lane64 +lane_to_serdes_map_nif_lane64.BCM8887X=rx67:tx71 +phy_rx_polarity_flip_phy64.BCM8887X=0 +phy_tx_polarity_flip_phy64.BCM8887X=0 +serdes_tx_taps_64.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 8 lane65 +lane_to_serdes_map_nif_lane65.BCM8887X=rx66:tx65 +phy_rx_polarity_flip_phy65.BCM8887X=0 +phy_tx_polarity_flip_phy65.BCM8887X=1 +serdes_tx_taps_65.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 8 lane66 +lane_to_serdes_map_nif_lane66.BCM8887X=rx70:tx70 +phy_rx_polarity_flip_phy66.BCM8887X=1 +phy_tx_polarity_flip_phy66.BCM8887X=1 +serdes_tx_taps_66.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 8 lane67 +lane_to_serdes_map_nif_lane67.BCM8887X=rx68:tx66 +phy_rx_polarity_flip_phy67.BCM8887X=1 +phy_tx_polarity_flip_phy67.BCM8887X=0 +serdes_tx_taps_67.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 8 lane68 +lane_to_serdes_map_nif_lane68.BCM8887X=rx69:tx67 +phy_rx_polarity_flip_phy68.BCM8887X=0 +phy_tx_polarity_flip_phy68.BCM8887X=0 +serdes_tx_taps_68.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 8 lane69 +lane_to_serdes_map_nif_lane69.BCM8887X=rx71:tx69 +phy_rx_polarity_flip_phy69.BCM8887X=1 +phy_tx_polarity_flip_phy69.BCM8887X=1 +serdes_tx_taps_69.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 8 lane70 +lane_to_serdes_map_nif_lane70.BCM8887X=rx65:tx68 +phy_rx_polarity_flip_phy70.BCM8887X=0 +phy_tx_polarity_flip_phy70.BCM8887X=0 +serdes_tx_taps_70.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 8 lane71 +lane_to_serdes_map_nif_lane71.BCM8887X=rx64:tx64 +phy_rx_polarity_flip_phy71.BCM8887X=1 +phy_tx_polarity_flip_phy71.BCM8887X=1 +serdes_tx_taps_71.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + + +# ---------------------------------------------------------------------------------------------------- +# core_9 +# ---------------------------------------------------------------------------------------------------- +ucode_port_137.BCM8887X=CDGE4_18:core_2.9 +tm_port_header_type_out_137.BCM8887X=ETH +ucode_port_141.BCM8887X=CDGE4_19:core_2.13 +tm_port_header_type_out_141.BCM8887X=ETH + +# core 9 lane72 +lane_to_serdes_map_nif_lane72.BCM8887X=rx75:tx79 +phy_rx_polarity_flip_phy72.BCM8887X=0 +phy_tx_polarity_flip_phy72.BCM8887X=0 +serdes_tx_taps_72.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 9 lane73 +lane_to_serdes_map_nif_lane73.BCM8887X=rx74:tx73 +phy_rx_polarity_flip_phy73.BCM8887X=0 +phy_tx_polarity_flip_phy73.BCM8887X=1 +serdes_tx_taps_73.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 9 lane74 +lane_to_serdes_map_nif_lane74.BCM8887X=rx78:tx78 +phy_rx_polarity_flip_phy74.BCM8887X=1 +phy_tx_polarity_flip_phy74.BCM8887X=1 +serdes_tx_taps_74.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 9 lane75 +lane_to_serdes_map_nif_lane75.BCM8887X=rx76:tx74 +phy_rx_polarity_flip_phy75.BCM8887X=1 +phy_tx_polarity_flip_phy75.BCM8887X=0 +serdes_tx_taps_75.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 9 lane76 +lane_to_serdes_map_nif_lane76.BCM8887X=rx77:tx75 +phy_rx_polarity_flip_phy76.BCM8887X=0 +phy_tx_polarity_flip_phy76.BCM8887X=0 +serdes_tx_taps_76.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 9 lane77 +lane_to_serdes_map_nif_lane77.BCM8887X=rx79:tx77 +phy_rx_polarity_flip_phy77.BCM8887X=1 +phy_tx_polarity_flip_phy77.BCM8887X=1 +serdes_tx_taps_77.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 9 lane78 +lane_to_serdes_map_nif_lane78.BCM8887X=rx73:tx76 +phy_rx_polarity_flip_phy78.BCM8887X=0 +phy_tx_polarity_flip_phy78.BCM8887X=0 +serdes_tx_taps_78.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 9 lane79 +lane_to_serdes_map_nif_lane79.BCM8887X=rx72:tx72 +phy_rx_polarity_flip_phy79.BCM8887X=1 +phy_tx_polarity_flip_phy79.BCM8887X=1 +serdes_tx_taps_79.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + + +# ---------------------------------------------------------------------------------------------------- +# core_10 +# ---------------------------------------------------------------------------------------------------- +ucode_port_145.BCM8887X=CDGE4_20:core_2.17 +tm_port_header_type_out_145.BCM8887X=ETH +ucode_port_149.BCM8887X=CDGE4_21:core_2.21 +tm_port_header_type_out_149.BCM8887X=ETH + +# core 10 lane80 +lane_to_serdes_map_nif_lane80.BCM8887X=rx83:tx87 +phy_rx_polarity_flip_phy80.BCM8887X=0 +phy_tx_polarity_flip_phy80.BCM8887X=0 +serdes_tx_taps_80.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 10 lane81 +lane_to_serdes_map_nif_lane81.BCM8887X=rx82:tx81 +phy_rx_polarity_flip_phy81.BCM8887X=0 +phy_tx_polarity_flip_phy81.BCM8887X=1 +serdes_tx_taps_81.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 10 lane82 +lane_to_serdes_map_nif_lane82.BCM8887X=rx86:tx86 +phy_rx_polarity_flip_phy82.BCM8887X=1 +phy_tx_polarity_flip_phy82.BCM8887X=1 +serdes_tx_taps_82.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 10 lane83 +lane_to_serdes_map_nif_lane83.BCM8887X=rx84:tx82 +phy_rx_polarity_flip_phy83.BCM8887X=1 +phy_tx_polarity_flip_phy83.BCM8887X=0 +serdes_tx_taps_83.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 10 lane84 +lane_to_serdes_map_nif_lane84.BCM8887X=rx85:tx83 +phy_rx_polarity_flip_phy84.BCM8887X=0 +phy_tx_polarity_flip_phy84.BCM8887X=0 +serdes_tx_taps_84.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 10 lane85 +lane_to_serdes_map_nif_lane85.BCM8887X=rx87:tx85 +phy_rx_polarity_flip_phy85.BCM8887X=1 +phy_tx_polarity_flip_phy85.BCM8887X=1 +serdes_tx_taps_85.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 10 lane86 +lane_to_serdes_map_nif_lane86.BCM8887X=rx81:tx84 +phy_rx_polarity_flip_phy86.BCM8887X=0 +phy_tx_polarity_flip_phy86.BCM8887X=0 +serdes_tx_taps_86.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 10 lane87 +lane_to_serdes_map_nif_lane87.BCM8887X=rx80:tx80 +phy_rx_polarity_flip_phy87.BCM8887X=1 +phy_tx_polarity_flip_phy87.BCM8887X=1 +serdes_tx_taps_87.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + + +# ---------------------------------------------------------------------------------------------------- +# core_11 +# ---------------------------------------------------------------------------------------------------- +ucode_port_153.BCM8887X=CDGE4_22:core_2.25 +tm_port_header_type_out_153.BCM8887X=ETH +ucode_port_157.BCM8887X=CDGE4_23:core_2.29 +tm_port_header_type_out_157.BCM8887X=ETH + +# core 11 lane88 +lane_to_serdes_map_nif_lane88.BCM8887X=rx91:tx95 +phy_rx_polarity_flip_phy88.BCM8887X=0 +phy_tx_polarity_flip_phy88.BCM8887X=0 +serdes_tx_taps_88.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 11 lane89 +lane_to_serdes_map_nif_lane89.BCM8887X=rx90:tx89 +phy_rx_polarity_flip_phy89.BCM8887X=0 +phy_tx_polarity_flip_phy89.BCM8887X=1 +serdes_tx_taps_89.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 11 lane90 +lane_to_serdes_map_nif_lane90.BCM8887X=rx94:tx94 +phy_rx_polarity_flip_phy90.BCM8887X=1 +phy_tx_polarity_flip_phy90.BCM8887X=1 +serdes_tx_taps_90.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 11 lane91 +lane_to_serdes_map_nif_lane91.BCM8887X=rx92:tx90 +phy_rx_polarity_flip_phy91.BCM8887X=1 +phy_tx_polarity_flip_phy91.BCM8887X=0 +serdes_tx_taps_91.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 11 lane92 +lane_to_serdes_map_nif_lane92.BCM8887X=rx93:tx91 +phy_rx_polarity_flip_phy92.BCM8887X=0 +phy_tx_polarity_flip_phy92.BCM8887X=0 +serdes_tx_taps_92.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 11 lane93 +lane_to_serdes_map_nif_lane93.BCM8887X=rx95:tx93 +phy_rx_polarity_flip_phy93.BCM8887X=1 +phy_tx_polarity_flip_phy93.BCM8887X=1 +serdes_tx_taps_93.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 11 lane94 +lane_to_serdes_map_nif_lane94.BCM8887X=rx89:tx92 +phy_rx_polarity_flip_phy94.BCM8887X=0 +phy_tx_polarity_flip_phy94.BCM8887X=0 +serdes_tx_taps_94.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 11 lane95 +lane_to_serdes_map_nif_lane95.BCM8887X=rx88:tx88 +phy_rx_polarity_flip_phy95.BCM8887X=1 +phy_tx_polarity_flip_phy95.BCM8887X=1 +serdes_tx_taps_95.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + + +# ---------------------------------------------------------------------------------------------------- +# core_12 +# ---------------------------------------------------------------------------------------------------- +ucode_port_1.BCM8887X=CGE24:core_3.1 +tm_port_header_type_out_1.BCM8887X=ETH +ucode_port_5.BCM8887X=CGE25:core_3.5 +tm_port_header_type_out_5.BCM8887X=ETH + +# core 12 lane96 +lane_to_serdes_map_nif_lane96.BCM8887X=rx100:tx103 +phy_rx_polarity_flip_phy96.BCM8887X=1 +phy_tx_polarity_flip_phy96.BCM8887X=0 +serdes_tx_taps_96.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 12 lane97 +lane_to_serdes_map_nif_lane97.BCM8887X=rx96:tx98 +phy_rx_polarity_flip_phy97.BCM8887X=1 +phy_tx_polarity_flip_phy97.BCM8887X=1 +serdes_tx_taps_97.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 12 lane98 +lane_to_serdes_map_nif_lane98.BCM8887X=rx99:tx99 +phy_rx_polarity_flip_phy98.BCM8887X=0 +phy_tx_polarity_flip_phy98.BCM8887X=0 +serdes_tx_taps_98.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 12 lane99 +lane_to_serdes_map_nif_lane99.BCM8887X=rx101:tx97 +phy_rx_polarity_flip_phy99.BCM8887X=0 +phy_tx_polarity_flip_phy99.BCM8887X=0 +serdes_tx_taps_99.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 12 lane100 +lane_to_serdes_map_nif_lane100.BCM8887X=rx98:tx100 +phy_rx_polarity_flip_phy100.BCM8887X=1 +phy_tx_polarity_flip_phy100.BCM8887X=0 +serdes_tx_taps_100.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 12 lane101 +lane_to_serdes_map_nif_lane101.BCM8887X=rx103:tx96 +phy_rx_polarity_flip_phy101.BCM8887X=1 +phy_tx_polarity_flip_phy101.BCM8887X=0 +serdes_tx_taps_101.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 12 lane102 +lane_to_serdes_map_nif_lane102.BCM8887X=rx102:tx101 +phy_rx_polarity_flip_phy102.BCM8887X=0 +phy_tx_polarity_flip_phy102.BCM8887X=1 +serdes_tx_taps_102.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 12 lane103 +lane_to_serdes_map_nif_lane103.BCM8887X=rx97:tx102 +phy_rx_polarity_flip_phy103.BCM8887X=1 +phy_tx_polarity_flip_phy103.BCM8887X=1 +serdes_tx_taps_103.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + + +# ---------------------------------------------------------------------------------------------------- +# core_13 +# ---------------------------------------------------------------------------------------------------- +ucode_port_9.BCM8887X=CGE26:core_3.9 +tm_port_header_type_out_9.BCM8887X=ETH +ucode_port_13.BCM8887X=CGE27:core_3.13 +tm_port_header_type_out_13.BCM8887X=ETH + +# core 13 lane104 +lane_to_serdes_map_nif_lane104.BCM8887X=rx107:tx108 +phy_rx_polarity_flip_phy104.BCM8887X=1 +phy_tx_polarity_flip_phy104.BCM8887X=0 +serdes_tx_taps_104.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 13 lane105 +lane_to_serdes_map_nif_lane105.BCM8887X=rx106:tx107 +phy_rx_polarity_flip_phy105.BCM8887X=0 +phy_tx_polarity_flip_phy105.BCM8887X=1 +serdes_tx_taps_105.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 13 lane106 +lane_to_serdes_map_nif_lane106.BCM8887X=rx110:tx110 +phy_rx_polarity_flip_phy106.BCM8887X=0 +phy_tx_polarity_flip_phy106.BCM8887X=0 +serdes_tx_taps_106.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 13 lane107 +lane_to_serdes_map_nif_lane107.BCM8887X=rx108:tx109 +phy_rx_polarity_flip_phy107.BCM8887X=0 +phy_tx_polarity_flip_phy107.BCM8887X=1 +serdes_tx_taps_107.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 13 lane108 +lane_to_serdes_map_nif_lane108.BCM8887X=rx105:tx111 +phy_rx_polarity_flip_phy108.BCM8887X=1 +phy_tx_polarity_flip_phy108.BCM8887X=1 +serdes_tx_taps_108.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 13 lane109 +lane_to_serdes_map_nif_lane109.BCM8887X=rx104:tx104 +phy_rx_polarity_flip_phy109.BCM8887X=0 +phy_tx_polarity_flip_phy109.BCM8887X=0 +serdes_tx_taps_109.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 13 lane110 +lane_to_serdes_map_nif_lane110.BCM8887X=rx111:tx106 +phy_rx_polarity_flip_phy110.BCM8887X=1 +phy_tx_polarity_flip_phy110.BCM8887X=1 +serdes_tx_taps_110.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 13 lane111 +lane_to_serdes_map_nif_lane111.BCM8887X=rx109:tx105 +phy_rx_polarity_flip_phy111.BCM8887X=1 +phy_tx_polarity_flip_phy111.BCM8887X=1 +serdes_tx_taps_111.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + + +# ---------------------------------------------------------------------------------------------------- +# core_14 +# ---------------------------------------------------------------------------------------------------- +ucode_port_17.BCM8887X=CGE28:core_3.17 +tm_port_header_type_out_17.BCM8887X=ETH +ucode_port_21.BCM8887X=CGE29:core_3.21 +tm_port_header_type_out_21.BCM8887X=ETH + +# core 14 lane112 +lane_to_serdes_map_nif_lane112.BCM8887X=rx115:tx116 +phy_rx_polarity_flip_phy112.BCM8887X=1 +phy_tx_polarity_flip_phy112.BCM8887X=0 +serdes_tx_taps_112.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 14 lane113 +lane_to_serdes_map_nif_lane113.BCM8887X=rx114:tx115 +phy_rx_polarity_flip_phy113.BCM8887X=1 +phy_tx_polarity_flip_phy113.BCM8887X=1 +serdes_tx_taps_113.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 14 lane114 +lane_to_serdes_map_nif_lane114.BCM8887X=rx118:tx118 +phy_rx_polarity_flip_phy114.BCM8887X=0 +phy_tx_polarity_flip_phy114.BCM8887X=0 +serdes_tx_taps_114.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 14 lane115 +lane_to_serdes_map_nif_lane115.BCM8887X=rx116:tx117 +phy_rx_polarity_flip_phy115.BCM8887X=0 +phy_tx_polarity_flip_phy115.BCM8887X=1 +serdes_tx_taps_115.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 14 lane116 +lane_to_serdes_map_nif_lane116.BCM8887X=rx113:tx119 +phy_rx_polarity_flip_phy116.BCM8887X=1 +phy_tx_polarity_flip_phy116.BCM8887X=1 +serdes_tx_taps_116.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 14 lane117 +lane_to_serdes_map_nif_lane117.BCM8887X=rx112:tx112 +phy_rx_polarity_flip_phy117.BCM8887X=0 +phy_tx_polarity_flip_phy117.BCM8887X=0 +serdes_tx_taps_117.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 14 lane118 +lane_to_serdes_map_nif_lane118.BCM8887X=rx119:tx114 +phy_rx_polarity_flip_phy118.BCM8887X=1 +phy_tx_polarity_flip_phy118.BCM8887X=1 +serdes_tx_taps_118.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 14 lane119 +lane_to_serdes_map_nif_lane119.BCM8887X=rx117:tx113 +phy_rx_polarity_flip_phy119.BCM8887X=1 +phy_tx_polarity_flip_phy119.BCM8887X=1 +serdes_tx_taps_119.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + + +# ---------------------------------------------------------------------------------------------------- +# core_15 +# ---------------------------------------------------------------------------------------------------- +ucode_port_25.BCM8887X=CGE30:core_3.25 +tm_port_header_type_out_25.BCM8887X=ETH +ucode_port_29.BCM8887X=CGE31:core_3.29 +tm_port_header_type_out_29.BCM8887X=ETH + +# core 15 lane120 +lane_to_serdes_map_nif_lane120.BCM8887X=rx123:tx124 +phy_rx_polarity_flip_phy120.BCM8887X=1 +phy_tx_polarity_flip_phy120.BCM8887X=0 +serdes_tx_taps_120.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 15 lane121 +lane_to_serdes_map_nif_lane121.BCM8887X=rx122:tx123 +phy_rx_polarity_flip_phy121.BCM8887X=1 +phy_tx_polarity_flip_phy121.BCM8887X=1 +serdes_tx_taps_121.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 15 lane122 +lane_to_serdes_map_nif_lane122.BCM8887X=rx126:tx126 +phy_rx_polarity_flip_phy122.BCM8887X=0 +phy_tx_polarity_flip_phy122.BCM8887X=0 +serdes_tx_taps_122.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 15 lane123 +lane_to_serdes_map_nif_lane123.BCM8887X=rx124:tx125 +phy_rx_polarity_flip_phy123.BCM8887X=0 +phy_tx_polarity_flip_phy123.BCM8887X=1 +serdes_tx_taps_123.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 15 lane124 +lane_to_serdes_map_nif_lane124.BCM8887X=rx121:tx127 +phy_rx_polarity_flip_phy124.BCM8887X=1 +phy_tx_polarity_flip_phy124.BCM8887X=1 +serdes_tx_taps_124.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 15 lane125 +lane_to_serdes_map_nif_lane125.BCM8887X=rx120:tx120 +phy_rx_polarity_flip_phy125.BCM8887X=0 +phy_tx_polarity_flip_phy125.BCM8887X=0 +serdes_tx_taps_125.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 15 lane126 +lane_to_serdes_map_nif_lane126.BCM8887X=rx127:tx122 +phy_rx_polarity_flip_phy126.BCM8887X=1 +phy_tx_polarity_flip_phy126.BCM8887X=1 +serdes_tx_taps_126.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 15 lane127 +lane_to_serdes_map_nif_lane127.BCM8887X=rx125:tx121 +phy_rx_polarity_flip_phy127.BCM8887X=1 +phy_tx_polarity_flip_phy127.BCM8887X=1 +serdes_tx_taps_127.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + + +# ---------------------------------------------------------------------------------------------------- +# core_16 +# ---------------------------------------------------------------------------------------------------- +ucode_port_65.BCM8887X=CGE32:core_4.1 +tm_port_header_type_out_65.BCM8887X=ETH +ucode_port_69.BCM8887X=CGE33:core_4.5 +tm_port_header_type_out_69.BCM8887X=ETH + +# core 16 lane128 +lane_to_serdes_map_nif_lane128.BCM8887X=rx131:tx135 +phy_rx_polarity_flip_phy128.BCM8887X=0 +phy_tx_polarity_flip_phy128.BCM8887X=0 +serdes_tx_taps_128.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 16 lane129 +lane_to_serdes_map_nif_lane129.BCM8887X=rx130:tx131 +phy_rx_polarity_flip_phy129.BCM8887X=0 +phy_tx_polarity_flip_phy129.BCM8887X=1 +serdes_tx_taps_129.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 16 lane130 +lane_to_serdes_map_nif_lane130.BCM8887X=rx129:tx129 +phy_rx_polarity_flip_phy130.BCM8887X=1 +phy_tx_polarity_flip_phy130.BCM8887X=1 +serdes_tx_taps_130.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 16 lane131 +lane_to_serdes_map_nif_lane131.BCM8887X=rx128:tx130 +phy_rx_polarity_flip_phy131.BCM8887X=0 +phy_tx_polarity_flip_phy131.BCM8887X=1 +serdes_tx_taps_131.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 16 lane132 +lane_to_serdes_map_nif_lane132.BCM8887X=rx133:tx132 +phy_rx_polarity_flip_phy132.BCM8887X=1 +phy_tx_polarity_flip_phy132.BCM8887X=1 +serdes_tx_taps_132.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 16 lane133 +lane_to_serdes_map_nif_lane133.BCM8887X=rx135:tx133 +phy_rx_polarity_flip_phy133.BCM8887X=0 +phy_tx_polarity_flip_phy133.BCM8887X=0 +serdes_tx_taps_133.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 16 lane134 +lane_to_serdes_map_nif_lane134.BCM8887X=rx132:tx128 +phy_rx_polarity_flip_phy134.BCM8887X=1 +phy_tx_polarity_flip_phy134.BCM8887X=1 +serdes_tx_taps_134.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 16 lane135 +lane_to_serdes_map_nif_lane135.BCM8887X=rx134:tx134 +phy_rx_polarity_flip_phy135.BCM8887X=0 +phy_tx_polarity_flip_phy135.BCM8887X=1 +serdes_tx_taps_135.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + + +# ---------------------------------------------------------------------------------------------------- +# core_17 +# ---------------------------------------------------------------------------------------------------- +ucode_port_73.BCM8887X=CGE34:core_4.9 +tm_port_header_type_out_73.BCM8887X=ETH +ucode_port_77.BCM8887X=CGE35:core_4.13 +tm_port_header_type_out_77.BCM8887X=ETH + +# core 17 lane136 +lane_to_serdes_map_nif_lane136.BCM8887X=rx139:tx143 +phy_rx_polarity_flip_phy136.BCM8887X=0 +phy_tx_polarity_flip_phy136.BCM8887X=0 +serdes_tx_taps_136.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 17 lane137 +lane_to_serdes_map_nif_lane137.BCM8887X=rx138:tx139 +phy_rx_polarity_flip_phy137.BCM8887X=0 +phy_tx_polarity_flip_phy137.BCM8887X=1 +serdes_tx_taps_137.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 17 lane138 +lane_to_serdes_map_nif_lane138.BCM8887X=rx137:tx137 +phy_rx_polarity_flip_phy138.BCM8887X=1 +phy_tx_polarity_flip_phy138.BCM8887X=1 +serdes_tx_taps_138.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 17 lane139 +lane_to_serdes_map_nif_lane139.BCM8887X=rx136:tx138 +phy_rx_polarity_flip_phy139.BCM8887X=1 +phy_tx_polarity_flip_phy139.BCM8887X=1 +serdes_tx_taps_139.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 17 lane140 +lane_to_serdes_map_nif_lane140.BCM8887X=rx141:tx140 +phy_rx_polarity_flip_phy140.BCM8887X=1 +phy_tx_polarity_flip_phy140.BCM8887X=1 +serdes_tx_taps_140.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 17 lane141 +lane_to_serdes_map_nif_lane141.BCM8887X=rx143:tx141 +phy_rx_polarity_flip_phy141.BCM8887X=0 +phy_tx_polarity_flip_phy141.BCM8887X=0 +serdes_tx_taps_141.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 17 lane142 +lane_to_serdes_map_nif_lane142.BCM8887X=rx140:tx136 +phy_rx_polarity_flip_phy142.BCM8887X=1 +phy_tx_polarity_flip_phy142.BCM8887X=1 +serdes_tx_taps_142.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 17 lane143 +lane_to_serdes_map_nif_lane143.BCM8887X=rx142:tx142 +phy_rx_polarity_flip_phy143.BCM8887X=0 +phy_tx_polarity_flip_phy143.BCM8887X=1 +serdes_tx_taps_143.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + + +# ---------------------------------------------------------------------------------------------------- +# core_18 +# ---------------------------------------------------------------------------------------------------- +ucode_port_81.BCM8887X=CGE36:core_4.17 +tm_port_header_type_out_81.BCM8887X=ETH +ucode_port_85.BCM8887X=CGE37:core_4.21 +tm_port_header_type_out_85.BCM8887X=ETH + +# core 18 lane144 +lane_to_serdes_map_nif_lane144.BCM8887X=rx147:tx151 +phy_rx_polarity_flip_phy144.BCM8887X=0 +phy_tx_polarity_flip_phy144.BCM8887X=0 +serdes_tx_taps_144.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 18 lane145 +lane_to_serdes_map_nif_lane145.BCM8887X=rx146:tx147 +phy_rx_polarity_flip_phy145.BCM8887X=0 +phy_tx_polarity_flip_phy145.BCM8887X=1 +serdes_tx_taps_145.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 18 lane146 +lane_to_serdes_map_nif_lane146.BCM8887X=rx145:tx145 +phy_rx_polarity_flip_phy146.BCM8887X=1 +phy_tx_polarity_flip_phy146.BCM8887X=1 +serdes_tx_taps_146.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 18 lane147 +lane_to_serdes_map_nif_lane147.BCM8887X=rx144:tx146 +phy_rx_polarity_flip_phy147.BCM8887X=0 +phy_tx_polarity_flip_phy147.BCM8887X=1 +serdes_tx_taps_147.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 18 lane148 +lane_to_serdes_map_nif_lane148.BCM8887X=rx149:tx148 +phy_rx_polarity_flip_phy148.BCM8887X=1 +phy_tx_polarity_flip_phy148.BCM8887X=1 +serdes_tx_taps_148.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 18 lane149 +lane_to_serdes_map_nif_lane149.BCM8887X=rx151:tx149 +phy_rx_polarity_flip_phy149.BCM8887X=0 +phy_tx_polarity_flip_phy149.BCM8887X=0 +serdes_tx_taps_149.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 18 lane150 +lane_to_serdes_map_nif_lane150.BCM8887X=rx148:tx144 +phy_rx_polarity_flip_phy150.BCM8887X=1 +phy_tx_polarity_flip_phy150.BCM8887X=1 +serdes_tx_taps_150.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 18 lane151 +lane_to_serdes_map_nif_lane151.BCM8887X=rx150:tx150 +phy_rx_polarity_flip_phy151.BCM8887X=0 +phy_tx_polarity_flip_phy151.BCM8887X=1 +serdes_tx_taps_151.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + + +# ---------------------------------------------------------------------------------------------------- +# core_19 +# ---------------------------------------------------------------------------------------------------- +ucode_port_89.BCM8887X=CGE38:core_4.25 +tm_port_header_type_out_89.BCM8887X=ETH +ucode_port_93.BCM8887X=CGE39:core_4.29 +tm_port_header_type_out_93.BCM8887X=ETH + +# core 19 lane152 +lane_to_serdes_map_nif_lane152.BCM8887X=rx155:tx156 +phy_rx_polarity_flip_phy152.BCM8887X=0 +phy_tx_polarity_flip_phy152.BCM8887X=1 +serdes_tx_taps_152.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 19 lane153 +lane_to_serdes_map_nif_lane153.BCM8887X=rx154:tx155 +phy_rx_polarity_flip_phy153.BCM8887X=0 +phy_tx_polarity_flip_phy153.BCM8887X=0 +serdes_tx_taps_153.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 19 lane154 +lane_to_serdes_map_nif_lane154.BCM8887X=rx158:tx158 +phy_rx_polarity_flip_phy154.BCM8887X=1 +phy_tx_polarity_flip_phy154.BCM8887X=1 +serdes_tx_taps_154.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 19 lane155 +lane_to_serdes_map_nif_lane155.BCM8887X=rx156:tx157 +phy_rx_polarity_flip_phy155.BCM8887X=1 +phy_tx_polarity_flip_phy155.BCM8887X=0 +serdes_tx_taps_155.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 19 lane156 +lane_to_serdes_map_nif_lane156.BCM8887X=rx153:tx159 +phy_rx_polarity_flip_phy156.BCM8887X=0 +phy_tx_polarity_flip_phy156.BCM8887X=0 +serdes_tx_taps_156.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 19 lane157 +lane_to_serdes_map_nif_lane157.BCM8887X=rx152:tx152 +phy_rx_polarity_flip_phy157.BCM8887X=1 +phy_tx_polarity_flip_phy157.BCM8887X=1 +serdes_tx_taps_157.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 19 lane158 +lane_to_serdes_map_nif_lane158.BCM8887X=rx159:tx154 +phy_rx_polarity_flip_phy158.BCM8887X=0 +phy_tx_polarity_flip_phy158.BCM8887X=0 +serdes_tx_taps_158.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 19 lane159 +lane_to_serdes_map_nif_lane159.BCM8887X=rx157:tx153 +phy_rx_polarity_flip_phy159.BCM8887X=0 +phy_tx_polarity_flip_phy159.BCM8887X=0 +serdes_tx_taps_159.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + + +# ---------------------------------------------------------------------------------------------------- +# core_20 +# ---------------------------------------------------------------------------------------------------- +ucode_port_193.BCM8887X=CDGE4_40:core_5.1 +tm_port_header_type_out_193.BCM8887X=ETH +ucode_port_197.BCM8887X=CDGE4_41:core_5.5 +tm_port_header_type_out_197.BCM8887X=ETH + +# core 20 lane160 +lane_to_serdes_map_nif_lane160.BCM8887X=rx166:tx167 +phy_rx_polarity_flip_phy160.BCM8887X=0 +phy_tx_polarity_flip_phy160.BCM8887X=1 +serdes_tx_taps_160.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 20 lane161 +lane_to_serdes_map_nif_lane161.BCM8887X=rx164:tx163 +phy_rx_polarity_flip_phy161.BCM8887X=1 +phy_tx_polarity_flip_phy161.BCM8887X=0 +serdes_tx_taps_161.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 20 lane162 +lane_to_serdes_map_nif_lane162.BCM8887X=rx160:tx162 +phy_rx_polarity_flip_phy162.BCM8887X=0 +phy_tx_polarity_flip_phy162.BCM8887X=1 +serdes_tx_taps_162.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 20 lane163 +lane_to_serdes_map_nif_lane163.BCM8887X=rx161:tx161 +phy_rx_polarity_flip_phy163.BCM8887X=0 +phy_tx_polarity_flip_phy163.BCM8887X=1 +serdes_tx_taps_163.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 20 lane164 +lane_to_serdes_map_nif_lane164.BCM8887X=rx162:tx166 +phy_rx_polarity_flip_phy164.BCM8887X=0 +phy_tx_polarity_flip_phy164.BCM8887X=1 +serdes_tx_taps_164.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 20 lane165 +lane_to_serdes_map_nif_lane165.BCM8887X=rx163:tx160 +phy_rx_polarity_flip_phy165.BCM8887X=0 +phy_tx_polarity_flip_phy165.BCM8887X=1 +serdes_tx_taps_165.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 20 lane166 +lane_to_serdes_map_nif_lane166.BCM8887X=rx167:tx164 +phy_rx_polarity_flip_phy166.BCM8887X=1 +phy_tx_polarity_flip_phy166.BCM8887X=1 +serdes_tx_taps_166.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 20 lane167 +lane_to_serdes_map_nif_lane167.BCM8887X=rx165:tx165 +phy_rx_polarity_flip_phy167.BCM8887X=0 +phy_tx_polarity_flip_phy167.BCM8887X=1 +serdes_tx_taps_167.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + + +# ---------------------------------------------------------------------------------------------------- +# core_21 +# ---------------------------------------------------------------------------------------------------- +ucode_port_201.BCM8887X=CDGE4_42:core_5.9 +tm_port_header_type_out_201.BCM8887X=ETH +ucode_port_205.BCM8887X=CDGE4_43:core_5.13 +tm_port_header_type_out_205.BCM8887X=ETH + +# core 21 lane168 +lane_to_serdes_map_nif_lane168.BCM8887X=rx170:tx174 +phy_rx_polarity_flip_phy168.BCM8887X=0 +phy_tx_polarity_flip_phy168.BCM8887X=1 +serdes_tx_taps_168.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 21 lane169 +lane_to_serdes_map_nif_lane169.BCM8887X=rx171:tx168 +phy_rx_polarity_flip_phy169.BCM8887X=0 +phy_tx_polarity_flip_phy169.BCM8887X=1 +serdes_tx_taps_169.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 21 lane170 +lane_to_serdes_map_nif_lane170.BCM8887X=rx175:tx172 +phy_rx_polarity_flip_phy170.BCM8887X=1 +phy_tx_polarity_flip_phy170.BCM8887X=1 +serdes_tx_taps_170.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 21 lane171 +lane_to_serdes_map_nif_lane171.BCM8887X=rx173:tx173 +phy_rx_polarity_flip_phy171.BCM8887X=0 +phy_tx_polarity_flip_phy171.BCM8887X=1 +serdes_tx_taps_171.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 21 lane172 +lane_to_serdes_map_nif_lane172.BCM8887X=rx174:tx175 +phy_rx_polarity_flip_phy172.BCM8887X=0 +phy_tx_polarity_flip_phy172.BCM8887X=1 +serdes_tx_taps_172.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 21 lane173 +lane_to_serdes_map_nif_lane173.BCM8887X=rx172:tx171 +phy_rx_polarity_flip_phy173.BCM8887X=1 +phy_tx_polarity_flip_phy173.BCM8887X=0 +serdes_tx_taps_173.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 21 lane174 +lane_to_serdes_map_nif_lane174.BCM8887X=rx168:tx170 +phy_rx_polarity_flip_phy174.BCM8887X=0 +phy_tx_polarity_flip_phy174.BCM8887X=1 +serdes_tx_taps_174.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 21 lane175 +lane_to_serdes_map_nif_lane175.BCM8887X=rx169:tx169 +phy_rx_polarity_flip_phy175.BCM8887X=0 +phy_tx_polarity_flip_phy175.BCM8887X=1 +serdes_tx_taps_175.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + + +# ---------------------------------------------------------------------------------------------------- +# core_22 +# ---------------------------------------------------------------------------------------------------- +ucode_port_209.BCM8887X=CDGE4_44:core_5.17 +tm_port_header_type_out_209.BCM8887X=ETH +ucode_port_213.BCM8887X=CDGE4_45:core_5.21 +tm_port_header_type_out_213.BCM8887X=ETH + +# core 22 lane176 +lane_to_serdes_map_nif_lane176.BCM8887X=rx178:tx182 +phy_rx_polarity_flip_phy176.BCM8887X=0 +phy_tx_polarity_flip_phy176.BCM8887X=1 +serdes_tx_taps_176.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 22 lane177 +lane_to_serdes_map_nif_lane177.BCM8887X=rx179:tx176 +phy_rx_polarity_flip_phy177.BCM8887X=0 +phy_tx_polarity_flip_phy177.BCM8887X=1 +serdes_tx_taps_177.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 22 lane178 +lane_to_serdes_map_nif_lane178.BCM8887X=rx183:tx180 +phy_rx_polarity_flip_phy178.BCM8887X=1 +phy_tx_polarity_flip_phy178.BCM8887X=1 +serdes_tx_taps_178.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 22 lane179 +lane_to_serdes_map_nif_lane179.BCM8887X=rx181:tx181 +phy_rx_polarity_flip_phy179.BCM8887X=0 +phy_tx_polarity_flip_phy179.BCM8887X=1 +serdes_tx_taps_179.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 22 lane180 +lane_to_serdes_map_nif_lane180.BCM8887X=rx182:tx183 +phy_rx_polarity_flip_phy180.BCM8887X=0 +phy_tx_polarity_flip_phy180.BCM8887X=1 +serdes_tx_taps_180.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 22 lane181 +lane_to_serdes_map_nif_lane181.BCM8887X=rx180:tx179 +phy_rx_polarity_flip_phy181.BCM8887X=1 +phy_tx_polarity_flip_phy181.BCM8887X=0 +serdes_tx_taps_181.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 22 lane182 +lane_to_serdes_map_nif_lane182.BCM8887X=rx176:tx178 +phy_rx_polarity_flip_phy182.BCM8887X=0 +phy_tx_polarity_flip_phy182.BCM8887X=1 +serdes_tx_taps_182.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 22 lane183 +lane_to_serdes_map_nif_lane183.BCM8887X=rx177:tx177 +phy_rx_polarity_flip_phy183.BCM8887X=0 +phy_tx_polarity_flip_phy183.BCM8887X=1 +serdes_tx_taps_183.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + + +# ---------------------------------------------------------------------------------------------------- +# core_23 +# ---------------------------------------------------------------------------------------------------- +ucode_port_217.BCM8887X=CDGE4_46:core_5.25 +tm_port_header_type_out_217.BCM8887X=ETH +ucode_port_221.BCM8887X=CDGE4_47:core_5.29 +tm_port_header_type_out_221.BCM8887X=ETH + +# core 23 lane184 +lane_to_serdes_map_nif_lane184.BCM8887X=rx187:tx191 +phy_rx_polarity_flip_phy184.BCM8887X=1 +phy_tx_polarity_flip_phy184.BCM8887X=1 +serdes_tx_taps_184.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 23 lane185 +lane_to_serdes_map_nif_lane185.BCM8887X=rx186:tx185 +phy_rx_polarity_flip_phy185.BCM8887X=1 +phy_tx_polarity_flip_phy185.BCM8887X=0 +serdes_tx_taps_185.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 23 lane186 +lane_to_serdes_map_nif_lane186.BCM8887X=rx190:tx190 +phy_rx_polarity_flip_phy186.BCM8887X=0 +phy_tx_polarity_flip_phy186.BCM8887X=0 +serdes_tx_taps_186.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 23 lane187 +lane_to_serdes_map_nif_lane187.BCM8887X=rx188:tx186 +phy_rx_polarity_flip_phy187.BCM8887X=0 +phy_tx_polarity_flip_phy187.BCM8887X=1 +serdes_tx_taps_187.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 23 lane188 +lane_to_serdes_map_nif_lane188.BCM8887X=rx189:tx187 +phy_rx_polarity_flip_phy188.BCM8887X=1 +phy_tx_polarity_flip_phy188.BCM8887X=1 +serdes_tx_taps_188.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 23 lane189 +lane_to_serdes_map_nif_lane189.BCM8887X=rx191:tx189 +phy_rx_polarity_flip_phy189.BCM8887X=0 +phy_tx_polarity_flip_phy189.BCM8887X=0 +serdes_tx_taps_189.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 23 lane190 +lane_to_serdes_map_nif_lane190.BCM8887X=rx185:tx188 +phy_rx_polarity_flip_phy190.BCM8887X=1 +phy_tx_polarity_flip_phy190.BCM8887X=1 +serdes_tx_taps_190.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 23 lane191 +lane_to_serdes_map_nif_lane191.BCM8887X=rx184:tx184 +phy_rx_polarity_flip_phy191.BCM8887X=0 +phy_tx_polarity_flip_phy191.BCM8887X=0 +serdes_tx_taps_191.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + + +# ---------------------------------------------------------------------------------------------------- +# core_24 +# ---------------------------------------------------------------------------------------------------- +ucode_port_121.BCM8887X=CGE48:core_6.1 +tm_port_header_type_out_121.BCM8887X=ETH +ucode_port_125.BCM8887X=CGE49:core_6.5 +tm_port_header_type_out_125.BCM8887X=ETH + +# core 24 lane192 +lane_to_serdes_map_nif_lane192.BCM8887X=rx194:tx195 +phy_rx_polarity_flip_phy192.BCM8887X=0 +phy_tx_polarity_flip_phy192.BCM8887X=0 +serdes_tx_taps_192.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 24 lane193 +lane_to_serdes_map_nif_lane193.BCM8887X=rx195:tx197 +phy_rx_polarity_flip_phy193.BCM8887X=1 +phy_tx_polarity_flip_phy193.BCM8887X=0 +serdes_tx_taps_193.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 24 lane194 +lane_to_serdes_map_nif_lane194.BCM8887X=rx196:tx196 +phy_rx_polarity_flip_phy194.BCM8887X=1 +phy_tx_polarity_flip_phy194.BCM8887X=0 +serdes_tx_taps_194.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 24 lane195 +lane_to_serdes_map_nif_lane195.BCM8887X=rx198:tx192 +phy_rx_polarity_flip_phy195.BCM8887X=0 +phy_tx_polarity_flip_phy195.BCM8887X=0 +serdes_tx_taps_195.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 24 lane196 +lane_to_serdes_map_nif_lane196.BCM8887X=rx192:tx198 +phy_rx_polarity_flip_phy196.BCM8887X=1 +phy_tx_polarity_flip_phy196.BCM8887X=1 +serdes_tx_taps_196.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 24 lane197 +lane_to_serdes_map_nif_lane197.BCM8887X=rx193:tx194 +phy_rx_polarity_flip_phy197.BCM8887X=0 +phy_tx_polarity_flip_phy197.BCM8887X=1 +serdes_tx_taps_197.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 24 lane198 +lane_to_serdes_map_nif_lane198.BCM8887X=rx199:tx199 +phy_rx_polarity_flip_phy198.BCM8887X=1 +phy_tx_polarity_flip_phy198.BCM8887X=0 +serdes_tx_taps_198.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 24 lane199 +lane_to_serdes_map_nif_lane199.BCM8887X=rx197:tx193 +phy_rx_polarity_flip_phy199.BCM8887X=1 +phy_tx_polarity_flip_phy199.BCM8887X=0 +serdes_tx_taps_199.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + + +# ---------------------------------------------------------------------------------------------------- +# core_25 +# ---------------------------------------------------------------------------------------------------- +ucode_port_113.BCM8887X=CGE50:core_6.9 +tm_port_header_type_out_113.BCM8887X=ETH +ucode_port_117.BCM8887X=CGE51:core_6.13 +tm_port_header_type_out_117.BCM8887X=ETH + +# core 25 lane200 +lane_to_serdes_map_nif_lane200.BCM8887X=rx202:tx203 +phy_rx_polarity_flip_phy200.BCM8887X=0 +phy_tx_polarity_flip_phy200.BCM8887X=0 +serdes_tx_taps_200.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 25 lane201 +lane_to_serdes_map_nif_lane201.BCM8887X=rx203:tx205 +phy_rx_polarity_flip_phy201.BCM8887X=1 +phy_tx_polarity_flip_phy201.BCM8887X=0 +serdes_tx_taps_201.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 25 lane202 +lane_to_serdes_map_nif_lane202.BCM8887X=rx204:tx204 +phy_rx_polarity_flip_phy202.BCM8887X=1 +phy_tx_polarity_flip_phy202.BCM8887X=0 +serdes_tx_taps_202.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 25 lane203 +lane_to_serdes_map_nif_lane203.BCM8887X=rx206:tx200 +phy_rx_polarity_flip_phy203.BCM8887X=0 +phy_tx_polarity_flip_phy203.BCM8887X=0 +serdes_tx_taps_203.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 25 lane204 +lane_to_serdes_map_nif_lane204.BCM8887X=rx200:tx206 +phy_rx_polarity_flip_phy204.BCM8887X=1 +phy_tx_polarity_flip_phy204.BCM8887X=1 +serdes_tx_taps_204.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 25 lane205 +lane_to_serdes_map_nif_lane205.BCM8887X=rx201:tx202 +phy_rx_polarity_flip_phy205.BCM8887X=1 +phy_tx_polarity_flip_phy205.BCM8887X=1 +serdes_tx_taps_205.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 25 lane206 +lane_to_serdes_map_nif_lane206.BCM8887X=rx207:tx207 +phy_rx_polarity_flip_phy206.BCM8887X=1 +phy_tx_polarity_flip_phy206.BCM8887X=0 +serdes_tx_taps_206.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 25 lane207 +lane_to_serdes_map_nif_lane207.BCM8887X=rx205:tx201 +phy_rx_polarity_flip_phy207.BCM8887X=1 +phy_tx_polarity_flip_phy207.BCM8887X=0 +serdes_tx_taps_207.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + + +# ---------------------------------------------------------------------------------------------------- +# core_26 +# ---------------------------------------------------------------------------------------------------- +ucode_port_105.BCM8887X=CGE52:core_6.17 +tm_port_header_type_out_105.BCM8887X=ETH +ucode_port_109.BCM8887X=CGE53:core_6.21 +tm_port_header_type_out_109.BCM8887X=ETH + +# core 26 lane208 +lane_to_serdes_map_nif_lane208.BCM8887X=rx210:tx211 +phy_rx_polarity_flip_phy208.BCM8887X=0 +phy_tx_polarity_flip_phy208.BCM8887X=0 +serdes_tx_taps_208.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 26 lane209 +lane_to_serdes_map_nif_lane209.BCM8887X=rx211:tx213 +phy_rx_polarity_flip_phy209.BCM8887X=1 +phy_tx_polarity_flip_phy209.BCM8887X=0 +serdes_tx_taps_209.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 26 lane210 +lane_to_serdes_map_nif_lane210.BCM8887X=rx212:tx212 +phy_rx_polarity_flip_phy210.BCM8887X=1 +phy_tx_polarity_flip_phy210.BCM8887X=0 +serdes_tx_taps_210.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 26 lane211 +lane_to_serdes_map_nif_lane211.BCM8887X=rx214:tx208 +phy_rx_polarity_flip_phy211.BCM8887X=0 +phy_tx_polarity_flip_phy211.BCM8887X=0 +serdes_tx_taps_211.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 26 lane212 +lane_to_serdes_map_nif_lane212.BCM8887X=rx208:tx214 +phy_rx_polarity_flip_phy212.BCM8887X=1 +phy_tx_polarity_flip_phy212.BCM8887X=1 +serdes_tx_taps_212.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 26 lane213 +lane_to_serdes_map_nif_lane213.BCM8887X=rx209:tx210 +phy_rx_polarity_flip_phy213.BCM8887X=1 +phy_tx_polarity_flip_phy213.BCM8887X=1 +serdes_tx_taps_213.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 26 lane214 +lane_to_serdes_map_nif_lane214.BCM8887X=rx215:tx215 +phy_rx_polarity_flip_phy214.BCM8887X=1 +phy_tx_polarity_flip_phy214.BCM8887X=0 +serdes_tx_taps_214.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 26 lane215 +lane_to_serdes_map_nif_lane215.BCM8887X=rx213:tx209 +phy_rx_polarity_flip_phy215.BCM8887X=1 +phy_tx_polarity_flip_phy215.BCM8887X=0 +serdes_tx_taps_215.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + + +# ---------------------------------------------------------------------------------------------------- +# core_27 +# ---------------------------------------------------------------------------------------------------- +ucode_port_97.BCM8887X=CGE54:core_6.25 +tm_port_header_type_out_97.BCM8887X=ETH +ucode_port_101.BCM8887X=CGE55:core_6.29 +tm_port_header_type_out_101.BCM8887X=ETH + +# core 27 lane216 +lane_to_serdes_map_nif_lane216.BCM8887X=rx218:tx219 +phy_rx_polarity_flip_phy216.BCM8887X=0 +phy_tx_polarity_flip_phy216.BCM8887X=0 +serdes_tx_taps_216.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 27 lane217 +lane_to_serdes_map_nif_lane217.BCM8887X=rx219:tx221 +phy_rx_polarity_flip_phy217.BCM8887X=1 +phy_tx_polarity_flip_phy217.BCM8887X=0 +serdes_tx_taps_217.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 27 lane218 +lane_to_serdes_map_nif_lane218.BCM8887X=rx220:tx220 +phy_rx_polarity_flip_phy218.BCM8887X=1 +phy_tx_polarity_flip_phy218.BCM8887X=0 +serdes_tx_taps_218.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 27 lane219 +lane_to_serdes_map_nif_lane219.BCM8887X=rx222:tx216 +phy_rx_polarity_flip_phy219.BCM8887X=0 +phy_tx_polarity_flip_phy219.BCM8887X=0 +serdes_tx_taps_219.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 27 lane220 +lane_to_serdes_map_nif_lane220.BCM8887X=rx216:tx222 +phy_rx_polarity_flip_phy220.BCM8887X=1 +phy_tx_polarity_flip_phy220.BCM8887X=1 +serdes_tx_taps_220.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 27 lane221 +lane_to_serdes_map_nif_lane221.BCM8887X=rx217:tx218 +phy_rx_polarity_flip_phy221.BCM8887X=1 +phy_tx_polarity_flip_phy221.BCM8887X=1 +serdes_tx_taps_221.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 27 lane222 +lane_to_serdes_map_nif_lane222.BCM8887X=rx223:tx223 +phy_rx_polarity_flip_phy222.BCM8887X=1 +phy_tx_polarity_flip_phy222.BCM8887X=0 +serdes_tx_taps_222.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + +# core 27 lane223 +lane_to_serdes_map_nif_lane223.BCM8887X=rx221:tx217 +phy_rx_polarity_flip_phy223.BCM8887X=1 +phy_tx_polarity_flip_phy223.BCM8887X=0 +serdes_tx_taps_223.BCM8887X=mode:NRZ,pre:0,main:127,post:0 + + +# ---------------------------------------------------------------------------------------------------- +# core_28 +# ---------------------------------------------------------------------------------------------------- +ucode_port_249.BCM8887X=CDGE4_56:core_7.1 +tm_port_header_type_out_249.BCM8887X=ETH +ucode_port_253.BCM8887X=CDGE4_57:core_7.5 +tm_port_header_type_out_253.BCM8887X=ETH + +# core 28 lane224 +lane_to_serdes_map_nif_lane224.BCM8887X=rx224:tx229 +phy_rx_polarity_flip_phy224.BCM8887X=0 +phy_tx_polarity_flip_phy224.BCM8887X=1 +serdes_tx_taps_224.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 28 lane225 +lane_to_serdes_map_nif_lane225.BCM8887X=rx228:tx230 +phy_rx_polarity_flip_phy225.BCM8887X=1 +phy_tx_polarity_flip_phy225.BCM8887X=0 +serdes_tx_taps_225.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 28 lane226 +lane_to_serdes_map_nif_lane226.BCM8887X=rx229:tx228 +phy_rx_polarity_flip_phy226.BCM8887X=1 +phy_tx_polarity_flip_phy226.BCM8887X=0 +serdes_tx_taps_226.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 28 lane227 +lane_to_serdes_map_nif_lane227.BCM8887X=rx227:tx224 +phy_rx_polarity_flip_phy227.BCM8887X=0 +phy_tx_polarity_flip_phy227.BCM8887X=1 +serdes_tx_taps_227.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 28 lane228 +lane_to_serdes_map_nif_lane228.BCM8887X=rx225:tx231 +phy_rx_polarity_flip_phy228.BCM8887X=0 +phy_tx_polarity_flip_phy228.BCM8887X=0 +serdes_tx_taps_228.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 28 lane229 +lane_to_serdes_map_nif_lane229.BCM8887X=rx230:tx226 +phy_rx_polarity_flip_phy229.BCM8887X=0 +phy_tx_polarity_flip_phy229.BCM8887X=0 +serdes_tx_taps_229.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 28 lane230 +lane_to_serdes_map_nif_lane230.BCM8887X=rx231:tx227 +phy_rx_polarity_flip_phy230.BCM8887X=0 +phy_tx_polarity_flip_phy230.BCM8887X=0 +serdes_tx_taps_230.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 28 lane231 +lane_to_serdes_map_nif_lane231.BCM8887X=rx226:tx225 +phy_rx_polarity_flip_phy231.BCM8887X=1 +phy_tx_polarity_flip_phy231.BCM8887X=1 +serdes_tx_taps_231.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + + +# ---------------------------------------------------------------------------------------------------- +# core_29 +# ---------------------------------------------------------------------------------------------------- +ucode_port_241.BCM8887X=CDGE4_58:core_7.9 +tm_port_header_type_out_241.BCM8887X=ETH +ucode_port_245.BCM8887X=CDGE4_59:core_7.13 +tm_port_header_type_out_245.BCM8887X=ETH + +# core 29 lane232 +lane_to_serdes_map_nif_lane232.BCM8887X=rx234:tx234 +phy_rx_polarity_flip_phy232.BCM8887X=1 +phy_tx_polarity_flip_phy232.BCM8887X=1 +serdes_tx_taps_232.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 29 lane233 +lane_to_serdes_map_nif_lane233.BCM8887X=rx235:tx233 +phy_rx_polarity_flip_phy233.BCM8887X=1 +phy_tx_polarity_flip_phy233.BCM8887X=0 +serdes_tx_taps_233.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 29 lane234 +lane_to_serdes_map_nif_lane234.BCM8887X=rx236:tx239 +phy_rx_polarity_flip_phy234.BCM8887X=1 +phy_tx_polarity_flip_phy234.BCM8887X=1 +serdes_tx_taps_234.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 29 lane235 +lane_to_serdes_map_nif_lane235.BCM8887X=rx238:tx232 +phy_rx_polarity_flip_phy235.BCM8887X=0 +phy_tx_polarity_flip_phy235.BCM8887X=1 +serdes_tx_taps_235.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 29 lane236 +lane_to_serdes_map_nif_lane236.BCM8887X=rx237:tx236 +phy_rx_polarity_flip_phy236.BCM8887X=0 +phy_tx_polarity_flip_phy236.BCM8887X=0 +serdes_tx_taps_236.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 29 lane237 +lane_to_serdes_map_nif_lane237.BCM8887X=rx239:tx235 +phy_rx_polarity_flip_phy237.BCM8887X=1 +phy_tx_polarity_flip_phy237.BCM8887X=0 +serdes_tx_taps_237.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 29 lane238 +lane_to_serdes_map_nif_lane238.BCM8887X=rx232:tx238 +phy_rx_polarity_flip_phy238.BCM8887X=1 +phy_tx_polarity_flip_phy238.BCM8887X=0 +serdes_tx_taps_238.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 29 lane239 +lane_to_serdes_map_nif_lane239.BCM8887X=rx233:tx237 +phy_rx_polarity_flip_phy239.BCM8887X=1 +phy_tx_polarity_flip_phy239.BCM8887X=0 +serdes_tx_taps_239.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + + +# ---------------------------------------------------------------------------------------------------- +# core_30 +# ---------------------------------------------------------------------------------------------------- +ucode_port_233.BCM8887X=CDGE4_60:core_7.17 +tm_port_header_type_out_233.BCM8887X=ETH +ucode_port_237.BCM8887X=CDGE4_61:core_7.21 +tm_port_header_type_out_237.BCM8887X=ETH + +# core 30 lane240 +lane_to_serdes_map_nif_lane240.BCM8887X=rx242:tx242 +phy_rx_polarity_flip_phy240.BCM8887X=0 +phy_tx_polarity_flip_phy240.BCM8887X=1 +serdes_tx_taps_240.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 30 lane241 +lane_to_serdes_map_nif_lane241.BCM8887X=rx243:tx241 +phy_rx_polarity_flip_phy241.BCM8887X=1 +phy_tx_polarity_flip_phy241.BCM8887X=0 +serdes_tx_taps_241.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 30 lane242 +lane_to_serdes_map_nif_lane242.BCM8887X=rx244:tx247 +phy_rx_polarity_flip_phy242.BCM8887X=1 +phy_tx_polarity_flip_phy242.BCM8887X=1 +serdes_tx_taps_242.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 30 lane243 +lane_to_serdes_map_nif_lane243.BCM8887X=rx246:tx240 +phy_rx_polarity_flip_phy243.BCM8887X=0 +phy_tx_polarity_flip_phy243.BCM8887X=1 +serdes_tx_taps_243.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 30 lane244 +lane_to_serdes_map_nif_lane244.BCM8887X=rx245:tx244 +phy_rx_polarity_flip_phy244.BCM8887X=0 +phy_tx_polarity_flip_phy244.BCM8887X=0 +serdes_tx_taps_244.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 30 lane245 +lane_to_serdes_map_nif_lane245.BCM8887X=rx247:tx243 +phy_rx_polarity_flip_phy245.BCM8887X=1 +phy_tx_polarity_flip_phy245.BCM8887X=0 +serdes_tx_taps_245.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 30 lane246 +lane_to_serdes_map_nif_lane246.BCM8887X=rx240:tx246 +phy_rx_polarity_flip_phy246.BCM8887X=1 +phy_tx_polarity_flip_phy246.BCM8887X=0 +serdes_tx_taps_246.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 30 lane247 +lane_to_serdes_map_nif_lane247.BCM8887X=rx241:tx245 +phy_rx_polarity_flip_phy247.BCM8887X=1 +phy_tx_polarity_flip_phy247.BCM8887X=0 +serdes_tx_taps_247.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + + +# ---------------------------------------------------------------------------------------------------- +# core_31 +# ---------------------------------------------------------------------------------------------------- +ucode_port_225.BCM8887X=CDGE4_62:core_7.25 +tm_port_header_type_out_225.BCM8887X=ETH +ucode_port_229.BCM8887X=CDGE4_63:core_7.29 +tm_port_header_type_out_229.BCM8887X=ETH + +# core 31 lane248 +lane_to_serdes_map_nif_lane248.BCM8887X=rx250:tx250 +phy_rx_polarity_flip_phy248.BCM8887X=0 +phy_tx_polarity_flip_phy248.BCM8887X=1 +serdes_tx_taps_248.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 31 lane249 +lane_to_serdes_map_nif_lane249.BCM8887X=rx251:tx249 +phy_rx_polarity_flip_phy249.BCM8887X=1 +phy_tx_polarity_flip_phy249.BCM8887X=0 +serdes_tx_taps_249.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 31 lane250 +lane_to_serdes_map_nif_lane250.BCM8887X=rx252:tx255 +phy_rx_polarity_flip_phy250.BCM8887X=1 +phy_tx_polarity_flip_phy250.BCM8887X=1 +serdes_tx_taps_250.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 31 lane251 +lane_to_serdes_map_nif_lane251.BCM8887X=rx254:tx248 +phy_rx_polarity_flip_phy251.BCM8887X=0 +phy_tx_polarity_flip_phy251.BCM8887X=1 +serdes_tx_taps_251.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 31 lane252 +lane_to_serdes_map_nif_lane252.BCM8887X=rx253:tx252 +phy_rx_polarity_flip_phy252.BCM8887X=0 +phy_tx_polarity_flip_phy252.BCM8887X=0 +serdes_tx_taps_252.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 31 lane253 +lane_to_serdes_map_nif_lane253.BCM8887X=rx255:tx251 +phy_rx_polarity_flip_phy253.BCM8887X=1 +phy_tx_polarity_flip_phy253.BCM8887X=0 +serdes_tx_taps_253.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 31 lane254 +lane_to_serdes_map_nif_lane254.BCM8887X=rx248:tx254 +phy_rx_polarity_flip_phy254.BCM8887X=1 +phy_tx_polarity_flip_phy254.BCM8887X=0 +serdes_tx_taps_254.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 31 lane255 +lane_to_serdes_map_nif_lane255.BCM8887X=rx249:tx253 +phy_rx_polarity_flip_phy255.BCM8887X=1 +phy_tx_polarity_flip_phy255.BCM8887X=0 +serdes_tx_taps_255.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# ---------------------------------------------------------------------------------------------------- +# core_32 +# ---------------------------------------------------------------------------------------------------- +ucode_port_257.BCM8887X=CGE64:core_2.33 +tm_port_header_type_out_257.BCM8887X=ETH + +# core 32 lane256 +lane_to_serdes_map_nif_lane256.BCM8887X=rx257:tx257 +phy_rx_polarity_flip_phy256.BCM8887X=0 +phy_tx_polarity_flip_phy256.BCM8887X=0 + +# core 32 lane257 +lane_to_serdes_map_nif_lane257.BCM8887X=rx256:tx256 +phy_rx_polarity_flip_phy257.BCM8887X=0 +phy_tx_polarity_flip_phy257.BCM8887X=1 + +# core 32 lane258 +lane_to_serdes_map_nif_lane258.BCM8887X=rx258:tx258 +phy_rx_polarity_flip_phy258.BCM8887X=1 +phy_tx_polarity_flip_phy258.BCM8887X=0 + +# core 32 lane259 +lane_to_serdes_map_nif_lane259.BCM8887X=rx259:tx259 +phy_rx_polarity_flip_phy259.BCM8887X=0 +phy_tx_polarity_flip_phy259.BCM8887X=0 + + +# ---------------------------------------------------------------------------------------------------- +# core_33 +# ---------------------------------------------------------------------------------------------------- +ucode_port_261.BCM8887X=CGE65:core_6.33 +tm_port_header_type_out_261.BCM8887X=ETH + +# core 33 lane260 +lane_to_serdes_map_nif_lane260.BCM8887X=rx260:tx260 +phy_rx_polarity_flip_phy260.BCM8887X=0 +phy_tx_polarity_flip_phy260.BCM8887X=0 + +# core 33 lane261 +lane_to_serdes_map_nif_lane261.BCM8887X=rx261:tx261 +phy_rx_polarity_flip_phy261.BCM8887X=0 +phy_tx_polarity_flip_phy261.BCM8887X=1 + +# core 33 lane262 +lane_to_serdes_map_nif_lane262.BCM8887X=rx262:tx262 +phy_rx_polarity_flip_phy262.BCM8887X=0 +phy_tx_polarity_flip_phy262.BCM8887X=0 + +# core 33 lane263 +lane_to_serdes_map_nif_lane263.BCM8887X=rx263:tx263 +phy_rx_polarity_flip_phy263.BCM8887X=0 +phy_tx_polarity_flip_phy263.BCM8887X=0 + + +# ---------------------------------------------------------------------------------------------------- +# Static Properties +# ---------------------------------------------------------------------------------------------------- + +port_init_speed_xl.BCM8887X=40000 +port_init_speed_cd.BCM8887X=400000 +port_init_speed_d3c.BCM8887X=800000 +port_init_speed_ce.BCM8887X=100000 +port_init_speed_le.BCM8887X=50000 +port_init_speed_fabric.BCM8887X=53125 +port_init_speed_xe.BCM8887X=25000 +port_init_speed_cc.BCM8887X=200000 +port_init_speed_ge.BCM8887X=1000 + +outlif_logical_to_physical_phase_map_1.BCM8887X=S1 +outlif_logical_to_physical_phase_map_2.BCM8887X=L1 +outlif_logical_to_physical_phase_map_3.BCM8887X=XL +outlif_logical_to_physical_phase_map_4.BCM8887X=L2 +outlif_logical_to_physical_phase_map_5.BCM8887X=M1 +outlif_logical_to_physical_phase_map_6.BCM8887X=M2 +outlif_logical_to_physical_phase_map_7.BCM8887X=M3 +outlif_logical_to_physical_phase_map_8.BCM8887X=S2 + +outlif_physical_phase_data_granularity_S1.BCM8887X=60 +outlif_physical_phase_data_granularity_S2.BCM8887X=60 +outlif_physical_phase_data_granularity_M1.BCM8887X=60 +outlif_physical_phase_data_granularity_M2.BCM8887X=60 +outlif_physical_phase_data_granularity_M3.BCM8887X=60 +outlif_physical_phase_data_granularity_L1.BCM8887X=60 +outlif_physical_phase_data_granularity_L2.BCM8887X=60 +outlif_physical_phase_data_granularity_XL.BCM8887X=60 + +appl_param_rcy_mirror_ports_range.BCM8887X=500-1000 + +# ----------------------------------------------- +# | FPP | FPP | FPP | FPP | FPP | FPP | +# | 11,12 | 13,14 | 15,16 | 17,18 | 19,20 | 21,22 | +# |-----------------------------------------------| +# | ETH | ETH | ETH | ETH | ETH | ETH | +# | 33,37 | 41,45 | 49,53 | 57,61 | 65,69 | 73,77 | +# ---------------|-----------------------------------------------|---------------- +# | | Core | Core | Core | Core | Core | Core | | +# | | 06 | 05 | 04 | 16 | 17 | 18 | | +# -----------------|------ ----------------------------------------------- ------|---------|------- +# | FPP | ETH | Core | | Core | ETH | FPP | +# | 09,10 | 185,189 | 07 | | 19 | 193,197 | 23,24 | +# |-------|---------|------| |------|---------|-------| +# | FPP | ETH | Core | | Core | ETH | FPP | +# | 07,08 | 177,181 | 15 | | 27 | 201,205 | 25,26 | +# |-------|---------|------| |------|---------|-------| +# | FPP | ETH | Core | AGERA2 -> QSFP_DD_112 | Core | ETH | FPP | +# | 05,06 | 169,173 | 14 | | 26 | 209,213 | 27,28 | +# |-------|---------|------| |------|---------|-------| +# | FPP | ETH | Core | | Core | ETH | FPP | +# | 03,04 | 161,165 | 13 | | 25 | 217,221 | 29,30 | +# |-------|---------|------| |------|---------|-------| +# | FPP | ETH | Core | | Core | ETH | FPP | +# | 01,02 | 153,157 | 12 | | 24 | 225,229 | 31,32 | +# |-------|---------|------|---------------------------- Q3D -------------------------------|------|---------|-------| +# | FPP | ETH | Core | | Core | ETH | FPP | +# | 33,34 | 129,133 | 08 | | 28 | 249,253 | 62,63 | +# |-------|---------|------| |------|---------|-------| +# | FPP | ETH | Core | | Core | ETH | FPP | +# | 35,36 | 137,141 | 09 | | 29 | 241,245 | 60,61 | +# |-------|---------|------| |------|---------|-------| +# | FPP | ETH | Core | | Core | ETH | FPP | +# | 36,37 | 145,149 | 10 | QSFP_112 | 30 | 233,237 | 58,59 | +# |-------|---------|------| |------|---------|-------| +# | FPP | ETH | Core | | Core | ETH | FPP | +# | 38,39 | 153,157 | 11 | | 31 | 225,229 | 56,57 | +# |-------|---------|------| |------|---------|-------| +# | FPP | ETH | Core | | Core | ETH | FPP | +# | 40,41 | 161,165 | 03 | | 23 | 217,221 | 54,55 | +# -----------------|------ _______________________________________________ ------|----------------- +# | | Core | Core | Core | Core | Core | Core | | +# | | 02 | 01 | 00 | 20 | 21 | 22 | | +# ---------------|-----------------------------------------------|---------------- +# | ETH | ETH | ETH | ETH | ETH | ETH | +# |169,173|177,181|185,189|193,197|201,205|209,213| +# |-----------------------------------------------| +# | FPP | FPP | FPP | FPP | FPP | FPP | +# | 42,43 | 44,45 | 46,47 | 48,49 | 50,51 | 52,53 | +# ----------------------------------------------- + +dpp_db_path=/usr/share/bcm/db +rif_id_max=8192 +trunk_group_max_members=128 +custom_feature_ts_pll_internal_clock_reference.BCM8887X=1 +port_init_cl72.BCM8887X=0 +port_priorities_d3c.BCM8887X=8 +port_priorities_cd.BCM8887X=8 +port_priorities_ce.BCM8887X=8 +port_priorities_xe.BCM8887X=8 +port_priorities_ge.BCM8887X=8 +port_priorities=8 +#port_priorities_sch=8 +#CPU ports +port_priorities_0=2 +port_priorities_sch_0=8 +port_priorities_380=2 +port_priorities_sch_380=8 +port_priorities_381=2 +port_priorities_sch_381=8 +port_priorities_382=2 +port_priorities_sch_382=8 +port_priorities_383=2 +port_priorities_sch_383=8 +port_priorities_384=2 +port_priorities_sch_384=8 +port_priorities_385=2 +port_priorities_sch_385=8 +port_priorities_386=2 +port_priorities_sch_386=8 +port_priorities_387=2 +port_priorities_sch_387=8 +port_priorities_rcy=2 +port_priorities_sch_rcy=8 + +appl_param_oam_enable=0 +soc_family.BCM8887X=BCM8887X + +#enable HBM +ext_ram_enabled_bitmap.BCM8887X=0xF + +#################################################### +##Reference applications related properties - End +#################################################### +###Default interfaces for Qumran3D +#CPU interfaces +ucode_port_0.BCM8887X=CPU.0:core_0.0 +ucode_port_380.BCM8887X=CPU.8:core_1.200 +ucode_port_381.BCM8887X=CPU.16:core_0.201 +ucode_port_382.BCM8887X=CPU.24:core_2.202 +ucode_port_383.BCM8887X=CPU.32:core_3.203 +ucode_port_384.BCM8887X=CPU.4:core_6.204 +ucode_port_385.BCM8887X=CPU.12:core_7.205 +ucode_port_386.BCM8887X=CPU.20:core_4.206 +ucode_port_387.BCM8887X=CPU.28:core_5.207 + +#SDK 6.5.31 +custom_feature_statdma_enable.BCM8887X=1 + +#special ports +ucode_port_330.BCM8887X=EVENTOR:core_0.230 + +#ucode_port_231.BCM8887X=EVENTOR:core_4.231 +ucode_port_340.BCM8887X=OLP0:core_0.240 +ucode_port_341.BCM8887X=OLP1:core_0.241 +ucode_port_342.BCM8887X=OLP0:core_4.242 +ucode_port_343.BCM8887X=OLP1:core_4.243 +ucode_port_332.BCM8887X=OAMP:core_0.232 +ucode_port_333.BCM8887X=OAMP:core_1.233 +ucode_port_334.BCM8887X=OAMP:core_2.234 +ucode_port_335.BCM8887X=OAMP:core_3.235 +ucode_port_336.BCM8887X=OAMP:core_4.236 +ucode_port_337.BCM8887X=OAMP:core_5.237 +ucode_port_338.BCM8887X=OAMP:core_6.238 +ucode_port_339.BCM8887X=OAMP:core_7.239 + + +ucode_port_332.BCM8887X_ADAPTER=OAMP:core_0.232 +ucode_port_333.BCM8887X_ADAPTER=OAMP:core_1.233 +ucode_port_334.BCM8887X_ADAPTER=OAMP:core_2.234 +ucode_port_335.BCM8887X_ADAPTER=OAMP:core_3.235 +ucode_port_336.BCM8887X_ADAPTER=OAMP:core_4.236 +ucode_port_337.BCM8887X_ADAPTER=OAMP:core_5.237 +ucode_port_338.BCM8887X_ADAPTER=OAMP:core_6.238 +ucode_port_339.BCM8887X_ADAPTER=OAMP:core_7.239 + + +#OAMP +oamp_dual_mode.BCM8887X=1 + +sai_disable_srcmacqedstmac_ctrl=1 + +#RCY ports +sai_recycle_port_lane_base=300 +ucode_port_321.BCM8887X=RCY.21:core_0.221 +tm_port_header_type_in_321.BCM8887X=ETH + +# SAT +## Enable SAT Interface. 0 - Disable, 1 - Enable (Default) +ucode_port_316.BCM8887X=SAT:core_2.216 +ucode_port_317.BCM8887X=SAT:core_3.217 +ucode_port_318.BCM8887X=SAT:core_0.218 +ucode_port_319.BCM8887X=SAT:core_1.219 +ucode_port_312.BCM8887X=SAT:core_6.212 +ucode_port_313.BCM8887X=SAT:core_7.213 +ucode_port_314.BCM8887X=SAT:core_4.214 +ucode_port_315.BCM8887X=SAT:core_5.215 +tm_port_header_type_in_316.BCM8887X=INJECTED_2 +tm_port_header_type_in_317.BCM8887X=INJECTED_2 +tm_port_header_type_in_318.BCM8887X=INJECTED_2 +tm_port_header_type_in_319.BCM8887X=INJECTED_2 +tm_port_header_type_in_312.BCM8887X=INJECTED_2 +tm_port_header_type_in_313.BCM8887X=INJECTED_2 +tm_port_header_type_in_314.BCM8887X=INJECTED_2 +tm_port_header_type_in_315.BCM8887X=INJECTED_2 +tm_port_header_type_out_316.BCM8887X=CPU +tm_port_header_type_out_317.BCM8887X=CPU +tm_port_header_type_out_318.BCM8887X=CPU +tm_port_header_type_out_319.BCM8887X=CPU +tm_port_header_type_out_312.BCM8887X=CPU +tm_port_header_type_out_313.BCM8887X=CPU +tm_port_header_type_out_314.BCM8887X=CPU +tm_port_header_type_out_315.BCM8887X=CPU + + +######################### +### High Availability ### +######################### +#if warmboot is not needed this property can be deleted +#warmboot_support.BCM8887X=on +#warmboot_support.BCM8887X_ADAPTER=on + +#size of memory block pre-allocated for sw-state use when working with warmboot_support=on +sw_state_max_size.BCM8887X=1650000000 +sw_state_max_size.BCM8887X_ADAPTER=1650000000 + +#location of warmboot NV memory +#Allowed options for dnx are - 3:external storage in filesystem 4:driver will save the state directly in shared memory +stable_location.BCM8887X=4 +stable_location.BCM8887X_ADAPTER=3 + +# Note that each unit should have a unique filename and that adapter does not play well with tmp and dev/shm folders. +stable_filename.BCM8887X_ADAPTER=warmboot_data_0 +stable_filename.BCM8887X=/dev/shm/warmboot_data_0 +stable_filename.1.BCM8887X=/dev/shm/warmboot_data_1 +stable_filename.2.BCM8887X=/dev/shm/warmboot_data_2 + +#Maximum size for NVM used for WB storage, must be larger than sw_state_max_size.BCM8887X +stable_size.BCM8887X=1700000000 +stable_size.BCM8887X_ADAPTER=1700000000 + +#disable counter thread +bcm_stat_interval.BCM8887X_ADAPTER=0 + +######################### +######################### +######################### + +### MDB configuration ### +mdb_profile.BCM8887X=Elastic-Balanced + +### Enable Descriptor-DMA ### +dma_desc_aggregator_chain_length_max.BCM8887X=256 +dma_desc_aggregator_buff_size_kb.BCM8887X=64 +dma_desc_aggregator_enable_specific_MDB_LPM.BCM8887X=1 +dma_desc_aggregator_enable_specific_MDB_FEC.BCM8887X=1 +dma_desc_aggregator_enable_specific_XLTCAM.BCM8887X=1 +dma_desc_aggregator_enable_specific_INIT.BCM8887X=1 + +# PMF Map payload size, can be any of 30/60/120 +pmf_maps_payload_size.BCM8887X=30 + +# Set CPU to work with PTCHoITMH header incoming direction and CPU - system headers + network headers outgoing direction +tm_port_header_type_in_0.BCM8887X=INJECTED_2 +tm_port_header_type_out_0.BCM8887X=CPU + +tm_port_header_type_in_380.BCM8887X=INJECTED_2_PP +tm_port_header_type_out_380.BCM8887X=ETH +tm_port_header_type_in_381.BCM8887X=INJECTED_2_PP +tm_port_header_type_out_381.BCM8887X=ETH +tm_port_header_type_in_382.BCM8887X=INJECTED_2_PP +tm_port_header_type_out_382.BCM8887X=ETH +tm_port_header_type_in_383.BCM8887X=INJECTED_2_PP +tm_port_header_type_out_383.BCM8887X=ETH +tm_port_header_type_in_384.BCM8887X=INJECTED_2_PP +tm_port_header_type_out_384.BCM8887X=ETH +tm_port_header_type_in_385.BCM8887X=INJECTED_2_PP +tm_port_header_type_out_385.BCM8887X=ETH +tm_port_header_type_in_386.BCM8887X=INJECTED_2_PP +tm_port_header_type_out_386.BCM8887X=ETH +tm_port_header_type_in_387.BCM8887X=INJECTED_2_PP +tm_port_header_type_out_387.BCM8887X=ETH + +# set EVENTOR port to work with PTCHoITMH +tm_port_header_type_in_330.BCM8887X=INJECTED_2 + + +#OAMP +tm_port_header_type_in_332.BCM8887X=INJECTED_2 +tm_port_header_type_out_332.BCM8887X=ENCAP_EXTERNAL_CPU +tm_port_header_type_in_333.BCM8887X=INJECTED_2 +tm_port_header_type_out_333.BCM8887X=ENCAP_EXTERNAL_CPU +tm_port_header_type_in_334.BCM8887X=INJECTED_2 +tm_port_header_type_out_334.BCM8887X=ENCAP_EXTERNAL_CPU +tm_port_header_type_in_335.BCM8887X=INJECTED_2 +tm_port_header_type_in_336.BCM8887X=INJECTED_2 +tm_port_header_type_out_336.BCM8887X=ENCAP_EXTERNAL_CPU +tm_port_header_type_in_337.BCM8887X=INJECTED_2 +tm_port_header_type_out_337.BCM8887X=ENCAP_EXTERNAL_CPU +tm_port_header_type_in_338.BCM8887X=INJECTED_2 +tm_port_header_type_out_338.BCM8887X=ENCAP_EXTERNAL_CPU +tm_port_header_type_in_339.BCM8887X=INJECTED_2 +tm_port_header_type_out_339.BCM8887X=ENCAP_EXTERNAL_CPU + +#OLP +tm_port_header_type_in_340.BCM8887X=TM +tm_port_header_type_out_340.BCM8887X=ETH +tm_port_header_type_in_341.BCM8887X=TM +tm_port_header_type_out_341.BCM8887X=ETH +tm_port_header_type_in_342.BCM8887X=TM +tm_port_header_type_out_342.BCM8887X=ETH +tm_port_header_type_in_343.BCM8887X=TM +tm_port_header_type_out_343.BCM8887X=ETH + +# Set statically the region mode per region id +# 0: queue connectors only. +# 3: [default] SE only (SharingOrder = Low-To-High) +# 7: SE only (SharingOrder = High-To-Low) +dtm_flow_mapping_mode_region_65.BCM8887X=3 +dtm_flow_mapping_mode_region_66.BCM8887X=3 +dtm_flow_mapping_mode_region_67.BCM8887X=3 +dtm_flow_mapping_mode_region_68.BCM8887X=3 +dtm_flow_mapping_mode_region_69.BCM8887X=3 +dtm_flow_mapping_mode_region_70.BCM8887X=3 +dtm_flow_mapping_mode_region_71.BCM8887X=3 +dtm_flow_mapping_mode_region_72.BCM8887X=3 +dtm_flow_mapping_mode_region_73.BCM8887X=3 +dtm_flow_mapping_mode_region_74.BCM8887X=7 +dtm_flow_mapping_mode_region_75.BCM8887X=3 +dtm_flow_mapping_mode_region_76.BCM8887X=3 +dtm_flow_mapping_mode_region_77.BCM8887X=3 +dtm_flow_mapping_mode_region_78.BCM8887X=3 +dtm_flow_mapping_mode_region_79.BCM8887X=3 +dtm_flow_mapping_mode_region_80.BCM8887X=3 +dtm_flow_mapping_mode_region_81.BCM8887X=3 +dtm_flow_mapping_mode_region_82.BCM8887X=3 +dtm_flow_mapping_mode_region_83.BCM8887X=3 +dtm_flow_mapping_mode_region_84.BCM8887X=3 +dtm_flow_mapping_mode_region_85.BCM8887X=3 +dtm_flow_mapping_mode_region_86.BCM8887X=3 +dtm_flow_mapping_mode_region_87.BCM8887X=3 +dtm_flow_mapping_mode_region_88.BCM8887X=3 +dtm_flow_mapping_mode_region_89.BCM8887X=3 +dtm_flow_mapping_mode_region_90.BCM8887X=3 +dtm_flow_mapping_mode_region_91.BCM8887X=3 +dtm_flow_mapping_mode_region_92.BCM8887X=3 +dtm_flow_mapping_mode_region_93.BCM8887X=3 +dtm_flow_mapping_mode_region_94.BCM8887X=3 + +# Set nof remote cores +dtm_flow_nof_remote_cores_region.BCM8887X=8 + +## Fabric transmission mode +# Set the Connect mode to the Fabric +# Options: FE - presence of a Fabric device (single stage) +# SINGLE_FAP - stand-alone device +# MESH - devices in Mesh +# Note: If 'diag_chassis' is on, value will be override in dnx.soc +# to be FE instead of SINGLE_FAP. +fabric_connect_mode.BCM8887X=SINGLE_FAP + +### Fabric configuration ### +#SFI speed rate +port_init_speed_fabric.BCM8887X=53125 + +### import SoC properties that shared with Ucode +#import config-qumran3d-ucode.bcm +#programmability_image_name.BCM8887X=S121 +# ucode input file, depending on image +#programmability_ucode_relative_path.BCM8887X=pemla/ucode/S121/jr3native/u_code_db2pem.txt + +custom_feature_adapter_do_collect_enable.BCM8887X_ADAPTER=1 +custom_feature_use_new_access.BCM8887X_ADAPTER=1 +mem_cache_enable_all.BCM8887X_ADAPTER=1 + +#Disable DMA stat +custom_feature_statdma_enable.BCM8887X_ADAPTER=0 + +#dram + +dram_temperature_monitor_enable.BCM8887X_ADAPTER=0 +#Interrupt polling mode on adapter +polled_irq_mode.BCM8887X_ADAPTER=1 +polled_irq_delay.BCM8887X_ADAPTER=200000 + +#Eventor SBUS DMA channels +eventor_sbus_dma_channels.BCM8887X=0,24,0,25,1,24,1,25 + +#Default CPU Tx Tc Queue +sai_default_cpu_tx_tc=7 diff --git a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/phy0_config.json b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/phy0_config.json new file mode 100644 index 00000000000..fcf79506e40 --- /dev/null +++ b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/phy0_config.json @@ -0,0 +1,59 @@ +{ + "lanes": [ + { + "index": 255, + "local_lane_id": 255, + "system_side": true, + "tx_polarity": 255, + "rx_polarity": 255, + "line_tx_lanemap": 255, + "line_rx_lanemap": 255, + "line_to_system_lanemap": 255, + "mdio_addr": "" + } + ], + "ports": [ + { + "index": 1, + "mdio_addr": "0", + "system_speed": 25000, + "system_fec": "none", + "system_auto_neg": false, + "system_loopback": "none", + "system_training": false, + "line_speed": 25000, + "line_fec": "none", + "line_auto_neg": false, + "line_loopback": "none", + "line_training": false, + "line_media_type": "fiber", + "line_intf_type": "none", + "line_adver_speed": [], + "line_adver_fec": [], + "line_adver_auto_neg": false, + "line_adver_asym_pause": false, + "line_adver_media_type": "fiber" + }, + { + "index": 2, + "mdio_addr": "0", + "system_speed": 25000, + "system_fec": "none", + "system_auto_neg": false, + "system_loopback": "none", + "system_training": false, + "line_speed": 25000, + "line_fec": "none", + "line_auto_neg": false, + "line_loopback": "none", + "line_training": false, + "line_media_type": "fiber", + "line_intf_type": "none", + "line_adver_speed": [], + "line_adver_fec": [], + "line_adver_auto_neg": false, + "line_adver_asym_pause": false, + "line_adver_media_type": "fiber" + } + ] +} \ No newline at end of file diff --git a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/phy10_config.json b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/phy10_config.json new file mode 100644 index 00000000000..08045857be9 --- /dev/null +++ b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/phy10_config.json @@ -0,0 +1,59 @@ +{ + "lanes": [ + { + "index": 255, + "local_lane_id": 255, + "system_side": true, + "tx_polarity": 255, + "rx_polarity": 255, + "line_tx_lanemap": 255, + "line_rx_lanemap": 255, + "line_to_system_lanemap": 255, + "mdio_addr": "" + } + ], + "ports": [ + { + "index": 21, + "mdio_addr": "0", + "system_speed": 25000, + "system_fec": "none", + "system_auto_neg": false, + "system_loopback": "none", + "system_training": false, + "line_speed": 25000, + "line_fec": "none", + "line_auto_neg": false, + "line_loopback": "none", + "line_training": false, + "line_media_type": "fiber", + "line_intf_type": "none", + "line_adver_speed": [], + "line_adver_fec": [], + "line_adver_auto_neg": false, + "line_adver_asym_pause": false, + "line_adver_media_type": "fiber" + }, + { + "index": 22, + "mdio_addr": "0", + "system_speed": 25000, + "system_fec": "none", + "system_auto_neg": false, + "system_loopback": "none", + "system_training": false, + "line_speed": 25000, + "line_fec": "none", + "line_auto_neg": false, + "line_loopback": "none", + "line_training": false, + "line_media_type": "fiber", + "line_intf_type": "none", + "line_adver_speed": [], + "line_adver_fec": [], + "line_adver_auto_neg": false, + "line_adver_asym_pause": false, + "line_adver_media_type": "fiber" + } + ] +} \ No newline at end of file diff --git a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/phy11_config.json b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/phy11_config.json new file mode 100644 index 00000000000..b9ef85f6193 --- /dev/null +++ b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/phy11_config.json @@ -0,0 +1,59 @@ +{ + "lanes": [ + { + "index": 255, + "local_lane_id": 255, + "system_side": true, + "tx_polarity": 255, + "rx_polarity": 255, + "line_tx_lanemap": 255, + "line_rx_lanemap": 255, + "line_to_system_lanemap": 255, + "mdio_addr": "" + } + ], + "ports": [ + { + "index": 23, + "mdio_addr": "0", + "system_speed": 25000, + "system_fec": "none", + "system_auto_neg": false, + "system_loopback": "none", + "system_training": false, + "line_speed": 25000, + "line_fec": "none", + "line_auto_neg": false, + "line_loopback": "none", + "line_training": false, + "line_media_type": "fiber", + "line_intf_type": "none", + "line_adver_speed": [], + "line_adver_fec": [], + "line_adver_auto_neg": false, + "line_adver_asym_pause": false, + "line_adver_media_type": "fiber" + }, + { + "index": 24, + "mdio_addr": "0", + "system_speed": 25000, + "system_fec": "none", + "system_auto_neg": false, + "system_loopback": "none", + "system_training": false, + "line_speed": 25000, + "line_fec": "none", + "line_auto_neg": false, + "line_loopback": "none", + "line_training": false, + "line_media_type": "fiber", + "line_intf_type": "none", + "line_adver_speed": [], + "line_adver_fec": [], + "line_adver_auto_neg": false, + "line_adver_asym_pause": false, + "line_adver_media_type": "fiber" + } + ] +} \ No newline at end of file diff --git a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/phy12_config.json b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/phy12_config.json new file mode 100644 index 00000000000..54b097a0e6a --- /dev/null +++ b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/phy12_config.json @@ -0,0 +1,59 @@ +{ + "lanes": [ + { + "index": 255, + "local_lane_id": 255, + "system_side": true, + "tx_polarity": 255, + "rx_polarity": 255, + "line_tx_lanemap": 255, + "line_rx_lanemap": 255, + "line_to_system_lanemap": 255, + "mdio_addr": "" + } + ], + "ports": [ + { + "index": 25, + "mdio_addr": "0", + "system_speed": 25000, + "system_fec": "none", + "system_auto_neg": false, + "system_loopback": "none", + "system_training": false, + "line_speed": 25000, + "line_fec": "none", + "line_auto_neg": false, + "line_loopback": "none", + "line_training": false, + "line_media_type": "fiber", + "line_intf_type": "none", + "line_adver_speed": [], + "line_adver_fec": [], + "line_adver_auto_neg": false, + "line_adver_asym_pause": false, + "line_adver_media_type": "fiber" + }, + { + "index": 26, + "mdio_addr": "0", + "system_speed": 25000, + "system_fec": "none", + "system_auto_neg": false, + "system_loopback": "none", + "system_training": false, + "line_speed": 25000, + "line_fec": "none", + "line_auto_neg": false, + "line_loopback": "none", + "line_training": false, + "line_media_type": "fiber", + "line_intf_type": "none", + "line_adver_speed": [], + "line_adver_fec": [], + "line_adver_auto_neg": false, + "line_adver_asym_pause": false, + "line_adver_media_type": "fiber" + } + ] +} \ No newline at end of file diff --git a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/phy13_config.json b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/phy13_config.json new file mode 100644 index 00000000000..0d09e7beda6 --- /dev/null +++ b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/phy13_config.json @@ -0,0 +1,59 @@ +{ + "lanes": [ + { + "index": 255, + "local_lane_id": 255, + "system_side": true, + "tx_polarity": 255, + "rx_polarity": 255, + "line_tx_lanemap": 255, + "line_rx_lanemap": 255, + "line_to_system_lanemap": 255, + "mdio_addr": "" + } + ], + "ports": [ + { + "index": 27, + "mdio_addr": "0", + "system_speed": 25000, + "system_fec": "none", + "system_auto_neg": false, + "system_loopback": "none", + "system_training": false, + "line_speed": 25000, + "line_fec": "none", + "line_auto_neg": false, + "line_loopback": "none", + "line_training": false, + "line_media_type": "fiber", + "line_intf_type": "none", + "line_adver_speed": [], + "line_adver_fec": [], + "line_adver_auto_neg": false, + "line_adver_asym_pause": false, + "line_adver_media_type": "fiber" + }, + { + "index": 28, + "mdio_addr": "0", + "system_speed": 25000, + "system_fec": "none", + "system_auto_neg": false, + "system_loopback": "none", + "system_training": false, + "line_speed": 25000, + "line_fec": "none", + "line_auto_neg": false, + "line_loopback": "none", + "line_training": false, + "line_media_type": "fiber", + "line_intf_type": "none", + "line_adver_speed": [], + "line_adver_fec": [], + "line_adver_auto_neg": false, + "line_adver_asym_pause": false, + "line_adver_media_type": "fiber" + } + ] +} \ No newline at end of file diff --git a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/phy14_config.json b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/phy14_config.json new file mode 100644 index 00000000000..2545eafc501 --- /dev/null +++ b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/phy14_config.json @@ -0,0 +1,59 @@ +{ + "lanes": [ + { + "index": 255, + "local_lane_id": 255, + "system_side": true, + "tx_polarity": 255, + "rx_polarity": 255, + "line_tx_lanemap": 255, + "line_rx_lanemap": 255, + "line_to_system_lanemap": 255, + "mdio_addr": "" + } + ], + "ports": [ + { + "index": 29, + "mdio_addr": "0", + "system_speed": 25000, + "system_fec": "none", + "system_auto_neg": false, + "system_loopback": "none", + "system_training": false, + "line_speed": 25000, + "line_fec": "none", + "line_auto_neg": false, + "line_loopback": "none", + "line_training": false, + "line_media_type": "fiber", + "line_intf_type": "none", + "line_adver_speed": [], + "line_adver_fec": [], + "line_adver_auto_neg": false, + "line_adver_asym_pause": false, + "line_adver_media_type": "fiber" + }, + { + "index": 30, + "mdio_addr": "0", + "system_speed": 25000, + "system_fec": "none", + "system_auto_neg": false, + "system_loopback": "none", + "system_training": false, + "line_speed": 25000, + "line_fec": "none", + "line_auto_neg": false, + "line_loopback": "none", + "line_training": false, + "line_media_type": "fiber", + "line_intf_type": "none", + "line_adver_speed": [], + "line_adver_fec": [], + "line_adver_auto_neg": false, + "line_adver_asym_pause": false, + "line_adver_media_type": "fiber" + } + ] +} \ No newline at end of file diff --git a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/phy15_config.json b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/phy15_config.json new file mode 100644 index 00000000000..ff3b38d8340 --- /dev/null +++ b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/phy15_config.json @@ -0,0 +1,59 @@ +{ + "lanes": [ + { + "index": 255, + "local_lane_id": 255, + "system_side": true, + "tx_polarity": 255, + "rx_polarity": 255, + "line_tx_lanemap": 255, + "line_rx_lanemap": 255, + "line_to_system_lanemap": 255, + "mdio_addr": "" + } + ], + "ports": [ + { + "index": 31, + "mdio_addr": "0", + "system_speed": 25000, + "system_fec": "none", + "system_auto_neg": false, + "system_loopback": "none", + "system_training": false, + "line_speed": 25000, + "line_fec": "none", + "line_auto_neg": false, + "line_loopback": "none", + "line_training": false, + "line_media_type": "fiber", + "line_intf_type": "none", + "line_adver_speed": [], + "line_adver_fec": [], + "line_adver_auto_neg": false, + "line_adver_asym_pause": false, + "line_adver_media_type": "fiber" + }, + { + "index": 32, + "mdio_addr": "0", + "system_speed": 25000, + "system_fec": "none", + "system_auto_neg": false, + "system_loopback": "none", + "system_training": false, + "line_speed": 25000, + "line_fec": "none", + "line_auto_neg": false, + "line_loopback": "none", + "line_training": false, + "line_media_type": "fiber", + "line_intf_type": "none", + "line_adver_speed": [], + "line_adver_fec": [], + "line_adver_auto_neg": false, + "line_adver_asym_pause": false, + "line_adver_media_type": "fiber" + } + ] +} \ No newline at end of file diff --git a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/phy1_config.json b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/phy1_config.json new file mode 100644 index 00000000000..af2c6b08ca3 --- /dev/null +++ b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/phy1_config.json @@ -0,0 +1,59 @@ +{ + "lanes": [ + { + "index": 255, + "local_lane_id": 255, + "system_side": true, + "tx_polarity": 255, + "rx_polarity": 255, + "line_tx_lanemap": 255, + "line_rx_lanemap": 255, + "line_to_system_lanemap": 255, + "mdio_addr": "" + } + ], + "ports": [ + { + "index": 3, + "mdio_addr": "0", + "system_speed": 25000, + "system_fec": "none", + "system_auto_neg": false, + "system_loopback": "none", + "system_training": false, + "line_speed": 25000, + "line_fec": "none", + "line_auto_neg": false, + "line_loopback": "none", + "line_training": false, + "line_media_type": "fiber", + "line_intf_type": "none", + "line_adver_speed": [], + "line_adver_fec": [], + "line_adver_auto_neg": false, + "line_adver_asym_pause": false, + "line_adver_media_type": "fiber" + }, + { + "index": 4, + "mdio_addr": "0", + "system_speed": 25000, + "system_fec": "none", + "system_auto_neg": false, + "system_loopback": "none", + "system_training": false, + "line_speed": 25000, + "line_fec": "none", + "line_auto_neg": false, + "line_loopback": "none", + "line_training": false, + "line_media_type": "fiber", + "line_intf_type": "none", + "line_adver_speed": [], + "line_adver_fec": [], + "line_adver_auto_neg": false, + "line_adver_asym_pause": false, + "line_adver_media_type": "fiber" + } + ] +} \ No newline at end of file diff --git a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/phy2_config.json b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/phy2_config.json new file mode 100644 index 00000000000..ef1bc1f9469 --- /dev/null +++ b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/phy2_config.json @@ -0,0 +1,59 @@ +{ + "lanes": [ + { + "index": 255, + "local_lane_id": 255, + "system_side": true, + "tx_polarity": 255, + "rx_polarity": 255, + "line_tx_lanemap": 255, + "line_rx_lanemap": 255, + "line_to_system_lanemap": 255, + "mdio_addr": "" + } + ], + "ports": [ + { + "index": 5, + "mdio_addr": "0", + "system_speed": 25000, + "system_fec": "none", + "system_auto_neg": false, + "system_loopback": "none", + "system_training": false, + "line_speed": 25000, + "line_fec": "none", + "line_auto_neg": false, + "line_loopback": "none", + "line_training": false, + "line_media_type": "fiber", + "line_intf_type": "none", + "line_adver_speed": [], + "line_adver_fec": [], + "line_adver_auto_neg": false, + "line_adver_asym_pause": false, + "line_adver_media_type": "fiber" + }, + { + "index": 6, + "mdio_addr": "0", + "system_speed": 25000, + "system_fec": "none", + "system_auto_neg": false, + "system_loopback": "none", + "system_training": false, + "line_speed": 25000, + "line_fec": "none", + "line_auto_neg": false, + "line_loopback": "none", + "line_training": false, + "line_media_type": "fiber", + "line_intf_type": "none", + "line_adver_speed": [], + "line_adver_fec": [], + "line_adver_auto_neg": false, + "line_adver_asym_pause": false, + "line_adver_media_type": "fiber" + } + ] +} \ No newline at end of file diff --git a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/phy3_config.json b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/phy3_config.json new file mode 100644 index 00000000000..8cc5b60b0d7 --- /dev/null +++ b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/phy3_config.json @@ -0,0 +1,59 @@ +{ + "lanes": [ + { + "index": 255, + "local_lane_id": 255, + "system_side": true, + "tx_polarity": 255, + "rx_polarity": 255, + "line_tx_lanemap": 255, + "line_rx_lanemap": 255, + "line_to_system_lanemap": 255, + "mdio_addr": "" + } + ], + "ports": [ + { + "index": 7, + "mdio_addr": "0", + "system_speed": 25000, + "system_fec": "none", + "system_auto_neg": false, + "system_loopback": "none", + "system_training": false, + "line_speed": 25000, + "line_fec": "none", + "line_auto_neg": false, + "line_loopback": "none", + "line_training": false, + "line_media_type": "fiber", + "line_intf_type": "none", + "line_adver_speed": [], + "line_adver_fec": [], + "line_adver_auto_neg": false, + "line_adver_asym_pause": false, + "line_adver_media_type": "fiber" + }, + { + "index": 8, + "mdio_addr": "0", + "system_speed": 25000, + "system_fec": "none", + "system_auto_neg": false, + "system_loopback": "none", + "system_training": false, + "line_speed": 25000, + "line_fec": "none", + "line_auto_neg": false, + "line_loopback": "none", + "line_training": false, + "line_media_type": "fiber", + "line_intf_type": "none", + "line_adver_speed": [], + "line_adver_fec": [], + "line_adver_auto_neg": false, + "line_adver_asym_pause": false, + "line_adver_media_type": "fiber" + } + ] +} \ No newline at end of file diff --git a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/phy4_config.json b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/phy4_config.json new file mode 100644 index 00000000000..4495d75aa00 --- /dev/null +++ b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/phy4_config.json @@ -0,0 +1,59 @@ +{ + "lanes": [ + { + "index": 255, + "local_lane_id": 255, + "system_side": true, + "tx_polarity": 255, + "rx_polarity": 255, + "line_tx_lanemap": 255, + "line_rx_lanemap": 255, + "line_to_system_lanemap": 255, + "mdio_addr": "" + } + ], + "ports": [ + { + "index": 9, + "mdio_addr": "0", + "system_speed": 25000, + "system_fec": "none", + "system_auto_neg": false, + "system_loopback": "none", + "system_training": false, + "line_speed": 25000, + "line_fec": "none", + "line_auto_neg": false, + "line_loopback": "none", + "line_training": false, + "line_media_type": "fiber", + "line_intf_type": "none", + "line_adver_speed": [], + "line_adver_fec": [], + "line_adver_auto_neg": false, + "line_adver_asym_pause": false, + "line_adver_media_type": "fiber" + }, + { + "index": 10, + "mdio_addr": "0", + "system_speed": 25000, + "system_fec": "none", + "system_auto_neg": false, + "system_loopback": "none", + "system_training": false, + "line_speed": 25000, + "line_fec": "none", + "line_auto_neg": false, + "line_loopback": "none", + "line_training": false, + "line_media_type": "fiber", + "line_intf_type": "none", + "line_adver_speed": [], + "line_adver_fec": [], + "line_adver_auto_neg": false, + "line_adver_asym_pause": false, + "line_adver_media_type": "fiber" + } + ] +} \ No newline at end of file diff --git a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/phy5_config.json b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/phy5_config.json new file mode 100644 index 00000000000..66c58adf6c2 --- /dev/null +++ b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/phy5_config.json @@ -0,0 +1,59 @@ +{ + "lanes": [ + { + "index": 255, + "local_lane_id": 255, + "system_side": true, + "tx_polarity": 255, + "rx_polarity": 255, + "line_tx_lanemap": 255, + "line_rx_lanemap": 255, + "line_to_system_lanemap": 255, + "mdio_addr": "" + } + ], + "ports": [ + { + "index": 11, + "mdio_addr": "0", + "system_speed": 25000, + "system_fec": "none", + "system_auto_neg": false, + "system_loopback": "none", + "system_training": false, + "line_speed": 25000, + "line_fec": "none", + "line_auto_neg": false, + "line_loopback": "none", + "line_training": false, + "line_media_type": "fiber", + "line_intf_type": "none", + "line_adver_speed": [], + "line_adver_fec": [], + "line_adver_auto_neg": false, + "line_adver_asym_pause": false, + "line_adver_media_type": "fiber" + }, + { + "index": 12, + "mdio_addr": "0", + "system_speed": 25000, + "system_fec": "none", + "system_auto_neg": false, + "system_loopback": "none", + "system_training": false, + "line_speed": 25000, + "line_fec": "none", + "line_auto_neg": false, + "line_loopback": "none", + "line_training": false, + "line_media_type": "fiber", + "line_intf_type": "none", + "line_adver_speed": [], + "line_adver_fec": [], + "line_adver_auto_neg": false, + "line_adver_asym_pause": false, + "line_adver_media_type": "fiber" + } + ] +} \ No newline at end of file diff --git a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/phy6_config.json b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/phy6_config.json new file mode 100644 index 00000000000..723f7e4e183 --- /dev/null +++ b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/phy6_config.json @@ -0,0 +1,59 @@ +{ + "lanes": [ + { + "index": 255, + "local_lane_id": 255, + "system_side": true, + "tx_polarity": 255, + "rx_polarity": 255, + "line_tx_lanemap": 255, + "line_rx_lanemap": 255, + "line_to_system_lanemap": 255, + "mdio_addr": "" + } + ], + "ports": [ + { + "index": 13, + "mdio_addr": "0", + "system_speed": 25000, + "system_fec": "none", + "system_auto_neg": false, + "system_loopback": "none", + "system_training": false, + "line_speed": 25000, + "line_fec": "none", + "line_auto_neg": false, + "line_loopback": "none", + "line_training": false, + "line_media_type": "fiber", + "line_intf_type": "none", + "line_adver_speed": [], + "line_adver_fec": [], + "line_adver_auto_neg": false, + "line_adver_asym_pause": false, + "line_adver_media_type": "fiber" + }, + { + "index": 14, + "mdio_addr": "0", + "system_speed": 25000, + "system_fec": "none", + "system_auto_neg": false, + "system_loopback": "none", + "system_training": false, + "line_speed": 25000, + "line_fec": "none", + "line_auto_neg": false, + "line_loopback": "none", + "line_training": false, + "line_media_type": "fiber", + "line_intf_type": "none", + "line_adver_speed": [], + "line_adver_fec": [], + "line_adver_auto_neg": false, + "line_adver_asym_pause": false, + "line_adver_media_type": "fiber" + } + ] +} \ No newline at end of file diff --git a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/phy7_config.json b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/phy7_config.json new file mode 100644 index 00000000000..a3eeacad669 --- /dev/null +++ b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/phy7_config.json @@ -0,0 +1,59 @@ +{ + "lanes": [ + { + "index": 255, + "local_lane_id": 255, + "system_side": true, + "tx_polarity": 255, + "rx_polarity": 255, + "line_tx_lanemap": 255, + "line_rx_lanemap": 255, + "line_to_system_lanemap": 255, + "mdio_addr": "" + } + ], + "ports": [ + { + "index": 15, + "mdio_addr": "0", + "system_speed": 25000, + "system_fec": "none", + "system_auto_neg": false, + "system_loopback": "none", + "system_training": false, + "line_speed": 25000, + "line_fec": "none", + "line_auto_neg": false, + "line_loopback": "none", + "line_training": false, + "line_media_type": "fiber", + "line_intf_type": "none", + "line_adver_speed": [], + "line_adver_fec": [], + "line_adver_auto_neg": false, + "line_adver_asym_pause": false, + "line_adver_media_type": "fiber" + }, + { + "index": 16, + "mdio_addr": "0", + "system_speed": 25000, + "system_fec": "none", + "system_auto_neg": false, + "system_loopback": "none", + "system_training": false, + "line_speed": 25000, + "line_fec": "none", + "line_auto_neg": false, + "line_loopback": "none", + "line_training": false, + "line_media_type": "fiber", + "line_intf_type": "none", + "line_adver_speed": [], + "line_adver_fec": [], + "line_adver_auto_neg": false, + "line_adver_asym_pause": false, + "line_adver_media_type": "fiber" + } + ] +} \ No newline at end of file diff --git a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/phy8_config.json b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/phy8_config.json new file mode 100644 index 00000000000..04d6efebfa7 --- /dev/null +++ b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/phy8_config.json @@ -0,0 +1,59 @@ +{ + "lanes": [ + { + "index": 255, + "local_lane_id": 255, + "system_side": true, + "tx_polarity": 255, + "rx_polarity": 255, + "line_tx_lanemap": 255, + "line_rx_lanemap": 255, + "line_to_system_lanemap": 255, + "mdio_addr": "" + } + ], + "ports": [ + { + "index": 17, + "mdio_addr": "0", + "system_speed": 25000, + "system_fec": "none", + "system_auto_neg": false, + "system_loopback": "none", + "system_training": false, + "line_speed": 25000, + "line_fec": "none", + "line_auto_neg": false, + "line_loopback": "none", + "line_training": false, + "line_media_type": "fiber", + "line_intf_type": "none", + "line_adver_speed": [], + "line_adver_fec": [], + "line_adver_auto_neg": false, + "line_adver_asym_pause": false, + "line_adver_media_type": "fiber" + }, + { + "index": 18, + "mdio_addr": "0", + "system_speed": 25000, + "system_fec": "none", + "system_auto_neg": false, + "system_loopback": "none", + "system_training": false, + "line_speed": 25000, + "line_fec": "none", + "line_auto_neg": false, + "line_loopback": "none", + "line_training": false, + "line_media_type": "fiber", + "line_intf_type": "none", + "line_adver_speed": [], + "line_adver_fec": [], + "line_adver_auto_neg": false, + "line_adver_asym_pause": false, + "line_adver_media_type": "fiber" + } + ] +} \ No newline at end of file diff --git a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/phy9_config.json b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/phy9_config.json new file mode 100644 index 00000000000..44ecc58b590 --- /dev/null +++ b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/phy9_config.json @@ -0,0 +1,59 @@ +{ + "lanes": [ + { + "index": 255, + "local_lane_id": 255, + "system_side": true, + "tx_polarity": 255, + "rx_polarity": 255, + "line_tx_lanemap": 255, + "line_rx_lanemap": 255, + "line_to_system_lanemap": 255, + "mdio_addr": "" + } + ], + "ports": [ + { + "index": 19, + "mdio_addr": "0", + "system_speed": 25000, + "system_fec": "none", + "system_auto_neg": false, + "system_loopback": "none", + "system_training": false, + "line_speed": 25000, + "line_fec": "none", + "line_auto_neg": false, + "line_loopback": "none", + "line_training": false, + "line_media_type": "fiber", + "line_intf_type": "none", + "line_adver_speed": [], + "line_adver_fec": [], + "line_adver_auto_neg": false, + "line_adver_asym_pause": false, + "line_adver_media_type": "fiber" + }, + { + "index": 20, + "mdio_addr": "0", + "system_speed": 25000, + "system_fec": "none", + "system_auto_neg": false, + "system_loopback": "none", + "system_training": false, + "line_speed": 25000, + "line_fec": "none", + "line_auto_neg": false, + "line_loopback": "none", + "line_training": false, + "line_media_type": "fiber", + "line_intf_type": "none", + "line_adver_speed": [], + "line_adver_fec": [], + "line_adver_auto_neg": false, + "line_adver_asym_pause": false, + "line_adver_media_type": "fiber" + } + ] +} \ No newline at end of file diff --git a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/port_config.ini b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/port_config.ini new file mode 100644 index 00000000000..2531d610880 --- /dev/null +++ b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/port_config.ini @@ -0,0 +1,68 @@ +# name lanes alias index role speed asic_port_name core_id core_port_id num_voq +Ethernet0 96,97,98,99 Port1 1 Ext 100000 Eth0 3 1 8 +Ethernet4 100,101,102,103 Port2 2 Ext 100000 Eth4 3 5 8 +Ethernet8 104,105,106,107 Port3 3 Ext 100000 Eth8 3 9 8 +Ethernet12 108,109,110,111 Port4 4 Ext 100000 Eth12 3 13 8 +Ethernet16 112,113,114,115 Port5 5 Ext 100000 Eth16 3 17 8 +Ethernet20 116,117,118,119 Port6 6 Ext 100000 Eth20 3 21 8 +Ethernet24 120,121,122,123 Port7 7 Ext 100000 Eth24 3 25 8 +Ethernet28 124,125,126,127 Port8 8 Ext 100000 Eth28 3 29 8 +Ethernet32 56,57,58,59 Port9 9 Ext 100000 Eth32 1 25 8 +Ethernet36 60,61,62,63 Port10 10 Ext 100000 Eth36 1 29 8 +Ethernet40 48,49,50,51 Port11 11 Ext 100000 Eth40 1 17 8 +Ethernet44 52,53,54,55 Port12 12 Ext 100000 Eth44 1 21 8 +Ethernet48 40,41,42,43 Port13 13 Ext 100000 Eth48 1 9 8 +Ethernet52 44,45,46,47 Port14 14 Ext 100000 Eth52 1 13 8 +Ethernet56 32,33,34,35 Port15 15 Ext 100000 Eth56 1 1 8 +Ethernet60 36,37,38,39 Port16 16 Ext 100000 Eth60 1 5 8 +Ethernet64 128,129,130,131 Port17 17 Ext 100000 Eth64 4 1 8 +Ethernet68 132,133,134,135 Port18 18 Ext 100000 Eth68 4 5 8 +Ethernet72 136,137,138,139 Port19 19 Ext 100000 Eth72 4 9 8 +Ethernet76 140,141,142,143 Port20 20 Ext 100000 Eth76 4 13 8 +Ethernet80 144,145,146,147 Port21 21 Ext 100000 Eth80 4 17 8 +Ethernet84 148,149,150,151 Port22 22 Ext 100000 Eth84 4 21 8 +Ethernet88 152,153,154,155 Port23 23 Ext 100000 Eth88 4 25 8 +Ethernet92 156,157,158,159 Port24 24 Ext 100000 Eth92 4 29 8 +Ethernet96 216,217,218,219 Port25 25 Ext 100000 Eth96 6 25 8 +Ethernet100 220,221,222,223 Port26 26 Ext 100000 Eth100 6 29 8 +Ethernet104 208,209,210,211 Port27 27 Ext 100000 Eth108 6 17 8 +Ethernet108 212,213,214,215 Port28 28 Ext 100000 Eth108 6 21 8 +Ethernet112 200,201,202,203 Port29 29 Ext 100000 Eth112 6 9 8 +Ethernet116 204,205,206,207 Port30 30 Ext 100000 Eth116 6 13 8 +Ethernet120 192,193,194,195 Port31 31 Ext 100000 Eth120 6 1 8 +Ethernet124 196,197,198,199 Port32 32 Ext 100000 Eth124 6 5 8 +Ethernet128 64,65,66,67 Port33 33 Ext 400000 Eth128 2 1 8 +Ethernet132 68,69,70,71 Port34 34 Ext 400000 Eth132 2 5 8 +Ethernet136 72,73,74,75 Port35 35 Ext 400000 Eth136 2 9 8 +Ethernet140 76,77,78,79 Port36 36 Ext 400000 Eth140 2 13 8 +Ethernet144 80,81,82,83 Port37 37 Ext 400000 Eth144 2 17 8 +Ethernet148 84,85,86,87 Port38 38 Ext 400000 Eth148 2 21 8 +Ethernet152 88,89,90,91 Port39 39 Ext 400000 Eth152 2 25 8 +Ethernet156 92,93,94,95 Port40 40 Ext 400000 Eth156 2 29 8 +Ethernet160 24,25,26,27 Port41 41 Ext 400000 Eth160 0 25 8 +Ethernet164 28,29,30,31 Port42 42 Ext 400000 Eth164 0 29 8 +Ethernet168 16,17,18,19 Port43 43 Ext 400000 Eth168 0 17 8 +Ethernet172 20,21,22,23 Port44 44 Ext 400000 Eth172 0 21 8 +Ethernet176 8,9,10,11 Port45 45 Ext 400000 Eth176 0 9 8 +Ethernet180 12,13,14,15 Port46 46 Ext 400000 Eth180 0 13 8 +Ethernet184 0,1,2,3 Port47 47 Ext 400000 Eth184 0 1 8 +Ethernet188 4,5,6,7 Port48 48 Ext 400000 Eth188 0 5 8 +Ethernet192 160,161,162,163 Port49 49 Ext 400000 Eth192 5 1 8 +Ethernet196 164,165,166,167 Port50 50 Ext 400000 Eth196 5 5 8 +Ethernet200 168,169,170,171 Port51 51 Ext 400000 Eth200 5 9 8 +Ethernet204 172,173,174,175 Port52 52 Ext 400000 Eth204 5 13 8 +Ethernet208 176,177,178,179 Port53 53 Ext 400000 Eth208 5 17 8 +Ethernet212 180,181,182,183 Port54 54 Ext 400000 Eth212 5 21 8 +Ethernet216 184,185,186,187 Port55 55 Ext 400000 Eth216 5 25 8 +Ethernet220 188,189,190,191 Port56 56 Ext 400000 Eth220 5 29 8 +Ethernet224 248,249,250,251 Port57 57 Ext 400000 Eth224 7 25 8 +Ethernet228 252,253,254,255 Port58 58 Ext 400000 Eth228 7 29 8 +Ethernet232 240,241,242,243 Port59 59 Ext 400000 Eth232 7 17 8 +Ethernet236 244,245,246,247 Port60 60 Ext 400000 Eth236 7 21 8 +Ethernet240 232,233,234,235 Port61 61 Ext 400000 Eth240 7 9 8 +Ethernet244 236,237,238,239 Port62 62 Ext 400000 Eth244 7 13 8 +Ethernet248 224,225,226,227 Port63 63 Ext 400000 Eth248 7 1 8 +Ethernet252 228,229,230,231 Port64 64 Ext 400000 Eth252 7 5 8 +Ethernet256 256,257,258,259 Port65 65 Ext 100000 Eth256 2 33 8 +Ethernet260 260,261,262,263 Port66 66 Ext 100000 Eth260 6 33 8 +Ethernet-Rec0 621 Port67 67 Rec 400000 Rcy0 0 221 8 diff --git a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/psai.profile b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/psai.profile new file mode 100644 index 00000000000..a094d074a3a --- /dev/null +++ b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/psai.profile @@ -0,0 +1 @@ +SAI_INIT_CONFIG_FILE=/usr/share/sonic/hwsku/agera2.bcm diff --git a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/qos.json.j2 b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/qos.json.j2 new file mode 100644 index 00000000000..42255ff45d9 --- /dev/null +++ b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/qos.json.j2 @@ -0,0 +1,172 @@ +{%- macro generate_dscp_to_tc_map_per_sku() -%} + "DSCP_TO_TC_MAP": { + "NH_DEFAULT_DSCP_TO_TC_MAP": { + "0" : "0", + "1" : "0", + "2" : "0", + "3" : "0", + "4" : "0", + "5" : "0", + "6" : "0", + "7" : "0", + "8" : "1", + "9" : "1", + "10": "1", + "11": "1", + "12": "1", + "13": "1", + "14": "1", + "15": "1", + "16": "2", + "17": "2", + "18": "2", + "19": "2", + "20": "2", + "21": "2", + "22": "2", + "23": "2", + "24": "3", + "25": "3", + "26": "3", + "27": "3", + "28": "3", + "29": "3", + "30": "3", + "31": "3", + "32": "4", + "33": "4", + "34": "4", + "35": "4", + "36": "4", + "37": "4", + "38": "4", + "39": "4", + "40": "5", + "41": "5", + "42": "5", + "43": "5", + "44": "5", + "45": "5", + "46": "5", + "47": "5", + "48": "6", + "49": "6", + "50": "6", + "51": "6", + "52": "6", + "53": "6", + "54": "6", + "55": "6", + "56": "7", + "57": "7", + "58": "7", + "59": "7", + "60": "7", + "61": "7", + "62": "7", + "63": "7" + } + }, +{%- endmacro -%} + +{%- macro generate_global_dscp_to_tc_map() %} +{# This is an empty macro since the global DSCP_TO_TC map is not required #} +{%- endmacro %} + +{%- macro generate_tc_to_queue_map_per_sku() -%} + "TC_TO_QUEUE_MAP": { + "NH_DEFAULT_TC_TO_QUEUE_MAP": { + "0": "0", + "1": "1", + "2": "2", + "3": "3", + "4": "4", + "5": "5", + "6": "6", + "7": "7" + } + }, +{%- endmacro -%} + +{%- macro generate_tc_to_pg_map_per_sku() -%} + "TC_TO_PRIORITY_GROUP_MAP": { + "NH_DEFAULT_TC_TO_PRI_GROUP_MAP": { + "0": "0", + "1": "1", + "2": "2", + "3": "3", + "4": "4", + "5": "5", + "6": "6", + "7": "7" + } + }, +{%- endmacro -%} + +{%- macro generate_port_qos_map(port_names_active) -%} + "PORT_QOS_MAP": { +{% for port in port_names_active.split(',') %} + "{{ port }}": { + "dscp_to_tc_map" : "NH_DEFAULT_DSCP_TO_TC_MAP", + "tc_to_queue_map" : "NH_DEFAULT_TC_TO_QUEUE_MAP", + "tc_to_pg_map" : "NH_DEFAULT_TC_TO_PRI_GROUP_MAP" + }{% if not loop.last %},{% endif %} +{% endfor %} + }, +{%- endmacro -%} + +{%- macro generate_scheduler_per_sku() -%} + "SCHEDULER": { + "scheduler.0": { + "type" : "DWRR", + "weight": "20" + }, + "scheduler.1": { + "type" : "DWRR", + "weight": "30" + }, + "scheduler.2": { + "type" : "DWRR", + "weight": "50" + }, + "scheduler.3": { + "cir": "2000000000", + "meter_type": "bytes", + "pir": "2000000000", + "type": "STRICT" + } + }, +{%- endmacro -%} + +{%- macro generate_single_queue_per_sku(port) -%} + "{{ port }}|0": { + "scheduler": "scheduler.0" + }, + "{{ port }}|1": { + "scheduler": "scheduler.0" + }, + "{{ port }}|2": { + "scheduler": "scheduler.1" + }, + "{{ port }}|3": { + "scheduler": "scheduler.2" + }, + "{{ port }}|4": { + "scheduler": "scheduler.2" + }, + "{{ port }}|5": { + "scheduler": "scheduler.2" + }, + "{{ port }}|6": { + "scheduler": "scheduler.3" + }, + "{{ port }}|7": { + "scheduler": "scheduler.3" + } +{%- endmacro -%} + +{%- macro generate_wred_profiles() %} +{# wred is disabled #} +{%- endmacro %} + +{%- include 'qos_config.j2' %} diff --git a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/sai.profile b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/sai.profile new file mode 100644 index 00000000000..f30aaeb5871 --- /dev/null +++ b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/sai.profile @@ -0,0 +1,2 @@ +SAI_INIT_CONFIG_FILE=/usr/share/sonic/hwsku/nh5010-default.bcm +SAI_NUM_ECMP_MEMBERS=128 diff --git a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/BALANCED/buffers.json.j2 b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/BALANCED/buffers.json.j2 new file mode 100644 index 00000000000..f34a844f4a8 --- /dev/null +++ b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/BALANCED/buffers.json.j2 @@ -0,0 +1,2 @@ +{%- set default_topo = 't2' %} +{%- include 'buffers_config.j2' %} diff --git a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/BALANCED/buffers_defaults_t2.j2 b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/BALANCED/buffers_defaults_t2.j2 new file mode 100644 index 00000000000..b13d888689d --- /dev/null +++ b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/BALANCED/buffers_defaults_t2.j2 @@ -0,0 +1,47 @@ +{%- set default_cable = '300m' %} + +{%- set ports2cable = { + 'torrouter_server' : '300m', + 'leafrouter_torrouter' : '300m', + 'spinerouter_leafrouter' : '300m', + 'regionalhub_spinerouter': '300m', + 'aznghub_spinerouter' : '300m' + } +-%} + +{%- macro generate_port_lists(PORT_ALL) %} + {# Generate list of ports #} + {%- for port_idx in range(0,256,8) %} + {%- if PORT_ALL.append("Ethernet%d" % (port_idx)) %}{%- endif %} + {%- endfor %} +{%- endmacro %} + +{%- macro generate_buffer_pool_and_profiles() %} + "BUFFER_POOL": { + "ingress_lossless_pool": { + "size": "56441610000", + "type": "both", + "mode": "dynamic", + "xoff": "2822080500" + } + }, + "BUFFER_PROFILE": { + "ingress_lossy_profile": { + "pool":"ingress_lossless_pool", + "size":"0", + "xon_offset": "0", + "dynamic_th":"0" + }, + "egress_lossless_profile": { + "pool":"ingress_lossless_pool", + "size":"0", + "dynamic_th":"-1" + }, + "egress_lossy_profile": { + "pool":"ingress_lossless_pool", + "size":"0", + "dynamic_th":"-4" + } + }, +{%- endmacro %} + diff --git a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/BALANCED/pg_profile_lookup.ini b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/BALANCED/pg_profile_lookup.ini new file mode 100644 index 00000000000..a417a9558d0 --- /dev/null +++ b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/BALANCED/pg_profile_lookup.ini @@ -0,0 +1,17 @@ +# PG lossless profiles. +# speed cable size xon xoff threshold xon_offset +25000 5m 18796 0 612140 0 3556 +25000 40m 18796 0 612140 0 3556 +25000 300m 18796 0 612140 0 3556 +100000 5m 18796 0 612140 0 3556 +100000 40m 18796 0 612140 0 3556 +100000 300m 18796 0 612140 0 3556 +200000 5m 18796 0 612140 0 3556 +200000 40m 18796 0 612140 0 3556 +200000 300m 18796 0 612140 0 3556 +400000 5m 18796 0 612140 0 3556 +400000 40m 18796 0 612140 0 3556 +400000 300m 18796 0 612140 0 3556 +800000 5m 18796 0 612140 0 3556 +800000 40m 18796 0 612140 0 3556 +800000 300m 18796 0 612140 0 3556 diff --git a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/BALANCED/qos.json.j2 b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/BALANCED/qos.json.j2 new file mode 100644 index 00000000000..af1c4dfb256 --- /dev/null +++ b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/BALANCED/qos.json.j2 @@ -0,0 +1,4 @@ +{%- macro generate_global_dscp_to_tc_map() %} +{# This is an empty macro since the global DSCP_TO_TC map is not required #} +{%- endmacro %} +{%- include 'qos_config.j2' %} diff --git a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/agera2.bcm b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/agera2.bcm new file mode 100644 index 00000000000..3a72ef15df2 --- /dev/null +++ b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/agera2.bcm @@ -0,0 +1,801 @@ +### PHY CONFIGURATION FILE +### Please refer to config_file_format.txt in the top level folder for configuration file format + +### PHY CONFIGURATIONS +phy_init_config_chip_id:9 = 85361 +phy_init_mode:9 = 0 +phy_init_config_ref_clk:9 = 312000000 + +### LANE CONFIGURATIONS +#---------------------------------------------------------------------------------------------------------------- +# Lane_Property : Global_Lane = PHY_ID, IF_Side, Local_Lane, Tx_Lane_Map, Rx_Lane_Map, Tx_Polarity, Rx_Polarity +#---------------------------------------------------------------------------------------------------------------- +# Line side lanes: +phy_lane_property : 288 = 9, 0, 0, 3, 3, 0, 0 +phy_lane_property : 289 = 9, 0, 1, 4, 4, 0, 1 +phy_lane_property : 290 = 9, 0, 2, 5, 5, 0, 0 +phy_lane_property : 291 = 9, 0, 3, 2, 2, 1, 1 +phy_lane_property : 292 = 9, 0, 4, 1, 1, 1, 0 +phy_lane_property : 293 = 9, 0, 5, 6, 6, 0, 1 +phy_lane_property : 294 = 9, 0, 6, 7, 7, 0, 0 +phy_lane_property : 295 = 9, 0, 7, 0, 0, 1, 1 +phy_lane_property : 296 = 9, 0, 8, D, D, 0, 0 +phy_lane_property : 297 = 9, 0, 9, A, A, 0, 1 +phy_lane_property : 298 = 9, 0, 10, B, B, 0, 0 +phy_lane_property : 299 = 9, 0, 11, C, C, 0, 1 +phy_lane_property : 300 = 9, 0, 12, F, F, 0, 0 +phy_lane_property : 301 = 9, 0, 13, 8, 8, 0, 1 +phy_lane_property : 302 = 9, 0, 14, 9, 9, 0, 0 +phy_lane_property : 303 = 9, 0, 15, E, E, 0, 1 + + +# System side lanes: +phy_lane_property : 304 = 9, 1, 4, 0, 0, 0, 0 # UNUSED +phy_lane_property : 305 = 9, 1, 5, 1, 1, 0, 0 # UNUSED +phy_lane_property : 306 = 9, 1, 6, 2, 2, 0, 0 # UNUSED +phy_lane_property : 307 = 9, 1, 7, 3, 3, 0, 0 # UNUSED +phy_lane_property : 308 = 9, 1, 0, 4, 4, 0, 0 +phy_lane_property : 309 = 9, 1, 1, 5, 5, 0, 0 +phy_lane_property : 310 = 9, 1, 2, 6, 6, 0, 0 +phy_lane_property : 311 = 9, 1, 3, 7, 7, 0, 0 +phy_lane_property : 312 = 9, 1, 8, 8, 8, 0, 0 +phy_lane_property : 313 = 9, 1, 9, 9, 9, 0, 0 +phy_lane_property : 314 = 9, 1, 10, A, A, 0, 0 +phy_lane_property : 315 = 9, 1, 11, B, B, 0, 0 +phy_lane_property : 316 = 9, 1, 12, C, C, 0, 0 # UNUSED +phy_lane_property : 317 = 9, 1, 13, D, D, 0, 0 # UNUSED +phy_lane_property : 318 = 9, 1, 14, E, E, 0, 0 # UNUSED +phy_lane_property : 319 = 9, 1, 15, F, F, 0, 0 # UNUSED + +#---------------------------------------------------------------------------------------------------------------- +### PHY CONFIGURATION FILE +### Please refer to config_file_format.txt in the top level folder for configuration file format + +### PHY CONFIGURATIONS +phy_init_config_chip_id:8 = 85361 +phy_init_mode:8 = 0 +phy_init_config_ref_clk:8 = 312000000 + +### LANE CONFIGURATIONS +#---------------------------------------------------------------------------------------------------------------- +# Lane_Property : Global_Lane = PHY_ID, IF_Side, Local_Lane, Tx_Lane_Map, Rx_Lane_Map, Tx_Polarity, Rx_Polarity +#---------------------------------------------------------------------------------------------------------------- +# Line side lanes: +phy_lane_property : 256 = 8, 0, 0, 3, 3, 0, 0 +phy_lane_property : 257 = 8, 0, 1, 4, 4, 0, 1 +phy_lane_property : 258 = 8, 0, 2, 5, 5, 0, 0 +phy_lane_property : 259 = 8, 0, 3, 2, 2, 1, 1 +phy_lane_property : 260 = 8, 0, 4, 1, 1, 1, 0 +phy_lane_property : 261 = 8, 0, 5, 6, 6, 0, 1 +phy_lane_property : 262 = 8, 0, 6, 7, 7, 0, 0 +phy_lane_property : 263 = 8, 0, 7, 0, 0, 1, 1 +phy_lane_property : 264 = 8, 0, 8, D, D, 0, 0 +phy_lane_property : 265 = 8, 0, 9, A, A, 0, 1 +phy_lane_property : 266 = 8, 0, 10, B, B, 0, 0 +phy_lane_property : 267 = 8, 0, 11, C, C, 0, 1 +phy_lane_property : 268 = 8, 0, 12, F, F, 0, 0 +phy_lane_property : 269 = 8, 0, 13, 8, 8, 0, 1 +phy_lane_property : 270 = 8, 0, 14, 9, 9, 0, 0 +phy_lane_property : 271 = 8, 0, 15, E, E, 0, 1 + + +# System side lanes: +phy_lane_property : 272 = 8, 1, 4, 0, 0, 0, 0 # UNUSED +phy_lane_property : 273 = 8, 1, 5, 1, 1, 0, 0 # UNUSED +phy_lane_property : 274 = 8, 1, 6, 2, 2, 0, 0 # UNUSED +phy_lane_property : 275 = 8, 1, 7, 3, 3, 0, 0 # UNUSED +phy_lane_property : 276 = 8, 1, 0, 4, 4, 0, 0 +phy_lane_property : 277 = 8, 1, 1, 5, 5, 0, 0 +phy_lane_property : 278 = 8, 1, 2, 6, 6, 0, 0 +phy_lane_property : 279 = 8, 1, 3, 7, 7, 0, 0 +phy_lane_property : 280 = 8, 1, 8, 8, 8, 0, 0 +phy_lane_property : 281 = 8, 1, 9, 9, 9, 0, 0 +phy_lane_property : 282 = 8, 1, 10, A, A, 0, 0 +phy_lane_property : 283 = 8, 1, 11, B, B, 0, 0 +phy_lane_property : 284 = 8, 1, 12, C, C, 0, 0 # UNUSED +phy_lane_property : 285 = 8, 1, 13, D, D, 0, 0 # UNUSED +phy_lane_property : 286 = 8, 1, 14, E, E, 0, 0 # UNUSED +phy_lane_property : 287 = 8, 1, 15, F, F, 0, 0 # UNUSED + +#---------------------------------------------------------------------------------------------------------------- +### PHY CONFIGURATION FILE +### Please refer to config_file_format.txt in the top level folder for configuration file format + +### PHY CONFIGURATIONS +phy_init_config_chip_id:10 = 85361 +phy_init_mode:10 = 0 +phy_init_config_ref_clk:10 = 312000000 + +### LANE CONFIGURATIONS +#---------------------------------------------------------------------------------------------------------------- +# Lane_Property : Global_Lane = PHY_ID, IF_Side, Local_Lane, Tx_Lane_Map, Rx_Lane_Map, Tx_Polarity, Rx_Polarity +#---------------------------------------------------------------------------------------------------------------- +# Line side lanes: +phy_lane_property : 320 = 10, 0, 0, 3, 3, 0, 0 +phy_lane_property : 321 = 10, 0, 1, 4, 4, 0, 1 +phy_lane_property : 322 = 10, 0, 2, 5, 5, 0, 0 +phy_lane_property : 323 = 10, 0, 3, 2, 2, 1, 1 +phy_lane_property : 324 = 10, 0, 4, 1, 1, 1, 0 +phy_lane_property : 325 = 10, 0, 5, 6, 6, 0, 1 +phy_lane_property : 326 = 10, 0, 6, 7, 7, 0, 0 +phy_lane_property : 327 = 10, 0, 7, 0, 0, 1, 1 +phy_lane_property : 328 = 10, 0, 8, D, D, 0, 0 +phy_lane_property : 329 = 10, 0, 9, A, A, 0, 1 +phy_lane_property : 330 = 10, 0, 10, B, B, 0, 0 +phy_lane_property : 331 = 10, 0, 11, C, C, 0, 1 +phy_lane_property : 332 = 10, 0, 12, F, F, 0, 0 +phy_lane_property : 333 = 10, 0, 13, 8, 8, 0, 1 +phy_lane_property : 334 = 10, 0, 14, 9, 9, 0, 0 +phy_lane_property : 335 = 10, 0, 15, E, E, 0, 1 + + +# System side lanes: +phy_lane_property : 336 = 10, 1, 4, 0, 0, 0, 0 # UNUSED +phy_lane_property : 337 = 10, 1, 5, 1, 1, 0, 0 # UNUSED +phy_lane_property : 338 = 10, 1, 6, 2, 2, 0, 0 # UNUSED +phy_lane_property : 339 = 10, 1, 7, 3, 3, 0, 0 # UNUSED +phy_lane_property : 340 = 10, 1, 0, 4, 4, 0, 0 +phy_lane_property : 341 = 10, 1, 1, 5, 5, 0, 0 +phy_lane_property : 342 = 10, 1, 2, 6, 6, 0, 0 +phy_lane_property : 343 = 10, 1, 3, 7, 7, 0, 0 +phy_lane_property : 344 = 10, 1, 8, 8, 8, 0, 0 +phy_lane_property : 345 = 10, 1, 9, 9, 9, 0, 0 +phy_lane_property : 346 = 10, 1, 10, A, A, 0, 0 +phy_lane_property : 347 = 10, 1, 11, B, B, 0, 0 +phy_lane_property : 348 = 10, 1, 12, C, C, 0, 0 # UNUSED +phy_lane_property : 349 = 10, 1, 13, D, D, 0, 0 # UNUSED +phy_lane_property : 350 = 10, 1, 14, E, E, 0, 0 # UNUSED +phy_lane_property : 351 = 10, 1, 15, F, F, 0, 0 # UNUSED + +#---------------------------------------------------------------------------------------------------------------- +### PHY CONFIGURATION FILE +### Please refer to config_file_format.txt in the top level folder for configuration file format + +### PHY CONFIGURATIONS +phy_init_config_chip_id:11 = 85361 +phy_init_mode:11 = 0 +phy_init_config_ref_clk:11 = 312000000 + +### LANE CONFIGURATIONS +#---------------------------------------------------------------------------------------------------------------- +# Lane_Property : Global_Lane = PHY_ID, IF_Side, Local_Lane, Tx_Lane_Map, Rx_Lane_Map, Tx_Polarity, Rx_Polarity +#---------------------------------------------------------------------------------------------------------------- +# Line side lanes: +phy_lane_property : 352 = 11, 0, 0, 3, 3, 0, 0 +phy_lane_property : 353 = 11, 0, 1, 4, 4, 0, 1 +phy_lane_property : 354 = 11, 0, 2, 5, 5, 0, 0 +phy_lane_property : 355 = 11, 0, 3, 2, 2, 1, 1 +phy_lane_property : 356 = 11, 0, 4, 1, 1, 1, 0 +phy_lane_property : 357 = 11, 0, 5, 6, 6, 0, 1 +phy_lane_property : 358 = 11, 0, 6, 7, 7, 0, 0 +phy_lane_property : 359 = 11, 0, 7, 0, 0, 1, 1 +phy_lane_property : 360 = 11, 0, 8, D, D, 0, 0 +phy_lane_property : 361 = 11, 0, 9, A, A, 0, 1 +phy_lane_property : 362 = 11, 0, 10, B, B, 0, 0 +phy_lane_property : 363 = 11, 0, 11, C, C, 0, 1 +phy_lane_property : 364 = 11, 0, 12, F, F, 0, 0 +phy_lane_property : 365 = 11, 0, 13, 8, 8, 0, 1 +phy_lane_property : 366 = 11, 0, 14, 9, 9, 0, 0 +phy_lane_property : 367 = 11, 0, 15, E, E, 0, 1 + + +# System side lanes: +phy_lane_property : 368 = 11, 1, 4, 0, 0, 0, 0 # UNUSED +phy_lane_property : 369 = 11, 1, 5, 1, 1, 0, 0 # UNUSED +phy_lane_property : 370 = 11, 1, 6, 2, 2, 0, 0 # UNUSED +phy_lane_property : 371 = 11, 1, 7, 3, 3, 0, 0 # UNUSED +phy_lane_property : 372 = 11, 1, 0, 4, 4, 0, 0 +phy_lane_property : 373 = 11, 1, 1, 5, 5, 0, 0 +phy_lane_property : 374 = 11, 1, 2, 6, 6, 0, 0 +phy_lane_property : 375 = 11, 1, 3, 7, 7, 0, 0 +phy_lane_property : 376 = 11, 1, 8, 8, 8, 0, 0 +phy_lane_property : 377 = 11, 1, 9, 9, 9, 0, 0 +phy_lane_property : 378 = 11, 1, 10, A, A, 0, 0 +phy_lane_property : 379 = 11, 1, 11, B, B, 0, 0 +phy_lane_property : 380 = 11, 1, 12, C, C, 0, 0 # UNUSED +phy_lane_property : 381 = 11, 1, 13, D, D, 0, 0 # UNUSED +phy_lane_property : 382 = 11, 1, 14, E, E, 0, 0 # UNUSED +phy_lane_property : 383 = 11, 1, 15, F, F, 0, 0 # UNUSED + +#---------------------------------------------------------------------------------------------------------------- +### PHY CONFIGURATION FILE +### Please refer to config_file_format.txt in the top level folder for configuration file format + +### PHY CONFIGURATIONS +phy_init_config_chip_id:12 = 85361 +phy_init_mode:12 = 0 +phy_init_config_ref_clk:12 = 312000000 + +### LANE CONFIGURATIONS +#---------------------------------------------------------------------------------------------------------------- +# Lane_Property : Global_Lane = PHY_ID, IF_Side, Local_Lane, Tx_Lane_Map, Rx_Lane_Map, Tx_Polarity, Rx_Polarity +#---------------------------------------------------------------------------------------------------------------- +# Line side lanes: +phy_lane_property : 384 = 12, 0, 0, 3, 3, 0, 0 +phy_lane_property : 385 = 12, 0, 1, 4, 4, 0, 1 +phy_lane_property : 386 = 12, 0, 2, 5, 5, 0, 0 +phy_lane_property : 387 = 12, 0, 3, 2, 2, 1, 1 +phy_lane_property : 388 = 12, 0, 4, 1, 1, 1, 0 +phy_lane_property : 389 = 12, 0, 5, 6, 6, 0, 1 +phy_lane_property : 390 = 12, 0, 6, 7, 7, 0, 0 +phy_lane_property : 391 = 12, 0, 7, 0, 0, 1, 1 +phy_lane_property : 392 = 12, 0, 8, D, D, 0, 0 +phy_lane_property : 393 = 12, 0, 9, A, A, 0, 1 +phy_lane_property : 394 = 12, 0, 10, B, B, 0, 0 +phy_lane_property : 395 = 12, 0, 11, C, C, 0, 1 +phy_lane_property : 396 = 12, 0, 12, F, F, 0, 0 +phy_lane_property : 397 = 12, 0, 13, 8, 8, 0, 1 +phy_lane_property : 398 = 12, 0, 14, 9, 9, 0, 0 +phy_lane_property : 399 = 12, 0, 15, E, E, 0, 1 + + +# System side lanes: +phy_lane_property : 400 = 12, 1, 4, 0, 0, 0, 0 # UNUSED +phy_lane_property : 401 = 12, 1, 5, 1, 1, 0, 0 # UNUSED +phy_lane_property : 402 = 12, 1, 6, 2, 2, 0, 0 # UNUSED +phy_lane_property : 403 = 12, 1, 7, 3, 3, 0, 0 # UNUSED +phy_lane_property : 404 = 12, 1, 0, 4, 4, 0, 0 +phy_lane_property : 405 = 12, 1, 1, 5, 5, 0, 0 +phy_lane_property : 406 = 12, 1, 2, 6, 6, 0, 0 +phy_lane_property : 407 = 12, 1, 3, 7, 7, 0, 0 +phy_lane_property : 408 = 12, 1, 8, 8, 8, 0, 0 +phy_lane_property : 409 = 12, 1, 9, 9, 9, 0, 0 +phy_lane_property : 410 = 12, 1, 10, A, A, 0, 0 +phy_lane_property : 411 = 12, 1, 11, B, B, 0, 0 +phy_lane_property : 412 = 12, 1, 12, C, C, 0, 0 # UNUSED +phy_lane_property : 413 = 12, 1, 13, D, D, 0, 0 # UNUSED +phy_lane_property : 414 = 12, 1, 14, E, E, 0, 0 # UNUSED +phy_lane_property : 415 = 12, 1, 15, F, F, 0, 0 # UNUSED + +#---------------------------------------------------------------------------------------------------------------- +### PHY CONFIGURATION FILE +### Please refer to config_file_format.txt in the top level folder for configuration file format + +### PHY CONFIGURATIONS +phy_init_config_chip_id:13 = 85361 +phy_init_mode:13 = 0 +phy_init_config_ref_clk:13 = 312000000 + +### LANE CONFIGURATIONS +#---------------------------------------------------------------------------------------------------------------- +# Lane_Property : Global_Lane = PHY_ID, IF_Side, Local_Lane, Tx_Lane_Map, Rx_Lane_Map, Tx_Polarity, Rx_Polarity +#---------------------------------------------------------------------------------------------------------------- +# Line side lanes: +phy_lane_property : 416 = 13, 0, 0, 3, 3, 0, 0 +phy_lane_property : 417 = 13, 0, 1, 4, 4, 0, 1 +phy_lane_property : 418 = 13, 0, 2, 5, 5, 0, 0 +phy_lane_property : 419 = 13, 0, 3, 2, 2, 1, 1 +phy_lane_property : 420 = 13, 0, 4, 1, 1, 1, 0 +phy_lane_property : 421 = 13, 0, 5, 6, 6, 0, 1 +phy_lane_property : 422 = 13, 0, 6, 7, 7, 0, 0 +phy_lane_property : 423 = 13, 0, 7, 0, 0, 1, 1 +phy_lane_property : 424 = 13, 0, 8, D, D, 0, 0 +phy_lane_property : 425 = 13, 0, 9, A, A, 0, 1 +phy_lane_property : 426 = 13, 0, 10, B, B, 0, 0 +phy_lane_property : 427 = 13, 0, 11, C, C, 0, 1 +phy_lane_property : 428 = 13, 0, 12, F, F, 0, 0 +phy_lane_property : 429 = 13, 0, 13, 8, 8, 0, 1 +phy_lane_property : 430 = 13, 0, 14, 9, 9, 0, 0 +phy_lane_property : 431 = 13, 0, 15, E, E, 0, 1 + + +# System side lanes: +phy_lane_property : 432 = 13, 1, 4, 0, 0, 0, 0 # UNUSED +phy_lane_property : 433 = 13, 1, 5, 1, 1, 0, 0 # UNUSED +phy_lane_property : 434 = 13, 1, 6, 2, 2, 0, 0 # UNUSED +phy_lane_property : 435 = 13, 1, 7, 3, 3, 0, 0 # UNUSED +phy_lane_property : 436 = 13, 1, 0, 4, 4, 0, 0 +phy_lane_property : 437 = 13, 1, 1, 5, 5, 0, 0 +phy_lane_property : 438 = 13, 1, 2, 6, 6, 0, 0 +phy_lane_property : 439 = 13, 1, 3, 7, 7, 0, 0 +phy_lane_property : 440 = 13, 1, 8, 8, 8, 0, 0 +phy_lane_property : 441 = 13, 1, 9, 9, 9, 0, 0 +phy_lane_property : 442 = 13, 1, 10, A, A, 0, 0 +phy_lane_property : 443 = 13, 1, 11, B, B, 0, 0 +phy_lane_property : 444 = 13, 1, 12, C, C, 0, 0 # UNUSED +phy_lane_property : 445 = 13, 1, 13, D, D, 0, 0 # UNUSED +phy_lane_property : 446 = 13, 1, 14, E, E, 0, 0 # UNUSED +phy_lane_property : 447 = 13, 1, 15, F, F, 0, 0 # UNUSED + +#---------------------------------------------------------------------------------------------------------------- +### PHY CONFIGURATION FILE +### Please refer to config_file_format.txt in the top level folder for configuration file format + +### PHY CONFIGURATIONS +phy_init_config_chip_id:14 = 85361 +phy_init_mode:14 = 0 +phy_init_config_ref_clk:14 = 312000000 + +### LANE CONFIGURATIONS +#---------------------------------------------------------------------------------------------------------------- +# Lane_Property : Global_Lane = PHY_ID, IF_Side, Local_Lane, Tx_Lane_Map, Rx_Lane_Map, Tx_Polarity, Rx_Polarity +#---------------------------------------------------------------------------------------------------------------- +# Line side lanes: +phy_lane_property : 448 = 14, 0, 0, 3, 3, 0, 0 +phy_lane_property : 449 = 14, 0, 1, 4, 4, 0, 1 +phy_lane_property : 450 = 14, 0, 2, 5, 5, 0, 0 +phy_lane_property : 451 = 14, 0, 3, 2, 2, 1, 1 +phy_lane_property : 452 = 14, 0, 4, 1, 1, 1, 0 +phy_lane_property : 453 = 14, 0, 5, 6, 6, 0, 1 +phy_lane_property : 454 = 14, 0, 6, 7, 7, 0, 0 +phy_lane_property : 455 = 14, 0, 7, 0, 0, 1, 1 +phy_lane_property : 456 = 14, 0, 8, D, D, 0, 0 +phy_lane_property : 457 = 14, 0, 9, A, A, 0, 1 +phy_lane_property : 458 = 14, 0, 10, B, B, 0, 0 +phy_lane_property : 459 = 14, 0, 11, C, C, 0, 1 +phy_lane_property : 460 = 14, 0, 12, F, F, 0, 0 +phy_lane_property : 461 = 14, 0, 13, 8, 8, 0, 1 +phy_lane_property : 462 = 14, 0, 14, 9, 9, 0, 0 +phy_lane_property : 463 = 14, 0, 15, E, E, 0, 1 + + +# System side lanes: +phy_lane_property : 464 = 14, 1, 4, 0, 0, 0, 0 # UNUSED +phy_lane_property : 465 = 14, 1, 5, 1, 1, 0, 0 # UNUSED +phy_lane_property : 466 = 14, 1, 6, 2, 2, 0, 0 # UNUSED +phy_lane_property : 467 = 14, 1, 7, 3, 3, 0, 0 # UNUSED +phy_lane_property : 468 = 14, 1, 0, 4, 4, 0, 0 +phy_lane_property : 469 = 14, 1, 1, 5, 5, 0, 0 +phy_lane_property : 470 = 14, 1, 2, 6, 6, 0, 0 +phy_lane_property : 471 = 14, 1, 3, 7, 7, 0, 0 +phy_lane_property : 472 = 14, 1, 8, 8, 8, 0, 0 +phy_lane_property : 473 = 14, 1, 9, 9, 9, 0, 0 +phy_lane_property : 474 = 14, 1, 10, A, A, 0, 0 +phy_lane_property : 475 = 14, 1, 11, B, B, 0, 0 +phy_lane_property : 476 = 14, 1, 12, C, C, 0, 0 # UNUSED +phy_lane_property : 477 = 14, 1, 13, D, D, 0, 0 # UNUSED +phy_lane_property : 478 = 14, 1, 14, E, E, 0, 0 # UNUSED +phy_lane_property : 479 = 14, 1, 15, F, F, 0, 0 # UNUSED + +#---------------------------------------------------------------------------------------------------------------- +### PHY CONFIGURATION FILE +### Please refer to config_file_format.txt in the top level folder for configuration file format + +### PHY CONFIGURATIONS +phy_init_config_chip_id:15 = 85361 +phy_init_mode:15 = 0 +phy_init_config_ref_clk:15 = 312000000 + +### LANE CONFIGURATIONS +#---------------------------------------------------------------------------------------------------------------- +# Lane_Property : Global_Lane = PHY_ID, IF_Side, Local_Lane, Tx_Lane_Map, Rx_Lane_Map, Tx_Polarity, Rx_Polarity +#---------------------------------------------------------------------------------------------------------------- +# Line side lanes: +phy_lane_property : 480 = 15, 0, 0, 3, 3, 0, 0 +phy_lane_property : 481 = 15, 0, 1, 4, 4, 0, 1 +phy_lane_property : 482 = 15, 0, 2, 5, 5, 0, 0 +phy_lane_property : 483 = 15, 0, 3, 2, 2, 1, 1 +phy_lane_property : 484 = 15, 0, 4, 1, 1, 1, 0 +phy_lane_property : 485 = 15, 0, 5, 6, 6, 0, 1 +phy_lane_property : 486 = 15, 0, 6, 7, 7, 0, 0 +phy_lane_property : 487 = 15, 0, 7, 0, 0, 1, 1 +phy_lane_property : 488 = 15, 0, 8, D, D, 0, 0 +phy_lane_property : 489 = 15, 0, 9, A, A, 0, 1 +phy_lane_property : 490 = 15, 0, 10, B, B, 0, 0 +phy_lane_property : 491 = 15, 0, 11, C, C, 0, 1 +phy_lane_property : 492 = 15, 0, 12, F, F, 0, 0 +phy_lane_property : 493 = 15, 0, 13, 8, 8, 0, 1 +phy_lane_property : 494 = 15, 0, 14, 9, 9, 0, 0 +phy_lane_property : 495 = 15, 0, 15, E, E, 0, 1 + + +# System side lanes: +phy_lane_property : 496 = 15, 1, 4, 0, 0, 0, 0 # UNUSED +phy_lane_property : 497 = 15, 1, 5, 1, 1, 0, 0 # UNUSED +phy_lane_property : 498 = 15, 1, 6, 2, 2, 0, 0 # UNUSED +phy_lane_property : 499 = 15, 1, 7, 3, 3, 0, 0 # UNUSED +phy_lane_property : 500 = 15, 1, 0, 4, 4, 0, 0 +phy_lane_property : 501 = 15, 1, 1, 5, 5, 0, 0 +phy_lane_property : 502 = 15, 1, 2, 6, 6, 0, 0 +phy_lane_property : 503 = 15, 1, 3, 7, 7, 0, 0 +phy_lane_property : 504 = 15, 1, 8, 8, 8, 0, 0 +phy_lane_property : 505 = 15, 1, 9, 9, 9, 0, 0 +phy_lane_property : 506 = 15, 1, 10, A, A, 0, 0 +phy_lane_property : 507 = 15, 1, 11, B, B, 0, 0 +phy_lane_property : 508 = 15, 1, 12, C, C, 0, 0 # UNUSED +phy_lane_property : 509 = 15, 1, 13, D, D, 0, 0 # UNUSED +phy_lane_property : 510 = 15, 1, 14, E, E, 0, 0 # UNUSED +phy_lane_property : 511 = 15, 1, 15, F, F, 0, 0 # UNUSED + +#---------------------------------------------------------------------------------------------------------------- +### PHY CONFIGURATION FILE +### Please refer to config_file_format.txt in the top level folder for configuration file format + +### PHY CONFIGURATIONS +phy_init_config_chip_id:0 = 85361 +phy_init_mode:0 = 0 +phy_init_config_ref_clk:0 = 312000000 + +### LANE CONFIGURATIONS +#---------------------------------------------------------------------------------------------------------------- +# Lane_Property : Global_Lane = PHY_ID, IF_Side, Local_Lane, Tx_Lane_Map, Rx_Lane_Map, Tx_Polarity, Rx_Polarity +#---------------------------------------------------------------------------------------------------------------- +# Line side lanes: +phy_lane_property : 0 = 0, 0, 0, 3, 3, 0, 0 +phy_lane_property : 1 = 0, 0, 1, 4, 4, 0, 1 +phy_lane_property : 2 = 0, 0, 2, 5, 5, 0, 0 +phy_lane_property : 3 = 0, 0, 3, 2, 2, 1, 1 +phy_lane_property : 4 = 0, 0, 4, 1, 1, 1, 0 +phy_lane_property : 5 = 0, 0, 5, 6, 6, 0, 1 +phy_lane_property : 6 = 0, 0, 6, 7, 7, 0, 0 +phy_lane_property : 7 = 0, 0, 7, 0, 0, 1, 1 +phy_lane_property : 8 = 0, 0, 8, D, D, 0, 0 +phy_lane_property : 9 = 0, 0, 9, A, A, 0, 1 +phy_lane_property : 10 = 0, 0, 10, B, B, 0, 0 +phy_lane_property : 11 = 0, 0, 11, C, C, 0, 1 +phy_lane_property : 12 = 0, 0, 12, F, F, 0, 0 +phy_lane_property : 13 = 0, 0, 13, 8, 8, 0, 1 +phy_lane_property : 14 = 0, 0, 14, 9, 9, 0, 0 +phy_lane_property : 15 = 0, 0, 15, E, E, 0, 1 + + +# System side lanes: +phy_lane_property : 16 = 0, 1, 4, 0, 0, 0, 0 # UNUSED +phy_lane_property : 17 = 0, 1, 5, 1, 1, 0, 0 # UNUSED +phy_lane_property : 18 = 0, 1, 6, 2, 2, 0, 0 # UNUSED +phy_lane_property : 19 = 0, 1, 7, 3, 3, 0, 0 # UNUSED +phy_lane_property : 20 = 0, 1, 0, 4, 4, 0, 0 +phy_lane_property : 21 = 0, 1, 1, 5, 5, 0, 0 +phy_lane_property : 22 = 0, 1, 2, 6, 6, 0, 0 +phy_lane_property : 23 = 0, 1, 3, 7, 7, 0, 0 +phy_lane_property : 24 = 0, 1, 8, 8, 8, 0, 0 +phy_lane_property : 25 = 0, 1, 9, 9, 9, 0, 0 +phy_lane_property : 26 = 0, 1, 10, A, A, 0, 0 +phy_lane_property : 27 = 0, 1, 11, B, B, 0, 0 +phy_lane_property : 28 = 0, 1, 12, C, C, 0, 0 # UNUSED +phy_lane_property : 29 = 0, 1, 13, D, D, 0, 0 # UNUSED +phy_lane_property : 30 = 0, 1, 14, E, E, 0, 0 # UNUSED +phy_lane_property : 31 = 0, 1, 15, F, F, 0, 0 # UNUSED + +#---------------------------------------------------------------------------------------------------------------- +### PHY CONFIGURATION FILE +### Please refer to config_file_format.txt in the top level folder for configuration file format + +### PHY CONFIGURATIONS +phy_init_config_chip_id:1 = 85361 +phy_init_mode:1 = 0 +phy_init_config_ref_clk:1 = 312000000 + +### LANE CONFIGURATIONS +#---------------------------------------------------------------------------------------------------------------- +# Lane_Property : Global_Lane = PHY_ID, IF_Side, Local_Lane, Tx_Lane_Map, Rx_Lane_Map, Tx_Polarity, Rx_Polarity +#---------------------------------------------------------------------------------------------------------------- +# Line side lanes: +phy_lane_property : 32 = 1, 0, 0, 3, 3, 0, 0 +phy_lane_property : 33 = 1, 0, 1, 4, 4, 0, 1 +phy_lane_property : 34 = 1, 0, 2, 5, 5, 0, 0 +phy_lane_property : 35 = 1, 0, 3, 2, 2, 1, 1 +phy_lane_property : 36 = 1, 0, 4, 1, 1, 1, 0 +phy_lane_property : 37 = 1, 0, 5, 6, 6, 0, 1 +phy_lane_property : 38 = 1, 0, 6, 7, 7, 0, 0 +phy_lane_property : 39 = 1, 0, 7, 0, 0, 1, 1 +phy_lane_property : 40 = 1, 0, 8, D, D, 0, 0 +phy_lane_property : 41 = 1, 0, 9, A, A, 0, 1 +phy_lane_property : 42 = 1, 0, 10, B, B, 0, 0 +phy_lane_property : 43 = 1, 0, 11, C, C, 0, 1 +phy_lane_property : 44 = 1, 0, 12, F, F, 0, 0 +phy_lane_property : 45 = 1, 0, 13, 8, 8, 0, 1 +phy_lane_property : 46 = 1, 0, 14, 9, 9, 0, 0 +phy_lane_property : 47 = 1, 0, 15, E, E, 0, 1 + + +# System side lanes: +phy_lane_property : 48 = 1, 1, 4, 0, 0, 0, 0 # UNUSED +phy_lane_property : 49 = 1, 1, 5, 1, 1, 0, 0 # UNUSED +phy_lane_property : 50 = 1, 1, 6, 2, 2, 0, 0 # UNUSED +phy_lane_property : 51 = 1, 1, 7, 3, 3, 0, 0 # UNUSED +phy_lane_property : 52 = 1, 1, 0, 4, 4, 0, 0 +phy_lane_property : 53 = 1, 1, 1, 5, 5, 0, 0 +phy_lane_property : 54 = 1, 1, 2, 6, 6, 0, 0 +phy_lane_property : 55 = 1, 1, 3, 7, 7, 0, 0 +phy_lane_property : 56 = 1, 1, 8, 8, 8, 0, 0 +phy_lane_property : 57 = 1, 1, 9, 9, 9, 0, 0 +phy_lane_property : 58 = 1, 1, 10, A, A, 0, 0 +phy_lane_property : 59 = 1, 1, 11, B, B, 0, 0 +phy_lane_property : 60 = 1, 1, 12, C, C, 0, 0 # UNUSED +phy_lane_property : 61 = 1, 1, 13, D, D, 0, 0 # UNUSED +phy_lane_property : 62 = 1, 1, 14, E, E, 0, 0 # UNUSED +phy_lane_property : 63 = 1, 1, 15, F, F, 0, 0 # UNUSED + +#---------------------------------------------------------------------------------------------------------------- +### PHY CONFIGURATION FILE +### Please refer to config_file_format.txt in the top level folder for configuration file format + +### PHY CONFIGURATIONS +phy_init_config_chip_id:2 = 85361 +phy_init_mode:2 = 0 +phy_init_config_ref_clk:2 = 312000000 + +### LANE CONFIGURATIONS +#---------------------------------------------------------------------------------------------------------------- +# Lane_Property : Global_Lane = PHY_ID, IF_Side, Local_Lane, Tx_Lane_Map, Rx_Lane_Map, Tx_Polarity, Rx_Polarity +#---------------------------------------------------------------------------------------------------------------- +# Line side lanes: +phy_lane_property : 64 = 2, 0, 0, 3, 3, 0, 0 +phy_lane_property : 65 = 2, 0, 1, 4, 4, 0, 1 +phy_lane_property : 66 = 2, 0, 2, 5, 5, 0, 0 +phy_lane_property : 67 = 2, 0, 3, 2, 2, 1, 1 +phy_lane_property : 68 = 2, 0, 4, 1, 1, 1, 0 +phy_lane_property : 69 = 2, 0, 5, 6, 6, 0, 1 +phy_lane_property : 70 = 2, 0, 6, 7, 7, 0, 0 +phy_lane_property : 71 = 2, 0, 7, 0, 0, 1, 1 +phy_lane_property : 72 = 2, 0, 8, D, D, 0, 0 +phy_lane_property : 73 = 2, 0, 9, A, A, 0, 1 +phy_lane_property : 74 = 2, 0, 10, B, B, 0, 0 +phy_lane_property : 75 = 2, 0, 11, C, C, 0, 1 +phy_lane_property : 76 = 2, 0, 12, F, F, 0, 0 +phy_lane_property : 77 = 2, 0, 13, 8, 8, 0, 1 +phy_lane_property : 78 = 2, 0, 14, 9, 9, 0, 0 +phy_lane_property : 79 = 2, 0, 15, E, E, 0, 1 + + +# System side lanes: +phy_lane_property : 80 = 2, 1, 4, 0, 0, 0, 0 # UNUSED +phy_lane_property : 81 = 2, 1, 5, 1, 1, 0, 0 # UNUSED +phy_lane_property : 82 = 2, 1, 6, 2, 2, 0, 0 # UNUSED +phy_lane_property : 83 = 2, 1, 7, 3, 3, 0, 0 # UNUSED +phy_lane_property : 84 = 2, 1, 0, 4, 4, 0, 0 +phy_lane_property : 85 = 2, 1, 1, 5, 5, 0, 0 +phy_lane_property : 86 = 2, 1, 2, 6, 6, 0, 0 +phy_lane_property : 87 = 2, 1, 3, 7, 7, 0, 0 +phy_lane_property : 88 = 2, 1, 8, 8, 8, 0, 0 +phy_lane_property : 89 = 2, 1, 9, 9, 9, 0, 0 +phy_lane_property : 90 = 2, 1, 10, A, A, 0, 0 +phy_lane_property : 91 = 2, 1, 11, B, B, 0, 0 +phy_lane_property : 92 = 2, 1, 12, C, C, 0, 0 # UNUSED +phy_lane_property : 93 = 2, 1, 13, D, D, 0, 0 # UNUSED +phy_lane_property : 94 = 2, 1, 14, E, E, 0, 0 # UNUSED +phy_lane_property : 95 = 2, 1, 15, F, F, 0, 0 # UNUSED + +#---------------------------------------------------------------------------------------------------------------- +### PHY CONFIGURATION FILE +### Please refer to config_file_format.txt in the top level folder for configuration file format + +### PHY CONFIGURATIONS +phy_init_config_chip_id:3 = 85361 +phy_init_mode:3 = 0 +phy_init_config_ref_clk:3 = 312000000 + +### LANE CONFIGURATIONS +#---------------------------------------------------------------------------------------------------------------- +# Lane_Property : Global_Lane = PHY_ID, IF_Side, Local_Lane, Tx_Lane_Map, Rx_Lane_Map, Tx_Polarity, Rx_Polarity +#---------------------------------------------------------------------------------------------------------------- +# Line side lanes: +phy_lane_property : 96 = 3, 0, 0, 3, 3, 0, 0 +phy_lane_property : 97 = 3, 0, 1, 4, 4, 0, 1 +phy_lane_property : 98 = 3, 0, 2, 5, 5, 0, 0 +phy_lane_property : 99 = 3, 0, 3, 2, 2, 1, 1 +phy_lane_property : 100 = 3, 0, 4, 1, 1, 1, 0 +phy_lane_property : 101 = 3, 0, 5, 6, 6, 0, 1 +phy_lane_property : 102 = 3, 0, 6, 7, 7, 0, 0 +phy_lane_property : 103 = 3, 0, 7, 0, 0, 1, 1 +phy_lane_property : 104 = 3, 0, 8, D, D, 0, 0 +phy_lane_property : 105 = 3, 0, 9, A, A, 0, 1 +phy_lane_property : 106 = 3, 0, 10, B, B, 0, 0 +phy_lane_property : 107 = 3, 0, 11, C, C, 0, 1 +phy_lane_property : 108 = 3, 0, 12, F, F, 0, 0 +phy_lane_property : 109 = 3, 0, 13, 8, 8, 0, 1 +phy_lane_property : 110 = 3, 0, 14, 9, 9, 0, 0 +phy_lane_property : 111 = 3, 0, 15, E, E, 0, 1 + + +# System side lanes: +phy_lane_property : 112 = 3, 1, 4, 0, 0, 0, 0 # UNUSED +phy_lane_property : 113 = 3, 1, 5, 1, 1, 0, 0 # UNUSED +phy_lane_property : 114 = 3, 1, 6, 2, 2, 0, 0 # UNUSED +phy_lane_property : 115 = 3, 1, 7, 3, 3, 0, 0 # UNUSED +phy_lane_property : 116 = 3, 1, 0, 4, 4, 0, 0 +phy_lane_property : 117 = 3, 1, 1, 5, 5, 0, 0 +phy_lane_property : 118 = 3, 1, 2, 6, 6, 0, 0 +phy_lane_property : 119 = 3, 1, 3, 7, 7, 0, 0 +phy_lane_property : 120 = 3, 1, 8, 8, 8, 0, 0 +phy_lane_property : 121 = 3, 1, 9, 9, 9, 0, 0 +phy_lane_property : 122 = 3, 1, 10, A, A, 0, 0 +phy_lane_property : 123 = 3, 1, 11, B, B, 0, 0 +phy_lane_property : 124 = 3, 1, 12, C, C, 0, 0 # UNUSED +phy_lane_property : 125 = 3, 1, 13, D, D, 0, 0 # UNUSED +phy_lane_property : 126 = 3, 1, 14, E, E, 0, 0 # UNUSED +phy_lane_property : 127 = 3, 1, 15, F, F, 0, 0 # UNUSED + +#---------------------------------------------------------------------------------------------------------------- +### PHY CONFIGURATION FILE +### Please refer to config_file_format.txt in the top level folder for configuration file format + +### PHY CONFIGURATIONS +phy_init_config_chip_id:4 = 85361 +phy_init_mode:4 = 0 +phy_init_config_ref_clk:4 = 312000000 + +### LANE CONFIGURATIONS +#---------------------------------------------------------------------------------------------------------------- +# Lane_Property : Global_Lane = PHY_ID, IF_Side, Local_Lane, Tx_Lane_Map, Rx_Lane_Map, Tx_Polarity, Rx_Polarity +#---------------------------------------------------------------------------------------------------------------- +# Line side lanes: +phy_lane_property : 128 = 4, 0, 0, 3, 3, 0, 0 +phy_lane_property : 129 = 4, 0, 1, 4, 4, 0, 1 +phy_lane_property : 130 = 4, 0, 2, 5, 5, 0, 0 +phy_lane_property : 131 = 4, 0, 3, 2, 2, 1, 1 +phy_lane_property : 132 = 4, 0, 4, 1, 1, 1, 0 +phy_lane_property : 133 = 4, 0, 5, 6, 6, 0, 1 +phy_lane_property : 134 = 4, 0, 6, 7, 7, 0, 0 +phy_lane_property : 135 = 4, 0, 7, 0, 0, 1, 1 +phy_lane_property : 136 = 4, 0, 8, D, D, 0, 0 +phy_lane_property : 137 = 4, 0, 9, A, A, 0, 1 +phy_lane_property : 138 = 4, 0, 10, B, B, 0, 0 +phy_lane_property : 139 = 4, 0, 11, C, C, 0, 1 +phy_lane_property : 140 = 4, 0, 12, F, F, 0, 0 +phy_lane_property : 141 = 4, 0, 13, 8, 8, 0, 1 +phy_lane_property : 142 = 4, 0, 14, 9, 9, 0, 0 +phy_lane_property : 143 = 4, 0, 15, E, E, 0, 1 + + +# System side lanes: +phy_lane_property : 144 = 4, 1, 4, 0, 0, 0, 0 # UNUSED +phy_lane_property : 145 = 4, 1, 5, 1, 1, 0, 0 # UNUSED +phy_lane_property : 146 = 4, 1, 6, 2, 2, 0, 0 # UNUSED +phy_lane_property : 147 = 4, 1, 7, 3, 3, 0, 0 # UNUSED +phy_lane_property : 148 = 4, 1, 0, 4, 4, 0, 0 +phy_lane_property : 149 = 4, 1, 1, 5, 5, 0, 0 +phy_lane_property : 150 = 4, 1, 2, 6, 6, 0, 0 +phy_lane_property : 151 = 4, 1, 3, 7, 7, 0, 0 +phy_lane_property : 152 = 4, 1, 8, 8, 8, 0, 0 +phy_lane_property : 153 = 4, 1, 9, 9, 9, 0, 0 +phy_lane_property : 154 = 4, 1, 10, A, A, 0, 0 +phy_lane_property : 155 = 4, 1, 11, B, B, 0, 0 +phy_lane_property : 156 = 4, 1, 12, C, C, 0, 0 # UNUSED +phy_lane_property : 157 = 4, 1, 13, D, D, 0, 0 # UNUSED +phy_lane_property : 158 = 4, 1, 14, E, E, 0, 0 # UNUSED +phy_lane_property : 159 = 4, 1, 15, F, F, 0, 0 # UNUSED + +#---------------------------------------------------------------------------------------------------------------- +### PHY CONFIGURATION FILE +### Please refer to config_file_format.txt in the top level folder for configuration file format + +### PHY CONFIGURATIONS +phy_init_config_chip_id:5 = 85361 +phy_init_mode:5 = 0 +phy_init_config_ref_clk:5 = 312000000 + +### LANE CONFIGURATIONS +#---------------------------------------------------------------------------------------------------------------- +# Lane_Property : Global_Lane = PHY_ID, IF_Side, Local_Lane, Tx_Lane_Map, Rx_Lane_Map, Tx_Polarity, Rx_Polarity +#---------------------------------------------------------------------------------------------------------------- +# Line side lanes: +phy_lane_property : 160 = 5, 0, 0, 3, 3, 0, 0 +phy_lane_property : 161 = 5, 0, 1, 4, 4, 0, 1 +phy_lane_property : 162 = 5, 0, 2, 5, 5, 0, 0 +phy_lane_property : 163 = 5, 0, 3, 2, 2, 1, 1 +phy_lane_property : 164 = 5, 0, 4, 1, 1, 1, 0 +phy_lane_property : 165 = 5, 0, 5, 6, 6, 0, 1 +phy_lane_property : 166 = 5, 0, 6, 7, 7, 0, 0 +phy_lane_property : 167 = 5, 0, 7, 0, 0, 1, 1 +phy_lane_property : 168 = 5, 0, 8, D, D, 0, 0 +phy_lane_property : 169 = 5, 0, 9, A, A, 0, 1 +phy_lane_property : 170 = 5, 0, 10, B, B, 0, 0 +phy_lane_property : 171 = 5, 0, 11, C, C, 0, 1 +phy_lane_property : 172 = 5, 0, 12, F, F, 0, 0 +phy_lane_property : 173 = 5, 0, 13, 8, 8, 0, 1 +phy_lane_property : 174 = 5, 0, 14, 9, 9, 0, 0 +phy_lane_property : 175 = 5, 0, 15, E, E, 0, 1 + + +# System side lanes: +phy_lane_property : 176 = 5, 1, 4, 0, 0, 0, 0 # UNUSED +phy_lane_property : 177 = 5, 1, 5, 1, 1, 0, 0 # UNUSED +phy_lane_property : 178 = 5, 1, 6, 2, 2, 0, 0 # UNUSED +phy_lane_property : 179 = 5, 1, 7, 3, 3, 0, 0 # UNUSED +phy_lane_property : 180 = 5, 1, 0, 4, 4, 0, 0 +phy_lane_property : 181 = 5, 1, 1, 5, 5, 0, 0 +phy_lane_property : 182 = 5, 1, 2, 6, 6, 0, 0 +phy_lane_property : 183 = 5, 1, 3, 7, 7, 0, 0 +phy_lane_property : 184 = 5, 1, 8, 8, 8, 0, 0 +phy_lane_property : 185 = 5, 1, 9, 9, 9, 0, 0 +phy_lane_property : 186 = 5, 1, 10, A, A, 0, 0 +phy_lane_property : 187 = 5, 1, 11, B, B, 0, 0 +phy_lane_property : 188 = 5, 1, 12, C, C, 0, 0 # UNUSED +phy_lane_property : 189 = 5, 1, 13, D, D, 0, 0 # UNUSED +phy_lane_property : 190 = 5, 1, 14, E, E, 0, 0 # UNUSED +phy_lane_property : 191 = 5, 1, 15, F, F, 0, 0 # UNUSED + +#---------------------------------------------------------------------------------------------------------------- +### PHY CONFIGURATION FILE +### Please refer to config_file_format.txt in the top level folder for configuration file format + +### PHY CONFIGURATIONS +phy_init_config_chip_id:6 = 85361 +phy_init_mode:6 = 0 +phy_init_config_ref_clk:6 = 312000000 + +### LANE CONFIGURATIONS +#---------------------------------------------------------------------------------------------------------------- +# Lane_Property : Global_Lane = PHY_ID, IF_Side, Local_Lane, Tx_Lane_Map, Rx_Lane_Map, Tx_Polarity, Rx_Polarity +#---------------------------------------------------------------------------------------------------------------- +# Line side lanes: +phy_lane_property : 192 = 6, 0, 0, 3, 3, 0, 0 +phy_lane_property : 193 = 6, 0, 1, 4, 4, 0, 1 +phy_lane_property : 194 = 6, 0, 2, 5, 5, 0, 0 +phy_lane_property : 195 = 6, 0, 3, 2, 2, 1, 1 +phy_lane_property : 196 = 6, 0, 4, 1, 1, 1, 0 +phy_lane_property : 197 = 6, 0, 5, 6, 6, 0, 1 +phy_lane_property : 198 = 6, 0, 6, 7, 7, 0, 0 +phy_lane_property : 199 = 6, 0, 7, 0, 0, 1, 1 +phy_lane_property : 200 = 6, 0, 8, D, D, 0, 0 +phy_lane_property : 201 = 6, 0, 9, A, A, 0, 1 +phy_lane_property : 202 = 6, 0, 10, B, B, 0, 0 +phy_lane_property : 203 = 6, 0, 11, C, C, 0, 1 +phy_lane_property : 204 = 6, 0, 12, F, F, 0, 0 +phy_lane_property : 205 = 6, 0, 13, 8, 8, 0, 1 +phy_lane_property : 206 = 6, 0, 14, 9, 9, 0, 0 +phy_lane_property : 207 = 6, 0, 15, E, E, 0, 1 + + +# System side lanes: +phy_lane_property : 208 = 6, 1, 4, 0, 0, 0, 0 # UNUSED +phy_lane_property : 209 = 6, 1, 5, 1, 1, 0, 0 # UNUSED +phy_lane_property : 210 = 6, 1, 6, 2, 2, 0, 0 # UNUSED +phy_lane_property : 211 = 6, 1, 7, 3, 3, 0, 0 # UNUSED +phy_lane_property : 212 = 6, 1, 0, 4, 4, 0, 0 +phy_lane_property : 213 = 6, 1, 1, 5, 5, 0, 0 +phy_lane_property : 214 = 6, 1, 2, 6, 6, 0, 0 +phy_lane_property : 215 = 6, 1, 3, 7, 7, 0, 0 +phy_lane_property : 216 = 6, 1, 8, 8, 8, 0, 0 +phy_lane_property : 217 = 6, 1, 9, 9, 9, 0, 0 +phy_lane_property : 218 = 6, 1, 10, A, A, 0, 0 +phy_lane_property : 219 = 6, 1, 11, B, B, 0, 0 +phy_lane_property : 220 = 6, 1, 12, C, C, 0, 0 # UNUSED +phy_lane_property : 221 = 6, 1, 13, D, D, 0, 0 # UNUSED +phy_lane_property : 222 = 6, 1, 14, E, E, 0, 0 # UNUSED +phy_lane_property : 223 = 6, 1, 15, F, F, 0, 0 # UNUSED + +#---------------------------------------------------------------------------------------------------------------- +### PHY CONFIGURATION FILE +### Please refer to config_file_format.txt in the top level folder for configuration file format + +### PHY CONFIGURATIONS +phy_init_config_chip_id:7 = 85361 +phy_init_mode:7 = 0 +phy_init_config_ref_clk:7 = 312000000 + +### LANE CONFIGURATIONS +#---------------------------------------------------------------------------------------------------------------- +# Lane_Property : Global_Lane = PHY_ID, IF_Side, Local_Lane, Tx_Lane_Map, Rx_Lane_Map, Tx_Polarity, Rx_Polarity +#---------------------------------------------------------------------------------------------------------------- +# Line side lanes: +phy_lane_property : 224 = 7, 0, 0, 3, 3, 0, 0 +phy_lane_property : 225 = 7, 0, 1, 4, 4, 0, 1 +phy_lane_property : 226 = 7, 0, 2, 5, 5, 0, 0 +phy_lane_property : 227 = 7, 0, 3, 2, 2, 1, 1 +phy_lane_property : 228 = 7, 0, 4, 1, 1, 1, 0 +phy_lane_property : 229 = 7, 0, 5, 6, 6, 0, 1 +phy_lane_property : 230 = 7, 0, 6, 7, 7, 0, 0 +phy_lane_property : 231 = 7, 0, 7, 0, 0, 1, 1 +phy_lane_property : 232 = 7, 0, 8, D, D, 0, 0 +phy_lane_property : 233 = 7, 0, 9, A, A, 0, 1 +phy_lane_property : 234 = 7, 0, 10, B, B, 0, 0 +phy_lane_property : 235 = 7, 0, 11, C, C, 0, 1 +phy_lane_property : 236 = 7, 0, 12, F, F, 0, 0 +phy_lane_property : 237 = 7, 0, 13, 8, 8, 0, 1 +phy_lane_property : 238 = 7, 0, 14, 9, 9, 0, 0 +phy_lane_property : 239 = 7, 0, 15, E, E, 0, 1 + + +# System side lanes: +phy_lane_property : 240 = 7, 1, 4, 0, 0, 0, 0 # UNUSED +phy_lane_property : 241 = 7, 1, 5, 1, 1, 0, 0 # UNUSED +phy_lane_property : 242 = 7, 1, 6, 2, 2, 0, 0 # UNUSED +phy_lane_property : 243 = 7, 1, 7, 3, 3, 0, 0 # UNUSED +phy_lane_property : 244 = 7, 1, 0, 4, 4, 0, 0 +phy_lane_property : 245 = 7, 1, 1, 5, 5, 0, 0 +phy_lane_property : 246 = 7, 1, 2, 6, 6, 0, 0 +phy_lane_property : 247 = 7, 1, 3, 7, 7, 0, 0 +phy_lane_property : 248 = 7, 1, 8, 8, 8, 0, 0 +phy_lane_property : 249 = 7, 1, 9, 9, 9, 0, 0 +phy_lane_property : 250 = 7, 1, 10, A, A, 0, 0 +phy_lane_property : 251 = 7, 1, 11, B, B, 0, 0 +phy_lane_property : 252 = 7, 1, 12, C, C, 0, 0 # UNUSED +phy_lane_property : 253 = 7, 1, 13, D, D, 0, 0 # UNUSED +phy_lane_property : 254 = 7, 1, 14, E, E, 0, 0 # UNUSED +phy_lane_property : 255 = 7, 1, 15, F, F, 0, 0 # UNUSED + +#---------------------------------------------------------------------------------------------------------------- + diff --git a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/buffer_ports.j2 b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/buffer_ports.j2 new file mode 100644 index 00000000000..ec6460f1243 --- /dev/null +++ b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/buffer_ports.j2 @@ -0,0 +1,6 @@ +{%- macro generate_port_lists(PORT_ALL) %} + {# Generate list of ports #} + {%- for port_idx in range(0, 260, 4) %} + {%- if PORT_ALL.append("Ethernet%d" % (port_idx)) %}{%- endif %} + {%- endfor %} +{%- endmacro %} diff --git a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/buffers.json.j2 b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/buffers.json.j2 new file mode 100644 index 00000000000..f34a844f4a8 --- /dev/null +++ b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/buffers.json.j2 @@ -0,0 +1,2 @@ +{%- set default_topo = 't2' %} +{%- include 'buffers_config.j2' %} diff --git a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/buffers_defaults_t2.j2 b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/buffers_defaults_t2.j2 new file mode 100644 index 00000000000..2cf7dca105c --- /dev/null +++ b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/buffers_defaults_t2.j2 @@ -0,0 +1,52 @@ +{%- set default_cable = '300m' %} + +{%- include 'buffer_ports.j2' %} + +{%- macro generate_port_lists(PORT_ALL) %} + {# Generate list of ports #} + {%- for port_idx in range(0,256,8) %} + {%- if PORT_ALL.append("Ethernet%d" % (port_idx)) %}{%- endif %} + {%- endfor %} +{%- endmacro %} + +{%- macro generate_buffer_pool_and_profiles() %} + "BUFFER_POOL": { + "ingress_pool": { + "size": "56441610000", + "type": "both", + "mode": "dynamic" + } + }, + "BUFFER_PROFILE": { + "ingress_lossy_profile": { + "pool":"ingress_pool", + "size":"0", + "dynamic_th":"3" + }, + "egress_lossy_profile": { + "pool":"ingress_pool", + "size":"0", + "dynamic_th":"3" + } + }, +{%- endmacro %} + +{%- macro generate_pg_profils(port_names_active) %} + "BUFFER_PG": { +{% for port in port_names_active.split(',') %} + "{{ port }}|0-7": { + "profile" : "ingress_lossy_profile" + }{% if not loop.last %},{% endif %} +{% endfor %} + }, +{%- endmacro %} + +{% macro generate_queue_buffers(port_names_active) %} + "BUFFER_QUEUE": { +{% for port in port_names_active.split(',') %} + "{{ port }}|0-7": { + "profile" : "egress_lossy_profile" + }{% if not loop.last %},{% endif %} +{% endfor %} + } +{% endmacro %} diff --git a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/context_config.json b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/context_config.json new file mode 100644 index 00000000000..e5e8c1f4768 --- /dev/null +++ b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/context_config.json @@ -0,0 +1,98 @@ +{ + "CONTEXTS": [ + { + "guid": 0, + "name": "sw0", + "dbAsic": "ASIC_DB", + "dbCounters": "COUNTERS_DB", + "dbFlex": "FLEX_COUNTER_DB", + "dbState": "STATE_DB", + "zmq_enable": false, + "zmq_endpoint": "tcp://127.0.0.1:5555", + "zmq_ntf_endpoint": "tcp://127.0.0.1:5556", + "switches": [ + { + "index": 0, + "hwinfo": "" + } + ] + }, + { + "guid": 1, + "name": "phy", + "dbAsic": "GB_ASIC_DB", + "dbCounters": "GB_COUNTERS_DB", + "dbFlex": "GB_FLEX_COUNTER_DB", + "dbState": "STATE_DB", + "zmq_enable": false, + "zmq_endpoint": "tcp://127.0.0.1:5565", + "zmq_ntf_endpoint": "tcp://127.0.0.1:5566", + "switches": [ + { + "index": 9, + "hwinfo": "9" + }, + { + "index": 8, + "hwinfo": "8" + }, + { + "index": 10, + "hwinfo": "10" + }, + { + "index": 11, + "hwinfo": "11" + }, + { + "index": 12, + "hwinfo": "12" + }, + { + "index": 13, + "hwinfo": "13" + }, + { + "index": 14, + "hwinfo": "14" + }, + { + "index": 15, + "hwinfo": "15" + }, + { + "index": 0, + "hwinfo": "0" + }, + { + "index": 1, + "hwinfo": "1" + }, + { + "index": 2, + "hwinfo": "2" + }, + { + "index": 3, + "hwinfo": "3" + }, + { + "index": 4, + "hwinfo": "4" + }, + { + "index": 5, + "hwinfo": "5" + }, + { + "index": 6, + "hwinfo": "6" + }, + { + "index": 7, + "hwinfo": "7" + } + ] + } + ] +} \ No newline at end of file diff --git a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/gearbox_config.json b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/gearbox_config.json new file mode 100644 index 00000000000..a60e21c62ba --- /dev/null +++ b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/gearbox_config.json @@ -0,0 +1,438 @@ +{ + "phys": [ + { + "phy_id": 0, + "name": "phy0", + "address": "2031617", + "lib_name": "libsai.so", + "firmware_path": "", + "config_file": "/usr/share/sonic/hwsku/phy0_config.json", + "sai_init_config_file": "", + "phy_access": "mdio", + "bus_id": 0, + "context_id": 1, + "hwinfo": "0" + }, + { + "phy_id": 1, + "name": "phy1", + "address": "2031616", + "lib_name": "libsai.so", + "firmware_path": "", + "config_file": "/usr/share/sonic/hwsku/phy1_config.json", + "sai_init_config_file": "", + "phy_access": "mdio", + "bus_id": 0, + "context_id": 1, + "hwinfo": "1" + }, + { + "phy_id": 2, + "name": "phy2", + "address": "2031619", + "lib_name": "libsai.so", + "firmware_path": "", + "config_file": "/usr/share/sonic/hwsku/phy2_config.json", + "sai_init_config_file": "", + "phy_access": "mdio", + "bus_id": 0, + "context_id": 1, + "hwinfo": "2" + }, + { + "phy_id": 3, + "name": "phy3", + "address": "2031618", + "lib_name": "libsai.so", + "firmware_path": "", + "config_file": "/usr/share/sonic/hwsku/phy3_config.json", + "sai_init_config_file": "", + "phy_access": "mdio", + "bus_id": 0, + "context_id": 1, + "hwinfo": "3" + }, + { + "phy_id": 4, + "name": "phy4", + "address": "2031621", + "lib_name": "libsai.so", + "firmware_path": "", + "config_file": "/usr/share/sonic/hwsku/phy4_config.json", + "sai_init_config_file": "", + "phy_access": "mdio", + "bus_id": 0, + "context_id": 1, + "hwinfo": "4" + }, + { + "phy_id": 5, + "name": "phy5", + "address": "2031620", + "lib_name": "libsai.so", + "firmware_path": "", + "config_file": "/usr/share/sonic/hwsku/phy5_config.json", + "sai_init_config_file": "", + "phy_access": "mdio", + "bus_id": 0, + "context_id": 1, + "hwinfo": "5" + }, + { + "phy_id": 6, + "name": "phy6", + "address": "2031623", + "lib_name": "libsai.so", + "firmware_path": "", + "config_file": "/usr/share/sonic/hwsku/phy6_config.json", + "sai_init_config_file": "", + "phy_access": "mdio", + "bus_id": 0, + "context_id": 1, + "hwinfo": "6" + }, + { + "phy_id": 7, + "name": "phy7", + "address": "2031622", + "lib_name": "libsai.so", + "firmware_path": "", + "config_file": "/usr/share/sonic/hwsku/phy7_config.json", + "sai_init_config_file": "", + "phy_access": "mdio", + "bus_id": 0, + "context_id": 1, + "hwinfo": "7" + }, + { + "phy_id": 8, + "name": "phy8", + "address": "2031625", + "lib_name": "libsai.so", + "firmware_path": "", + "config_file": "/usr/share/sonic/hwsku/phy8_config.json", + "sai_init_config_file": "", + "phy_access": "mdio", + "bus_id": 0, + "context_id": 1, + "hwinfo": "8" + }, + { + "phy_id": 9, + "name": "phy9", + "address": "2031624", + "lib_name": "libsai.so", + "firmware_path": "", + "config_file": "/usr/share/sonic/hwsku/phy9_config.json", + "sai_init_config_file": "", + "phy_access": "mdio", + "bus_id": 0, + "context_id": 1, + "hwinfo": "9" + }, + { + "phy_id": 10, + "name": "phy10", + "address": "2031626", + "lib_name": "libsai.so", + "firmware_path": "", + "config_file": "/usr/share/sonic/hwsku/phy10_config.json", + "sai_init_config_file": "", + "phy_access": "mdio", + "bus_id": 0, + "context_id": 1, + "hwinfo": "10" + }, + { + "phy_id": 11, + "name": "phy11", + "address": "2031627", + "lib_name": "libsai.so", + "firmware_path": "", + "config_file": "/usr/share/sonic/hwsku/phy11_config.json", + "sai_init_config_file": "", + "phy_access": "mdio", + "bus_id": 0, + "context_id": 1, + "hwinfo": "11" + }, + { + "phy_id": 12, + "name": "phy12", + "address": "2031628", + "lib_name": "libsai.so", + "firmware_path": "", + "config_file": "/usr/share/sonic/hwsku/phy12_config.json", + "sai_init_config_file": "", + "phy_access": "mdio", + "bus_id": 0, + "context_id": 1, + "hwinfo": "12" + }, + { + "phy_id": 13, + "name": "phy13", + "address": "2031629", + "lib_name": "libsai.so", + "firmware_path": "", + "config_file": "/usr/share/sonic/hwsku/phy13_config.json", + "sai_init_config_file": "", + "phy_access": "mdio", + "bus_id": 0, + "context_id": 1, + "hwinfo": "13" + }, + { + "phy_id": 14, + "name": "phy14", + "address": "2031630", + "lib_name": "libsai.so", + "firmware_path": "", + "config_file": "/usr/share/sonic/hwsku/phy14_config.json", + "sai_init_config_file": "", + "phy_access": "mdio", + "bus_id": 0, + "context_id": 1, + "hwinfo": "14" + }, + { + "phy_id": 15, + "name": "phy15", + "address": "2031631", + "lib_name": "libsai.so", + "firmware_path": "", + "config_file": "/usr/share/sonic/hwsku/phy15_config.json", + "sai_init_config_file": "", + "phy_access": "mdio", + "bus_id": 0, + "context_id": 1, + "hwinfo": "15" + } + ], + "interfaces": [ + { + "name": "Ethernet0", + "index": 1, + "phy_id": 0, + "system_lanes": [20,21,22,23], + "line_lanes": [0,1,2,3,4,5,6,7] + }, + { + "name": "Ethernet4", + "index": 2, + "phy_id": 0, + "system_lanes": [24,25,26,27], + "line_lanes": [8,9,10,11,12,13,14,15] + }, + { + "name": "Ethernet8", + "index": 3, + "phy_id": 1, + "system_lanes": [52,53,54,55], + "line_lanes": [32,33,34,35,36,37,38,39] + }, + { + "name": "Ethernet12", + "index": 4, + "phy_id": 1, + "system_lanes": [56,57,58,59], + "line_lanes": [40,41,42,43,44,45,46,47] + }, + { + "name": "Ethernet16", + "index": 5, + "phy_id": 2, + "system_lanes": [84,85,86,87], + "line_lanes": [64,65,66,67,68,69,70,71] + }, + { + "name": "Ethernet20", + "index": 6, + "phy_id": 2, + "system_lanes": [88,89,90,91], + "line_lanes": [72,73,74,75,76,77,78,79] + }, + { + "name": "Ethernet24", + "index": 7, + "phy_id": 3, + "system_lanes": [116,117,118,119], + "line_lanes": [96,97,98,99,100,101,102,103] + }, + { + "name": "Ethernet28", + "index": 8, + "phy_id": 3, + "system_lanes": [120,121,122,123], + "line_lanes": [104,105,106,107,108,109,110,111] + }, + { + "name": "Ethernet32", + "index": 9, + "phy_id": 4, + "system_lanes": [148,149,150,151], + "line_lanes": [128,129,130,131,132,133,134,135] + }, + { + "name": "Ethernet36", + "index": 10, + "phy_id": 4, + "system_lanes": [152,153,154,155], + "line_lanes": [136,137,138,139,140,141,142,143] + }, + { + "name": "Ethernet40", + "index": 11, + "phy_id": 5, + "system_lanes": [180,181,182,183], + "line_lanes": [160,161,162,163,164,165,166,167] + }, + { + "name": "Ethernet44", + "index": 12, + "phy_id": 5, + "system_lanes": [184,185,186,187], + "line_lanes": [168,169,170,171,172,173,174,175] + }, + { + "name": "Ethernet48", + "index": 13, + "phy_id": 6, + "system_lanes": [212,213,214,215], + "line_lanes": [192,193,194,195,196,197,198,199] + }, + { + "name": "Ethernet52", + "index": 14, + "phy_id": 6, + "system_lanes": [216,217,218,219], + "line_lanes": [200,201,202,203,204,205,206,207] + }, + { + "name": "Ethernet56", + "index": 15, + "phy_id": 7, + "system_lanes": [244,245,246,247], + "line_lanes": [224,225,226,227,228,229,230,231] + }, + { + "name": "Ethernet60", + "index": 16, + "phy_id": 7, + "system_lanes": [248,249,250,251], + "line_lanes": [232,233,234,235,236,237,238,239] + }, + { + "name": "Ethernet64", + "index": 17, + "phy_id": 8, + "system_lanes": [276,277,278,279], + "line_lanes": [256,257,258,259,260,261,262,263] + }, + { + "name": "Ethernet68", + "index": 18, + "phy_id": 8, + "system_lanes": [280,281,282,283], + "line_lanes": [264,265,266,267,268,269,270,271] + }, + { + "name": "Ethernet72", + "index": 19, + "phy_id": 9, + "system_lanes": [308,309,310,311], + "line_lanes": [288,289,290,291,292,293,294,295] + }, + { + "name": "Ethernet76", + "index": 20, + "phy_id": 9, + "system_lanes": [312,313,314,315], + "line_lanes": [296,297,298,299,300,301,302,303] + }, + { + "name": "Ethernet80", + "index": 21, + "phy_id": 10, + "system_lanes": [340,341,342,343], + "line_lanes": [320,321,322,323,324,325,326,327] + }, + { + "name": "Ethernet84", + "index": 22, + "phy_id": 10, + "system_lanes": [344,345,346,347], + "line_lanes": [328,329,330,331,332,333,334,335] + }, + { + "name": "Ethernet88", + "index": 23, + "phy_id": 11, + "system_lanes": [372,373,374,375], + "line_lanes": [352,353,354,355,356,357,358,359] + }, + { + "name": "Ethernet92", + "index": 24, + "phy_id": 11, + "system_lanes": [376,377,378,379], + "line_lanes": [360,361,362,363,364,365,366,367] + }, + { + "name": "Ethernet96", + "index": 25, + "phy_id": 12, + "system_lanes": [404,405,406,407], + "line_lanes": [384,385,386,387,388,389,390,391] + }, + { + "name": "Ethernet100", + "index": 26, + "phy_id": 12, + "system_lanes": [408,409,410,411], + "line_lanes": [392,393,394,395,396,397,398,399] + }, + { + "name": "Ethernet104", + "index": 27, + "phy_id": 13, + "system_lanes": [436,437,438,439], + "line_lanes": [416,417,418,419,420,421,422,423] + }, + { + "name": "Ethernet108", + "index": 28, + "phy_id": 13, + "system_lanes": [440,441,442,443], + "line_lanes": [424,425,426,427,428,429,430,431] + }, + { + "name": "Ethernet112", + "index": 29, + "phy_id": 14, + "system_lanes": [468,469,470,471], + "line_lanes": [448,449,450,451,452,453,454,455] + }, + { + "name": "Ethernet116", + "index": 30, + "phy_id": 14, + "system_lanes": [472,473,474,475], + "line_lanes": [456,457,458,459,460,461,462,463] + }, + { + "name": "Ethernet120", + "index": 31, + "phy_id": 15, + "system_lanes": [500,501,502,503], + "line_lanes": [480,481,482,483,484,485,486,487] + }, + { + "name": "Ethernet124", + "index": 32, + "phy_id": 15, + "system_lanes": [504,505,506,507], + "line_lanes": [488,489,490,491,492,493,494,495] + } + ] +} diff --git a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/hwsku.json b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/hwsku.json new file mode 100644 index 00000000000..74f7410180a --- /dev/null +++ b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/hwsku.json @@ -0,0 +1,334 @@ +{ + "interfaces": { + "Ethernet0": { + "autoneg": "off", + "default_brkout_mode": "1x400G", + "fec": "rs" + }, + "Ethernet4": { + "autoneg": "off", + "default_brkout_mode": "1x400G", + "fec": "rs" + }, + "Ethernet8": { + "autoneg": "off", + "default_brkout_mode": "1x400G", + "fec": "rs" + }, + "Ethernet12": { + "autoneg": "off", + "default_brkout_mode": "1x400G", + "fec": "rs" + }, + "Ethernet16": { + "autoneg": "off", + "default_brkout_mode": "1x400G", + "fec": "rs" + }, + "Ethernet20": { + "autoneg": "off", + "default_brkout_mode": "1x400G", + "fec": "rs" + }, + "Ethernet24": { + "autoneg": "off", + "default_brkout_mode": "1x400G", + "fec": "rs" + }, + "Ethernet28": { + "autoneg": "off", + "default_brkout_mode": "1x400G", + "fec": "rs" + }, + "Ethernet32": { + "autoneg": "off", + "default_brkout_mode": "1x400G", + "fec": "rs" + }, + "Ethernet36": { + "autoneg": "off", + "default_brkout_mode": "1x400G", + "fec": "rs" + }, + "Ethernet40": { + "autoneg": "off", + "default_brkout_mode": "1x400G", + "fec": "rs" + }, + "Ethernet44": { + "autoneg": "off", + "default_brkout_mode": "1x400G", + "fec": "rs" + }, + "Ethernet48": { + "autoneg": "off", + "default_brkout_mode": "1x400G", + "fec": "rs" + }, + "Ethernet52": { + "autoneg": "off", + "default_brkout_mode": "1x400G", + "fec": "rs" + }, + "Ethernet56": { + "autoneg": "off", + "default_brkout_mode": "1x400G", + "fec": "rs" + }, + "Ethernet60": { + "autoneg": "off", + "default_brkout_mode": "1x400G", + "fec": "rs" + }, + "Ethernet64": { + "autoneg": "off", + "default_brkout_mode": "1x400G", + "fec": "rs" + }, + "Ethernet68": { + "autoneg": "off", + "default_brkout_mode": "1x400G", + "fec": "rs" + }, + "Ethernet72": { + "autoneg": "off", + "default_brkout_mode": "1x400G", + "fec": "rs" + }, + "Ethernet76": { + "autoneg": "off", + "default_brkout_mode": "1x400G", + "fec": "rs" + }, + "Ethernet80": { + "autoneg": "off", + "default_brkout_mode": "1x400G", + "fec": "rs" + }, + "Ethernet84": { + "autoneg": "off", + "default_brkout_mode": "1x400G", + "fec": "rs" + }, + "Ethernet88": { + "autoneg": "off", + "default_brkout_mode": "1x400G", + "fec": "rs" + }, + "Ethernet92": { + "autoneg": "off", + "default_brkout_mode": "1x400G", + "fec": "rs" + }, + "Ethernet96": { + "autoneg": "off", + "default_brkout_mode": "1x400G", + "fec": "rs" + }, + "Ethernet100": { + "autoneg": "off", + "default_brkout_mode": "1x400G", + "fec": "rs" + }, + "Ethernet104": { + "autoneg": "off", + "default_brkout_mode": "1x400G", + "fec": "rs" + }, + "Ethernet108": { + "autoneg": "off", + "default_brkout_mode": "1x400G", + "fec": "rs" + }, + "Ethernet112": { + "autoneg": "off", + "default_brkout_mode": "1x400G", + "fec": "rs" + }, + "Ethernet116": { + "autoneg": "off", + "default_brkout_mode": "1x400G", + "fec": "rs" + }, + "Ethernet120": { + "autoneg": "off", + "default_brkout_mode": "1x400G", + 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"0xffffffe8" + }, + "main": { + "lane0": "0x5a", + "lane1": "0x5a", + "lane2": "0x5a", + "lane3": "0x5a" + }, + "post1": { + "lane0": "0xfffffff4", + "lane1": "0xfffffff4", + "lane2": "0xfffffff4", + "lane3": "0xfffffff4" + }, + "post2": { + "lane0": "0x0", + "lane1": "0x0", + "lane2": "0x0", + "lane3": "0x0" + } + } + }, + "50": { + "OPTICAL100": { + "pre3": { + "lane0": "0x0", + "lane1": "0x0", + "lane2": "0x0", + "lane3": "0x0" + }, + "pre2": { + "lane0": "0x2", + "lane1": "0x2", + "lane2": "0x2", + "lane3": "0x2" + }, + "pre1": { + "lane0": "0xffffffe8", + "lane1": "0xffffffe8", + "lane2": "0xffffffe8", + "lane3": "0xffffffe8" + }, + "main": { + "lane0": "0x5c", + "lane1": "0x5c", + "lane2": "0x5c", + "lane3": "0x5c" + }, + "post1": { + "lane0": "0xfffffff2", + "lane1": "0xfffffff2", + "lane2": "0xfffffff2", + "lane3": "0xfffffff2" + }, + "post2": { + "lane0": "0x0", + "lane1": "0x0", + "lane2": "0x0", + "lane3": "0x0" + } + } + }, + "51": { + "OPTICAL100": { + "pre3": { + "lane0": "0x0", + "lane1": "0x0", + "lane2": "0x0", + "lane3": "0x0" + }, + "pre2": { + "lane0": "0x2", + "lane1": "0x2", + "lane2": "0x2", + "lane3": "0x2" + }, + "pre1": { + "lane0": "0xffffffe8", + "lane1": "0xffffffe8", + "lane2": "0xffffffe8", + "lane3": "0xffffffe8" + }, + "main": { + "lane0": "0x5c", + "lane1": "0x5c", + "lane2": "0x5c", + "lane3": "0x5c" + }, + "post1": { + "lane0": "0xfffffff2", + "lane1": "0xfffffff2", + "lane2": "0xfffffff2", + "lane3": "0xfffffff2" + }, + "post2": { + "lane0": "0x0", + "lane1": "0x0", + "lane2": "0x0", + "lane3": "0x0" + } + } + }, + "52": { + "OPTICAL100": { + "pre3": { + "lane0": "0x0", + "lane1": "0x0", + "lane2": "0x0", + "lane3": "0x0" + }, + "pre2": { + "lane0": "0x0", + "lane1": "0x0", + "lane2": "0x0", + "lane3": "0x0" + }, + "pre1": { + "lane0": "0xffffffe8", + "lane1": "0xffffffe8", + "lane2": "0xffffffe8", + "lane3": "0xffffffe8" + }, + "main": { + "lane0": "0x5a", + "lane1": "0x5a", + "lane2": "0x5a", + "lane3": "0x5a" + }, + "post1": { + "lane0": "0xfffffff4", + "lane1": "0xfffffff4", + "lane2": "0xfffffff4", + "lane3": "0xfffffff4" + }, + "post2": { + "lane0": "0x0", + "lane1": "0x0", + "lane2": "0x0", + "lane3": "0x0" + } + } + }, + "53": { + "OPTICAL100": { + "pre3": { + "lane0": "0x0", + "lane1": "0x0", + "lane2": "0x0", + "lane3": "0x0" + }, + "pre2": { + "lane0": "0x0", + "lane1": "0x0", + "lane2": "0x0", + "lane3": "0x0" + }, + "pre1": { + "lane0": "0xffffffe8", + "lane1": "0xffffffe8", + "lane2": "0xffffffe8", + "lane3": "0xffffffe8" + }, + "main": { + "lane0": "0x5a", + "lane1": "0x5a", + "lane2": "0x5a", + "lane3": "0x5a" + }, + "post1": { + "lane0": "0xfffffff4", + "lane1": "0xfffffff4", + "lane2": "0xfffffff4", + "lane3": "0xfffffff4" + }, + "post2": { + "lane0": "0x0", + "lane1": "0x0", + "lane2": "0x0", + "lane3": "0x0" + } + } + }, + "54": { + "OPTICAL100": { + "pre3": { + "lane0": "0x0", + "lane1": "0x0", + "lane2": "0x0", + "lane3": "0x0" + }, + "pre2": { + "lane0": "0x2", + "lane1": "0x2", + "lane2": "0x2", + "lane3": "0x2" + }, + "pre1": { + "lane0": "0xffffffe8", + "lane1": "0xffffffe8", + "lane2": "0xffffffe8", + "lane3": "0xffffffe8" + }, + "main": { + "lane0": "0x5c", + "lane1": "0x5c", + "lane2": "0x5c", + "lane3": "0x5c" + }, + "post1": { + "lane0": "0xfffffff2", + "lane1": "0xfffffff2", + "lane2": "0xfffffff2", + "lane3": "0xfffffff2" + }, + "post2": { + "lane0": "0x0", + "lane1": "0x0", + "lane2": "0x0", + "lane3": "0x0" + } + } + }, + "55": { + "OPTICAL100": { + "pre3": { + "lane0": "0x0", + "lane1": "0x0", + "lane2": "0x0", + "lane3": "0x0" + }, + "pre2": { + "lane0": "0x2", + "lane1": "0x2", + "lane2": "0x2", + "lane3": "0x2" + }, + "pre1": { + "lane0": "0xffffffe8", + "lane1": "0xffffffe8", + "lane2": "0xffffffe8", + "lane3": "0xffffffe8" + }, + "main": { + "lane0": "0x5c", + "lane1": "0x5c", + "lane2": "0x5c", + "lane3": "0x5c" + }, + "post1": { + "lane0": "0xfffffff4", + "lane1": "0xfffffff4", + "lane2": "0xfffffff4", + "lane3": "0xfffffff4" + }, + "post2": { + "lane0": "0x0", + "lane1": "0x0", + "lane2": "0x0", + "lane3": "0x0" + } + } + }, + "56": { + "OPTICAL100": { + "pre3": { + "lane0": "0x0", + "lane1": "0x0", + "lane2": "0x0", + "lane3": "0x0" + }, + "pre2": { + "lane0": "0x2", + "lane1": "0x2", + "lane2": "0x2", + "lane3": "0x2" + }, + "pre1": { + "lane0": "0xffffffe8", + "lane1": "0xffffffe8", + "lane2": "0xffffffe8", + "lane3": "0xffffffe8" + }, + "main": { + "lane0": "0x5c", + "lane1": "0x5c", + "lane2": "0x5c", + "lane3": "0x5c" + }, + "post1": { + "lane0": "0xfffffff4", + "lane1": "0xfffffff4", + "lane2": "0xfffffff4", + "lane3": "0xfffffff4" + }, + "post2": { + "lane0": "0x0", + "lane1": "0x0", + "lane2": "0x0", + "lane3": "0x0" + } + } + }, + "57": { + "OPTICAL100": { + "pre3": { + "lane0": "0x0", + "lane1": "0x0", + "lane2": "0x0", + "lane3": "0x0" + }, + "pre2": { + "lane0": "0x2", + "lane1": "0x2", + "lane2": "0x2", + "lane3": "0x2" + }, + "pre1": { + "lane0": "0xffffffe8", + "lane1": "0xffffffe8", + "lane2": "0xffffffe8", + "lane3": "0xffffffe8" + }, + "main": { + "lane0": "0x5c", + "lane1": "0x5c", + "lane2": "0x5c", + "lane3": "0x5c" + }, + "post1": { + "lane0": "0xfffffff4", + "lane1": "0xfffffff4", + "lane2": "0xfffffff4", + "lane3": "0xfffffff4" + }, + "post2": { + "lane0": "0x0", + "lane1": "0x0", + "lane2": "0x0", + "lane3": "0x0" + } + } + }, + "58": { + "OPTICAL100": { + "pre3": { + "lane0": "0x0", + "lane1": "0x0", + "lane2": "0x0", + "lane3": "0x0" + }, + "pre2": { + "lane0": "0x2", + "lane1": "0x2", + "lane2": "0x2", + "lane3": "0x2" + }, + "pre1": { + "lane0": "0xffffffe8", + "lane1": "0xffffffe8", + "lane2": "0xffffffe8", + "lane3": "0xffffffe8" + }, + "main": { + "lane0": "0x5c", + "lane1": "0x5c", + "lane2": "0x5c", + "lane3": "0x5c" + }, + "post1": { + "lane0": "0xfffffff4", + "lane1": "0xfffffff4", + "lane2": "0xfffffff4", + "lane3": "0xfffffff4" + }, + "post2": { + "lane0": "0x0", + "lane1": "0x0", + "lane2": "0x0", + "lane3": "0x0" + } + } + }, + "59": { + "OPTICAL100": { + "pre3": { + "lane0": "0x0", + "lane1": "0x0", + "lane2": "0x0", + "lane3": "0x0" + }, + "pre2": { + "lane0": "0x2", + "lane1": "0x2", + "lane2": "0x2", + "lane3": "0x2" + }, + "pre1": { + "lane0": "0xffffffe8", + "lane1": "0xffffffe8", + "lane2": "0xffffffe8", + "lane3": "0xffffffe8" + }, + "main": { + "lane0": "0x5a", + "lane1": "0x5a", + "lane2": "0x5a", + "lane3": "0x5a" + }, + "post1": { + "lane0": "0xfffffff4", + "lane1": "0xfffffff4", + "lane2": "0xfffffff4", + "lane3": "0xfffffff4" + }, + "post2": { + "lane0": "0x0", + "lane1": "0x0", + "lane2": "0x0", + "lane3": "0x0" + } + } + }, + "60": { + "OPTICAL100": { + "pre3": { + "lane0": "0x0", + "lane1": "0x0", + "lane2": "0x0", + "lane3": "0x0" + }, + "pre2": { + "lane0": "0x2", + "lane1": "0x2", + "lane2": "0x2", + "lane3": "0x2" + }, + "pre1": { + "lane0": "0xffffffe8", + "lane1": "0xffffffe8", + "lane2": "0xffffffe8", + "lane3": "0xffffffe8" + }, + "main": { + "lane0": "0x5a", + "lane1": "0x5a", + "lane2": "0x5a", + "lane3": "0x5a" + }, + "post1": { + "lane0": "0xfffffff4", + "lane1": "0xfffffff4", + "lane2": "0xfffffff4", + "lane3": "0xfffffff4" + }, + "post2": { + "lane0": "0x0", + "lane1": "0x0", + "lane2": "0x0", + "lane3": "0x0" + } + } + }, + "61": { + "OPTICAL100": { + "pre3": { + "lane0": "0x0", + "lane1": "0x0", + "lane2": "0x0", + "lane3": "0x0" + }, + "pre2": { + "lane0": "0x2", + "lane1": "0x2", + "lane2": "0x2", + "lane3": "0x2" + }, + "pre1": { + "lane0": "0xffffffe8", + "lane1": "0xffffffe8", + "lane2": "0xffffffe8", + "lane3": "0xffffffe8" + }, + "main": { + "lane0": "0x5a", + "lane1": "0x5a", + "lane2": "0x5a", + "lane3": "0x5a" + }, + "post1": { + "lane0": "0xfffffff4", + "lane1": "0xfffffff4", + "lane2": "0xfffffff4", + "lane3": "0xfffffff4" + }, + "post2": { + "lane0": "0x0", + "lane1": "0x0", + "lane2": "0x0", + "lane3": "0x0" + } + } + }, + "62": { + "OPTICAL100": { + "pre3": { + "lane0": "0x0", + "lane1": "0x0", + "lane2": "0x0", + "lane3": "0x0" + }, + "pre2": { + "lane0": "0x2", + "lane1": "0x2", + "lane2": "0x2", + "lane3": "0x2" + }, + "pre1": { + "lane0": "0xffffffe8", + "lane1": "0xffffffe8", + "lane2": "0xffffffe8", + "lane3": "0xffffffe8" + }, + "main": { + "lane0": "0x5a", + "lane1": "0x5a", + "lane2": "0x5a", + "lane3": "0x5a" + }, + "post1": { + "lane0": "0xfffffff4", + "lane1": "0xfffffff4", + "lane2": "0xfffffff4", + "lane3": "0xfffffff4" + }, + "post2": { + "lane0": "0x0", + "lane1": "0x0", + "lane2": "0x0", + "lane3": "0x0" + } + } + }, + "63": { + "OPTICAL100": { + "pre3": { + "lane0": "0x0", + "lane1": "0x0", + "lane2": "0x0", + "lane3": "0x0" + }, + "pre2": { + "lane0": "0x2", + "lane1": "0x2", + "lane2": "0x2", + "lane3": "0x2" + }, + "pre1": { + "lane0": "0xffffffe8", + "lane1": "0xffffffe8", + "lane2": "0xffffffe8", + "lane3": "0xffffffe8" + }, + "main": { + "lane0": "0x5a", + "lane1": "0x5a", + "lane2": "0x5a", + "lane3": "0x5a" + }, + "post1": { + "lane0": "0xfffffff4", + "lane1": "0xfffffff4", + "lane2": "0xfffffff4", + "lane3": "0xfffffff4" + }, + "post2": { + "lane0": "0x0", + "lane1": "0x0", + "lane2": "0x0", + "lane3": "0x0" + } + } + }, + "64": { + "OPTICAL100": { + "pre3": { + "lane0": "0x0", + "lane1": "0x0", + "lane2": "0x0", + "lane3": "0x0" + }, + "pre2": { + "lane0": "0x2", + "lane1": "0x2", + "lane2": "0x2", + "lane3": "0x2" + }, + "pre1": { + "lane0": "0xffffffe8", + "lane1": "0xffffffe8", + "lane2": "0xffffffe8", + "lane3": "0xffffffe8" + }, + "main": { + "lane0": "0x5a", + "lane1": "0x5a", + "lane2": "0x5a", + "lane3": "0x5a" + }, + "post1": { + "lane0": "0xfffffff4", + "lane1": "0xfffffff4", + "lane2": "0xfffffff4", + "lane3": "0xfffffff4" + }, + "post2": { + "lane0": "0x0", + "lane1": "0x0", + "lane2": "0x0", + "lane3": "0x0" + } + } + } + } +} \ No newline at end of file diff --git a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/nh5010-default.bcm b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/nh5010-default.bcm new file mode 100644 index 00000000000..2d0b66812b5 --- /dev/null +++ b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/nh5010-default.bcm @@ -0,0 +1,2260 @@ +# ---------------------------------------------------------------------------------------------------- +# core_0 +# ---------------------------------------------------------------------------------------------------- +ucode_port_185.BCM8887X=CDGE4_0:core_0.1 +tm_port_header_type_out_185.BCM8887X=ETH +ucode_port_189.BCM8887X=CDGE4_1:core_0.5 +tm_port_header_type_out_189.BCM8887X=ETH + +# core 0 lane0 +lane_to_serdes_map_nif_lane0.BCM8887X=rx6:tx7 +phy_rx_polarity_flip_phy0.BCM8887X=0 +phy_tx_polarity_flip_phy0.BCM8887X=1 +serdes_tx_taps_0.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 0 lane1 +lane_to_serdes_map_nif_lane1.BCM8887X=rx4:tx3 +phy_rx_polarity_flip_phy1.BCM8887X=0 +phy_tx_polarity_flip_phy1.BCM8887X=1 +serdes_tx_taps_1.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 0 lane2 +lane_to_serdes_map_nif_lane2.BCM8887X=rx7:tx1 +phy_rx_polarity_flip_phy2.BCM8887X=0 +phy_tx_polarity_flip_phy2.BCM8887X=0 +serdes_tx_taps_2.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 0 lane3 +lane_to_serdes_map_nif_lane3.BCM8887X=rx5:tx2 +phy_rx_polarity_flip_phy3.BCM8887X=0 +phy_tx_polarity_flip_phy3.BCM8887X=1 +serdes_tx_taps_3.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 0 lane4 +lane_to_serdes_map_nif_lane4.BCM8887X=rx2:tx0 +phy_rx_polarity_flip_phy4.BCM8887X=0 +phy_tx_polarity_flip_phy4.BCM8887X=0 +serdes_tx_taps_4.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 0 lane5 +lane_to_serdes_map_nif_lane5.BCM8887X=rx3:tx6 +phy_rx_polarity_flip_phy5.BCM8887X=1 +phy_tx_polarity_flip_phy5.BCM8887X=1 +serdes_tx_taps_5.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 0 lane6 +lane_to_serdes_map_nif_lane6.BCM8887X=rx0:tx4 +phy_rx_polarity_flip_phy6.BCM8887X=0 +phy_tx_polarity_flip_phy6.BCM8887X=0 +serdes_tx_taps_6.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 0 lane7 +lane_to_serdes_map_nif_lane7.BCM8887X=rx1:tx5 +phy_rx_polarity_flip_phy7.BCM8887X=0 +phy_tx_polarity_flip_phy7.BCM8887X=0 +serdes_tx_taps_7.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + + +# ---------------------------------------------------------------------------------------------------- +# core_1 +# ---------------------------------------------------------------------------------------------------- +ucode_port_177.BCM8887X=CDGE4_2:core_0.9 +tm_port_header_type_out_177.BCM8887X=ETH +ucode_port_181.BCM8887X=CDGE4_3:core_0.13 +tm_port_header_type_out_181.BCM8887X=ETH + +# core 1 lane8 +lane_to_serdes_map_nif_lane8.BCM8887X=rx10:tx8 +phy_rx_polarity_flip_phy8.BCM8887X=0 +phy_tx_polarity_flip_phy8.BCM8887X=0 +serdes_tx_taps_8.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 1 lane9 +lane_to_serdes_map_nif_lane9.BCM8887X=rx11:tx14 +phy_rx_polarity_flip_phy9.BCM8887X=1 +phy_tx_polarity_flip_phy9.BCM8887X=1 +serdes_tx_taps_9.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 1 lane10 +lane_to_serdes_map_nif_lane10.BCM8887X=rx8:tx12 +phy_rx_polarity_flip_phy10.BCM8887X=1 +phy_tx_polarity_flip_phy10.BCM8887X=0 +serdes_tx_taps_10.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 1 lane11 +lane_to_serdes_map_nif_lane11.BCM8887X=rx9:tx13 +phy_rx_polarity_flip_phy11.BCM8887X=0 +phy_tx_polarity_flip_phy11.BCM8887X=0 +serdes_tx_taps_11.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 1 lane12 +lane_to_serdes_map_nif_lane12.BCM8887X=rx14:tx15 +phy_rx_polarity_flip_phy12.BCM8887X=0 +phy_tx_polarity_flip_phy12.BCM8887X=1 +serdes_tx_taps_12.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 1 lane13 +lane_to_serdes_map_nif_lane13.BCM8887X=rx12:tx11 +phy_rx_polarity_flip_phy13.BCM8887X=0 +phy_tx_polarity_flip_phy13.BCM8887X=1 +serdes_tx_taps_13.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 1 lane14 +lane_to_serdes_map_nif_lane14.BCM8887X=rx15:tx9 +phy_rx_polarity_flip_phy14.BCM8887X=0 +phy_tx_polarity_flip_phy14.BCM8887X=0 +serdes_tx_taps_14.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 1 lane15 +lane_to_serdes_map_nif_lane15.BCM8887X=rx13:tx10 +phy_rx_polarity_flip_phy15.BCM8887X=0 +phy_tx_polarity_flip_phy15.BCM8887X=1 +serdes_tx_taps_15.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + + +# ---------------------------------------------------------------------------------------------------- +# core_2 +# ---------------------------------------------------------------------------------------------------- +ucode_port_169.BCM8887X=CDGE4_4:core_0.17 +tm_port_header_type_out_169.BCM8887X=ETH +ucode_port_173.BCM8887X=CDGE4_5:core_0.21 +tm_port_header_type_out_173.BCM8887X=ETH + +# core 2 lane16 +lane_to_serdes_map_nif_lane16.BCM8887X=rx18:tx16 +phy_rx_polarity_flip_phy16.BCM8887X=0 +phy_tx_polarity_flip_phy16.BCM8887X=0 +serdes_tx_taps_16.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 2 lane17 +lane_to_serdes_map_nif_lane17.BCM8887X=rx19:tx22 +phy_rx_polarity_flip_phy17.BCM8887X=1 +phy_tx_polarity_flip_phy17.BCM8887X=1 +serdes_tx_taps_17.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 2 lane18 +lane_to_serdes_map_nif_lane18.BCM8887X=rx16:tx20 +phy_rx_polarity_flip_phy18.BCM8887X=0 +phy_tx_polarity_flip_phy18.BCM8887X=0 +serdes_tx_taps_18.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 2 lane19 +lane_to_serdes_map_nif_lane19.BCM8887X=rx17:tx21 +phy_rx_polarity_flip_phy19.BCM8887X=0 +phy_tx_polarity_flip_phy19.BCM8887X=0 +serdes_tx_taps_19.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 2 lane20 +lane_to_serdes_map_nif_lane20.BCM8887X=rx22:tx23 +phy_rx_polarity_flip_phy20.BCM8887X=0 +phy_tx_polarity_flip_phy20.BCM8887X=1 +serdes_tx_taps_20.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 2 lane21 +lane_to_serdes_map_nif_lane21.BCM8887X=rx20:tx19 +phy_rx_polarity_flip_phy21.BCM8887X=0 +phy_tx_polarity_flip_phy21.BCM8887X=1 +serdes_tx_taps_21.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 2 lane22 +lane_to_serdes_map_nif_lane22.BCM8887X=rx23:tx17 +phy_rx_polarity_flip_phy22.BCM8887X=0 +phy_tx_polarity_flip_phy22.BCM8887X=0 +serdes_tx_taps_22.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 2 lane23 +lane_to_serdes_map_nif_lane23.BCM8887X=rx21:tx18 +phy_rx_polarity_flip_phy23.BCM8887X=0 +phy_tx_polarity_flip_phy23.BCM8887X=1 +serdes_tx_taps_23.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + + +# ---------------------------------------------------------------------------------------------------- +# core_3 +# ---------------------------------------------------------------------------------------------------- +ucode_port_161.BCM8887X=CDGE4_6:core_0.25 +tm_port_header_type_out_161.BCM8887X=ETH +ucode_port_165.BCM8887X=CDGE4_7:core_0.29 +tm_port_header_type_out_165.BCM8887X=ETH + +# core 3 lane24 +lane_to_serdes_map_nif_lane24.BCM8887X=rx26:tx26 +phy_rx_polarity_flip_phy24.BCM8887X=1 +phy_tx_polarity_flip_phy24.BCM8887X=0 +serdes_tx_taps_24.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 3 lane25 +lane_to_serdes_map_nif_lane25.BCM8887X=rx27:tx25 +phy_rx_polarity_flip_phy25.BCM8887X=0 +phy_tx_polarity_flip_phy25.BCM8887X=1 +serdes_tx_taps_25.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 3 lane26 +lane_to_serdes_map_nif_lane26.BCM8887X=rx28:tx31 +phy_rx_polarity_flip_phy26.BCM8887X=0 +phy_tx_polarity_flip_phy26.BCM8887X=0 +serdes_tx_taps_26.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 3 lane27 +lane_to_serdes_map_nif_lane27.BCM8887X=rx30:tx24 +phy_rx_polarity_flip_phy27.BCM8887X=1 +phy_tx_polarity_flip_phy27.BCM8887X=0 +serdes_tx_taps_27.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 3 lane28 +lane_to_serdes_map_nif_lane28.BCM8887X=rx29:tx28 +phy_rx_polarity_flip_phy28.BCM8887X=1 +phy_tx_polarity_flip_phy28.BCM8887X=1 +serdes_tx_taps_28.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 3 lane29 +lane_to_serdes_map_nif_lane29.BCM8887X=rx31:tx27 +phy_rx_polarity_flip_phy29.BCM8887X=0 +phy_tx_polarity_flip_phy29.BCM8887X=1 +serdes_tx_taps_29.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 3 lane30 +lane_to_serdes_map_nif_lane30.BCM8887X=rx24:tx30 +phy_rx_polarity_flip_phy30.BCM8887X=0 +phy_tx_polarity_flip_phy30.BCM8887X=1 +serdes_tx_taps_30.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 3 lane31 +lane_to_serdes_map_nif_lane31.BCM8887X=rx25:tx29 +phy_rx_polarity_flip_phy31.BCM8887X=0 +phy_tx_polarity_flip_phy31.BCM8887X=1 +serdes_tx_taps_31.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + + +# ---------------------------------------------------------------------------------------------------- +# core_4 +# ---------------------------------------------------------------------------------------------------- +ucode_port_57.BCM8887X=CDGE4_8:core_1.1 +tm_port_header_type_out_57.BCM8887X=ETH +ucode_port_61.BCM8887X=CDGE4_9:core_1.5 +tm_port_header_type_out_61.BCM8887X=ETH + +# core 4 lane32 +lane_to_serdes_map_nif_lane32.BCM8887X=rx35:tx39 +phy_rx_polarity_flip_phy32.BCM8887X=1 +phy_tx_polarity_flip_phy32.BCM8887X=0 +serdes_tx_taps_32.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 4 lane33 +lane_to_serdes_map_nif_lane33.BCM8887X=rx34:tx35 +phy_rx_polarity_flip_phy33.BCM8887X=0 +phy_tx_polarity_flip_phy33.BCM8887X=0 +serdes_tx_taps_33.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 4 lane34 +lane_to_serdes_map_nif_lane34.BCM8887X=rx37:tx34 +phy_rx_polarity_flip_phy34.BCM8887X=1 +phy_tx_polarity_flip_phy34.BCM8887X=0 +serdes_tx_taps_34.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 4 lane35 +lane_to_serdes_map_nif_lane35.BCM8887X=rx39:tx33 +phy_rx_polarity_flip_phy35.BCM8887X=1 +phy_tx_polarity_flip_phy35.BCM8887X=1 +serdes_tx_taps_35.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 4 lane36 +lane_to_serdes_map_nif_lane36.BCM8887X=rx33:tx36 +phy_rx_polarity_flip_phy36.BCM8887X=1 +phy_tx_polarity_flip_phy36.BCM8887X=0 +serdes_tx_taps_36.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 4 lane37 +lane_to_serdes_map_nif_lane37.BCM8887X=rx32:tx37 +phy_rx_polarity_flip_phy37.BCM8887X=0 +phy_tx_polarity_flip_phy37.BCM8887X=1 +serdes_tx_taps_37.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 4 lane38 +lane_to_serdes_map_nif_lane38.BCM8887X=rx36:tx38 +phy_rx_polarity_flip_phy38.BCM8887X=0 +phy_tx_polarity_flip_phy38.BCM8887X=0 +serdes_tx_taps_38.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 4 lane39 +lane_to_serdes_map_nif_lane39.BCM8887X=rx38:tx32 +phy_rx_polarity_flip_phy39.BCM8887X=0 +phy_tx_polarity_flip_phy39.BCM8887X=1 +serdes_tx_taps_39.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + + +# ---------------------------------------------------------------------------------------------------- +# core_5 +# ---------------------------------------------------------------------------------------------------- +ucode_port_49.BCM8887X=CDGE4_10:core_1.9 +tm_port_header_type_out_49.BCM8887X=ETH +ucode_port_53.BCM8887X=CDGE4_11:core_1.13 +tm_port_header_type_out_53.BCM8887X=ETH + +# core 5 lane40 +lane_to_serdes_map_nif_lane40.BCM8887X=rx43:tx47 +phy_rx_polarity_flip_phy40.BCM8887X=1 +phy_tx_polarity_flip_phy40.BCM8887X=0 +serdes_tx_taps_40.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 5 lane41 +lane_to_serdes_map_nif_lane41.BCM8887X=rx42:tx43 +phy_rx_polarity_flip_phy41.BCM8887X=0 +phy_tx_polarity_flip_phy41.BCM8887X=0 +serdes_tx_taps_41.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 5 lane42 +lane_to_serdes_map_nif_lane42.BCM8887X=rx45:tx42 +phy_rx_polarity_flip_phy42.BCM8887X=1 +phy_tx_polarity_flip_phy42.BCM8887X=0 +serdes_tx_taps_42.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 5 lane43 +lane_to_serdes_map_nif_lane43.BCM8887X=rx47:tx41 +phy_rx_polarity_flip_phy43.BCM8887X=1 +phy_tx_polarity_flip_phy43.BCM8887X=1 +serdes_tx_taps_43.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 5 lane44 +lane_to_serdes_map_nif_lane44.BCM8887X=rx41:tx44 +phy_rx_polarity_flip_phy44.BCM8887X=1 +phy_tx_polarity_flip_phy44.BCM8887X=0 +serdes_tx_taps_44.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 5 lane45 +lane_to_serdes_map_nif_lane45.BCM8887X=rx40:tx45 +phy_rx_polarity_flip_phy45.BCM8887X=0 +phy_tx_polarity_flip_phy45.BCM8887X=1 +serdes_tx_taps_45.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 5 lane46 +lane_to_serdes_map_nif_lane46.BCM8887X=rx44:tx46 +phy_rx_polarity_flip_phy46.BCM8887X=0 +phy_tx_polarity_flip_phy46.BCM8887X=0 +serdes_tx_taps_46.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 5 lane47 +lane_to_serdes_map_nif_lane47.BCM8887X=rx46:tx40 +phy_rx_polarity_flip_phy47.BCM8887X=0 +phy_tx_polarity_flip_phy47.BCM8887X=1 +serdes_tx_taps_47.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + + +# ---------------------------------------------------------------------------------------------------- +# core_6 +# ---------------------------------------------------------------------------------------------------- +ucode_port_41.BCM8887X=CDGE4_12:core_1.17 +tm_port_header_type_out_41.BCM8887X=ETH +ucode_port_45.BCM8887X=CDGE4_13:core_1.21 +tm_port_header_type_out_45.BCM8887X=ETH + +# core 6 lane48 +lane_to_serdes_map_nif_lane48.BCM8887X=rx51:tx55 +phy_rx_polarity_flip_phy48.BCM8887X=1 +phy_tx_polarity_flip_phy48.BCM8887X=0 +serdes_tx_taps_48.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 6 lane49 +lane_to_serdes_map_nif_lane49.BCM8887X=rx50:tx51 +phy_rx_polarity_flip_phy49.BCM8887X=0 +phy_tx_polarity_flip_phy49.BCM8887X=0 +serdes_tx_taps_49.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 6 lane50 +lane_to_serdes_map_nif_lane50.BCM8887X=rx53:tx50 +phy_rx_polarity_flip_phy50.BCM8887X=1 +phy_tx_polarity_flip_phy50.BCM8887X=0 +serdes_tx_taps_50.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 6 lane51 +lane_to_serdes_map_nif_lane51.BCM8887X=rx55:tx49 +phy_rx_polarity_flip_phy51.BCM8887X=1 +phy_tx_polarity_flip_phy51.BCM8887X=1 +serdes_tx_taps_51.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 6 lane52 +lane_to_serdes_map_nif_lane52.BCM8887X=rx49:tx52 +phy_rx_polarity_flip_phy52.BCM8887X=1 +phy_tx_polarity_flip_phy52.BCM8887X=0 +serdes_tx_taps_52.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 6 lane53 +lane_to_serdes_map_nif_lane53.BCM8887X=rx48:tx53 +phy_rx_polarity_flip_phy53.BCM8887X=0 +phy_tx_polarity_flip_phy53.BCM8887X=1 +serdes_tx_taps_53.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 6 lane54 +lane_to_serdes_map_nif_lane54.BCM8887X=rx52:tx54 +phy_rx_polarity_flip_phy54.BCM8887X=0 +phy_tx_polarity_flip_phy54.BCM8887X=0 +serdes_tx_taps_54.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 6 lane55 +lane_to_serdes_map_nif_lane55.BCM8887X=rx54:tx48 +phy_rx_polarity_flip_phy55.BCM8887X=0 +phy_tx_polarity_flip_phy55.BCM8887X=1 +serdes_tx_taps_55.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + + +# ---------------------------------------------------------------------------------------------------- +# core_7 +# ---------------------------------------------------------------------------------------------------- +ucode_port_33.BCM8887X=CDGE4_14:core_1.25 +tm_port_header_type_out_33.BCM8887X=ETH +ucode_port_37.BCM8887X=CDGE4_15:core_1.29 +tm_port_header_type_out_37.BCM8887X=ETH + +# core 7 lane56 +lane_to_serdes_map_nif_lane56.BCM8887X=rx58:tx59 +phy_rx_polarity_flip_phy56.BCM8887X=1 +phy_tx_polarity_flip_phy56.BCM8887X=1 +serdes_tx_taps_56.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 7 lane57 +lane_to_serdes_map_nif_lane57.BCM8887X=rx59:tx61 +phy_rx_polarity_flip_phy57.BCM8887X=0 +phy_tx_polarity_flip_phy57.BCM8887X=1 +serdes_tx_taps_57.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 7 lane58 +lane_to_serdes_map_nif_lane58.BCM8887X=rx60:tx60 +phy_rx_polarity_flip_phy58.BCM8887X=0 +phy_tx_polarity_flip_phy58.BCM8887X=1 +serdes_tx_taps_58.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 7 lane59 +lane_to_serdes_map_nif_lane59.BCM8887X=rx62:tx56 +phy_rx_polarity_flip_phy59.BCM8887X=1 +phy_tx_polarity_flip_phy59.BCM8887X=1 +serdes_tx_taps_59.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 7 lane60 +lane_to_serdes_map_nif_lane60.BCM8887X=rx56:tx62 +phy_rx_polarity_flip_phy60.BCM8887X=0 +phy_tx_polarity_flip_phy60.BCM8887X=0 +serdes_tx_taps_60.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 7 lane61 +lane_to_serdes_map_nif_lane61.BCM8887X=rx57:tx58 +phy_rx_polarity_flip_phy61.BCM8887X=0 +phy_tx_polarity_flip_phy61.BCM8887X=0 +serdes_tx_taps_61.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 7 lane62 +lane_to_serdes_map_nif_lane62.BCM8887X=rx63:tx63 +phy_rx_polarity_flip_phy62.BCM8887X=0 +phy_tx_polarity_flip_phy62.BCM8887X=1 +serdes_tx_taps_62.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 7 lane63 +lane_to_serdes_map_nif_lane63.BCM8887X=rx61:tx57 +phy_rx_polarity_flip_phy63.BCM8887X=0 +phy_tx_polarity_flip_phy63.BCM8887X=1 +serdes_tx_taps_63.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + + +# ---------------------------------------------------------------------------------------------------- +# core_8 +# ---------------------------------------------------------------------------------------------------- +ucode_port_129.BCM8887X=CDGE4_16:core_2.1 +tm_port_header_type_out_129.BCM8887X=ETH +ucode_port_133.BCM8887X=CDGE4_17:core_2.5 +tm_port_header_type_out_133.BCM8887X=ETH + +# core 8 lane64 +lane_to_serdes_map_nif_lane64.BCM8887X=rx67:tx71 +phy_rx_polarity_flip_phy64.BCM8887X=0 +phy_tx_polarity_flip_phy64.BCM8887X=0 +serdes_tx_taps_64.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 8 lane65 +lane_to_serdes_map_nif_lane65.BCM8887X=rx66:tx65 +phy_rx_polarity_flip_phy65.BCM8887X=0 +phy_tx_polarity_flip_phy65.BCM8887X=1 +serdes_tx_taps_65.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 8 lane66 +lane_to_serdes_map_nif_lane66.BCM8887X=rx70:tx70 +phy_rx_polarity_flip_phy66.BCM8887X=1 +phy_tx_polarity_flip_phy66.BCM8887X=1 +serdes_tx_taps_66.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 8 lane67 +lane_to_serdes_map_nif_lane67.BCM8887X=rx68:tx66 +phy_rx_polarity_flip_phy67.BCM8887X=1 +phy_tx_polarity_flip_phy67.BCM8887X=0 +serdes_tx_taps_67.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 8 lane68 +lane_to_serdes_map_nif_lane68.BCM8887X=rx69:tx67 +phy_rx_polarity_flip_phy68.BCM8887X=0 +phy_tx_polarity_flip_phy68.BCM8887X=0 +serdes_tx_taps_68.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 8 lane69 +lane_to_serdes_map_nif_lane69.BCM8887X=rx71:tx69 +phy_rx_polarity_flip_phy69.BCM8887X=1 +phy_tx_polarity_flip_phy69.BCM8887X=1 +serdes_tx_taps_69.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 8 lane70 +lane_to_serdes_map_nif_lane70.BCM8887X=rx65:tx68 +phy_rx_polarity_flip_phy70.BCM8887X=0 +phy_tx_polarity_flip_phy70.BCM8887X=0 +serdes_tx_taps_70.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 8 lane71 +lane_to_serdes_map_nif_lane71.BCM8887X=rx64:tx64 +phy_rx_polarity_flip_phy71.BCM8887X=1 +phy_tx_polarity_flip_phy71.BCM8887X=1 +serdes_tx_taps_71.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + + +# ---------------------------------------------------------------------------------------------------- +# core_9 +# ---------------------------------------------------------------------------------------------------- +ucode_port_137.BCM8887X=CDGE4_18:core_2.9 +tm_port_header_type_out_137.BCM8887X=ETH +ucode_port_141.BCM8887X=CDGE4_19:core_2.13 +tm_port_header_type_out_141.BCM8887X=ETH + +# core 9 lane72 +lane_to_serdes_map_nif_lane72.BCM8887X=rx75:tx79 +phy_rx_polarity_flip_phy72.BCM8887X=0 +phy_tx_polarity_flip_phy72.BCM8887X=0 +serdes_tx_taps_72.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 9 lane73 +lane_to_serdes_map_nif_lane73.BCM8887X=rx74:tx73 +phy_rx_polarity_flip_phy73.BCM8887X=0 +phy_tx_polarity_flip_phy73.BCM8887X=1 +serdes_tx_taps_73.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 9 lane74 +lane_to_serdes_map_nif_lane74.BCM8887X=rx78:tx78 +phy_rx_polarity_flip_phy74.BCM8887X=1 +phy_tx_polarity_flip_phy74.BCM8887X=1 +serdes_tx_taps_74.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 9 lane75 +lane_to_serdes_map_nif_lane75.BCM8887X=rx76:tx74 +phy_rx_polarity_flip_phy75.BCM8887X=1 +phy_tx_polarity_flip_phy75.BCM8887X=0 +serdes_tx_taps_75.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 9 lane76 +lane_to_serdes_map_nif_lane76.BCM8887X=rx77:tx75 +phy_rx_polarity_flip_phy76.BCM8887X=0 +phy_tx_polarity_flip_phy76.BCM8887X=0 +serdes_tx_taps_76.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 9 lane77 +lane_to_serdes_map_nif_lane77.BCM8887X=rx79:tx77 +phy_rx_polarity_flip_phy77.BCM8887X=1 +phy_tx_polarity_flip_phy77.BCM8887X=1 +serdes_tx_taps_77.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 9 lane78 +lane_to_serdes_map_nif_lane78.BCM8887X=rx73:tx76 +phy_rx_polarity_flip_phy78.BCM8887X=0 +phy_tx_polarity_flip_phy78.BCM8887X=0 +serdes_tx_taps_78.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 9 lane79 +lane_to_serdes_map_nif_lane79.BCM8887X=rx72:tx72 +phy_rx_polarity_flip_phy79.BCM8887X=1 +phy_tx_polarity_flip_phy79.BCM8887X=1 +serdes_tx_taps_79.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + + +# ---------------------------------------------------------------------------------------------------- +# core_10 +# ---------------------------------------------------------------------------------------------------- +ucode_port_145.BCM8887X=CDGE4_20:core_2.17 +tm_port_header_type_out_145.BCM8887X=ETH +ucode_port_149.BCM8887X=CDGE4_21:core_2.21 +tm_port_header_type_out_149.BCM8887X=ETH + +# core 10 lane80 +lane_to_serdes_map_nif_lane80.BCM8887X=rx83:tx87 +phy_rx_polarity_flip_phy80.BCM8887X=0 +phy_tx_polarity_flip_phy80.BCM8887X=0 +serdes_tx_taps_80.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 10 lane81 +lane_to_serdes_map_nif_lane81.BCM8887X=rx82:tx81 +phy_rx_polarity_flip_phy81.BCM8887X=0 +phy_tx_polarity_flip_phy81.BCM8887X=1 +serdes_tx_taps_81.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 10 lane82 +lane_to_serdes_map_nif_lane82.BCM8887X=rx86:tx86 +phy_rx_polarity_flip_phy82.BCM8887X=1 +phy_tx_polarity_flip_phy82.BCM8887X=1 +serdes_tx_taps_82.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 10 lane83 +lane_to_serdes_map_nif_lane83.BCM8887X=rx84:tx82 +phy_rx_polarity_flip_phy83.BCM8887X=1 +phy_tx_polarity_flip_phy83.BCM8887X=0 +serdes_tx_taps_83.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 10 lane84 +lane_to_serdes_map_nif_lane84.BCM8887X=rx85:tx83 +phy_rx_polarity_flip_phy84.BCM8887X=0 +phy_tx_polarity_flip_phy84.BCM8887X=0 +serdes_tx_taps_84.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 10 lane85 +lane_to_serdes_map_nif_lane85.BCM8887X=rx87:tx85 +phy_rx_polarity_flip_phy85.BCM8887X=1 +phy_tx_polarity_flip_phy85.BCM8887X=1 +serdes_tx_taps_85.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 10 lane86 +lane_to_serdes_map_nif_lane86.BCM8887X=rx81:tx84 +phy_rx_polarity_flip_phy86.BCM8887X=0 +phy_tx_polarity_flip_phy86.BCM8887X=0 +serdes_tx_taps_86.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 10 lane87 +lane_to_serdes_map_nif_lane87.BCM8887X=rx80:tx80 +phy_rx_polarity_flip_phy87.BCM8887X=1 +phy_tx_polarity_flip_phy87.BCM8887X=1 +serdes_tx_taps_87.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + + +# ---------------------------------------------------------------------------------------------------- +# core_11 +# ---------------------------------------------------------------------------------------------------- +ucode_port_153.BCM8887X=CDGE4_22:core_2.25 +tm_port_header_type_out_153.BCM8887X=ETH +ucode_port_157.BCM8887X=CDGE4_23:core_2.29 +tm_port_header_type_out_157.BCM8887X=ETH + +# core 11 lane88 +lane_to_serdes_map_nif_lane88.BCM8887X=rx91:tx95 +phy_rx_polarity_flip_phy88.BCM8887X=0 +phy_tx_polarity_flip_phy88.BCM8887X=0 +serdes_tx_taps_88.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 11 lane89 +lane_to_serdes_map_nif_lane89.BCM8887X=rx90:tx89 +phy_rx_polarity_flip_phy89.BCM8887X=0 +phy_tx_polarity_flip_phy89.BCM8887X=1 +serdes_tx_taps_89.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 11 lane90 +lane_to_serdes_map_nif_lane90.BCM8887X=rx94:tx94 +phy_rx_polarity_flip_phy90.BCM8887X=1 +phy_tx_polarity_flip_phy90.BCM8887X=1 +serdes_tx_taps_90.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 11 lane91 +lane_to_serdes_map_nif_lane91.BCM8887X=rx92:tx90 +phy_rx_polarity_flip_phy91.BCM8887X=1 +phy_tx_polarity_flip_phy91.BCM8887X=0 +serdes_tx_taps_91.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 11 lane92 +lane_to_serdes_map_nif_lane92.BCM8887X=rx93:tx91 +phy_rx_polarity_flip_phy92.BCM8887X=0 +phy_tx_polarity_flip_phy92.BCM8887X=0 +serdes_tx_taps_92.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 11 lane93 +lane_to_serdes_map_nif_lane93.BCM8887X=rx95:tx93 +phy_rx_polarity_flip_phy93.BCM8887X=1 +phy_tx_polarity_flip_phy93.BCM8887X=1 +serdes_tx_taps_93.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 11 lane94 +lane_to_serdes_map_nif_lane94.BCM8887X=rx89:tx92 +phy_rx_polarity_flip_phy94.BCM8887X=0 +phy_tx_polarity_flip_phy94.BCM8887X=0 +serdes_tx_taps_94.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 11 lane95 +lane_to_serdes_map_nif_lane95.BCM8887X=rx88:tx88 +phy_rx_polarity_flip_phy95.BCM8887X=1 +phy_tx_polarity_flip_phy95.BCM8887X=1 +serdes_tx_taps_95.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + + +# ---------------------------------------------------------------------------------------------------- +# core_12 +# ---------------------------------------------------------------------------------------------------- +ucode_port_1.BCM8887X=CDGE4_24:core_3.1 +tm_port_header_type_out_1.BCM8887X=ETH +ucode_port_5.BCM8887X=CDGE4_25:core_3.5 +tm_port_header_type_out_5.BCM8887X=ETH + +# core 12 lane96 +lane_to_serdes_map_nif_lane96.BCM8887X=rx100:tx103 +phy_rx_polarity_flip_phy96.BCM8887X=1 +phy_tx_polarity_flip_phy96.BCM8887X=0 +serdes_tx_taps_96.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 12 lane97 +lane_to_serdes_map_nif_lane97.BCM8887X=rx96:tx98 +phy_rx_polarity_flip_phy97.BCM8887X=1 +phy_tx_polarity_flip_phy97.BCM8887X=1 +serdes_tx_taps_97.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 12 lane98 +lane_to_serdes_map_nif_lane98.BCM8887X=rx99:tx99 +phy_rx_polarity_flip_phy98.BCM8887X=0 +phy_tx_polarity_flip_phy98.BCM8887X=0 +serdes_tx_taps_98.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 12 lane99 +lane_to_serdes_map_nif_lane99.BCM8887X=rx101:tx97 +phy_rx_polarity_flip_phy99.BCM8887X=0 +phy_tx_polarity_flip_phy99.BCM8887X=0 +serdes_tx_taps_99.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 12 lane100 +lane_to_serdes_map_nif_lane100.BCM8887X=rx98:tx100 +phy_rx_polarity_flip_phy100.BCM8887X=1 +phy_tx_polarity_flip_phy100.BCM8887X=0 +serdes_tx_taps_100.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 12 lane101 +lane_to_serdes_map_nif_lane101.BCM8887X=rx103:tx96 +phy_rx_polarity_flip_phy101.BCM8887X=1 +phy_tx_polarity_flip_phy101.BCM8887X=0 +serdes_tx_taps_101.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 12 lane102 +lane_to_serdes_map_nif_lane102.BCM8887X=rx102:tx101 +phy_rx_polarity_flip_phy102.BCM8887X=0 +phy_tx_polarity_flip_phy102.BCM8887X=1 +serdes_tx_taps_102.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 12 lane103 +lane_to_serdes_map_nif_lane103.BCM8887X=rx97:tx102 +phy_rx_polarity_flip_phy103.BCM8887X=1 +phy_tx_polarity_flip_phy103.BCM8887X=1 +serdes_tx_taps_103.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + + +# ---------------------------------------------------------------------------------------------------- +# core_13 +# ---------------------------------------------------------------------------------------------------- +ucode_port_9.BCM8887X=CDGE4_26:core_3.9 +tm_port_header_type_out_9.BCM8887X=ETH +ucode_port_13.BCM8887X=CDGE4_27:core_3.13 +tm_port_header_type_out_13.BCM8887X=ETH + +# core 13 lane104 +lane_to_serdes_map_nif_lane104.BCM8887X=rx107:tx108 +phy_rx_polarity_flip_phy104.BCM8887X=1 +phy_tx_polarity_flip_phy104.BCM8887X=0 +serdes_tx_taps_104.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 13 lane105 +lane_to_serdes_map_nif_lane105.BCM8887X=rx106:tx107 +phy_rx_polarity_flip_phy105.BCM8887X=0 +phy_tx_polarity_flip_phy105.BCM8887X=1 +serdes_tx_taps_105.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 13 lane106 +lane_to_serdes_map_nif_lane106.BCM8887X=rx110:tx110 +phy_rx_polarity_flip_phy106.BCM8887X=0 +phy_tx_polarity_flip_phy106.BCM8887X=0 +serdes_tx_taps_106.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 13 lane107 +lane_to_serdes_map_nif_lane107.BCM8887X=rx108:tx109 +phy_rx_polarity_flip_phy107.BCM8887X=0 +phy_tx_polarity_flip_phy107.BCM8887X=1 +serdes_tx_taps_107.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 13 lane108 +lane_to_serdes_map_nif_lane108.BCM8887X=rx105:tx111 +phy_rx_polarity_flip_phy108.BCM8887X=1 +phy_tx_polarity_flip_phy108.BCM8887X=1 +serdes_tx_taps_108.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 13 lane109 +lane_to_serdes_map_nif_lane109.BCM8887X=rx104:tx104 +phy_rx_polarity_flip_phy109.BCM8887X=0 +phy_tx_polarity_flip_phy109.BCM8887X=0 +serdes_tx_taps_109.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 13 lane110 +lane_to_serdes_map_nif_lane110.BCM8887X=rx111:tx106 +phy_rx_polarity_flip_phy110.BCM8887X=1 +phy_tx_polarity_flip_phy110.BCM8887X=1 +serdes_tx_taps_110.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 13 lane111 +lane_to_serdes_map_nif_lane111.BCM8887X=rx109:tx105 +phy_rx_polarity_flip_phy111.BCM8887X=1 +phy_tx_polarity_flip_phy111.BCM8887X=1 +serdes_tx_taps_111.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + + +# ---------------------------------------------------------------------------------------------------- +# core_14 +# ---------------------------------------------------------------------------------------------------- +ucode_port_17.BCM8887X=CDGE4_28:core_3.17 +tm_port_header_type_out_17.BCM8887X=ETH +ucode_port_21.BCM8887X=CDGE4_29:core_3.21 +tm_port_header_type_out_21.BCM8887X=ETH + +# core 14 lane112 +lane_to_serdes_map_nif_lane112.BCM8887X=rx115:tx116 +phy_rx_polarity_flip_phy112.BCM8887X=1 +phy_tx_polarity_flip_phy112.BCM8887X=0 +serdes_tx_taps_112.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 14 lane113 +lane_to_serdes_map_nif_lane113.BCM8887X=rx114:tx115 +phy_rx_polarity_flip_phy113.BCM8887X=1 +phy_tx_polarity_flip_phy113.BCM8887X=1 +serdes_tx_taps_113.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 14 lane114 +lane_to_serdes_map_nif_lane114.BCM8887X=rx118:tx118 +phy_rx_polarity_flip_phy114.BCM8887X=0 +phy_tx_polarity_flip_phy114.BCM8887X=0 +serdes_tx_taps_114.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 14 lane115 +lane_to_serdes_map_nif_lane115.BCM8887X=rx116:tx117 +phy_rx_polarity_flip_phy115.BCM8887X=0 +phy_tx_polarity_flip_phy115.BCM8887X=1 +serdes_tx_taps_115.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 14 lane116 +lane_to_serdes_map_nif_lane116.BCM8887X=rx113:tx119 +phy_rx_polarity_flip_phy116.BCM8887X=1 +phy_tx_polarity_flip_phy116.BCM8887X=1 +serdes_tx_taps_116.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 14 lane117 +lane_to_serdes_map_nif_lane117.BCM8887X=rx112:tx112 +phy_rx_polarity_flip_phy117.BCM8887X=0 +phy_tx_polarity_flip_phy117.BCM8887X=0 +serdes_tx_taps_117.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 14 lane118 +lane_to_serdes_map_nif_lane118.BCM8887X=rx119:tx114 +phy_rx_polarity_flip_phy118.BCM8887X=1 +phy_tx_polarity_flip_phy118.BCM8887X=1 +serdes_tx_taps_118.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 14 lane119 +lane_to_serdes_map_nif_lane119.BCM8887X=rx117:tx113 +phy_rx_polarity_flip_phy119.BCM8887X=1 +phy_tx_polarity_flip_phy119.BCM8887X=1 +serdes_tx_taps_119.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + + +# ---------------------------------------------------------------------------------------------------- +# core_15 +# ---------------------------------------------------------------------------------------------------- +ucode_port_25.BCM8887X=CDGE4_30:core_3.25 +tm_port_header_type_out_25.BCM8887X=ETH +ucode_port_29.BCM8887X=CDGE4_31:core_3.29 +tm_port_header_type_out_29.BCM8887X=ETH + +# core 15 lane120 +lane_to_serdes_map_nif_lane120.BCM8887X=rx123:tx124 +phy_rx_polarity_flip_phy120.BCM8887X=1 +phy_tx_polarity_flip_phy120.BCM8887X=0 +serdes_tx_taps_120.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 15 lane121 +lane_to_serdes_map_nif_lane121.BCM8887X=rx122:tx123 +phy_rx_polarity_flip_phy121.BCM8887X=1 +phy_tx_polarity_flip_phy121.BCM8887X=1 +serdes_tx_taps_121.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 15 lane122 +lane_to_serdes_map_nif_lane122.BCM8887X=rx126:tx126 +phy_rx_polarity_flip_phy122.BCM8887X=0 +phy_tx_polarity_flip_phy122.BCM8887X=0 +serdes_tx_taps_122.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 15 lane123 +lane_to_serdes_map_nif_lane123.BCM8887X=rx124:tx125 +phy_rx_polarity_flip_phy123.BCM8887X=0 +phy_tx_polarity_flip_phy123.BCM8887X=1 +serdes_tx_taps_123.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 15 lane124 +lane_to_serdes_map_nif_lane124.BCM8887X=rx121:tx127 +phy_rx_polarity_flip_phy124.BCM8887X=1 +phy_tx_polarity_flip_phy124.BCM8887X=1 +serdes_tx_taps_124.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 15 lane125 +lane_to_serdes_map_nif_lane125.BCM8887X=rx120:tx120 +phy_rx_polarity_flip_phy125.BCM8887X=0 +phy_tx_polarity_flip_phy125.BCM8887X=0 +serdes_tx_taps_125.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 15 lane126 +lane_to_serdes_map_nif_lane126.BCM8887X=rx127:tx122 +phy_rx_polarity_flip_phy126.BCM8887X=1 +phy_tx_polarity_flip_phy126.BCM8887X=1 +serdes_tx_taps_126.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 15 lane127 +lane_to_serdes_map_nif_lane127.BCM8887X=rx125:tx121 +phy_rx_polarity_flip_phy127.BCM8887X=1 +phy_tx_polarity_flip_phy127.BCM8887X=1 +serdes_tx_taps_127.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + + +# ---------------------------------------------------------------------------------------------------- +# core_16 +# ---------------------------------------------------------------------------------------------------- +ucode_port_65.BCM8887X=CDGE4_32:core_4.1 +tm_port_header_type_out_65.BCM8887X=ETH +ucode_port_69.BCM8887X=CDGE4_33:core_4.5 +tm_port_header_type_out_69.BCM8887X=ETH + +# core 16 lane128 +lane_to_serdes_map_nif_lane128.BCM8887X=rx131:tx135 +phy_rx_polarity_flip_phy128.BCM8887X=0 +phy_tx_polarity_flip_phy128.BCM8887X=0 +serdes_tx_taps_128.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 16 lane129 +lane_to_serdes_map_nif_lane129.BCM8887X=rx130:tx131 +phy_rx_polarity_flip_phy129.BCM8887X=0 +phy_tx_polarity_flip_phy129.BCM8887X=1 +serdes_tx_taps_129.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 16 lane130 +lane_to_serdes_map_nif_lane130.BCM8887X=rx129:tx129 +phy_rx_polarity_flip_phy130.BCM8887X=1 +phy_tx_polarity_flip_phy130.BCM8887X=1 +serdes_tx_taps_130.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 16 lane131 +lane_to_serdes_map_nif_lane131.BCM8887X=rx128:tx130 +phy_rx_polarity_flip_phy131.BCM8887X=0 +phy_tx_polarity_flip_phy131.BCM8887X=1 +serdes_tx_taps_131.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 16 lane132 +lane_to_serdes_map_nif_lane132.BCM8887X=rx133:tx132 +phy_rx_polarity_flip_phy132.BCM8887X=1 +phy_tx_polarity_flip_phy132.BCM8887X=1 +serdes_tx_taps_132.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 16 lane133 +lane_to_serdes_map_nif_lane133.BCM8887X=rx135:tx133 +phy_rx_polarity_flip_phy133.BCM8887X=0 +phy_tx_polarity_flip_phy133.BCM8887X=0 +serdes_tx_taps_133.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 16 lane134 +lane_to_serdes_map_nif_lane134.BCM8887X=rx132:tx128 +phy_rx_polarity_flip_phy134.BCM8887X=1 +phy_tx_polarity_flip_phy134.BCM8887X=1 +serdes_tx_taps_134.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 16 lane135 +lane_to_serdes_map_nif_lane135.BCM8887X=rx134:tx134 +phy_rx_polarity_flip_phy135.BCM8887X=0 +phy_tx_polarity_flip_phy135.BCM8887X=1 +serdes_tx_taps_135.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + + +# ---------------------------------------------------------------------------------------------------- +# core_17 +# ---------------------------------------------------------------------------------------------------- +ucode_port_73.BCM8887X=CDGE4_34:core_4.9 +tm_port_header_type_out_73.BCM8887X=ETH +ucode_port_77.BCM8887X=CDGE4_35:core_4.13 +tm_port_header_type_out_77.BCM8887X=ETH + +# core 17 lane136 +lane_to_serdes_map_nif_lane136.BCM8887X=rx139:tx143 +phy_rx_polarity_flip_phy136.BCM8887X=0 +phy_tx_polarity_flip_phy136.BCM8887X=0 +serdes_tx_taps_136.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 17 lane137 +lane_to_serdes_map_nif_lane137.BCM8887X=rx138:tx139 +phy_rx_polarity_flip_phy137.BCM8887X=0 +phy_tx_polarity_flip_phy137.BCM8887X=1 +serdes_tx_taps_137.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 17 lane138 +lane_to_serdes_map_nif_lane138.BCM8887X=rx137:tx137 +phy_rx_polarity_flip_phy138.BCM8887X=1 +phy_tx_polarity_flip_phy138.BCM8887X=1 +serdes_tx_taps_138.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 17 lane139 +lane_to_serdes_map_nif_lane139.BCM8887X=rx136:tx138 +phy_rx_polarity_flip_phy139.BCM8887X=1 +phy_tx_polarity_flip_phy139.BCM8887X=1 +serdes_tx_taps_139.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 17 lane140 +lane_to_serdes_map_nif_lane140.BCM8887X=rx141:tx140 +phy_rx_polarity_flip_phy140.BCM8887X=1 +phy_tx_polarity_flip_phy140.BCM8887X=1 +serdes_tx_taps_140.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 17 lane141 +lane_to_serdes_map_nif_lane141.BCM8887X=rx143:tx141 +phy_rx_polarity_flip_phy141.BCM8887X=0 +phy_tx_polarity_flip_phy141.BCM8887X=0 +serdes_tx_taps_141.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 17 lane142 +lane_to_serdes_map_nif_lane142.BCM8887X=rx140:tx136 +phy_rx_polarity_flip_phy142.BCM8887X=1 +phy_tx_polarity_flip_phy142.BCM8887X=1 +serdes_tx_taps_142.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 17 lane143 +lane_to_serdes_map_nif_lane143.BCM8887X=rx142:tx142 +phy_rx_polarity_flip_phy143.BCM8887X=0 +phy_tx_polarity_flip_phy143.BCM8887X=1 +serdes_tx_taps_143.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + + +# ---------------------------------------------------------------------------------------------------- +# core_18 +# ---------------------------------------------------------------------------------------------------- +ucode_port_81.BCM8887X=CDGE4_36:core_4.17 +tm_port_header_type_out_81.BCM8887X=ETH +ucode_port_85.BCM8887X=CDGE4_37:core_4.21 +tm_port_header_type_out_85.BCM8887X=ETH + +# core 18 lane144 +lane_to_serdes_map_nif_lane144.BCM8887X=rx147:tx151 +phy_rx_polarity_flip_phy144.BCM8887X=0 +phy_tx_polarity_flip_phy144.BCM8887X=0 +serdes_tx_taps_144.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 18 lane145 +lane_to_serdes_map_nif_lane145.BCM8887X=rx146:tx147 +phy_rx_polarity_flip_phy145.BCM8887X=0 +phy_tx_polarity_flip_phy145.BCM8887X=1 +serdes_tx_taps_145.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 18 lane146 +lane_to_serdes_map_nif_lane146.BCM8887X=rx145:tx145 +phy_rx_polarity_flip_phy146.BCM8887X=1 +phy_tx_polarity_flip_phy146.BCM8887X=1 +serdes_tx_taps_146.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 18 lane147 +lane_to_serdes_map_nif_lane147.BCM8887X=rx144:tx146 +phy_rx_polarity_flip_phy147.BCM8887X=0 +phy_tx_polarity_flip_phy147.BCM8887X=1 +serdes_tx_taps_147.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 18 lane148 +lane_to_serdes_map_nif_lane148.BCM8887X=rx149:tx148 +phy_rx_polarity_flip_phy148.BCM8887X=1 +phy_tx_polarity_flip_phy148.BCM8887X=1 +serdes_tx_taps_148.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 18 lane149 +lane_to_serdes_map_nif_lane149.BCM8887X=rx151:tx149 +phy_rx_polarity_flip_phy149.BCM8887X=0 +phy_tx_polarity_flip_phy149.BCM8887X=0 +serdes_tx_taps_149.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 18 lane150 +lane_to_serdes_map_nif_lane150.BCM8887X=rx148:tx144 +phy_rx_polarity_flip_phy150.BCM8887X=1 +phy_tx_polarity_flip_phy150.BCM8887X=1 +serdes_tx_taps_150.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 18 lane151 +lane_to_serdes_map_nif_lane151.BCM8887X=rx150:tx150 +phy_rx_polarity_flip_phy151.BCM8887X=0 +phy_tx_polarity_flip_phy151.BCM8887X=1 +serdes_tx_taps_151.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + + +# ---------------------------------------------------------------------------------------------------- +# core_19 +# ---------------------------------------------------------------------------------------------------- +ucode_port_89.BCM8887X=CDGE4_38:core_4.25 +tm_port_header_type_out_89.BCM8887X=ETH +ucode_port_93.BCM8887X=CDGE4_39:core_4.29 +tm_port_header_type_out_93.BCM8887X=ETH + +# core 19 lane152 +lane_to_serdes_map_nif_lane152.BCM8887X=rx155:tx156 +phy_rx_polarity_flip_phy152.BCM8887X=0 +phy_tx_polarity_flip_phy152.BCM8887X=1 +serdes_tx_taps_152.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 19 lane153 +lane_to_serdes_map_nif_lane153.BCM8887X=rx154:tx155 +phy_rx_polarity_flip_phy153.BCM8887X=0 +phy_tx_polarity_flip_phy153.BCM8887X=0 +serdes_tx_taps_153.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 19 lane154 +lane_to_serdes_map_nif_lane154.BCM8887X=rx158:tx158 +phy_rx_polarity_flip_phy154.BCM8887X=1 +phy_tx_polarity_flip_phy154.BCM8887X=1 +serdes_tx_taps_154.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 19 lane155 +lane_to_serdes_map_nif_lane155.BCM8887X=rx156:tx157 +phy_rx_polarity_flip_phy155.BCM8887X=1 +phy_tx_polarity_flip_phy155.BCM8887X=0 +serdes_tx_taps_155.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 19 lane156 +lane_to_serdes_map_nif_lane156.BCM8887X=rx153:tx159 +phy_rx_polarity_flip_phy156.BCM8887X=0 +phy_tx_polarity_flip_phy156.BCM8887X=0 +serdes_tx_taps_156.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 19 lane157 +lane_to_serdes_map_nif_lane157.BCM8887X=rx152:tx152 +phy_rx_polarity_flip_phy157.BCM8887X=1 +phy_tx_polarity_flip_phy157.BCM8887X=1 +serdes_tx_taps_157.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 19 lane158 +lane_to_serdes_map_nif_lane158.BCM8887X=rx159:tx154 +phy_rx_polarity_flip_phy158.BCM8887X=0 +phy_tx_polarity_flip_phy158.BCM8887X=0 +serdes_tx_taps_158.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 19 lane159 +lane_to_serdes_map_nif_lane159.BCM8887X=rx157:tx153 +phy_rx_polarity_flip_phy159.BCM8887X=0 +phy_tx_polarity_flip_phy159.BCM8887X=0 +serdes_tx_taps_159.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + + +# ---------------------------------------------------------------------------------------------------- +# core_20 +# ---------------------------------------------------------------------------------------------------- +ucode_port_193.BCM8887X=CDGE4_40:core_5.1 +tm_port_header_type_out_193.BCM8887X=ETH +ucode_port_197.BCM8887X=CDGE4_41:core_5.5 +tm_port_header_type_out_197.BCM8887X=ETH + +# core 20 lane160 +lane_to_serdes_map_nif_lane160.BCM8887X=rx166:tx167 +phy_rx_polarity_flip_phy160.BCM8887X=0 +phy_tx_polarity_flip_phy160.BCM8887X=1 +serdes_tx_taps_160.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 20 lane161 +lane_to_serdes_map_nif_lane161.BCM8887X=rx164:tx163 +phy_rx_polarity_flip_phy161.BCM8887X=1 +phy_tx_polarity_flip_phy161.BCM8887X=0 +serdes_tx_taps_161.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 20 lane162 +lane_to_serdes_map_nif_lane162.BCM8887X=rx160:tx162 +phy_rx_polarity_flip_phy162.BCM8887X=0 +phy_tx_polarity_flip_phy162.BCM8887X=1 +serdes_tx_taps_162.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 20 lane163 +lane_to_serdes_map_nif_lane163.BCM8887X=rx161:tx161 +phy_rx_polarity_flip_phy163.BCM8887X=0 +phy_tx_polarity_flip_phy163.BCM8887X=1 +serdes_tx_taps_163.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 20 lane164 +lane_to_serdes_map_nif_lane164.BCM8887X=rx162:tx166 +phy_rx_polarity_flip_phy164.BCM8887X=0 +phy_tx_polarity_flip_phy164.BCM8887X=1 +serdes_tx_taps_164.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 20 lane165 +lane_to_serdes_map_nif_lane165.BCM8887X=rx163:tx160 +phy_rx_polarity_flip_phy165.BCM8887X=0 +phy_tx_polarity_flip_phy165.BCM8887X=1 +serdes_tx_taps_165.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 20 lane166 +lane_to_serdes_map_nif_lane166.BCM8887X=rx167:tx164 +phy_rx_polarity_flip_phy166.BCM8887X=1 +phy_tx_polarity_flip_phy166.BCM8887X=1 +serdes_tx_taps_166.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 20 lane167 +lane_to_serdes_map_nif_lane167.BCM8887X=rx165:tx165 +phy_rx_polarity_flip_phy167.BCM8887X=0 +phy_tx_polarity_flip_phy167.BCM8887X=1 +serdes_tx_taps_167.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + + +# ---------------------------------------------------------------------------------------------------- +# core_21 +# ---------------------------------------------------------------------------------------------------- +ucode_port_201.BCM8887X=CDGE4_42:core_5.9 +tm_port_header_type_out_201.BCM8887X=ETH +ucode_port_205.BCM8887X=CDGE4_43:core_5.13 +tm_port_header_type_out_205.BCM8887X=ETH + +# core 21 lane168 +lane_to_serdes_map_nif_lane168.BCM8887X=rx170:tx174 +phy_rx_polarity_flip_phy168.BCM8887X=0 +phy_tx_polarity_flip_phy168.BCM8887X=1 +serdes_tx_taps_168.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 21 lane169 +lane_to_serdes_map_nif_lane169.BCM8887X=rx171:tx168 +phy_rx_polarity_flip_phy169.BCM8887X=0 +phy_tx_polarity_flip_phy169.BCM8887X=1 +serdes_tx_taps_169.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 21 lane170 +lane_to_serdes_map_nif_lane170.BCM8887X=rx175:tx172 +phy_rx_polarity_flip_phy170.BCM8887X=1 +phy_tx_polarity_flip_phy170.BCM8887X=1 +serdes_tx_taps_170.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 21 lane171 +lane_to_serdes_map_nif_lane171.BCM8887X=rx173:tx173 +phy_rx_polarity_flip_phy171.BCM8887X=0 +phy_tx_polarity_flip_phy171.BCM8887X=1 +serdes_tx_taps_171.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 21 lane172 +lane_to_serdes_map_nif_lane172.BCM8887X=rx174:tx175 +phy_rx_polarity_flip_phy172.BCM8887X=0 +phy_tx_polarity_flip_phy172.BCM8887X=1 +serdes_tx_taps_172.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 21 lane173 +lane_to_serdes_map_nif_lane173.BCM8887X=rx172:tx171 +phy_rx_polarity_flip_phy173.BCM8887X=1 +phy_tx_polarity_flip_phy173.BCM8887X=0 +serdes_tx_taps_173.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 21 lane174 +lane_to_serdes_map_nif_lane174.BCM8887X=rx168:tx170 +phy_rx_polarity_flip_phy174.BCM8887X=0 +phy_tx_polarity_flip_phy174.BCM8887X=1 +serdes_tx_taps_174.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 21 lane175 +lane_to_serdes_map_nif_lane175.BCM8887X=rx169:tx169 +phy_rx_polarity_flip_phy175.BCM8887X=0 +phy_tx_polarity_flip_phy175.BCM8887X=1 +serdes_tx_taps_175.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + + +# ---------------------------------------------------------------------------------------------------- +# core_22 +# ---------------------------------------------------------------------------------------------------- +ucode_port_209.BCM8887X=CDGE4_44:core_5.17 +tm_port_header_type_out_209.BCM8887X=ETH +ucode_port_213.BCM8887X=CDGE4_45:core_5.21 +tm_port_header_type_out_213.BCM8887X=ETH + +# core 22 lane176 +lane_to_serdes_map_nif_lane176.BCM8887X=rx178:tx182 +phy_rx_polarity_flip_phy176.BCM8887X=0 +phy_tx_polarity_flip_phy176.BCM8887X=1 +serdes_tx_taps_176.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 22 lane177 +lane_to_serdes_map_nif_lane177.BCM8887X=rx179:tx176 +phy_rx_polarity_flip_phy177.BCM8887X=0 +phy_tx_polarity_flip_phy177.BCM8887X=1 +serdes_tx_taps_177.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 22 lane178 +lane_to_serdes_map_nif_lane178.BCM8887X=rx183:tx180 +phy_rx_polarity_flip_phy178.BCM8887X=1 +phy_tx_polarity_flip_phy178.BCM8887X=1 +serdes_tx_taps_178.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 22 lane179 +lane_to_serdes_map_nif_lane179.BCM8887X=rx181:tx181 +phy_rx_polarity_flip_phy179.BCM8887X=0 +phy_tx_polarity_flip_phy179.BCM8887X=1 +serdes_tx_taps_179.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 22 lane180 +lane_to_serdes_map_nif_lane180.BCM8887X=rx182:tx183 +phy_rx_polarity_flip_phy180.BCM8887X=0 +phy_tx_polarity_flip_phy180.BCM8887X=1 +serdes_tx_taps_180.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 22 lane181 +lane_to_serdes_map_nif_lane181.BCM8887X=rx180:tx179 +phy_rx_polarity_flip_phy181.BCM8887X=1 +phy_tx_polarity_flip_phy181.BCM8887X=0 +serdes_tx_taps_181.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 22 lane182 +lane_to_serdes_map_nif_lane182.BCM8887X=rx176:tx178 +phy_rx_polarity_flip_phy182.BCM8887X=0 +phy_tx_polarity_flip_phy182.BCM8887X=1 +serdes_tx_taps_182.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 22 lane183 +lane_to_serdes_map_nif_lane183.BCM8887X=rx177:tx177 +phy_rx_polarity_flip_phy183.BCM8887X=0 +phy_tx_polarity_flip_phy183.BCM8887X=1 +serdes_tx_taps_183.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + + +# ---------------------------------------------------------------------------------------------------- +# core_23 +# ---------------------------------------------------------------------------------------------------- +ucode_port_217.BCM8887X=CDGE4_46:core_5.25 +tm_port_header_type_out_217.BCM8887X=ETH +ucode_port_221.BCM8887X=CDGE4_47:core_5.29 +tm_port_header_type_out_221.BCM8887X=ETH + +# core 23 lane184 +lane_to_serdes_map_nif_lane184.BCM8887X=rx187:tx191 +phy_rx_polarity_flip_phy184.BCM8887X=1 +phy_tx_polarity_flip_phy184.BCM8887X=1 +serdes_tx_taps_184.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 23 lane185 +lane_to_serdes_map_nif_lane185.BCM8887X=rx186:tx185 +phy_rx_polarity_flip_phy185.BCM8887X=1 +phy_tx_polarity_flip_phy185.BCM8887X=0 +serdes_tx_taps_185.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 23 lane186 +lane_to_serdes_map_nif_lane186.BCM8887X=rx190:tx190 +phy_rx_polarity_flip_phy186.BCM8887X=0 +phy_tx_polarity_flip_phy186.BCM8887X=0 +serdes_tx_taps_186.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 23 lane187 +lane_to_serdes_map_nif_lane187.BCM8887X=rx188:tx186 +phy_rx_polarity_flip_phy187.BCM8887X=0 +phy_tx_polarity_flip_phy187.BCM8887X=1 +serdes_tx_taps_187.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 23 lane188 +lane_to_serdes_map_nif_lane188.BCM8887X=rx189:tx187 +phy_rx_polarity_flip_phy188.BCM8887X=1 +phy_tx_polarity_flip_phy188.BCM8887X=1 +serdes_tx_taps_188.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 23 lane189 +lane_to_serdes_map_nif_lane189.BCM8887X=rx191:tx189 +phy_rx_polarity_flip_phy189.BCM8887X=0 +phy_tx_polarity_flip_phy189.BCM8887X=0 +serdes_tx_taps_189.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 23 lane190 +lane_to_serdes_map_nif_lane190.BCM8887X=rx185:tx188 +phy_rx_polarity_flip_phy190.BCM8887X=1 +phy_tx_polarity_flip_phy190.BCM8887X=1 +serdes_tx_taps_190.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 23 lane191 +lane_to_serdes_map_nif_lane191.BCM8887X=rx184:tx184 +phy_rx_polarity_flip_phy191.BCM8887X=0 +phy_tx_polarity_flip_phy191.BCM8887X=0 +serdes_tx_taps_191.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + + +# ---------------------------------------------------------------------------------------------------- +# core_24 +# ---------------------------------------------------------------------------------------------------- +ucode_port_121.BCM8887X=CDGE4_48:core_6.1 +tm_port_header_type_out_121.BCM8887X=ETH +ucode_port_125.BCM8887X=CDGE4_49:core_6.5 +tm_port_header_type_out_125.BCM8887X=ETH + +# core 24 lane192 +lane_to_serdes_map_nif_lane192.BCM8887X=rx194:tx195 +phy_rx_polarity_flip_phy192.BCM8887X=0 +phy_tx_polarity_flip_phy192.BCM8887X=0 +serdes_tx_taps_192.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 24 lane193 +lane_to_serdes_map_nif_lane193.BCM8887X=rx195:tx197 +phy_rx_polarity_flip_phy193.BCM8887X=1 +phy_tx_polarity_flip_phy193.BCM8887X=0 +serdes_tx_taps_193.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 24 lane194 +lane_to_serdes_map_nif_lane194.BCM8887X=rx196:tx196 +phy_rx_polarity_flip_phy194.BCM8887X=1 +phy_tx_polarity_flip_phy194.BCM8887X=0 +serdes_tx_taps_194.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 24 lane195 +lane_to_serdes_map_nif_lane195.BCM8887X=rx198:tx192 +phy_rx_polarity_flip_phy195.BCM8887X=0 +phy_tx_polarity_flip_phy195.BCM8887X=0 +serdes_tx_taps_195.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 24 lane196 +lane_to_serdes_map_nif_lane196.BCM8887X=rx192:tx198 +phy_rx_polarity_flip_phy196.BCM8887X=1 +phy_tx_polarity_flip_phy196.BCM8887X=1 +serdes_tx_taps_196.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 24 lane197 +lane_to_serdes_map_nif_lane197.BCM8887X=rx193:tx194 +phy_rx_polarity_flip_phy197.BCM8887X=0 +phy_tx_polarity_flip_phy197.BCM8887X=1 +serdes_tx_taps_197.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 24 lane198 +lane_to_serdes_map_nif_lane198.BCM8887X=rx199:tx199 +phy_rx_polarity_flip_phy198.BCM8887X=1 +phy_tx_polarity_flip_phy198.BCM8887X=0 +serdes_tx_taps_198.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 24 lane199 +lane_to_serdes_map_nif_lane199.BCM8887X=rx197:tx193 +phy_rx_polarity_flip_phy199.BCM8887X=1 +phy_tx_polarity_flip_phy199.BCM8887X=0 +serdes_tx_taps_199.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + + +# ---------------------------------------------------------------------------------------------------- +# core_25 +# ---------------------------------------------------------------------------------------------------- +ucode_port_113.BCM8887X=CDGE4_50:core_6.9 +tm_port_header_type_out_113.BCM8887X=ETH +ucode_port_117.BCM8887X=CDGE4_51:core_6.13 +tm_port_header_type_out_117.BCM8887X=ETH + +# core 25 lane200 +lane_to_serdes_map_nif_lane200.BCM8887X=rx202:tx203 +phy_rx_polarity_flip_phy200.BCM8887X=0 +phy_tx_polarity_flip_phy200.BCM8887X=0 +serdes_tx_taps_200.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 25 lane201 +lane_to_serdes_map_nif_lane201.BCM8887X=rx203:tx205 +phy_rx_polarity_flip_phy201.BCM8887X=1 +phy_tx_polarity_flip_phy201.BCM8887X=0 +serdes_tx_taps_201.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 25 lane202 +lane_to_serdes_map_nif_lane202.BCM8887X=rx204:tx204 +phy_rx_polarity_flip_phy202.BCM8887X=1 +phy_tx_polarity_flip_phy202.BCM8887X=0 +serdes_tx_taps_202.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 25 lane203 +lane_to_serdes_map_nif_lane203.BCM8887X=rx206:tx200 +phy_rx_polarity_flip_phy203.BCM8887X=0 +phy_tx_polarity_flip_phy203.BCM8887X=0 +serdes_tx_taps_203.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 25 lane204 +lane_to_serdes_map_nif_lane204.BCM8887X=rx200:tx206 +phy_rx_polarity_flip_phy204.BCM8887X=1 +phy_tx_polarity_flip_phy204.BCM8887X=1 +serdes_tx_taps_204.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 25 lane205 +lane_to_serdes_map_nif_lane205.BCM8887X=rx201:tx202 +phy_rx_polarity_flip_phy205.BCM8887X=1 +phy_tx_polarity_flip_phy205.BCM8887X=1 +serdes_tx_taps_205.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 25 lane206 +lane_to_serdes_map_nif_lane206.BCM8887X=rx207:tx207 +phy_rx_polarity_flip_phy206.BCM8887X=1 +phy_tx_polarity_flip_phy206.BCM8887X=0 +serdes_tx_taps_206.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 25 lane207 +lane_to_serdes_map_nif_lane207.BCM8887X=rx205:tx201 +phy_rx_polarity_flip_phy207.BCM8887X=1 +phy_tx_polarity_flip_phy207.BCM8887X=0 +serdes_tx_taps_207.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + + +# ---------------------------------------------------------------------------------------------------- +# core_26 +# ---------------------------------------------------------------------------------------------------- +ucode_port_105.BCM8887X=CDGE4_52:core_6.17 +tm_port_header_type_out_105.BCM8887X=ETH +ucode_port_109.BCM8887X=CDGE4_53:core_6.21 +tm_port_header_type_out_109.BCM8887X=ETH + +# core 26 lane208 +lane_to_serdes_map_nif_lane208.BCM8887X=rx210:tx211 +phy_rx_polarity_flip_phy208.BCM8887X=0 +phy_tx_polarity_flip_phy208.BCM8887X=0 +serdes_tx_taps_208.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 26 lane209 +lane_to_serdes_map_nif_lane209.BCM8887X=rx211:tx213 +phy_rx_polarity_flip_phy209.BCM8887X=1 +phy_tx_polarity_flip_phy209.BCM8887X=0 +serdes_tx_taps_209.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 26 lane210 +lane_to_serdes_map_nif_lane210.BCM8887X=rx212:tx212 +phy_rx_polarity_flip_phy210.BCM8887X=1 +phy_tx_polarity_flip_phy210.BCM8887X=0 +serdes_tx_taps_210.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 26 lane211 +lane_to_serdes_map_nif_lane211.BCM8887X=rx214:tx208 +phy_rx_polarity_flip_phy211.BCM8887X=0 +phy_tx_polarity_flip_phy211.BCM8887X=0 +serdes_tx_taps_211.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 26 lane212 +lane_to_serdes_map_nif_lane212.BCM8887X=rx208:tx214 +phy_rx_polarity_flip_phy212.BCM8887X=1 +phy_tx_polarity_flip_phy212.BCM8887X=1 +serdes_tx_taps_212.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 26 lane213 +lane_to_serdes_map_nif_lane213.BCM8887X=rx209:tx210 +phy_rx_polarity_flip_phy213.BCM8887X=1 +phy_tx_polarity_flip_phy213.BCM8887X=1 +serdes_tx_taps_213.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 26 lane214 +lane_to_serdes_map_nif_lane214.BCM8887X=rx215:tx215 +phy_rx_polarity_flip_phy214.BCM8887X=1 +phy_tx_polarity_flip_phy214.BCM8887X=0 +serdes_tx_taps_214.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 26 lane215 +lane_to_serdes_map_nif_lane215.BCM8887X=rx213:tx209 +phy_rx_polarity_flip_phy215.BCM8887X=1 +phy_tx_polarity_flip_phy215.BCM8887X=0 +serdes_tx_taps_215.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + + +# ---------------------------------------------------------------------------------------------------- +# core_27 +# ---------------------------------------------------------------------------------------------------- +ucode_port_97.BCM8887X=CDGE4_54:core_6.25 +tm_port_header_type_out_97.BCM8887X=ETH +ucode_port_101.BCM8887X=CDGE4_55:core_6.29 +tm_port_header_type_out_101.BCM8887X=ETH + +# core 27 lane216 +lane_to_serdes_map_nif_lane216.BCM8887X=rx218:tx219 +phy_rx_polarity_flip_phy216.BCM8887X=0 +phy_tx_polarity_flip_phy216.BCM8887X=0 +serdes_tx_taps_216.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 27 lane217 +lane_to_serdes_map_nif_lane217.BCM8887X=rx219:tx221 +phy_rx_polarity_flip_phy217.BCM8887X=1 +phy_tx_polarity_flip_phy217.BCM8887X=0 +serdes_tx_taps_217.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 27 lane218 +lane_to_serdes_map_nif_lane218.BCM8887X=rx220:tx220 +phy_rx_polarity_flip_phy218.BCM8887X=1 +phy_tx_polarity_flip_phy218.BCM8887X=0 +serdes_tx_taps_218.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 27 lane219 +lane_to_serdes_map_nif_lane219.BCM8887X=rx222:tx216 +phy_rx_polarity_flip_phy219.BCM8887X=0 +phy_tx_polarity_flip_phy219.BCM8887X=0 +serdes_tx_taps_219.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 27 lane220 +lane_to_serdes_map_nif_lane220.BCM8887X=rx216:tx222 +phy_rx_polarity_flip_phy220.BCM8887X=1 +phy_tx_polarity_flip_phy220.BCM8887X=1 +serdes_tx_taps_220.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 27 lane221 +lane_to_serdes_map_nif_lane221.BCM8887X=rx217:tx218 +phy_rx_polarity_flip_phy221.BCM8887X=1 +phy_tx_polarity_flip_phy221.BCM8887X=1 +serdes_tx_taps_221.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 27 lane222 +lane_to_serdes_map_nif_lane222.BCM8887X=rx223:tx223 +phy_rx_polarity_flip_phy222.BCM8887X=1 +phy_tx_polarity_flip_phy222.BCM8887X=0 +serdes_tx_taps_222.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 27 lane223 +lane_to_serdes_map_nif_lane223.BCM8887X=rx221:tx217 +phy_rx_polarity_flip_phy223.BCM8887X=1 +phy_tx_polarity_flip_phy223.BCM8887X=0 +serdes_tx_taps_223.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + + +# ---------------------------------------------------------------------------------------------------- +# core_28 +# ---------------------------------------------------------------------------------------------------- +ucode_port_249.BCM8887X=CDGE4_56:core_7.1 +tm_port_header_type_out_249.BCM8887X=ETH +ucode_port_253.BCM8887X=CDGE4_57:core_7.5 +tm_port_header_type_out_253.BCM8887X=ETH + +# core 28 lane224 +lane_to_serdes_map_nif_lane224.BCM8887X=rx224:tx229 +phy_rx_polarity_flip_phy224.BCM8887X=0 +phy_tx_polarity_flip_phy224.BCM8887X=1 +serdes_tx_taps_224.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 28 lane225 +lane_to_serdes_map_nif_lane225.BCM8887X=rx228:tx230 +phy_rx_polarity_flip_phy225.BCM8887X=1 +phy_tx_polarity_flip_phy225.BCM8887X=0 +serdes_tx_taps_225.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 28 lane226 +lane_to_serdes_map_nif_lane226.BCM8887X=rx229:tx228 +phy_rx_polarity_flip_phy226.BCM8887X=1 +phy_tx_polarity_flip_phy226.BCM8887X=0 +serdes_tx_taps_226.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 28 lane227 +lane_to_serdes_map_nif_lane227.BCM8887X=rx227:tx224 +phy_rx_polarity_flip_phy227.BCM8887X=0 +phy_tx_polarity_flip_phy227.BCM8887X=1 +serdes_tx_taps_227.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 28 lane228 +lane_to_serdes_map_nif_lane228.BCM8887X=rx225:tx231 +phy_rx_polarity_flip_phy228.BCM8887X=0 +phy_tx_polarity_flip_phy228.BCM8887X=0 +serdes_tx_taps_228.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 28 lane229 +lane_to_serdes_map_nif_lane229.BCM8887X=rx230:tx226 +phy_rx_polarity_flip_phy229.BCM8887X=0 +phy_tx_polarity_flip_phy229.BCM8887X=0 +serdes_tx_taps_229.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 28 lane230 +lane_to_serdes_map_nif_lane230.BCM8887X=rx231:tx227 +phy_rx_polarity_flip_phy230.BCM8887X=0 +phy_tx_polarity_flip_phy230.BCM8887X=0 +serdes_tx_taps_230.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 28 lane231 +lane_to_serdes_map_nif_lane231.BCM8887X=rx226:tx225 +phy_rx_polarity_flip_phy231.BCM8887X=1 +phy_tx_polarity_flip_phy231.BCM8887X=1 +serdes_tx_taps_231.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + + +# ---------------------------------------------------------------------------------------------------- +# core_29 +# ---------------------------------------------------------------------------------------------------- +ucode_port_241.BCM8887X=CDGE4_58:core_7.9 +tm_port_header_type_out_241.BCM8887X=ETH +ucode_port_245.BCM8887X=CDGE4_59:core_7.13 +tm_port_header_type_out_245.BCM8887X=ETH + +# core 29 lane232 +lane_to_serdes_map_nif_lane232.BCM8887X=rx234:tx234 +phy_rx_polarity_flip_phy232.BCM8887X=1 +phy_tx_polarity_flip_phy232.BCM8887X=1 +serdes_tx_taps_232.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 29 lane233 +lane_to_serdes_map_nif_lane233.BCM8887X=rx235:tx233 +phy_rx_polarity_flip_phy233.BCM8887X=1 +phy_tx_polarity_flip_phy233.BCM8887X=0 +serdes_tx_taps_233.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 29 lane234 +lane_to_serdes_map_nif_lane234.BCM8887X=rx236:tx239 +phy_rx_polarity_flip_phy234.BCM8887X=1 +phy_tx_polarity_flip_phy234.BCM8887X=1 +serdes_tx_taps_234.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 29 lane235 +lane_to_serdes_map_nif_lane235.BCM8887X=rx238:tx232 +phy_rx_polarity_flip_phy235.BCM8887X=0 +phy_tx_polarity_flip_phy235.BCM8887X=1 +serdes_tx_taps_235.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 29 lane236 +lane_to_serdes_map_nif_lane236.BCM8887X=rx237:tx236 +phy_rx_polarity_flip_phy236.BCM8887X=0 +phy_tx_polarity_flip_phy236.BCM8887X=0 +serdes_tx_taps_236.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 29 lane237 +lane_to_serdes_map_nif_lane237.BCM8887X=rx239:tx235 +phy_rx_polarity_flip_phy237.BCM8887X=1 +phy_tx_polarity_flip_phy237.BCM8887X=0 +serdes_tx_taps_237.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 29 lane238 +lane_to_serdes_map_nif_lane238.BCM8887X=rx232:tx238 +phy_rx_polarity_flip_phy238.BCM8887X=1 +phy_tx_polarity_flip_phy238.BCM8887X=0 +serdes_tx_taps_238.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 29 lane239 +lane_to_serdes_map_nif_lane239.BCM8887X=rx233:tx237 +phy_rx_polarity_flip_phy239.BCM8887X=1 +phy_tx_polarity_flip_phy239.BCM8887X=0 +serdes_tx_taps_239.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + + +# ---------------------------------------------------------------------------------------------------- +# core_30 +# ---------------------------------------------------------------------------------------------------- +ucode_port_233.BCM8887X=CDGE4_60:core_7.17 +tm_port_header_type_out_233.BCM8887X=ETH +ucode_port_237.BCM8887X=CDGE4_61:core_7.21 +tm_port_header_type_out_237.BCM8887X=ETH + +# core 30 lane240 +lane_to_serdes_map_nif_lane240.BCM8887X=rx242:tx242 +phy_rx_polarity_flip_phy240.BCM8887X=0 +phy_tx_polarity_flip_phy240.BCM8887X=1 +serdes_tx_taps_240.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 30 lane241 +lane_to_serdes_map_nif_lane241.BCM8887X=rx243:tx241 +phy_rx_polarity_flip_phy241.BCM8887X=1 +phy_tx_polarity_flip_phy241.BCM8887X=0 +serdes_tx_taps_241.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 30 lane242 +lane_to_serdes_map_nif_lane242.BCM8887X=rx244:tx247 +phy_rx_polarity_flip_phy242.BCM8887X=1 +phy_tx_polarity_flip_phy242.BCM8887X=1 +serdes_tx_taps_242.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 30 lane243 +lane_to_serdes_map_nif_lane243.BCM8887X=rx246:tx240 +phy_rx_polarity_flip_phy243.BCM8887X=0 +phy_tx_polarity_flip_phy243.BCM8887X=1 +serdes_tx_taps_243.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 30 lane244 +lane_to_serdes_map_nif_lane244.BCM8887X=rx245:tx244 +phy_rx_polarity_flip_phy244.BCM8887X=0 +phy_tx_polarity_flip_phy244.BCM8887X=0 +serdes_tx_taps_244.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 30 lane245 +lane_to_serdes_map_nif_lane245.BCM8887X=rx247:tx243 +phy_rx_polarity_flip_phy245.BCM8887X=1 +phy_tx_polarity_flip_phy245.BCM8887X=0 +serdes_tx_taps_245.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 30 lane246 +lane_to_serdes_map_nif_lane246.BCM8887X=rx240:tx246 +phy_rx_polarity_flip_phy246.BCM8887X=1 +phy_tx_polarity_flip_phy246.BCM8887X=0 +serdes_tx_taps_246.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 30 lane247 +lane_to_serdes_map_nif_lane247.BCM8887X=rx241:tx245 +phy_rx_polarity_flip_phy247.BCM8887X=1 +phy_tx_polarity_flip_phy247.BCM8887X=0 +serdes_tx_taps_247.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + + +# ---------------------------------------------------------------------------------------------------- +# core_31 +# ---------------------------------------------------------------------------------------------------- +ucode_port_225.BCM8887X=CDGE4_62:core_7.25 +tm_port_header_type_out_225.BCM8887X=ETH +ucode_port_229.BCM8887X=CDGE4_63:core_7.29 +tm_port_header_type_out_229.BCM8887X=ETH + +# core 31 lane248 +lane_to_serdes_map_nif_lane248.BCM8887X=rx250:tx250 +phy_rx_polarity_flip_phy248.BCM8887X=0 +phy_tx_polarity_flip_phy248.BCM8887X=1 +serdes_tx_taps_248.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 31 lane249 +lane_to_serdes_map_nif_lane249.BCM8887X=rx251:tx249 +phy_rx_polarity_flip_phy249.BCM8887X=1 +phy_tx_polarity_flip_phy249.BCM8887X=0 +serdes_tx_taps_249.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 31 lane250 +lane_to_serdes_map_nif_lane250.BCM8887X=rx252:tx255 +phy_rx_polarity_flip_phy250.BCM8887X=1 +phy_tx_polarity_flip_phy250.BCM8887X=1 +serdes_tx_taps_250.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 31 lane251 +lane_to_serdes_map_nif_lane251.BCM8887X=rx254:tx248 +phy_rx_polarity_flip_phy251.BCM8887X=0 +phy_tx_polarity_flip_phy251.BCM8887X=1 +serdes_tx_taps_251.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 31 lane252 +lane_to_serdes_map_nif_lane252.BCM8887X=rx253:tx252 +phy_rx_polarity_flip_phy252.BCM8887X=0 +phy_tx_polarity_flip_phy252.BCM8887X=0 +serdes_tx_taps_252.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 31 lane253 +lane_to_serdes_map_nif_lane253.BCM8887X=rx255:tx251 +phy_rx_polarity_flip_phy253.BCM8887X=1 +phy_tx_polarity_flip_phy253.BCM8887X=0 +serdes_tx_taps_253.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 31 lane254 +lane_to_serdes_map_nif_lane254.BCM8887X=rx248:tx254 +phy_rx_polarity_flip_phy254.BCM8887X=1 +phy_tx_polarity_flip_phy254.BCM8887X=0 +serdes_tx_taps_254.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# core 31 lane255 +lane_to_serdes_map_nif_lane255.BCM8887X=rx249:tx253 +phy_rx_polarity_flip_phy255.BCM8887X=1 +phy_tx_polarity_flip_phy255.BCM8887X=0 +serdes_tx_taps_255.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 + +# ---------------------------------------------------------------------------------------------------- +# core_32 +# ---------------------------------------------------------------------------------------------------- +ucode_port_257.BCM8887X=CGE64:core_2.33 +tm_port_header_type_out_257.BCM8887X=ETH + +# core 32 lane256 +lane_to_serdes_map_nif_lane256.BCM8887X=rx257:tx257 +phy_rx_polarity_flip_phy256.BCM8887X=0 +phy_tx_polarity_flip_phy256.BCM8887X=0 + +# core 32 lane257 +lane_to_serdes_map_nif_lane257.BCM8887X=rx256:tx256 +phy_rx_polarity_flip_phy257.BCM8887X=0 +phy_tx_polarity_flip_phy257.BCM8887X=1 + +# core 32 lane258 +lane_to_serdes_map_nif_lane258.BCM8887X=rx258:tx258 +phy_rx_polarity_flip_phy258.BCM8887X=1 +phy_tx_polarity_flip_phy258.BCM8887X=0 + +# core 32 lane259 +lane_to_serdes_map_nif_lane259.BCM8887X=rx259:tx259 +phy_rx_polarity_flip_phy259.BCM8887X=0 +phy_tx_polarity_flip_phy259.BCM8887X=0 + + +# ---------------------------------------------------------------------------------------------------- +# core_33 +# ---------------------------------------------------------------------------------------------------- +ucode_port_261.BCM8887X=CGE65:core_6.33 +tm_port_header_type_out_261.BCM8887X=ETH + +# core 33 lane260 +lane_to_serdes_map_nif_lane260.BCM8887X=rx260:tx260 +phy_rx_polarity_flip_phy260.BCM8887X=0 +phy_tx_polarity_flip_phy260.BCM8887X=0 + +# core 33 lane261 +lane_to_serdes_map_nif_lane261.BCM8887X=rx261:tx261 +phy_rx_polarity_flip_phy261.BCM8887X=0 +phy_tx_polarity_flip_phy261.BCM8887X=1 + +# core 33 lane262 +lane_to_serdes_map_nif_lane262.BCM8887X=rx262:tx262 +phy_rx_polarity_flip_phy262.BCM8887X=0 +phy_tx_polarity_flip_phy262.BCM8887X=0 + +# core 33 lane263 +lane_to_serdes_map_nif_lane263.BCM8887X=rx263:tx263 +phy_rx_polarity_flip_phy263.BCM8887X=0 +phy_tx_polarity_flip_phy263.BCM8887X=0 + + +# ---------------------------------------------------------------------------------------------------- +# Static Properties +# ---------------------------------------------------------------------------------------------------- + +port_init_speed_xl.BCM8887X=40000 +port_init_speed_cd.BCM8887X=400000 +port_init_speed_d3c.BCM8887X=800000 +port_init_speed_ce.BCM8887X=100000 +port_init_speed_le.BCM8887X=50000 +port_init_speed_fabric.BCM8887X=53125 +port_init_speed_xe.BCM8887X=25000 +port_init_speed_cc.BCM8887X=200000 +port_init_speed_ge.BCM8887X=1000 + +outlif_logical_to_physical_phase_map_1.BCM8887X=S1 +outlif_logical_to_physical_phase_map_2.BCM8887X=L1 +outlif_logical_to_physical_phase_map_3.BCM8887X=XL +outlif_logical_to_physical_phase_map_4.BCM8887X=L2 +outlif_logical_to_physical_phase_map_5.BCM8887X=M1 +outlif_logical_to_physical_phase_map_6.BCM8887X=M2 +outlif_logical_to_physical_phase_map_7.BCM8887X=M3 +outlif_logical_to_physical_phase_map_8.BCM8887X=S2 + +outlif_physical_phase_data_granularity_S1.BCM8887X=60 +outlif_physical_phase_data_granularity_S2.BCM8887X=60 +outlif_physical_phase_data_granularity_M1.BCM8887X=60 +outlif_physical_phase_data_granularity_M2.BCM8887X=60 +outlif_physical_phase_data_granularity_M3.BCM8887X=60 +outlif_physical_phase_data_granularity_L1.BCM8887X=60 +outlif_physical_phase_data_granularity_L2.BCM8887X=60 +outlif_physical_phase_data_granularity_XL.BCM8887X=60 + +appl_param_rcy_mirror_ports_range.BCM8887X=500-1000 + +# ----------------------------------------------- +# | FPP | FPP | FPP | FPP | FPP | FPP | +# | 11,12 | 13,14 | 15,16 | 17,18 | 19,20 | 21,22 | +# |-----------------------------------------------| +# | ETH | ETH | ETH | ETH | ETH | ETH | +# | 33,37 | 41,45 | 49,53 | 57,61 | 65,69 | 73,77 | +# ---------------|-----------------------------------------------|---------------- +# | | Core | Core | Core | Core | Core | Core | | +# | | 06 | 05 | 04 | 16 | 17 | 18 | | +# -----------------|------ ----------------------------------------------- ------|---------|------- +# | FPP | ETH | Core | | Core | ETH | FPP | +# | 09,10 | 185,189 | 07 | | 19 | 193,197 | 23,24 | +# |-------|---------|------| |------|---------|-------| +# | FPP | ETH | Core | | Core | ETH | FPP | +# | 07,08 | 177,181 | 15 | | 27 | 201,205 | 25,26 | +# |-------|---------|------| |------|---------|-------| +# | FPP | ETH | Core | AGERA2 -> QSFP_DD_112 | Core | ETH | FPP | +# | 05,06 | 169,173 | 14 | | 26 | 209,213 | 27,28 | +# |-------|---------|------| |------|---------|-------| +# | FPP | ETH | Core | | Core | ETH | FPP | +# | 03,04 | 161,165 | 13 | | 25 | 217,221 | 29,30 | +# |-------|---------|------| |------|---------|-------| +# | FPP | ETH | Core | | Core | ETH | FPP | +# | 01,02 | 153,157 | 12 | | 24 | 225,229 | 31,32 | +# |-------|---------|------|---------------------------- Q3D -------------------------------|------|---------|-------| +# | FPP | ETH | Core | | Core | ETH | FPP | +# | 33,34 | 129,133 | 08 | | 28 | 249,253 | 62,63 | +# |-------|---------|------| |------|---------|-------| +# | FPP | ETH | Core | | Core | ETH | FPP | +# | 35,36 | 137,141 | 09 | | 29 | 241,245 | 60,61 | +# |-------|---------|------| |------|---------|-------| +# | FPP | ETH | Core | | Core | ETH | FPP | +# | 36,37 | 145,149 | 10 | QSFP_112 | 30 | 233,237 | 58,59 | +# |-------|---------|------| |------|---------|-------| +# | FPP | ETH | Core | | Core | ETH | FPP | +# | 38,39 | 153,157 | 11 | | 31 | 225,229 | 56,57 | +# |-------|---------|------| |------|---------|-------| +# | FPP | ETH | Core | | Core | ETH | FPP | +# | 40,41 | 161,165 | 03 | | 23 | 217,221 | 54,55 | +# -----------------|------ _______________________________________________ ------|----------------- +# | | Core | Core | Core | Core | Core | Core | | +# | | 02 | 01 | 00 | 20 | 21 | 22 | | +# ---------------|-----------------------------------------------|---------------- +# | ETH | ETH | ETH | ETH | ETH | ETH | +# |169,173|177,181|185,189|193,197|201,205|209,213| +# |-----------------------------------------------| +# | FPP | FPP | FPP | FPP | FPP | FPP | +# | 42,43 | 44,45 | 46,47 | 48,49 | 50,51 | 52,53 | +# ----------------------------------------------- + +dpp_db_path=/usr/share/bcm/db +rif_id_max=8192 +trunk_group_max_members=128 +custom_feature_ts_pll_internal_clock_reference.BCM8887X=1 +port_init_cl72.BCM8887X=0 +port_priorities_d3c.BCM8887X=8 +port_priorities_cd.BCM8887X=8 +port_priorities_ce.BCM8887X=8 +port_priorities_xe.BCM8887X=8 +port_priorities_ge.BCM8887X=8 +port_priorities=8 +#port_priorities_sch=8 +#CPU ports +port_priorities_0=2 +port_priorities_sch_0=8 +port_priorities_380=2 +port_priorities_sch_380=8 +port_priorities_381=2 +port_priorities_sch_381=8 +port_priorities_382=2 +port_priorities_sch_382=8 +port_priorities_383=2 +port_priorities_sch_383=8 +port_priorities_384=2 +port_priorities_sch_384=8 +port_priorities_385=2 +port_priorities_sch_385=8 +port_priorities_386=2 +port_priorities_sch_386=8 +port_priorities_387=2 +port_priorities_sch_387=8 +port_priorities_rcy=2 +port_priorities_sch_rcy=8 + +appl_param_oam_enable=0 +soc_family.BCM8887X=BCM8887X + +#enable HBM +ext_ram_enabled_bitmap.BCM8887X=0xF + +#################################################### +##Reference applications related properties - End +#################################################### +###Default interfaces for Qumran3D +#CPU interfaces +ucode_port_0.BCM8887X=CPU.0:core_0.0 +ucode_port_380.BCM8887X=CPU.8:core_1.200 +ucode_port_381.BCM8887X=CPU.16:core_0.201 +ucode_port_382.BCM8887X=CPU.24:core_2.202 +ucode_port_383.BCM8887X=CPU.32:core_3.203 +ucode_port_384.BCM8887X=CPU.4:core_6.204 +ucode_port_385.BCM8887X=CPU.12:core_7.205 +ucode_port_386.BCM8887X=CPU.20:core_4.206 +ucode_port_387.BCM8887X=CPU.28:core_5.207 + +#SDK 6.5.31 +custom_feature_statdma_enable.BCM8887X=1 + +#special ports +ucode_port_330.BCM8887X=EVENTOR:core_0.230 + +#ucode_port_231.BCM8887X=EVENTOR:core_4.231 +ucode_port_340.BCM8887X=OLP0:core_0.240 +ucode_port_341.BCM8887X=OLP1:core_0.241 +ucode_port_342.BCM8887X=OLP0:core_4.242 +ucode_port_343.BCM8887X=OLP1:core_4.243 +ucode_port_332.BCM8887X=OAMP:core_0.232 +ucode_port_333.BCM8887X=OAMP:core_1.233 +ucode_port_334.BCM8887X=OAMP:core_2.234 +ucode_port_335.BCM8887X=OAMP:core_3.235 +ucode_port_336.BCM8887X=OAMP:core_4.236 +ucode_port_337.BCM8887X=OAMP:core_5.237 +ucode_port_338.BCM8887X=OAMP:core_6.238 +ucode_port_339.BCM8887X=OAMP:core_7.239 + + +ucode_port_332.BCM8887X_ADAPTER=OAMP:core_0.232 +ucode_port_333.BCM8887X_ADAPTER=OAMP:core_1.233 +ucode_port_334.BCM8887X_ADAPTER=OAMP:core_2.234 +ucode_port_335.BCM8887X_ADAPTER=OAMP:core_3.235 +ucode_port_336.BCM8887X_ADAPTER=OAMP:core_4.236 +ucode_port_337.BCM8887X_ADAPTER=OAMP:core_5.237 +ucode_port_338.BCM8887X_ADAPTER=OAMP:core_6.238 +ucode_port_339.BCM8887X_ADAPTER=OAMP:core_7.239 + + +#OAMP +oamp_dual_mode.BCM8887X=1 + +sai_disable_srcmacqedstmac_ctrl=1 + +#RCY ports +sai_recycle_port_lane_base=300 +ucode_port_321.BCM8887X=RCY.21:core_0.221 +tm_port_header_type_in_321.BCM8887X=ETH + +# SAT +## Enable SAT Interface. 0 - Disable, 1 - Enable (Default) +ucode_port_316.BCM8887X=SAT:core_2.216 +ucode_port_317.BCM8887X=SAT:core_3.217 +ucode_port_318.BCM8887X=SAT:core_0.218 +ucode_port_319.BCM8887X=SAT:core_1.219 +ucode_port_312.BCM8887X=SAT:core_6.212 +ucode_port_313.BCM8887X=SAT:core_7.213 +ucode_port_314.BCM8887X=SAT:core_4.214 +ucode_port_315.BCM8887X=SAT:core_5.215 +tm_port_header_type_in_316.BCM8887X=INJECTED_2 +tm_port_header_type_in_317.BCM8887X=INJECTED_2 +tm_port_header_type_in_318.BCM8887X=INJECTED_2 +tm_port_header_type_in_319.BCM8887X=INJECTED_2 +tm_port_header_type_in_312.BCM8887X=INJECTED_2 +tm_port_header_type_in_313.BCM8887X=INJECTED_2 +tm_port_header_type_in_314.BCM8887X=INJECTED_2 +tm_port_header_type_in_315.BCM8887X=INJECTED_2 +tm_port_header_type_out_316.BCM8887X=CPU +tm_port_header_type_out_317.BCM8887X=CPU +tm_port_header_type_out_318.BCM8887X=CPU +tm_port_header_type_out_319.BCM8887X=CPU +tm_port_header_type_out_312.BCM8887X=CPU +tm_port_header_type_out_313.BCM8887X=CPU +tm_port_header_type_out_314.BCM8887X=CPU +tm_port_header_type_out_315.BCM8887X=CPU + + +######################### +### High Availability ### +######################### +#if warmboot is not needed this property can be deleted +#warmboot_support.BCM8887X=on +#warmboot_support.BCM8887X_ADAPTER=on + +#size of memory block pre-allocated for sw-state use when working with warmboot_support=on +sw_state_max_size.BCM8887X=1650000000 +sw_state_max_size.BCM8887X_ADAPTER=1650000000 + +#location of warmboot NV memory +#Allowed options for dnx are - 3:external storage in filesystem 4:driver will save the state directly in shared memory +stable_location.BCM8887X=4 +stable_location.BCM8887X_ADAPTER=3 + +# Note that each unit should have a unique filename and that adapter does not play well with tmp and dev/shm folders. +stable_filename.BCM8887X_ADAPTER=warmboot_data_0 +stable_filename.BCM8887X=/dev/shm/warmboot_data_0 +stable_filename.1.BCM8887X=/dev/shm/warmboot_data_1 +stable_filename.2.BCM8887X=/dev/shm/warmboot_data_2 + +#Maximum size for NVM used for WB storage, must be larger than sw_state_max_size.BCM8887X +stable_size.BCM8887X=1700000000 +stable_size.BCM8887X_ADAPTER=1700000000 + +#disable counter thread +bcm_stat_interval.BCM8887X_ADAPTER=0 + +######################### +######################### +######################### + +### MDB configuration ### +mdb_profile.BCM8887X=Elastic-Balanced + +### Enable Descriptor-DMA ### +dma_desc_aggregator_chain_length_max.BCM8887X=256 +dma_desc_aggregator_buff_size_kb.BCM8887X=64 +dma_desc_aggregator_enable_specific_MDB_LPM.BCM8887X=1 +dma_desc_aggregator_enable_specific_MDB_FEC.BCM8887X=1 +dma_desc_aggregator_enable_specific_XLTCAM.BCM8887X=1 +dma_desc_aggregator_enable_specific_INIT.BCM8887X=1 + +# PMF Map payload size, can be any of 30/60/120 +pmf_maps_payload_size.BCM8887X=30 + +# Set CPU to work with PTCHoITMH header incoming direction and CPU - system headers + network headers outgoing direction +tm_port_header_type_in_0.BCM8887X=INJECTED_2 +tm_port_header_type_out_0.BCM8887X=CPU + +tm_port_header_type_in_380.BCM8887X=INJECTED_2_PP +tm_port_header_type_out_380.BCM8887X=ETH +tm_port_header_type_in_381.BCM8887X=INJECTED_2_PP +tm_port_header_type_out_381.BCM8887X=ETH +tm_port_header_type_in_382.BCM8887X=INJECTED_2_PP +tm_port_header_type_out_382.BCM8887X=ETH +tm_port_header_type_in_383.BCM8887X=INJECTED_2_PP +tm_port_header_type_out_383.BCM8887X=ETH +tm_port_header_type_in_384.BCM8887X=INJECTED_2_PP +tm_port_header_type_out_384.BCM8887X=ETH +tm_port_header_type_in_385.BCM8887X=INJECTED_2_PP +tm_port_header_type_out_385.BCM8887X=ETH +tm_port_header_type_in_386.BCM8887X=INJECTED_2_PP +tm_port_header_type_out_386.BCM8887X=ETH +tm_port_header_type_in_387.BCM8887X=INJECTED_2_PP +tm_port_header_type_out_387.BCM8887X=ETH + +# set EVENTOR port to work with PTCHoITMH +tm_port_header_type_in_330.BCM8887X=INJECTED_2 + + +#OAMP +tm_port_header_type_in_332.BCM8887X=INJECTED_2 +tm_port_header_type_out_332.BCM8887X=ENCAP_EXTERNAL_CPU +tm_port_header_type_in_333.BCM8887X=INJECTED_2 +tm_port_header_type_out_333.BCM8887X=ENCAP_EXTERNAL_CPU +tm_port_header_type_in_334.BCM8887X=INJECTED_2 +tm_port_header_type_out_334.BCM8887X=ENCAP_EXTERNAL_CPU +tm_port_header_type_in_335.BCM8887X=INJECTED_2 +tm_port_header_type_in_336.BCM8887X=INJECTED_2 +tm_port_header_type_out_336.BCM8887X=ENCAP_EXTERNAL_CPU +tm_port_header_type_in_337.BCM8887X=INJECTED_2 +tm_port_header_type_out_337.BCM8887X=ENCAP_EXTERNAL_CPU +tm_port_header_type_in_338.BCM8887X=INJECTED_2 +tm_port_header_type_out_338.BCM8887X=ENCAP_EXTERNAL_CPU +tm_port_header_type_in_339.BCM8887X=INJECTED_2 +tm_port_header_type_out_339.BCM8887X=ENCAP_EXTERNAL_CPU + +#OLP +tm_port_header_type_in_340.BCM8887X=TM +tm_port_header_type_out_340.BCM8887X=ETH +tm_port_header_type_in_341.BCM8887X=TM +tm_port_header_type_out_341.BCM8887X=ETH +tm_port_header_type_in_342.BCM8887X=TM +tm_port_header_type_out_342.BCM8887X=ETH +tm_port_header_type_in_343.BCM8887X=TM +tm_port_header_type_out_343.BCM8887X=ETH + +# Set statically the region mode per region id +# 0: queue connectors only. +# 3: [default] SE only (SharingOrder = Low-To-High) +# 7: SE only (SharingOrder = High-To-Low) +dtm_flow_mapping_mode_region_65.BCM8887X=3 +dtm_flow_mapping_mode_region_66.BCM8887X=3 +dtm_flow_mapping_mode_region_67.BCM8887X=3 +dtm_flow_mapping_mode_region_68.BCM8887X=3 +dtm_flow_mapping_mode_region_69.BCM8887X=3 +dtm_flow_mapping_mode_region_70.BCM8887X=3 +dtm_flow_mapping_mode_region_71.BCM8887X=3 +dtm_flow_mapping_mode_region_72.BCM8887X=3 +dtm_flow_mapping_mode_region_73.BCM8887X=3 +dtm_flow_mapping_mode_region_74.BCM8887X=7 +dtm_flow_mapping_mode_region_75.BCM8887X=3 +dtm_flow_mapping_mode_region_76.BCM8887X=3 +dtm_flow_mapping_mode_region_77.BCM8887X=3 +dtm_flow_mapping_mode_region_78.BCM8887X=3 +dtm_flow_mapping_mode_region_79.BCM8887X=3 +dtm_flow_mapping_mode_region_80.BCM8887X=3 +dtm_flow_mapping_mode_region_81.BCM8887X=3 +dtm_flow_mapping_mode_region_82.BCM8887X=3 +dtm_flow_mapping_mode_region_83.BCM8887X=3 +dtm_flow_mapping_mode_region_84.BCM8887X=3 +dtm_flow_mapping_mode_region_85.BCM8887X=3 +dtm_flow_mapping_mode_region_86.BCM8887X=3 +dtm_flow_mapping_mode_region_87.BCM8887X=3 +dtm_flow_mapping_mode_region_88.BCM8887X=3 +dtm_flow_mapping_mode_region_89.BCM8887X=3 +dtm_flow_mapping_mode_region_90.BCM8887X=3 +dtm_flow_mapping_mode_region_91.BCM8887X=3 +dtm_flow_mapping_mode_region_92.BCM8887X=3 +dtm_flow_mapping_mode_region_93.BCM8887X=3 +dtm_flow_mapping_mode_region_94.BCM8887X=3 + +# Set nof remote cores +dtm_flow_nof_remote_cores_region.BCM8887X=8 + +## Fabric transmission mode +# Set the Connect mode to the Fabric +# Options: FE - presence of a Fabric device (single stage) +# SINGLE_FAP - stand-alone device +# MESH - devices in Mesh +# Note: If 'diag_chassis' is on, value will be override in dnx.soc +# to be FE instead of SINGLE_FAP. +fabric_connect_mode.BCM8887X=SINGLE_FAP + +### Fabric configuration ### +#SFI speed rate +port_init_speed_fabric.BCM8887X=53125 + +### import SoC properties that shared with Ucode +#import config-qumran3d-ucode.bcm +#programmability_image_name.BCM8887X=S121 +# ucode input file, depending on image +#programmability_ucode_relative_path.BCM8887X=pemla/ucode/S121/jr3native/u_code_db2pem.txt + +custom_feature_adapter_do_collect_enable.BCM8887X_ADAPTER=1 +custom_feature_use_new_access.BCM8887X_ADAPTER=1 +mem_cache_enable_all.BCM8887X_ADAPTER=1 + +#Disable DMA stat +custom_feature_statdma_enable.BCM8887X_ADAPTER=0 + +#dram + +dram_temperature_monitor_enable.BCM8887X_ADAPTER=0 +#Interrupt polling mode on adapter +polled_irq_mode.BCM8887X_ADAPTER=1 +polled_irq_delay.BCM8887X_ADAPTER=200000 + +#Eventor SBUS DMA channels +eventor_sbus_dma_channels.BCM8887X=0,24,0,25,1,24,1,25 + +#Default CPU Tx Tc Queue +sai_default_cpu_tx_tc=7 diff --git a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/phy0_config.json b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/phy0_config.json new file mode 100644 index 00000000000..1f5c14635b7 --- /dev/null +++ b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/phy0_config.json @@ -0,0 +1,59 @@ +{ + "lanes": [ + { + "index": 255, + "local_lane_id": 255, + "system_side": true, + "tx_polarity": 255, + "rx_polarity": 255, + "line_tx_lanemap": 255, + "line_rx_lanemap": 255, + "line_to_system_lanemap": 255, + "mdio_addr": "" + } + ], + "ports": [ + { + "index": 1, + "mdio_addr": "0", + "system_speed": 100000, + "system_fec": "none", + "system_auto_neg": false, + "system_loopback": "none", + "system_training": false, + "line_speed": 50000, + "line_fec": "none", + "line_auto_neg": false, + "line_loopback": "none", + "line_training": false, + "line_media_type": "fiber", + "line_intf_type": "none", + "line_adver_speed": [], + "line_adver_fec": [], + "line_adver_auto_neg": false, + "line_adver_asym_pause": false, + "line_adver_media_type": "fiber" + }, + { + "index": 2, + "mdio_addr": "0", + "system_speed": 100000, + "system_fec": "none", + "system_auto_neg": false, + "system_loopback": "none", + "system_training": false, + "line_speed": 50000, + "line_fec": "none", + "line_auto_neg": false, + "line_loopback": "none", + "line_training": false, + "line_media_type": "fiber", + "line_intf_type": "none", + "line_adver_speed": [], + "line_adver_fec": [], + "line_adver_auto_neg": false, + "line_adver_asym_pause": false, + "line_adver_media_type": "fiber" + } + ] +} diff --git a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/phy10_config.json b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/phy10_config.json new file mode 100644 index 00000000000..1d2586c9bab --- /dev/null +++ b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/phy10_config.json @@ -0,0 +1,59 @@ +{ + "lanes": [ + { + "index": 255, + "local_lane_id": 255, + "system_side": true, + "tx_polarity": 255, + "rx_polarity": 255, + "line_tx_lanemap": 255, + "line_rx_lanemap": 255, + "line_to_system_lanemap": 255, + "mdio_addr": "" + } + ], + "ports": [ + { + "index": 21, + "mdio_addr": "0", + "system_speed": 100000, + "system_fec": "none", + "system_auto_neg": false, + "system_loopback": "none", + "system_training": false, + "line_speed": 50000, + "line_fec": "none", + "line_auto_neg": false, + "line_loopback": "none", + "line_training": false, + "line_media_type": "fiber", + "line_intf_type": "none", + "line_adver_speed": [], + "line_adver_fec": [], + "line_adver_auto_neg": false, + "line_adver_asym_pause": false, + "line_adver_media_type": "fiber" + }, + { + "index": 22, + "mdio_addr": "0", + "system_speed": 100000, + "system_fec": "none", + "system_auto_neg": false, + "system_loopback": "none", + "system_training": false, + "line_speed": 50000, + "line_fec": "none", + "line_auto_neg": false, + "line_loopback": "none", + "line_training": false, + "line_media_type": "fiber", + "line_intf_type": "none", + "line_adver_speed": [], + "line_adver_fec": [], + "line_adver_auto_neg": false, + "line_adver_asym_pause": false, + "line_adver_media_type": "fiber" + } + ] +} diff --git a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/phy11_config.json b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/phy11_config.json new file mode 100644 index 00000000000..0b2aba262bf --- /dev/null +++ b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/phy11_config.json @@ -0,0 +1,59 @@ +{ + "lanes": [ + { + "index": 255, + "local_lane_id": 255, + "system_side": true, + "tx_polarity": 255, + "rx_polarity": 255, + "line_tx_lanemap": 255, + "line_rx_lanemap": 255, + "line_to_system_lanemap": 255, + "mdio_addr": "" + } + ], + "ports": [ + { + "index": 23, + "mdio_addr": "0", + "system_speed": 100000, + "system_fec": "none", + "system_auto_neg": false, + "system_loopback": "none", + "system_training": false, + "line_speed": 50000, + "line_fec": "none", + "line_auto_neg": false, + "line_loopback": "none", + "line_training": false, + "line_media_type": "fiber", + "line_intf_type": "none", + "line_adver_speed": [], + "line_adver_fec": [], + "line_adver_auto_neg": false, + "line_adver_asym_pause": false, + "line_adver_media_type": "fiber" + }, + { + "index": 24, + "mdio_addr": "0", + "system_speed": 100000, + "system_fec": "none", + "system_auto_neg": false, + "system_loopback": "none", + "system_training": false, + "line_speed": 50000, + "line_fec": "none", + "line_auto_neg": false, + "line_loopback": "none", + "line_training": false, + "line_media_type": "fiber", + "line_intf_type": "none", + "line_adver_speed": [], + "line_adver_fec": [], + "line_adver_auto_neg": false, + "line_adver_asym_pause": false, + "line_adver_media_type": "fiber" + } + ] +} diff --git a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/phy12_config.json b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/phy12_config.json new file mode 100644 index 00000000000..397ea037c53 --- /dev/null +++ b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/phy12_config.json @@ -0,0 +1,59 @@ +{ + "lanes": [ + { + "index": 255, + "local_lane_id": 255, + "system_side": true, + "tx_polarity": 255, + "rx_polarity": 255, + "line_tx_lanemap": 255, + "line_rx_lanemap": 255, + "line_to_system_lanemap": 255, + "mdio_addr": "" + } + ], + "ports": [ + { + "index": 25, + "mdio_addr": "0", + "system_speed": 100000, + "system_fec": "none", + "system_auto_neg": false, + "system_loopback": "none", + "system_training": false, + "line_speed": 50000, + "line_fec": "none", + "line_auto_neg": false, + "line_loopback": "none", + "line_training": false, + "line_media_type": "fiber", + "line_intf_type": "none", + "line_adver_speed": [], + "line_adver_fec": [], + "line_adver_auto_neg": false, + "line_adver_asym_pause": false, + "line_adver_media_type": "fiber" + }, + { + "index": 26, + "mdio_addr": "0", + "system_speed": 100000, + "system_fec": "none", + "system_auto_neg": false, + "system_loopback": "none", + "system_training": false, + "line_speed": 50000, + "line_fec": "none", + "line_auto_neg": false, + "line_loopback": "none", + "line_training": false, + "line_media_type": "fiber", + "line_intf_type": "none", + "line_adver_speed": [], + "line_adver_fec": [], + "line_adver_auto_neg": false, + "line_adver_asym_pause": false, + "line_adver_media_type": "fiber" + } + ] +} diff --git a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/phy13_config.json b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/phy13_config.json new file mode 100644 index 00000000000..f10286d41a7 --- /dev/null +++ b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/phy13_config.json @@ -0,0 +1,59 @@ +{ + "lanes": [ + { + "index": 255, + "local_lane_id": 255, + "system_side": true, + "tx_polarity": 255, + "rx_polarity": 255, + "line_tx_lanemap": 255, + "line_rx_lanemap": 255, + "line_to_system_lanemap": 255, + "mdio_addr": "" + } + ], + "ports": [ + { + "index": 27, + "mdio_addr": "0", + "system_speed": 100000, + "system_fec": "none", + "system_auto_neg": false, + "system_loopback": "none", + "system_training": false, + "line_speed": 50000, + "line_fec": "none", + "line_auto_neg": false, + "line_loopback": "none", + "line_training": false, + "line_media_type": "fiber", + "line_intf_type": "none", + "line_adver_speed": [], + "line_adver_fec": [], + "line_adver_auto_neg": false, + "line_adver_asym_pause": false, + "line_adver_media_type": "fiber" + }, + { + "index": 28, + "mdio_addr": "0", + "system_speed": 100000, + "system_fec": "none", + "system_auto_neg": false, + "system_loopback": "none", + "system_training": false, + "line_speed": 50000, + "line_fec": "none", + "line_auto_neg": false, + "line_loopback": "none", + "line_training": false, + "line_media_type": "fiber", + "line_intf_type": "none", + "line_adver_speed": [], + "line_adver_fec": [], + "line_adver_auto_neg": false, + "line_adver_asym_pause": false, + "line_adver_media_type": "fiber" + } + ] +} diff --git a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/phy14_config.json b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/phy14_config.json new file mode 100644 index 00000000000..9d12f7af544 --- /dev/null +++ b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/phy14_config.json @@ -0,0 +1,59 @@ +{ + "lanes": [ + { + "index": 255, + "local_lane_id": 255, + "system_side": true, + "tx_polarity": 255, + "rx_polarity": 255, + "line_tx_lanemap": 255, + "line_rx_lanemap": 255, + "line_to_system_lanemap": 255, + "mdio_addr": "" + } + ], + "ports": [ + { + "index": 29, + "mdio_addr": "0", + "system_speed": 100000, + "system_fec": "none", + "system_auto_neg": false, + "system_loopback": "none", + "system_training": false, + "line_speed": 50000, + "line_fec": "none", + "line_auto_neg": false, + "line_loopback": "none", + "line_training": false, + "line_media_type": "fiber", + "line_intf_type": "none", + "line_adver_speed": [], + "line_adver_fec": [], + "line_adver_auto_neg": false, + "line_adver_asym_pause": false, + "line_adver_media_type": "fiber" + }, + { + "index": 30, + "mdio_addr": "0", + "system_speed": 100000, + "system_fec": "none", + "system_auto_neg": false, + "system_loopback": "none", + "system_training": false, + "line_speed": 50000, + "line_fec": "none", + "line_auto_neg": false, + "line_loopback": "none", + "line_training": false, + "line_media_type": "fiber", + "line_intf_type": "none", + "line_adver_speed": [], + "line_adver_fec": [], + "line_adver_auto_neg": false, + "line_adver_asym_pause": false, + "line_adver_media_type": "fiber" + } + ] +} diff --git a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/phy15_config.json b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/phy15_config.json new file mode 100644 index 00000000000..b112d087e25 --- /dev/null +++ b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/phy15_config.json @@ -0,0 +1,59 @@ +{ + "lanes": [ + { + "index": 255, + "local_lane_id": 255, + "system_side": true, + "tx_polarity": 255, + "rx_polarity": 255, + "line_tx_lanemap": 255, + "line_rx_lanemap": 255, + "line_to_system_lanemap": 255, + "mdio_addr": "" + } + ], + "ports": [ + { + "index": 31, + "mdio_addr": "0", + "system_speed": 100000, + "system_fec": "none", + "system_auto_neg": false, + "system_loopback": "none", + "system_training": false, + "line_speed": 50000, + "line_fec": "none", + "line_auto_neg": false, + "line_loopback": "none", + "line_training": false, + "line_media_type": "fiber", + "line_intf_type": "none", + "line_adver_speed": [], + "line_adver_fec": [], + "line_adver_auto_neg": false, + "line_adver_asym_pause": false, + "line_adver_media_type": "fiber" + }, + { + "index": 32, + "mdio_addr": "0", + "system_speed": 100000, + "system_fec": "none", + "system_auto_neg": false, + "system_loopback": "none", + "system_training": false, + "line_speed": 50000, + "line_fec": "none", + "line_auto_neg": false, + "line_loopback": "none", + "line_training": false, + "line_media_type": "fiber", + "line_intf_type": "none", + "line_adver_speed": [], + "line_adver_fec": [], + "line_adver_auto_neg": false, + "line_adver_asym_pause": false, + "line_adver_media_type": "fiber" + } + ] +} diff --git a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/phy1_config.json b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/phy1_config.json new file mode 100644 index 00000000000..2af2d426b3c --- /dev/null +++ b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/phy1_config.json @@ -0,0 +1,59 @@ +{ + "lanes": [ + { + "index": 255, + "local_lane_id": 255, + "system_side": true, + "tx_polarity": 255, + "rx_polarity": 255, + "line_tx_lanemap": 255, + "line_rx_lanemap": 255, + "line_to_system_lanemap": 255, + "mdio_addr": "" + } + ], + "ports": [ + { + "index": 3, + "mdio_addr": "0", + "system_speed": 100000, + "system_fec": "none", + "system_auto_neg": false, + "system_loopback": "none", + "system_training": false, + "line_speed": 50000, + "line_fec": "none", + "line_auto_neg": false, + "line_loopback": "none", + "line_training": false, + "line_media_type": "fiber", + "line_intf_type": "none", + "line_adver_speed": [], + "line_adver_fec": [], + "line_adver_auto_neg": false, + "line_adver_asym_pause": false, + "line_adver_media_type": "fiber" + }, + { + "index": 4, + "mdio_addr": "0", + "system_speed": 100000, + "system_fec": "none", + "system_auto_neg": false, + "system_loopback": "none", + "system_training": false, + "line_speed": 50000, + "line_fec": "none", + "line_auto_neg": false, + "line_loopback": "none", + "line_training": false, + "line_media_type": "fiber", + "line_intf_type": "none", + "line_adver_speed": [], + "line_adver_fec": [], + "line_adver_auto_neg": false, + "line_adver_asym_pause": false, + "line_adver_media_type": "fiber" + } + ] +} diff --git a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/phy2_config.json b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/phy2_config.json new file mode 100644 index 00000000000..12a676effcc --- /dev/null +++ b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/phy2_config.json @@ -0,0 +1,59 @@ +{ + "lanes": [ + { + "index": 255, + "local_lane_id": 255, + "system_side": true, + "tx_polarity": 255, + "rx_polarity": 255, + "line_tx_lanemap": 255, + "line_rx_lanemap": 255, + "line_to_system_lanemap": 255, + "mdio_addr": "" + } + ], + "ports": [ + { + "index": 5, + "mdio_addr": "0", + "system_speed": 100000, + "system_fec": "none", + "system_auto_neg": false, + "system_loopback": "none", + "system_training": false, + "line_speed": 50000, + "line_fec": "none", + "line_auto_neg": false, + "line_loopback": "none", + "line_training": false, + "line_media_type": "fiber", + "line_intf_type": "none", + "line_adver_speed": [], + "line_adver_fec": [], + "line_adver_auto_neg": false, + "line_adver_asym_pause": false, + "line_adver_media_type": "fiber" + }, + { + "index": 6, + "mdio_addr": "0", + "system_speed": 100000, + "system_fec": "none", + "system_auto_neg": false, + "system_loopback": "none", + "system_training": false, + "line_speed": 50000, + "line_fec": "none", + "line_auto_neg": false, + "line_loopback": "none", + "line_training": false, + "line_media_type": "fiber", + "line_intf_type": "none", + "line_adver_speed": [], + "line_adver_fec": [], + "line_adver_auto_neg": false, + "line_adver_asym_pause": false, + "line_adver_media_type": "fiber" + } + ] +} diff --git a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/phy3_config.json b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/phy3_config.json new file mode 100644 index 00000000000..2d4b763d1c1 --- /dev/null +++ b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/phy3_config.json @@ -0,0 +1,59 @@ +{ + "lanes": [ + { + "index": 255, + "local_lane_id": 255, + "system_side": true, + "tx_polarity": 255, + "rx_polarity": 255, + "line_tx_lanemap": 255, + "line_rx_lanemap": 255, + "line_to_system_lanemap": 255, + "mdio_addr": "" + } + ], + "ports": [ + { + "index": 7, + "mdio_addr": "0", + "system_speed": 100000, + "system_fec": "none", + "system_auto_neg": false, + "system_loopback": "none", + "system_training": false, + "line_speed": 50000, + "line_fec": "none", + "line_auto_neg": false, + "line_loopback": "none", + "line_training": false, + "line_media_type": "fiber", + "line_intf_type": "none", + "line_adver_speed": [], + "line_adver_fec": [], + "line_adver_auto_neg": false, + "line_adver_asym_pause": false, + "line_adver_media_type": "fiber" + }, + { + "index": 8, + "mdio_addr": "0", + "system_speed": 100000, + "system_fec": "none", + "system_auto_neg": false, + "system_loopback": "none", + "system_training": false, + "line_speed": 50000, + "line_fec": "none", + "line_auto_neg": false, + "line_loopback": "none", + "line_training": false, + "line_media_type": "fiber", + "line_intf_type": "none", + "line_adver_speed": [], + "line_adver_fec": [], + "line_adver_auto_neg": false, + "line_adver_asym_pause": false, + "line_adver_media_type": "fiber" + } + ] +} diff --git a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/phy4_config.json b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/phy4_config.json new file mode 100644 index 00000000000..790f73e4211 --- /dev/null +++ b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/phy4_config.json @@ -0,0 +1,59 @@ +{ + "lanes": [ + { + "index": 255, + "local_lane_id": 255, + "system_side": true, + "tx_polarity": 255, + "rx_polarity": 255, + "line_tx_lanemap": 255, + "line_rx_lanemap": 255, + "line_to_system_lanemap": 255, + "mdio_addr": "" + } + ], + "ports": [ + { + "index": 9, + "mdio_addr": "0", + "system_speed": 100000, + "system_fec": "none", + "system_auto_neg": false, + "system_loopback": "none", + "system_training": false, + "line_speed": 50000, + "line_fec": "none", + "line_auto_neg": false, + "line_loopback": "none", + "line_training": false, + "line_media_type": "fiber", + "line_intf_type": "none", + "line_adver_speed": [], + "line_adver_fec": [], + "line_adver_auto_neg": false, + "line_adver_asym_pause": false, + "line_adver_media_type": "fiber" + }, + { + "index": 10, + "mdio_addr": "0", + "system_speed": 100000, + "system_fec": "none", + "system_auto_neg": false, + "system_loopback": "none", + "system_training": false, + "line_speed": 50000, + "line_fec": "none", + "line_auto_neg": false, + "line_loopback": "none", + "line_training": false, + "line_media_type": "fiber", + "line_intf_type": "none", + "line_adver_speed": [], + "line_adver_fec": [], + "line_adver_auto_neg": false, + "line_adver_asym_pause": false, + "line_adver_media_type": "fiber" + } + ] +} diff --git a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/phy5_config.json b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/phy5_config.json new file mode 100644 index 00000000000..0985f78e3e0 --- /dev/null +++ b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/phy5_config.json @@ -0,0 +1,59 @@ +{ + "lanes": [ + { + "index": 255, + "local_lane_id": 255, + "system_side": true, + "tx_polarity": 255, + "rx_polarity": 255, + "line_tx_lanemap": 255, + "line_rx_lanemap": 255, + "line_to_system_lanemap": 255, + "mdio_addr": "" + } + ], + "ports": [ + { + "index": 11, + "mdio_addr": "0", + "system_speed": 100000, + "system_fec": "none", + "system_auto_neg": false, + "system_loopback": "none", + "system_training": false, + "line_speed": 50000, + "line_fec": "none", + "line_auto_neg": false, + "line_loopback": "none", + "line_training": false, + "line_media_type": "fiber", + "line_intf_type": "none", + "line_adver_speed": [], + "line_adver_fec": [], + "line_adver_auto_neg": false, + "line_adver_asym_pause": false, + "line_adver_media_type": "fiber" + }, + { + "index": 12, + "mdio_addr": "0", + "system_speed": 100000, + "system_fec": "none", + "system_auto_neg": false, + "system_loopback": "none", + "system_training": false, + "line_speed": 50000, + "line_fec": "none", + "line_auto_neg": false, + "line_loopback": "none", + "line_training": false, + "line_media_type": "fiber", + "line_intf_type": "none", + "line_adver_speed": [], + "line_adver_fec": [], + "line_adver_auto_neg": false, + "line_adver_asym_pause": false, + "line_adver_media_type": "fiber" + } + ] +} diff --git a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/phy6_config.json b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/phy6_config.json new file mode 100644 index 00000000000..8c101dc8366 --- /dev/null +++ b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/phy6_config.json @@ -0,0 +1,59 @@ +{ + "lanes": [ + { + "index": 255, + "local_lane_id": 255, + "system_side": true, + "tx_polarity": 255, + "rx_polarity": 255, + "line_tx_lanemap": 255, + "line_rx_lanemap": 255, + "line_to_system_lanemap": 255, + "mdio_addr": "" + } + ], + "ports": [ + { + "index": 13, + "mdio_addr": "0", + "system_speed": 100000, + "system_fec": "none", + "system_auto_neg": false, + "system_loopback": "none", + "system_training": false, + "line_speed": 50000, + "line_fec": "none", + "line_auto_neg": false, + "line_loopback": "none", + "line_training": false, + "line_media_type": "fiber", + "line_intf_type": "none", + "line_adver_speed": [], + "line_adver_fec": [], + "line_adver_auto_neg": false, + "line_adver_asym_pause": false, + "line_adver_media_type": "fiber" + }, + { + "index": 14, + "mdio_addr": "0", + "system_speed": 100000, + "system_fec": "none", + "system_auto_neg": false, + "system_loopback": "none", + "system_training": false, + "line_speed": 50000, + "line_fec": "none", + "line_auto_neg": false, + "line_loopback": "none", + "line_training": false, + "line_media_type": "fiber", + "line_intf_type": "none", + "line_adver_speed": [], + "line_adver_fec": [], + "line_adver_auto_neg": false, + "line_adver_asym_pause": false, + "line_adver_media_type": "fiber" + } + ] +} diff --git a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/phy7_config.json b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/phy7_config.json new file mode 100644 index 00000000000..6aca433a6a7 --- /dev/null +++ b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/phy7_config.json @@ -0,0 +1,59 @@ +{ + "lanes": [ + { + "index": 255, + "local_lane_id": 255, + "system_side": true, + "tx_polarity": 255, + "rx_polarity": 255, + "line_tx_lanemap": 255, + "line_rx_lanemap": 255, + "line_to_system_lanemap": 255, + "mdio_addr": "" + } + ], + "ports": [ + { + "index": 15, + "mdio_addr": "0", + "system_speed": 100000, + "system_fec": "none", + "system_auto_neg": false, + "system_loopback": "none", + "system_training": false, + "line_speed": 50000, + "line_fec": "none", + "line_auto_neg": false, + "line_loopback": "none", + "line_training": false, + "line_media_type": "fiber", + "line_intf_type": "none", + "line_adver_speed": [], + "line_adver_fec": [], + "line_adver_auto_neg": false, + "line_adver_asym_pause": false, + "line_adver_media_type": "fiber" + }, + { + "index": 16, + "mdio_addr": "0", + "system_speed": 100000, + "system_fec": "none", + "system_auto_neg": false, + "system_loopback": "none", + "system_training": false, + "line_speed": 50000, + "line_fec": "none", + "line_auto_neg": false, + "line_loopback": "none", + "line_training": false, + "line_media_type": "fiber", + "line_intf_type": "none", + "line_adver_speed": [], + "line_adver_fec": [], + "line_adver_auto_neg": false, + "line_adver_asym_pause": false, + "line_adver_media_type": "fiber" + } + ] +} diff --git a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/phy8_config.json b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/phy8_config.json new file mode 100644 index 00000000000..e24d582c70f --- /dev/null +++ b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/phy8_config.json @@ -0,0 +1,59 @@ +{ + "lanes": [ + { + "index": 255, + "local_lane_id": 255, + "system_side": true, + "tx_polarity": 255, + "rx_polarity": 255, + "line_tx_lanemap": 255, + "line_rx_lanemap": 255, + "line_to_system_lanemap": 255, + "mdio_addr": "" + } + ], + "ports": [ + { + "index": 17, + "mdio_addr": "0", + "system_speed": 100000, + "system_fec": "none", + "system_auto_neg": false, + "system_loopback": "none", + "system_training": false, + "line_speed": 50000, + "line_fec": "none", + "line_auto_neg": false, + "line_loopback": "none", + "line_training": false, + "line_media_type": "fiber", + "line_intf_type": "none", + "line_adver_speed": [], + "line_adver_fec": [], + "line_adver_auto_neg": false, + "line_adver_asym_pause": false, + "line_adver_media_type": "fiber" + }, + { + "index": 18, + "mdio_addr": "0", + "system_speed": 100000, + "system_fec": "none", + "system_auto_neg": false, + "system_loopback": "none", + "system_training": false, + "line_speed": 50000, + "line_fec": "none", + "line_auto_neg": false, + "line_loopback": "none", + "line_training": false, + "line_media_type": "fiber", + "line_intf_type": "none", + "line_adver_speed": [], + "line_adver_fec": [], + "line_adver_auto_neg": false, + "line_adver_asym_pause": false, + "line_adver_media_type": "fiber" + } + ] +} diff --git a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/phy9_config.json b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/phy9_config.json new file mode 100644 index 00000000000..612553a8a25 --- /dev/null +++ b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/phy9_config.json @@ -0,0 +1,59 @@ +{ + "lanes": [ + { + "index": 255, + "local_lane_id": 255, + "system_side": true, + "tx_polarity": 255, + "rx_polarity": 255, + "line_tx_lanemap": 255, + "line_rx_lanemap": 255, + "line_to_system_lanemap": 255, + "mdio_addr": "" + } + ], + "ports": [ + { + "index": 19, + "mdio_addr": "0", + "system_speed": 100000, + "system_fec": "none", + "system_auto_neg": false, + "system_loopback": "none", + "system_training": false, + "line_speed": 50000, + "line_fec": "none", + "line_auto_neg": false, + "line_loopback": "none", + "line_training": false, + "line_media_type": "fiber", + "line_intf_type": "none", + "line_adver_speed": [], + "line_adver_fec": [], + "line_adver_auto_neg": false, + "line_adver_asym_pause": false, + "line_adver_media_type": "fiber" + }, + { + "index": 20, + "mdio_addr": "0", + "system_speed": 100000, + "system_fec": "none", + "system_auto_neg": false, + "system_loopback": "none", + "system_training": false, + "line_speed": 50000, + "line_fec": "none", + "line_auto_neg": false, + "line_loopback": "none", + "line_training": false, + "line_media_type": "fiber", + "line_intf_type": "none", + "line_adver_speed": [], + "line_adver_fec": [], + "line_adver_auto_neg": false, + "line_adver_asym_pause": false, + "line_adver_media_type": "fiber" + } + ] +} diff --git a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/port_config.ini b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/port_config.ini new file mode 100644 index 00000000000..9d1540e394f --- /dev/null +++ b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/port_config.ini @@ -0,0 +1,68 @@ +# name lanes alias index role speed asic_port_name core_id core_port_id num_voq +Ethernet0 96,97,98,99 Port1 1 Ext 400000 Eth0 3 1 8 +Ethernet4 100,101,102,103 Port2 2 Ext 400000 Eth4 3 5 8 +Ethernet8 104,105,106,107 Port3 3 Ext 400000 Eth8 3 9 8 +Ethernet12 108,109,110,111 Port4 4 Ext 400000 Eth12 3 13 8 +Ethernet16 112,113,114,115 Port5 5 Ext 400000 Eth16 3 17 8 +Ethernet20 116,117,118,119 Port6 6 Ext 400000 Eth20 3 21 8 +Ethernet24 120,121,122,123 Port7 7 Ext 400000 Eth24 3 25 8 +Ethernet28 124,125,126,127 Port8 8 Ext 400000 Eth28 3 29 8 +Ethernet32 56,57,58,59 Port9 9 Ext 400000 Eth32 1 25 8 +Ethernet36 60,61,62,63 Port10 10 Ext 400000 Eth36 1 29 8 +Ethernet40 48,49,50,51 Port11 11 Ext 400000 Eth40 1 17 8 +Ethernet44 52,53,54,55 Port12 12 Ext 400000 Eth44 1 21 8 +Ethernet48 40,41,42,43 Port13 13 Ext 400000 Eth48 1 9 8 +Ethernet52 44,45,46,47 Port14 14 Ext 400000 Eth52 1 13 8 +Ethernet56 32,33,34,35 Port15 15 Ext 400000 Eth56 1 1 8 +Ethernet60 36,37,38,39 Port16 16 Ext 400000 Eth60 1 5 8 +Ethernet64 128,129,130,131 Port17 17 Ext 400000 Eth64 4 1 8 +Ethernet68 132,133,134,135 Port18 18 Ext 400000 Eth68 4 5 8 +Ethernet72 136,137,138,139 Port19 19 Ext 400000 Eth72 4 9 8 +Ethernet76 140,141,142,143 Port20 20 Ext 400000 Eth76 4 13 8 +Ethernet80 144,145,146,147 Port21 21 Ext 400000 Eth80 4 17 8 +Ethernet84 148,149,150,151 Port22 22 Ext 400000 Eth84 4 21 8 +Ethernet88 152,153,154,155 Port23 23 Ext 400000 Eth88 4 25 8 +Ethernet92 156,157,158,159 Port24 24 Ext 400000 Eth92 4 29 8 +Ethernet96 216,217,218,219 Port25 25 Ext 400000 Eth96 6 25 8 +Ethernet100 220,221,222,223 Port26 26 Ext 400000 Eth100 6 29 8 +Ethernet104 208,209,210,211 Port27 27 Ext 400000 Eth108 6 17 8 +Ethernet108 212,213,214,215 Port28 28 Ext 400000 Eth108 6 21 8 +Ethernet112 200,201,202,203 Port29 29 Ext 400000 Eth112 6 9 8 +Ethernet116 204,205,206,207 Port30 30 Ext 400000 Eth116 6 13 8 +Ethernet120 192,193,194,195 Port31 31 Ext 400000 Eth120 6 1 8 +Ethernet124 196,197,198,199 Port32 32 Ext 400000 Eth124 6 5 8 +Ethernet128 64,65,66,67 Port33 33 Ext 400000 Eth128 2 1 8 +Ethernet132 68,69,70,71 Port34 34 Ext 400000 Eth132 2 5 8 +Ethernet136 72,73,74,75 Port35 35 Ext 400000 Eth136 2 9 8 +Ethernet140 76,77,78,79 Port36 36 Ext 400000 Eth140 2 13 8 +Ethernet144 80,81,82,83 Port37 37 Ext 400000 Eth144 2 17 8 +Ethernet148 84,85,86,87 Port38 38 Ext 400000 Eth148 2 21 8 +Ethernet152 88,89,90,91 Port39 39 Ext 400000 Eth152 2 25 8 +Ethernet156 92,93,94,95 Port40 40 Ext 400000 Eth156 2 29 8 +Ethernet160 24,25,26,27 Port41 41 Ext 400000 Eth160 0 25 8 +Ethernet164 28,29,30,31 Port42 42 Ext 400000 Eth164 0 29 8 +Ethernet168 16,17,18,19 Port43 43 Ext 400000 Eth168 0 17 8 +Ethernet172 20,21,22,23 Port44 44 Ext 400000 Eth172 0 21 8 +Ethernet176 8,9,10,11 Port45 45 Ext 400000 Eth176 0 9 8 +Ethernet180 12,13,14,15 Port46 46 Ext 400000 Eth180 0 13 8 +Ethernet184 0,1,2,3 Port47 47 Ext 400000 Eth184 0 1 8 +Ethernet188 4,5,6,7 Port48 48 Ext 400000 Eth188 0 5 8 +Ethernet192 160,161,162,163 Port49 49 Ext 400000 Eth192 5 1 8 +Ethernet196 164,165,166,167 Port50 50 Ext 400000 Eth196 5 5 8 +Ethernet200 168,169,170,171 Port51 51 Ext 400000 Eth200 5 9 8 +Ethernet204 172,173,174,175 Port52 52 Ext 400000 Eth204 5 13 8 +Ethernet208 176,177,178,179 Port53 53 Ext 400000 Eth208 5 17 8 +Ethernet212 180,181,182,183 Port54 54 Ext 400000 Eth212 5 21 8 +Ethernet216 184,185,186,187 Port55 55 Ext 400000 Eth216 5 25 8 +Ethernet220 188,189,190,191 Port56 56 Ext 400000 Eth220 5 29 8 +Ethernet224 248,249,250,251 Port57 57 Ext 400000 Eth224 7 25 8 +Ethernet228 252,253,254,255 Port58 58 Ext 400000 Eth228 7 29 8 +Ethernet232 240,241,242,243 Port59 59 Ext 400000 Eth232 7 17 8 +Ethernet236 244,245,246,247 Port60 60 Ext 400000 Eth236 7 21 8 +Ethernet240 232,233,234,235 Port61 61 Ext 400000 Eth240 7 9 8 +Ethernet244 236,237,238,239 Port62 62 Ext 400000 Eth244 7 13 8 +Ethernet248 224,225,226,227 Port63 63 Ext 400000 Eth248 7 1 8 +Ethernet252 228,229,230,231 Port64 64 Ext 400000 Eth252 7 5 8 +Ethernet256 256,257,258,259 Port65 65 Ext 100000 Eth256 2 33 8 +Ethernet260 260,261,262,263 Port66 66 Ext 100000 Eth260 6 33 8 +Ethernet-Rec0 621 Port67 67 Rec 400000 Rcy0 0 221 8 diff --git a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/psai.profile b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/psai.profile new file mode 100644 index 00000000000..a094d074a3a --- /dev/null +++ b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/psai.profile @@ -0,0 +1 @@ +SAI_INIT_CONFIG_FILE=/usr/share/sonic/hwsku/agera2.bcm diff --git a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/qos.json.j2 b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/qos.json.j2 new file mode 100644 index 00000000000..42255ff45d9 --- /dev/null +++ b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/qos.json.j2 @@ -0,0 +1,172 @@ +{%- macro generate_dscp_to_tc_map_per_sku() -%} + "DSCP_TO_TC_MAP": { + "NH_DEFAULT_DSCP_TO_TC_MAP": { + "0" : "0", + "1" : "0", + "2" : "0", + "3" : "0", + "4" : "0", + "5" : "0", + "6" : "0", + "7" : "0", + "8" : "1", + "9" : "1", + "10": "1", + "11": "1", + "12": "1", + "13": "1", + "14": "1", + "15": "1", + "16": "2", + "17": "2", + "18": "2", + "19": "2", + "20": "2", + "21": "2", + "22": "2", + "23": "2", + "24": "3", + "25": "3", + "26": "3", + "27": "3", + "28": "3", + "29": "3", + "30": "3", + "31": "3", + "32": "4", + "33": "4", + "34": "4", + "35": "4", + "36": "4", + "37": "4", + "38": "4", + "39": "4", + "40": "5", + "41": "5", + "42": "5", + "43": "5", + "44": "5", + "45": "5", + "46": "5", + "47": "5", + "48": "6", + "49": "6", + "50": "6", + "51": "6", + "52": "6", + "53": "6", + "54": "6", + "55": "6", + "56": "7", + "57": "7", + "58": "7", + "59": "7", + "60": "7", + "61": "7", + "62": "7", + "63": "7" + } + }, +{%- endmacro -%} + +{%- macro generate_global_dscp_to_tc_map() %} +{# This is an empty macro since the global DSCP_TO_TC map is not required #} +{%- endmacro %} + +{%- macro generate_tc_to_queue_map_per_sku() -%} + "TC_TO_QUEUE_MAP": { + "NH_DEFAULT_TC_TO_QUEUE_MAP": { + "0": "0", + "1": "1", + "2": "2", + "3": "3", + "4": "4", + "5": "5", + "6": "6", + "7": "7" + } + }, +{%- endmacro -%} + +{%- macro generate_tc_to_pg_map_per_sku() -%} + "TC_TO_PRIORITY_GROUP_MAP": { + "NH_DEFAULT_TC_TO_PRI_GROUP_MAP": { + "0": "0", + "1": "1", + "2": "2", + "3": "3", + "4": "4", + "5": "5", + "6": "6", + "7": "7" + } + }, +{%- endmacro -%} + +{%- macro generate_port_qos_map(port_names_active) -%} + "PORT_QOS_MAP": { +{% for port in port_names_active.split(',') %} + "{{ port }}": { + "dscp_to_tc_map" : "NH_DEFAULT_DSCP_TO_TC_MAP", + "tc_to_queue_map" : "NH_DEFAULT_TC_TO_QUEUE_MAP", + "tc_to_pg_map" : "NH_DEFAULT_TC_TO_PRI_GROUP_MAP" + }{% if not loop.last %},{% endif %} +{% endfor %} + }, +{%- endmacro -%} + +{%- macro generate_scheduler_per_sku() -%} + "SCHEDULER": { + "scheduler.0": { + "type" : "DWRR", + "weight": "20" + }, + "scheduler.1": { + "type" : "DWRR", + "weight": "30" + }, + "scheduler.2": { + "type" : "DWRR", + "weight": "50" + }, + "scheduler.3": { + "cir": "2000000000", + "meter_type": "bytes", + "pir": "2000000000", + "type": "STRICT" + } + }, +{%- endmacro -%} + +{%- macro generate_single_queue_per_sku(port) -%} + "{{ port }}|0": { + "scheduler": "scheduler.0" + }, + "{{ port }}|1": { + "scheduler": "scheduler.0" + }, + "{{ port }}|2": { + "scheduler": "scheduler.1" + }, + "{{ port }}|3": { + "scheduler": "scheduler.2" + }, + "{{ port }}|4": { + "scheduler": "scheduler.2" + }, + "{{ port }}|5": { + "scheduler": "scheduler.2" + }, + "{{ port }}|6": { + "scheduler": "scheduler.3" + }, + "{{ port }}|7": { + "scheduler": "scheduler.3" + } +{%- endmacro -%} + +{%- macro generate_wred_profiles() %} +{# wred is disabled #} +{%- endmacro %} + +{%- include 'qos_config.j2' %} diff --git a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/sai.profile b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/sai.profile new file mode 100644 index 00000000000..f30aaeb5871 --- /dev/null +++ b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/sai.profile @@ -0,0 +1,2 @@ +SAI_INIT_CONFIG_FILE=/usr/share/sonic/hwsku/nh5010-default.bcm +SAI_NUM_ECMP_MEMBERS=128 diff --git a/device/nexthop/x86_64-nexthop_5010-r0/default_sku b/device/nexthop/x86_64-nexthop_5010-r0/default_sku new file mode 100644 index 00000000000..ad29380a0f4 --- /dev/null +++ b/device/nexthop/x86_64-nexthop_5010-r0/default_sku @@ -0,0 +1 @@ +NH-5010-F-O64 l1 diff --git a/device/nexthop/x86_64-nexthop_5010-r0/gbsyncd.ini b/device/nexthop/x86_64-nexthop_5010-r0/gbsyncd.ini new file mode 100644 index 00000000000..6324bdd874f --- /dev/null +++ b/device/nexthop/x86_64-nexthop_5010-r0/gbsyncd.ini @@ -0,0 +1 @@ +platform=gbsyncd-agera2 diff --git a/device/nexthop/x86_64-nexthop_5010-r0/installer.conf b/device/nexthop/x86_64-nexthop_5010-r0/installer.conf new file mode 100644 index 00000000000..e172a88fc88 --- /dev/null +++ b/device/nexthop/x86_64-nexthop_5010-r0/installer.conf @@ -0,0 +1 @@ +ONIE_PLATFORM_EXTRA_CMDLINE_LINUX="crashkernel=512M" diff --git a/device/nexthop/x86_64-nexthop_5010-r0/pcie-variables.yaml b/device/nexthop/x86_64-nexthop_5010-r0/pcie-variables.yaml new file mode 100644 index 00000000000..de3d6c566ec --- /dev/null +++ b/device/nexthop/x86_64-nexthop_5010-r0/pcie-variables.yaml @@ -0,0 +1,41 @@ +# Commands to retrieve the bus number for each PCIe device. +# Context: PCIe bus numbers are non-deterministic and can be looked up +# from the root ports after boot. +# +# Strings in pcie.yaml.j2 matching "{{}}" will be replaced with +# the result of the lookup_command, to generate /usr/share/sonic/platform/pcie.yaml. + +- name: "asic_1_bus" + lookup_command: "setpci -s 00:01.2 0x19.b" + +- name: "cpu_card_fpga_bus" + lookup_command: "setpci -s 00:02.1 0x19.b" + +- name: "switchcard_fpga_bus" + lookup_command: "setpci -s 00:02.2 0x19.b" + +- name: "asic_2_bus" + lookup_command: "setpci -s 00:02.3 0x19.b" + +- name: "nvme_bus" + lookup_command: "setpci -s 00:02.4 0x19.b" + +- name: "amd_soc_group_1_bus" + lookup_command: "setpci -s 00:08.1 0x19.b" + +- name: "amd_soc_group_2_bus" + lookup_command: "setpci -s 00:08.2 0x19.b" + +- name: "amd_soc_group_3_bus" + lookup_command: "setpci -s 00:08.3 0x19.b" + +# Commands to retrieve the PCIe address for each device. +# Strings in pddf-device.json.j2 matching "{{}}"" will be replaced with +# the result of the lookup_command, to generate /usr/share/sonic/platform/pddf/pddf-device.json. + +- name: "cpu_card_fpga_bdf" + lookup_command: "setpci -s 00:02.1 0x19.b | xargs printf '0000:%s:00.0'" + +- name: "switchcard_fpga_bdf" + lookup_command: "setpci -s 00:02.2 0x19.b | xargs printf '0000:%s:00.0'" + diff --git a/device/nexthop/x86_64-nexthop_5010-r0/pcie.yaml b/device/nexthop/x86_64-nexthop_5010-r0/pcie.yaml new file mode 100644 index 00000000000..7a125466e0f --- /dev/null +++ b/device/nexthop/x86_64-nexthop_5010-r0/pcie.yaml @@ -0,0 +1 @@ +- description: "Generated at runtime by pcie.yaml.j2" diff --git a/device/nexthop/x86_64-nexthop_5010-r0/pcie.yaml.j2 b/device/nexthop/x86_64-nexthop_5010-r0/pcie.yaml.j2 new file mode 100644 index 00000000000..a99df0da55c --- /dev/null +++ b/device/nexthop/x86_64-nexthop_5010-r0/pcie.yaml.j2 @@ -0,0 +1,141 @@ +- bus: '00' + dev: '00' + fn: '0' + id: 14b5 + name: 'Host bridge: Advanced Micro Devices, Inc. [AMD] Family 17h-19h PCIe Root + Complex (rev 01)' +- bus: '00' + dev: '00' + fn: '2' + id: 14b6 + name: 'IOMMU: Advanced Micro Devices, Inc. [AMD] Family 17h-19h IOMMU' +- bus: '00' + dev: '01' + fn: '0' + id: 14b7 + name: 'Host bridge: Advanced Micro Devices, Inc. [AMD] Family 17h-19h PCIe Dummy + Host Bridge (rev 01)' +- bus: '00' + dev: '01' + fn: '2' + id: 14b8 + name: 'PCI bridge: Advanced Micro Devices, Inc. [AMD] Family 17h-19h PCIe GPP Bridge' +- bus: '00' + dev: '02' + fn: '0' + id: 14b7 + name: 'Host bridge: Advanced Micro Devices, Inc. [AMD] Family 17h-19h PCIe Dummy + Host Bridge (rev 01)' +- bus: '00' + dev: '02' + fn: '1' + id: 14ba + name: 'PCI bridge: Advanced Micro Devices, Inc. [AMD] Family 17h-19h PCIe GPP Bridge' +- bus: '00' + dev: '02' + fn: '2' + id: 14ba + name: 'PCI bridge: Advanced Micro Devices, Inc. [AMD] Family 17h-19h PCIe GPP Bridge' +- bus: '00' + dev: '02' + fn: '3' + id: 14ba + name: 'PCI bridge: Advanced Micro Devices, Inc. [AMD] Family 17h-19h PCIe GPP Bridge' +- bus: '00' + dev: '02' + fn: '4' + id: 14ba + name: 'PCI bridge: Advanced Micro Devices, Inc. [AMD] Family 17h-19h PCIe GPP Bridge' +- bus: '00' + dev: '03' + fn: '0' + id: 14b7 + name: 'Host bridge: Advanced Micro Devices, Inc. [AMD] Family 17h-19h PCIe Dummy + Host Bridge (rev 01)' +- bus: '00' + dev: '04' + fn: '0' + id: 14b7 + name: 'Host bridge: Advanced Micro Devices, Inc. [AMD] Family 17h-19h PCIe Dummy + Host Bridge (rev 01)' +- bus: '00' + dev: 08 + fn: '0' + id: 14b7 + name: 'Host bridge: Advanced Micro Devices, Inc. [AMD] Family 17h-19h PCIe Dummy + Host Bridge (rev 01)' +- bus: '00' + dev: 08 + fn: '1' + id: 14b9 + name: 'PCI bridge: Advanced Micro Devices, Inc. [AMD] Family 17h-19h Internal PCIe + GPP Bridge (rev 10)' +- bus: '00' + dev: 08 + fn: '2' + id: 14b9 + name: 'PCI bridge: Advanced Micro Devices, Inc. [AMD] Family 17h-19h Internal PCIe + GPP Bridge (rev 10)' +- bus: '00' + dev: 08 + fn: '3' + id: 14b9 + name: 'PCI bridge: Advanced Micro Devices, Inc. [AMD] Family 17h-19h Internal PCIe + GPP Bridge (rev 10)' +- bus: '00' + dev: '14' + fn: '0' + id: 790b + name: 'SMBus: Advanced Micro Devices, Inc. [AMD] FCH SMBus Controller (rev 71)' +- bus: '00' + dev: '14' + fn: '3' + id: '1682' + name: 'ISA bridge: Advanced Micro Devices, Inc. [AMD] Device 1682 (rev 51)' +- bus: '{{asic_1_bus}}' + dev: '00' + fn: '0' + id: '8870' + name: 'Ethernet controller: Broadcom Inc. and subsidiaries Device 8870 (rev 02)' +- bus: '{{cpu_card_fpga_bus}}' + dev: '00' + fn: '0' + id: '7011' + name: 'Serial controller: Xilinx Corporation 7-Series FPGA Hard PCIe block (AXI/debug)' +- bus: '{{switchcard_fpga_bus}}' + dev: '00' + fn: '0' + id: '7012' + name: 'Serial controller: Xilinx Corporation 7-Series FPGA Hard PCIe block (AXI/debug)' +- bus: '{{asic_2_bus}}' + dev: '00' + fn: '0' + id: '8870' + name: 'Ethernet controller: Broadcom Inc. and subsidiaries Device 8870 (rev 02)' +- bus: '{{nvme_bus}}' + dev: '00' + fn: '0' + id: 110b + name: 'Non-Volatile memory controller: ATP ELECTRONICS INC Device 110b (rev 03)' +- bus: '{{amd_soc_group_1_bus}}' + dev: '00' + fn: '2' + id: '1649' + name: 'Encryption controller: Advanced Micro Devices, Inc. [AMD] VanGogh PSP/CCP' +- bus: '{{amd_soc_group_2_bus}}' + dev: '00' + fn: '0' + id: 145a + name: 'Non-Essential Instrumentation [1300]: Advanced Micro Devices, Inc. [AMD] + Zeppelin/Raven/Raven2 PCIe Dummy Function (rev a1)' +- bus: '{{amd_soc_group_2_bus}}' + dev: '00' + fn: '2' + id: '1458' + name: 'Ethernet controller: Advanced Micro Devices, Inc. [AMD] XGMAC 10GbE Controller' +- bus: '{{amd_soc_group_2_bus}}' + dev: '00' + fn: '3' + id: '1458' + name: 'Ethernet controller: Advanced Micro Devices, Inc. [AMD] XGMAC 10GbE Controller' + diff --git a/device/nexthop/x86_64-nexthop_5010-r0/pddf/pd-plugin.json b/device/nexthop/x86_64-nexthop_5010-r0/pddf/pd-plugin.json new file mode 100644 index 00000000000..ab136e44827 --- /dev/null +++ b/device/nexthop/x86_64-nexthop_5010-r0/pddf/pd-plugin.json @@ -0,0 +1,78 @@ +{ + "PSU": { + "name": { + "1": "PSU1", + "2": "PSU2" + }, + "fan_name": { + "1": { + "1": "PSU1_FAN1" + }, + "2": { + "1": "PSU2_FAN1" + } + }, + "thermal_name": { + "1": "PSU1_TEMP1", + "2": "PSU1_TEMP2", + "3": "PSU1_TEMP3", + "4": "PSU2_TEMP1", + "5": "PSU2_TEMP2", + "6": "PSU2_TEMP3" + }, + "psu_present": { + "i2c": { + "valmap": { + "1": false, + "0": true + } + } + }, + "psu_power_good": { + "i2c": { + "valmap": { + "1": true, + "0": false + } + } + }, + "psu_fan_dir": { + "i2c": { + "valmap": { + "D1U74T-W-3200-12-HB4C": "exhaust" + } + } + }, + "PSU_FAN_MAX_SPEED": "37000" + }, + "FAN": { + "present": { + "i2c": { + "valmap": { + "1": true, + "0": false + } + } + }, + "direction": { + "i2c": { + "valmap": { + "1": "exhaust" + } + } + }, + "fault": { + "i2c": { + "valmap": { + "1": true, + "0": false + } + } + }, + "duty_cycle_to_pwm": "lambda dc: ((dc/100) * 255)", + "pwm_to_duty_cycle": "lambda pwm: ((pwm/255) * 100)" + }, + "REBOOT_CAUSE": { + "reboot_cause_file": "/host/reboot-cause/reboot-cause.txt" + } +} diff --git a/device/nexthop/x86_64-nexthop_5010-r0/pddf/pddf-device.json b/device/nexthop/x86_64-nexthop_5010-r0/pddf/pddf-device.json new file mode 100644 index 00000000000..f12f708c904 --- /dev/null +++ b/device/nexthop/x86_64-nexthop_5010-r0/pddf/pddf-device.json @@ -0,0 +1,3 @@ +{ + "description": "Generated at runtime by pddf-device.json.j2" +} diff --git a/device/nexthop/x86_64-nexthop_5010-r0/pddf/pddf-device.json.j2 b/device/nexthop/x86_64-nexthop_5010-r0/pddf/pddf-device.json.j2 new file mode 100644 index 00000000000..17265b6a6e5 --- /dev/null +++ b/device/nexthop/x86_64-nexthop_5010-r0/pddf/pddf-device.json.j2 @@ -0,0 +1,16953 @@ +{ + "PLATFORM": { + "num_psus": 2, + "num_fantrays": 4, + "num_fans_pertray": 2, + "num_ports": 66, + "num_temps": 31, + "num_asic_temps": 52, + "num_voltage_sensors": 82, + "num_current_sensors": 20, + "num_components": 7, + "pddf_dev_types": { + "description": " - Below is the list of supported PDDF device types (chip names) for various components. If any component uses some other driver, we will create the client using 'echo > /new_device' method", + "MULTIFPGAPCIE": [ + "multifpgapci" + ], + "PORT_MODULE": [ + "pddf_xcvr" + ], + "FAN": [ + "fan_multifpgapci" + ], + "PSU": [ + "psu_pmbus" + ], + "CPLDMUX": [ + "multifpgapci_mux" + ] + }, + "std_kos": [ + "at24", + "i2c-dev", + "adm1266", + "optoe" + ], + "pddf_kos": [ + "pddf_multifpgapci_i2c_module", + "pddf_multifpgapci_gpio_module", + "pddf_multifpgapci_mdio_module", + "pddf_multifpgapci_spi_module", + "pddf_client_module", + "pddf_multifpgapci_driver", + "pddf_multifpgapci_module", + "pddf_led_module", + "pddf_psu_module", + "pddf_fan_driver_module", + "pddf_fan_module", + "pddf_xcvr_module", + "pddf_xcvr_driver_module", + "pddf_cpldmux_module", + "pddf_cpldmux_driver", + "pddf_multifpgapci_gpio_driver" + ], + "custom_kos": [ + "pddf_custom_fpga_algo", + "pddf_custom_mdio_algo", + "nh_pmbus_core", + "nh_tda38740", + "nh_tmp464" + ] + }, + "COMPONENT1": { + "comp_attr": { + "name": "SWITCHCARD_FPGA", + "type": "fpga", + "description": "Switchcard FPGA", + "boot_type": "none" + }, + "attr_list": [ + { + "attr_name": "version", + "get_cmd": "fpga read32 {{switchcard_fpga_bdf}} 0x0 | sed 's/^0x//'" + }, + { + "attr_name": "model", + "get_cmd": "echo 'N/A'" + }, + { + "attr_name": "serial", + "get_cmd": "echo 'N/A'" + }, + { + "attr_name": "revision", + "get_cmd": "echo 'N/A'" + }, + { + "attr_name": "update", + "cmd": "/var/platform/fwpackage/fwpackage/update_firmware.py NH-5010-F SWITCHCARD_FPGA {}" + } + ] + }, + "COMPONENT2": { + "comp_attr": { + "name": "MEZZCARD_FPGA", + "type": "fpga", + "description": "Mezzcard FPGA", + "boot_type": "none" + }, + "attr_list": [ + { + "attr_name": "version", + "get_cmd": "fpga read32 {{switchcard_fpga_bdf}} 0x4000 | sed 's/^0x//'" + }, + { + "attr_name": "model", + "get_cmd": "echo 'N/A'" + }, + { + "attr_name": "serial", + "get_cmd": "echo 'N/A'" + }, + { + "attr_name": "revision", + "get_cmd": "echo 'N/A'" + }, + { + "attr_name": "update", + "cmd": "/var/platform/fwpackage/fwpackage/update_firmware.py NH-5010-F MEZZCARD_FPGA {}" + } + ] + }, + "COMPONENT3": { + "comp_attr": { + "name": "CPUCARD_FPGA", + "type": "fpga", + "description": "CPU card FPGA", + "boot_type": "none" + }, + "attr_list": [ + { + "attr_name": "version", + "get_cmd": "fpga read32 {{cpu_card_fpga_bdf}} 0x0 | sed 's/^0x//'" + }, + { + "attr_name": "model", + "get_cmd": "echo 'N/A'" + }, + { + "attr_name": "serial", + "get_cmd": "echo 'N/A'" + }, + { + "attr_name": "revision", + "get_cmd": "echo 'N/A'" + }, + { + "attr_name": "update", + "cmd": "/var/platform/fwpackage/fwpackage/update_firmware.py NH-5010-F CPUCARD_FPGA {}" + } + ] + }, + "COMPONENT4": { + "comp_attr": { + "name": "BIOS", + "type": "bios", + "description": "CPU card BIOS", + "boot_type": "cold" + }, + "attr_list": [ + { + "attr_name": "version", + "get_cmd": "dmidecode -s bios-version" + }, + { + "attr_name": "model", + "get_cmd": "echo 'N/A'" + }, + { + "attr_name": "serial", + "get_cmd": "echo 'N/A'" + }, + { + "attr_name": "revision", + "get_cmd": "echo 'N/A'" + }, + { + "attr_name": "update", + "cmd": "/var/platform/fwpackage/fwpackage/update_firmware.py NH-5010-F BIOS {}" + } + ] + }, + "COMPONENT5": { + "comp_attr": { + "name": "ONIE", + "type": "bios", + "description": "ONIE", + "boot_type": "cold" + }, + "attr_list": [ + { + "attr_name": "version", + "get_cmd": "awk -F = '/onie_version/ {print $2}' /host/machine.conf" + }, + { + "attr_name": "model", + "get_cmd": "echo 'N/A'" + }, + { + "attr_name": "serial", + "get_cmd": "echo 'N/A'" + }, + { + "attr_name": "revision", + "get_cmd": "echo 'N/A'" + }, + { + "attr_name": "update", + "cmd": "/var/platform/fwpackage/fwpackage/update_firmware.py NH-5010-F ONIE {}" + } + ] + }, + "COMPONENT6": { + "comp_attr": { + "name": "TPM", + "type": "tpm", + "description": "TPM", + "boot_type": "cold" + }, + "attr_list": [ + { + "attr_name": "version", + "get_cmd": "dmidecode --type 43|awk '/Firmware Revision:/{print $3}'" + }, + { + "attr_name": "model", + "get_cmd": "tpm2_getcap properties-fixed | grep -A 2 'TPM2_PT_VENDOR_STRING_[12]' | awk '/value:/ { ORS=\"\"; gsub(\"\\\"\", \"\", $2); print $2 }'" + }, + { + "attr_name": "serial", + "get_cmd": "echo 'N/A'" + }, + { + "attr_name": "revision", + "get_cmd": "tpm2_getcap properties-fixed | grep -A 2 TPM2_PT_REVISION | awk '/value:/ { print $2 }'" + }, + { + "attr_name": "update", + "cmd": "/var/platform/fwpackage/fwpackage/update_firmware.py NH-5010-F TPM {}" + } + ] + }, + "COMPONENT7": { + "comp_attr": { + "name": "NVMe", + "type": "storage", + "description": "NVMe storage", + "boot_type": "cold" + }, + "attr_list": [ + { + "attr_name": "version", + "get_cmd": "cat /sys/class/nvme/nvme0/firmware_rev" + }, + { + "attr_name": "model", + "get_cmd": "cat /sys/class/nvme/nvme0/model" + }, + { + "attr_name": "serial", + "get_cmd": "cat /sys/class/nvme/nvme0/serial" + }, + { + "attr_name": "revision", + "get_cmd": "echo N/A" + }, + { + "attr_name": "update", + "cmd": "/var/platform/fwpackage/fwpackage/update_firmware.py NH-5010-F NVMe {}" + } + ] + }, + "SYSTEM": { + "dev_info": { + "device_type": "CPU", + "device_name": "ROOT_COMPLEX", + "device_parent": null + }, + "i2c": { + "CONTROLLERS": [ + { + "dev_name": "pcie-0", + "dev": "PCIE0" + } + ] + } + }, + "MULTIFPGAPCIESYSTEM0": { + "dev_info": { + "device_type": "MULTIFPGAPCIESYSTEM", + "device_name": "MULTIFPGAPCIESYSTEM0", + "device_parent": null + }, + "dev_attr": { + "PCI_DEVICE_IDS": [ + { + "vendor": "0x10ee", + "device": "0x7011" + }, + { + "vendor": "0x10ee", + "device": "0x7012" + }, + { + "vendor": "0x10ee", + "device": "0x7013" + }, + { + "vendor": "0x20a4", + "device": "0x7011" + }, + { + "vendor": "0x20a4", + "device": "0x7012" + }, + { + "vendor": "0x20a4", + "device": "0x7013" + } + ] + } + }, + "PCIE0": { + "dev_info": { + "device_type": "PCIE", + "device_name": "PCIE0", + "device_parent": "SYSTEM" + }, + "i2c": { + "DEVICES": [ + { + "dev": "MULTIFPGAPCIE0" + }, + { + "dev": "MULTIFPGAPCIE1" + } + ] + } + }, + "MULTIFPGAPCIE0": { + "dev_info": { + "device_type": "MULTIFPGAPCIE", + "device_name": "CPUCARD_FPGA", + "device_parent": "PCIE0", + "device_bdf": "{{cpu_card_fpga_bdf}}", + "dev_attr": {} + }, + "dev_attr": { + "pwr_cycle_reg_offset": "0x8", + "pwr_cycle_enable_word": "0xdeadbeef" + }, + "i2c": { + "dev_attr": { + "virt_bus": "0x4", + "ch_base_offset": "0x40000", + "ch_size": "0x200", + "num_virt_ch": "0x8" + }, + "channel": [ + { + "chn": "3", + "dev": "DPM1" + }, + { + "chn": "5", + "dev": "DPM2" + }, + { + "chn": "5", + "dev": "DPM3" + }, + { + "chn": "5", + "dev": "DPM4" + }, + { + "chn": "6", + "dev": "EEPROM1" + }, + { + "chn": "6", + "dev": "EEPROM2" + }, + { + "chn": "6", + "dev": "TMP468-1" + }, + { + "chn": "6", + "dev": "TMP468-2" + }, + { + "chn": "6", + "dev": "TMP464" + } + ] + }, + "gpio": { + "line0": { + "attr_list": [ + { + "offset": "0xb4", + "bit": "0x0", + "direction": "0x1" + } + ] + }, + "line1": { + "attr_list": [ + { + "offset": "0xb4", + "bit": "0x1", + "direction": "0x1" + } + ] + }, + "line2": { + "attr_list": [ + { + "offset": "0xb4", + "bit": "0x2", + "direction": "0x0" + } + ] + }, + "line3": { + "attr_list": [ + { + "offset": "0xb4", + "bit": "0x10", + "direction": "0x1" + } + ] + } + } + }, + "EEPROM1": { + "dev_info": { + "device_type": "EEPROM", + "device_name": "EEPROM1", + "device_parent": "MULTIFPGAPCIE0" + }, + "i2c": { + "topo_info": { + "parent_bus": "0xa", + "dev_addr": "0x50", + "dev_type": "24c64" + }, + "dev_attr": { + "access_mode": "BLOCK" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "EEPROM2": { + "dev_info": { + "device_type": "EEPROM", + "device_name": "EEPROM2", + "device_parent": "MULTIFPGAPCIE0" + }, + "i2c": { + "topo_info": { + "parent_bus": "0xa", + "dev_addr": "0x51", + "dev_type": "24c64" + }, + "dev_attr": { + "access_mode": "BLOCK" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "TMP468-1": { + "dev_info": { + "device_type": "TEMP_SENSOR", + "device_name": "TMP468-1", + "device_parent": "MULTIFPGAPCIE0" + }, + "i2c": { + "topo_info": { + "parent_bus": "0xa", + "dev_addr": "0x48", + "dev_type": "nh_tmp468" + }, + "attr_list": [ + { + "attr_name": "temp1_high_threshold", + "drv_attr_name": "temp1_max" + }, + { + "attr_name": "temp1_max_hyst" + }, + { + "attr_name": "temp1_input" + } + ] + } + }, + "TMP468-2": { + "dev_info": { + "device_type": "TEMP_SENSOR", + "device_name": "TMP468-2", + "device_parent": "MULTIFPGAPCIE0" + }, + "i2c": { + "topo_info": { + "parent_bus": "0xa", + "dev_addr": "0x49", + "dev_type": "nh_tmp468" + }, + "attr_list": [ + { + "attr_name": "temp1_high_threshold", + "drv_attr_name": "temp1_max" + }, + { + "attr_name": "temp1_max_hyst" + }, + { + "attr_name": "temp1_input" + } + ] + } + }, + "TMP464": { + "dev_info": { + "device_type": "TEMP_SENSOR", + "device_name": "TMP464", + "device_parent": "MULTIFPGAPCIE0" + }, + "i2c": { + "topo_info": { + "parent_bus": "0xa", + "dev_addr": "0x4a", + "dev_type": "nh_tmp464" + }, + "attr_list": [ + { + "attr_name": "temp1_high_threshold", + "drv_attr_name": "temp1_max" + }, + { + "attr_name": "temp1_max_hyst" + }, + { + "attr_name": "temp1_input" + } + ] + } + }, + "TEMP1": { + "dev_info": { + "device_type": "TEMP_SENSOR", + "device_name": "TMP468-1-CH1", + "device_parent": "MULTIFPGAPCIE0", + "virt_parent": "TMP468-1" + }, + "dev_attr": { + "display_name": "Switch Card Left Lower Rear" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "temp1_input", + "drv_attr_name": "temp1_input" + }, + { + "attr_name": "temp1_high_threshold", + "drv_attr_name": "temp1_max" + }, + { + "attr_name": "temp1_high_crit_threshold", + "drv_attr_name": "temp1_crit" + } + ] + } + }, + "TEMP2": { + "dev_info": { + "device_type": "TEMP_SENSOR", + "device_name": "TMP468-1-CH2", + "device_parent": "MULTIFPGAPCIE0", + "virt_parent": "TMP468-1" + }, + "dev_attr": { + "display_name": "Left Port Side Intake" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "temp1_input", + "drv_attr_name": "temp2_input" + }, + { + "attr_name": "temp1_high_threshold", + "drv_attr_name": "temp2_max" + }, + { + "attr_name": "temp1_high_crit_threshold", + "drv_attr_name": "temp2_crit" + } + ] + } + }, + "TEMP3": { + "dev_info": { + "device_type": "TEMP_SENSOR", + "device_name": "TMP468-1-CH3", + "device_parent": "MULTIFPGAPCIE0", + "virt_parent": "TMP468-1" + }, + "dev_attr": { + "display_name": "ASIC Diode 0 PADS tsen" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "temp1_input", + "drv_attr_name": "temp3_input" + }, + { + "attr_name": "temp1_high_threshold", + "drv_attr_name": "temp3_max" + }, + { + "attr_name": "temp1_high_crit_threshold", + "drv_attr_name": "temp3_crit" + } + ] + } + }, + "TEMP4": { + "dev_info": { + "device_type": "TEMP_SENSOR", + "device_name": "TMP468-1-CH4", + "device_parent": "MULTIFPGAPCIE0", + "virt_parent": "TMP468-1" + }, + "dev_attr": { + "display_name": "ASIC Diode 0 NIF0 tsen" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "temp1_input", + "drv_attr_name": "temp4_input" + }, + { + "attr_name": "temp1_high_threshold", + "drv_attr_name": "temp4_max" + }, + { + "attr_name": "temp1_high_crit_threshold", + "drv_attr_name": "temp4_crit" + } + ] + } + }, + "TEMP5": { + "dev_info": { + "device_type": "TEMP_SENSOR", + "device_name": "TMP468-1-CH5", + "device_parent": "MULTIFPGAPCIE0", + "virt_parent": "TMP468-1" + }, + "dev_attr": { + "display_name": "ASIC Diode 0 CORE tsen" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "temp1_input", + "drv_attr_name": "temp5_input" + }, + { + "attr_name": "temp1_high_threshold", + "drv_attr_name": "temp5_max" + }, + { + "attr_name": "temp1_high_crit_threshold", + "drv_attr_name": "temp5_crit" + } + ] + } + }, + "TEMP6": { + "dev_info": { + "device_type": "TEMP_SENSOR", + "device_name": "TMP468-1-CH6", + "device_parent": "MULTIFPGAPCIE0", + "virt_parent": "TMP468-1" + }, + "dev_attr": { + "display_name": "ASIC Diode 0 NIF1 tsen" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "temp1_input", + "drv_attr_name": "temp6_input" + }, + { + "attr_name": "temp1_high_threshold", + "drv_attr_name": "temp6_max" + }, + { + "attr_name": "temp1_high_crit_threshold", + "drv_attr_name": "temp6_crit" + } + ] + } + }, + "TEMP7": { + "dev_info": { + "device_type": "TEMP_SENSOR", + "device_name": "TMP468-1-CH7", + "device_parent": "MULTIFPGAPCIE0", + "virt_parent": "TMP468-1" + }, + "dev_attr": { + "display_name": "ASIC Diode 0 HBM_PHY1 tsen" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "temp1_input", + "drv_attr_name": "temp7_input" + }, + { + "attr_name": "temp1_high_threshold", + "drv_attr_name": "temp7_max" + }, + { + "attr_name": "temp1_high_crit_threshold", + "drv_attr_name": "temp7_crit" + } + ] + } + }, + "TEMP8": { + "dev_info": { + "device_type": "TEMP_SENSOR", + "device_name": "TMP468-1-CH8", + "device_parent": "MULTIFPGAPCIE0", + "virt_parent": "TMP468-1" + }, + "dev_attr": { + "display_name": "ASIC Diode 0 HBM_PHY2 tsen" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "temp1_input", + "drv_attr_name": "temp8_input" + }, + { + "attr_name": "temp1_high_threshold", + "drv_attr_name": "temp8_max" + }, + { + "attr_name": "temp1_high_crit_threshold", + "drv_attr_name": "temp8_crit" + } + ] + } + }, + "TEMP9": { + "dev_info": { + "device_type": "TEMP_SENSOR", + "device_name": "TMP468-2-CH1", + "device_parent": "MULTIFPGAPCIE0", + "virt_parent": "TMP468-2" + }, + "dev_attr": { + "display_name": "Switch Card Right Lower Rear" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "temp1_input", + "drv_attr_name": "temp1_input" + }, + { + "attr_name": "temp1_high_threshold", + "drv_attr_name": "temp1_max" + }, + { + "attr_name": "temp1_high_crit_threshold", + "drv_attr_name": "temp1_crit" + } + ] + } + }, + "TEMP10": { + "dev_info": { + "device_type": "TEMP_SENSOR", + "device_name": "TMP468-2-CH2", + "device_parent": "MULTIFPGAPCIE0", + "virt_parent": "TMP468-2" + }, + "dev_attr": { + "display_name": "Right Port Side Intake" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "temp1_input", + "drv_attr_name": "temp2_input" + }, + { + "attr_name": "temp1_high_threshold", + "drv_attr_name": "temp2_max" + }, + { + "attr_name": "temp1_high_crit_threshold", + "drv_attr_name": "temp2_crit" + } + ] + } + }, + "TEMP11": { + "dev_info": { + "device_type": "TEMP_SENSOR", + "device_name": "TMP468-2-CH3", + "device_parent": "MULTIFPGAPCIE0", + "virt_parent": "TMP468-2" + }, + "dev_attr": { + "display_name": "ASIC Diode 1 PADS tsen" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "temp1_input", + "drv_attr_name": "temp3_input" + }, + { + "attr_name": "temp1_high_threshold", + "drv_attr_name": "temp3_max" + }, + { + "attr_name": "temp1_high_crit_threshold", + "drv_attr_name": "temp3_crit" + } + ] + } + }, + "TEMP12": { + "dev_info": { + "device_type": "TEMP_SENSOR", + "device_name": "TMP468-2-CH4", + "device_parent": "MULTIFPGAPCIE0", + "virt_parent": "TMP468-2" + }, + "dev_attr": { + "display_name": "ASIC Diode 1 NIF0 tsen" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "temp1_input", + "drv_attr_name": "temp4_input" + }, + { + "attr_name": "temp1_high_threshold", + "drv_attr_name": "temp4_max" + }, + { + "attr_name": "temp1_high_crit_threshold", + "drv_attr_name": "temp4_crit" + } + ] + } + }, + "TEMP13": { + "dev_info": { + "device_type": "TEMP_SENSOR", + "device_name": "TMP468-2-CH5", + "device_parent": "MULTIFPGAPCIE0", + "virt_parent": "TMP468-2" + }, + "dev_attr": { + "display_name": "ASIC Diode 1 CORE tsen" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "temp1_input", + "drv_attr_name": "temp5_input" + }, + { + "attr_name": "temp1_high_threshold", + "drv_attr_name": "temp5_max" + }, + { + "attr_name": "temp1_high_crit_threshold", + "drv_attr_name": "temp5_crit" + } + ] + } + }, + "TEMP14": { + "dev_info": { + "device_type": "TEMP_SENSOR", + "device_name": "TMP468-2-CH6", + "device_parent": "MULTIFPGAPCIE0", + "virt_parent": "TMP468-2" + }, + "dev_attr": { + "display_name": "ASIC Diode 1 NIF1 tsen" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "temp1_input", + "drv_attr_name": "temp6_input" + }, + { + "attr_name": "temp1_high_threshold", + "drv_attr_name": "temp6_max" + }, + { + "attr_name": "temp1_high_crit_threshold", + "drv_attr_name": "temp6_crit" + } + ] + } + }, + "TEMP15": { + "dev_info": { + "device_type": "TEMP_SENSOR", + "device_name": "TMP468-2-CH7", + "device_parent": "MULTIFPGAPCIE0", + "virt_parent": "TMP468-2" + }, + "dev_attr": { + "display_name": "ASIC Diode 1 HBM_PHY1 tsen" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "temp1_input", + "drv_attr_name": "temp7_input" + }, + { + "attr_name": "temp1_high_threshold", + "drv_attr_name": "temp7_max" + }, + { + "attr_name": "temp1_high_crit_threshold", + "drv_attr_name": "temp7_crit" + } + ] + } + }, + "TEMP16": { + "dev_info": { + "device_type": "TEMP_SENSOR", + "device_name": "TMP468-2-CH8", + "device_parent": "MULTIFPGAPCIE0", + "virt_parent": "TMP468-2" + }, + "dev_attr": { + "display_name": "ASIC Diode 1 HBM_PHY2 tsen" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "temp1_input", + "drv_attr_name": "temp8_input" + }, + { + "attr_name": "temp1_high_threshold", + "drv_attr_name": "temp8_max" + }, + { + "attr_name": "temp1_high_crit_threshold", + "drv_attr_name": "temp8_crit" + } + ] + } + }, + "ASIC_TEMP1": { + "dev_info": { + "device_type": "ASIC_TEMP_SENSOR", + "device_name": "ASIC_TEMP1", + "device_parent": "None", + "nexthop_thermal_pid_domain": "None" + }, + "dev_attr": { + "display_name": "ASIC D0_VTMON_CORE", + "temp1_high_threshold": 95, + "temp1_high_crit_threshold": 110 + } + }, + "ASIC_TEMP2": { + "dev_info": { + "device_type": "ASIC_TEMP_SENSOR", + "device_name": "ASIC_TEMP2", + "device_parent": "None", + "nexthop_thermal_pid_domain": "None" + }, + "dev_attr": { + "display_name": "ASIC D0_VTMON_HBM_PHY1", + "temp1_high_threshold": 95, + "temp1_high_crit_threshold": 110 + } + }, + "ASIC_TEMP3": { + "dev_info": { + "device_type": "ASIC_TEMP_SENSOR", + "device_name": "ASIC_TEMP3", + "device_parent": "None", + "nexthop_thermal_pid_domain": "None" + }, + "dev_attr": { + "display_name": "ASIC D0_VTMON_HBM_PHY2", + "temp1_high_threshold": 95, + "temp1_high_crit_threshold": 110 + } + }, + "ASIC_TEMP4": { + "dev_info": { + "device_type": "ASIC_TEMP_SENSOR", + "device_name": "ASIC_TEMP4", + "device_parent": "None", + "nexthop_thermal_pid_domain": "None" + }, + "dev_attr": { + "display_name": "ASIC D0_VTMON_NIF0", + "temp1_high_threshold": 95, + "temp1_high_crit_threshold": 110 + } + }, + "ASIC_TEMP5": { + "dev_info": { + "device_type": "ASIC_TEMP_SENSOR", + "device_name": "ASIC_TEMP5", + "device_parent": "None", + "nexthop_thermal_pid_domain": "None" + }, + "dev_attr": { + "display_name": "ASIC D0_VTMON_NIF1", + "temp1_high_threshold": 95, + "temp1_high_crit_threshold": 110 + } + }, + "ASIC_TEMP6": { + "dev_info": { + "device_type": "ASIC_TEMP_SENSOR", + "device_name": "ASIC_TEMP6", + "device_parent": "None", + "nexthop_thermal_pid_domain": "None" + }, + "dev_attr": { + "display_name": "ASIC D0_VTMON_PADS", + "temp1_high_threshold": 95, + "temp1_high_crit_threshold": 110 + } + }, + "ASIC_TEMP7": { + "dev_info": { + "device_type": "ASIC_TEMP_SENSOR", + "device_name": "ASIC_TEMP7", + "device_parent": "None", + "nexthop_thermal_pid_domain": "None" + }, + "dev_attr": { + "display_name": "ASIC D1_VTMON_CORE", + "temp1_high_threshold": 95, + "temp1_high_crit_threshold": 110 + } + }, + "ASIC_TEMP8": { + "dev_info": { + "device_type": "ASIC_TEMP_SENSOR", + "device_name": "ASIC_TEMP8", + "device_parent": "None", + "nexthop_thermal_pid_domain": "None" + }, + "dev_attr": { + "display_name": "ASIC D1_VTMON_HBM_PHY1", + "temp1_high_threshold": 95, + "temp1_high_crit_threshold": 110 + } + }, + "ASIC_TEMP9": { + "dev_info": { + "device_type": "ASIC_TEMP_SENSOR", + "device_name": "ASIC_TEMP9", + "device_parent": "None", + "nexthop_thermal_pid_domain": "None" + }, + "dev_attr": { + "display_name": "ASIC D1_VTMON_HBM_PHY2", + "temp1_high_threshold": 95, + "temp1_high_crit_threshold": 110 + } + }, + "ASIC_TEMP10": { + "dev_info": { + "device_type": "ASIC_TEMP_SENSOR", + "device_name": "ASIC_TEMP10", + "device_parent": "None", + "nexthop_thermal_pid_domain": "None" + }, + "dev_attr": { + "display_name": "ASIC D1_VTMON_NIF0", + "temp1_high_threshold": 95, + "temp1_high_crit_threshold": 110 + } + }, + "ASIC_TEMP11": { + "dev_info": { + "device_type": "ASIC_TEMP_SENSOR", + "device_name": "ASIC_TEMP11", + "device_parent": "None", + "nexthop_thermal_pid_domain": "None" + }, + "dev_attr": { + "display_name": "ASIC D1_VTMON_NIF1", + "temp1_high_threshold": 95, + "temp1_high_crit_threshold": 110 + } + }, + "ASIC_TEMP12": { + "dev_info": { + "device_type": "ASIC_TEMP_SENSOR", + "device_name": "ASIC_TEMP12", + "device_parent": "None", + "nexthop_thermal_pid_domain": "None" + }, + "dev_attr": { + "display_name": "ASIC D1_VTMON_PADS", + "temp1_high_threshold": 95, + "temp1_high_crit_threshold": 110 + } + }, + "ASIC_TEMP13": { + "dev_info": { + "device_type": "ASIC_TEMP_SENSOR", + "device_name": "ASIC_TEMP13", + "device_parent": "None", + "nexthop_thermal_pid_domain": "None" + }, + "dev_attr": { + "display_name": "ASIC NIF0", + "temp1_high_threshold": 95, + "temp1_high_crit_threshold": 110 + } + }, + "ASIC_TEMP14": { + "dev_info": { + "device_type": "ASIC_TEMP_SENSOR", + "device_name": "ASIC_TEMP14", + "device_parent": "None", + "nexthop_thermal_pid_domain": "None" + }, + "dev_attr": { + "display_name": "ASIC NIF1", + "temp1_high_threshold": 95, + "temp1_high_crit_threshold": 110 + } + }, + "ASIC_TEMP15": { + "dev_info": { + "device_type": "ASIC_TEMP_SENSOR", + "device_name": "ASIC_TEMP15", + "device_parent": "None", + "nexthop_thermal_pid_domain": "None" + }, + "dev_attr": { + "display_name": "ASIC NIF2", + "temp1_high_threshold": 95, + "temp1_high_crit_threshold": 110 + } + }, + "ASIC_TEMP16": { + "dev_info": { + "device_type": "ASIC_TEMP_SENSOR", + "device_name": "ASIC_TEMP16", + "device_parent": "None", + "nexthop_thermal_pid_domain": "None" + }, + "dev_attr": { + "display_name": "ASIC NIF3", + "temp1_high_threshold": 95, + "temp1_high_crit_threshold": 110 + } + }, + "ASIC_TEMP17": { + "dev_info": { + "device_type": "ASIC_TEMP_SENSOR", + "device_name": "ASIC_TEMP17", + "device_parent": "None", + "nexthop_thermal_pid_domain": "None" + }, + "dev_attr": { + "display_name": "ASIC NIF4", + "temp1_high_threshold": 95, + "temp1_high_crit_threshold": 110 + } + }, + "ASIC_TEMP18": { + "dev_info": { + "device_type": "ASIC_TEMP_SENSOR", + "device_name": "ASIC_TEMP18", + "device_parent": "None", + "nexthop_thermal_pid_domain": "None" + }, + "dev_attr": { + "display_name": "ASIC NIF5", + "temp1_high_threshold": 95, + "temp1_high_crit_threshold": 110 + } + }, + "ASIC_TEMP19": { + "dev_info": { + "device_type": "ASIC_TEMP_SENSOR", + "device_name": "ASIC_TEMP19", + "device_parent": "None", + "nexthop_thermal_pid_domain": "None" + }, + "dev_attr": { + "display_name": "ASIC NIF6", + "temp1_high_threshold": 95, + "temp1_high_crit_threshold": 110 + } + }, + "ASIC_TEMP20": { + "dev_info": { + "device_type": "ASIC_TEMP_SENSOR", + "device_name": "ASIC_TEMP20", + "device_parent": "None", + "nexthop_thermal_pid_domain": "None" + }, + "dev_attr": { + "display_name": "ASIC NIF7", + "temp1_high_threshold": 95, + "temp1_high_crit_threshold": 110 + } + }, + "ASIC_TEMP21": { + "dev_info": { + "device_type": "ASIC_TEMP_SENSOR", + "device_name": "ASIC_TEMP21", + "device_parent": "None", + "nexthop_thermal_pid_domain": "None" + }, + "dev_attr": { + "display_name": "ASIC NIF8", + "temp1_high_threshold": 95, + "temp1_high_crit_threshold": 110 + } + }, + "ASIC_TEMP22": { + "dev_info": { + "device_type": "ASIC_TEMP_SENSOR", + "device_name": "ASIC_TEMP22", + "device_parent": "None", + "nexthop_thermal_pid_domain": "None" + }, + "dev_attr": { + "display_name": "ASIC NIF9", + "temp1_high_threshold": 95, + "temp1_high_crit_threshold": 110 + } + }, + "ASIC_TEMP23": { + "dev_info": { + "device_type": "ASIC_TEMP_SENSOR", + "device_name": "ASIC_TEMP23", + "device_parent": "None", + "nexthop_thermal_pid_domain": "None" + }, + "dev_attr": { + "display_name": "ASIC NIF10", + "temp1_high_threshold": 95, + "temp1_high_crit_threshold": 110 + } + }, + "ASIC_TEMP24": { + "dev_info": { + "device_type": "ASIC_TEMP_SENSOR", + "device_name": "ASIC_TEMP24", + "device_parent": "None", + "nexthop_thermal_pid_domain": "None" + }, + "dev_attr": { + "display_name": "ASIC NIF11", + "temp1_high_threshold": 95, + "temp1_high_crit_threshold": 110 + } + }, + "ASIC_TEMP25": { + "dev_info": { + "device_type": "ASIC_TEMP_SENSOR", + "device_name": "ASIC_TEMP25", + "device_parent": "None", + "nexthop_thermal_pid_domain": "None" + }, + "dev_attr": { + "display_name": "ASIC NIF12", + "temp1_high_threshold": 95, + "temp1_high_crit_threshold": 110 + } + }, + "ASIC_TEMP26": { + "dev_info": { + "device_type": "ASIC_TEMP_SENSOR", + "device_name": "ASIC_TEMP26", + "device_parent": "None", + "nexthop_thermal_pid_domain": "None" + }, + "dev_attr": { + "display_name": "ASIC NIF13", + "temp1_high_threshold": 95, + "temp1_high_crit_threshold": 110 + } + }, + "ASIC_TEMP27": { + "dev_info": { + "device_type": "ASIC_TEMP_SENSOR", + "device_name": "ASIC_TEMP27", + "device_parent": "None", + "nexthop_thermal_pid_domain": "None" + }, + "dev_attr": { + "display_name": "ASIC NIF14", + "temp1_high_threshold": 95, + "temp1_high_crit_threshold": 110 + } + }, + "ASIC_TEMP28": { + "dev_info": { + "device_type": "ASIC_TEMP_SENSOR", + "device_name": "ASIC_TEMP28", + "device_parent": "None", + "nexthop_thermal_pid_domain": "None" + }, + "dev_attr": { + "display_name": "ASIC NIF15", + "temp1_high_threshold": 95, + "temp1_high_crit_threshold": 110 + } + }, + "ASIC_TEMP29": { + "dev_info": { + "device_type": "ASIC_TEMP_SENSOR", + "device_name": "ASIC_TEMP29", + "device_parent": "None", + "nexthop_thermal_pid_domain": "None" + }, + "dev_attr": { + "display_name": "ASIC NIF16", + "temp1_high_threshold": 95, + "temp1_high_crit_threshold": 110 + } + }, + "ASIC_TEMP30": { + "dev_info": { + "device_type": "ASIC_TEMP_SENSOR", + "device_name": "ASIC_TEMP30", + "device_parent": "None", + "nexthop_thermal_pid_domain": "None" + }, + "dev_attr": { + "display_name": "ASIC NIF17", + "temp1_high_threshold": 95, + "temp1_high_crit_threshold": 110 + } + }, + "ASIC_TEMP31": { + "dev_info": { + "device_type": "ASIC_TEMP_SENSOR", + "device_name": "ASIC_TEMP31", + "device_parent": "None", + "nexthop_thermal_pid_domain": "None" + }, + "dev_attr": { + "display_name": "ASIC NIF18", + "temp1_high_threshold": 95, + "temp1_high_crit_threshold": 110 + } + }, + "ASIC_TEMP32": { + "dev_info": { + "device_type": "ASIC_TEMP_SENSOR", + "device_name": "ASIC_TEMP32", + "device_parent": "None", + "nexthop_thermal_pid_domain": "None" + }, + "dev_attr": { + "display_name": "ASIC NIF19", + "temp1_high_threshold": 95, + "temp1_high_crit_threshold": 110 + } + }, + "ASIC_TEMP33": { + "dev_info": { + "device_type": "ASIC_TEMP_SENSOR", + "device_name": "ASIC_TEMP33", + "device_parent": "None", + "nexthop_thermal_pid_domain": "None" + }, + "dev_attr": { + "display_name": "ASIC NIF20", + "temp1_high_threshold": 95, + "temp1_high_crit_threshold": 110 + } + }, + "ASIC_TEMP34": { + "dev_info": { + "device_type": "ASIC_TEMP_SENSOR", + "device_name": "ASIC_TEMP34", + "device_parent": "None", + "nexthop_thermal_pid_domain": "None" + }, + "dev_attr": { + "display_name": "ASIC NIF21", + "temp1_high_threshold": 95, + "temp1_high_crit_threshold": 110 + } + }, + "ASIC_TEMP35": { + "dev_info": { + "device_type": "ASIC_TEMP_SENSOR", + "device_name": "ASIC_TEMP35", + "device_parent": "None", + "nexthop_thermal_pid_domain": "None" + }, + "dev_attr": { + "display_name": "ASIC NIF22", + "temp1_high_threshold": 95, + "temp1_high_crit_threshold": 110 + } + }, + "ASIC_TEMP36": { + "dev_info": { + "device_type": "ASIC_TEMP_SENSOR", + "device_name": "ASIC_TEMP36", + "device_parent": "None", + "nexthop_thermal_pid_domain": "None" + }, + "dev_attr": { + "display_name": "ASIC NIF23", + "temp1_high_threshold": 95, + "temp1_high_crit_threshold": 110 + } + }, + "ASIC_TEMP37": { + "dev_info": { + "device_type": "ASIC_TEMP_SENSOR", + "device_name": "ASIC_TEMP37", + "device_parent": "None", + "nexthop_thermal_pid_domain": "None" + }, + "dev_attr": { + "display_name": "ASIC NIF24", + "temp1_high_threshold": 95, + "temp1_high_crit_threshold": 110 + } + }, + "ASIC_TEMP38": { + "dev_info": { + "device_type": "ASIC_TEMP_SENSOR", + "device_name": "ASIC_TEMP38", + "device_parent": "None", + "nexthop_thermal_pid_domain": "None" + }, + "dev_attr": { + "display_name": "ASIC NIF25", + "temp1_high_threshold": 95, + "temp1_high_crit_threshold": 110 + } + }, + "ASIC_TEMP39": { + "dev_info": { + "device_type": "ASIC_TEMP_SENSOR", + "device_name": "ASIC_TEMP39", + "device_parent": "None", + "nexthop_thermal_pid_domain": "None" + }, + "dev_attr": { + "display_name": "ASIC NIF26", + "temp1_high_threshold": 95, + "temp1_high_crit_threshold": 110 + } + }, + "ASIC_TEMP40": { + "dev_info": { + "device_type": "ASIC_TEMP_SENSOR", + "device_name": "ASIC_TEMP40", + "device_parent": "None", + "nexthop_thermal_pid_domain": "None" + }, + "dev_attr": { + "display_name": "ASIC NIF27", + "temp1_high_threshold": 95, + "temp1_high_crit_threshold": 110 + } + }, + "ASIC_TEMP41": { + "dev_info": { + "device_type": "ASIC_TEMP_SENSOR", + "device_name": "ASIC_TEMP41", + "device_parent": "None", + "nexthop_thermal_pid_domain": "None" + }, + "dev_attr": { + "display_name": "ASIC NIF28", + "temp1_high_threshold": 95, + "temp1_high_crit_threshold": 110 + } + }, + "ASIC_TEMP42": { + "dev_info": { + "device_type": "ASIC_TEMP_SENSOR", + "device_name": "ASIC_TEMP42", + "device_parent": "None", + "nexthop_thermal_pid_domain": "None" + }, + "dev_attr": { + "display_name": "ASIC NIF29", + "temp1_high_threshold": 95, + "temp1_high_crit_threshold": 110 + } + }, + "ASIC_TEMP43": { + "dev_info": { + "device_type": "ASIC_TEMP_SENSOR", + "device_name": "ASIC_TEMP43", + "device_parent": "None", + "nexthop_thermal_pid_domain": "None" + }, + "dev_attr": { + "display_name": "ASIC NIF30", + "temp1_high_threshold": 95, + "temp1_high_crit_threshold": 110 + } + }, + "ASIC_TEMP44": { + "dev_info": { + "device_type": "ASIC_TEMP_SENSOR", + "device_name": "ASIC_TEMP44", + "device_parent": "None", + "nexthop_thermal_pid_domain": "None" + }, + "dev_attr": { + "display_name": "ASIC NIF31", + "temp1_high_threshold": 95, + "temp1_high_crit_threshold": 110 + } + }, + "ASIC_TEMP45": { + "dev_info": { + "device_type": "ASIC_TEMP_SENSOR", + "device_name": "ASIC_TEMP45", + "device_parent": "None", + "nexthop_thermal_pid_domain": "None" + }, + "dev_attr": { + "display_name": "ASIC PHY_BRIDGE0", + "temp1_high_threshold": 95, + "temp1_high_crit_threshold": 110 + } + }, + "ASIC_TEMP46": { + "dev_info": { + "device_type": "ASIC_TEMP_SENSOR", + "device_name": "ASIC_TEMP46", + "device_parent": "None", + "nexthop_thermal_pid_domain": "None" + }, + "dev_attr": { + "display_name": "ASIC PHY_BRIDGE1", + "temp1_high_threshold": 95, + "temp1_high_crit_threshold": 110 + } + }, + "ASIC_TEMP47": { + "dev_info": { + "device_type": "ASIC_TEMP_SENSOR", + "device_name": "ASIC_TEMP47", + "device_parent": "None", + "nexthop_thermal_pid_domain": "None" + }, + "dev_attr": { + "display_name": "ASIC PHY_BRIDGE2", + "temp1_high_threshold": 95, + "temp1_high_crit_threshold": 110 + } + }, + "ASIC_TEMP48": { + "dev_info": { + "device_type": "ASIC_TEMP_SENSOR", + "device_name": "ASIC_TEMP48", + "device_parent": "None", + "nexthop_thermal_pid_domain": "None" + }, + "dev_attr": { + "display_name": "ASIC PHY_BRIDGE3", + "temp1_high_threshold": 95, + "temp1_high_crit_threshold": 110 + } + }, + "ASIC_TEMP49": { + "dev_info": { + "device_type": "ASIC_TEMP_SENSOR", + "device_name": "ASIC_TEMP49", + "device_parent": "None", + "nexthop_thermal_pid_domain": "None" + }, + "dev_attr": { + "display_name": "ASIC PHY_BRIDGE4", + "temp1_high_threshold": 95, + "temp1_high_crit_threshold": 110 + } + }, + "ASIC_TEMP50": { + "dev_info": { + "device_type": "ASIC_TEMP_SENSOR", + "device_name": "ASIC_TEMP50", + "device_parent": "None", + "nexthop_thermal_pid_domain": "None" + }, + "dev_attr": { + "display_name": "ASIC PHY_BRIDGE5", + "temp1_high_threshold": 95, + "temp1_high_crit_threshold": 110 + } + }, + "ASIC_TEMP51": { + "dev_info": { + "device_type": "ASIC_TEMP_SENSOR", + "device_name": "ASIC_TEMP51", + "device_parent": "None", + "nexthop_thermal_pid_domain": "None" + }, + "dev_attr": { + "display_name": "ASIC PHY_BRIDGE6", + "temp1_high_threshold": 95, + "temp1_high_crit_threshold": 110 + } + }, + "ASIC_TEMP52": { + "dev_info": { + "device_type": "ASIC_TEMP_SENSOR", + "device_name": "ASIC_TEMP52", + "device_parent": "None", + "nexthop_thermal_pid_domain": "None" + }, + "dev_attr": { + "display_name": "ASIC PHY_BRIDGE7", + "temp1_high_threshold": 95, + "temp1_high_crit_threshold": 110 + } + }, + "MULTIFPGAPCIE1": { + "dev_info": { + "device_type": "MULTIFPGAPCIE", + "device_name": "SWITCHCARD_FPGA", + "device_parent": "PCIE0", + "device_bdf": "{{switchcard_fpga_bdf}}", + "dev_attr": {} + }, + "dev_attr": { + "pwr_cycle_reg_offset": "0x4", + "pwr_cycle_enable_word": "0xdeadbeef" + }, + "i2c": { + "dev_attr": { + "virt_bus": "0xc", + "ch_base_offset": "0x40000", + "ch_size": "0x200", + "num_virt_ch": "0x49" + }, + "channel": [ + { + "chn": "0", + "dev": "FAN-CTRL" + }, + { + "chn": "0", + "dev": "SWITCHCARD_CPLDMUX0" + }, + { + "chn": "1", + "dev": "SWITCHCARD_CPLDMUX1" + }, + { + "chn": "4", + "dev": "PORT65" + }, + { + "chn": "5", + "dev": "PORT66" + }, + { + "chn": "6", + "dev": "PORT33" + }, + { + "chn": "7", + "dev": "PORT34" + }, + { + "chn": "8", + "dev": "PORT35" + }, + { + "chn": "9", + "dev": "PORT36" + }, + { + "chn": "10", + "dev": "PORT37" + }, + { + "chn": "11", + "dev": "PORT38" + }, + { + "chn": "12", + "dev": "PORT39" + }, + { + "chn": "13", + "dev": "PORT40" + }, + { + "chn": "14", + "dev": "PORT41" + }, + { + "chn": "15", + "dev": "PORT42" + }, + { + "chn": "16", + "dev": "PORT43" + }, + { + "chn": "17", + "dev": "PORT44" + }, + { + "chn": "18", + "dev": "PORT45" + }, + { + "chn": "19", + "dev": "PORT46" + }, + { + "chn": "20", + "dev": "PORT47" + }, + { + "chn": "21", + "dev": "PORT48" + }, + { + "chn": "22", + "dev": "PORT49" + }, + { + "chn": "23", + "dev": "PORT50" + }, + { + "chn": "24", + "dev": "PORT51" + }, + { + "chn": "25", + "dev": "PORT52" + }, + { + "chn": "26", + "dev": "PORT53" + }, + { + "chn": "27", + "dev": "PORT54" + }, + { + "chn": "28", + "dev": "PORT55" + }, + { + "chn": "29", + "dev": "PORT56" + }, + { + "chn": "30", + "dev": "PORT57" + }, + { + "chn": "31", + "dev": "PORT58" + }, + { + "chn": "32", + "dev": "PORT59" + }, + { + "chn": "33", + "dev": "PORT60" + }, + { + "chn": "34", + "dev": "PORT61" + }, + { + "chn": "35", + "dev": "PORT62" + }, + { + "chn": "36", + "dev": "PORT63" + }, + { + "chn": "37", + "dev": "PORT64" + }, + { + "chn": "38", + "dev": "MEZZCARD_CPLDMUX0" + }, + { + "chn": "41", + "dev": "PORT1" + }, + { + "chn": "42", + "dev": "PORT2" + }, + { + "chn": "43", + "dev": "PORT3" + }, + { + "chn": "44", + "dev": "PORT4" + }, + { + "chn": "45", + "dev": "PORT5" + }, + { + "chn": "46", + "dev": "PORT6" + }, + { + "chn": "47", + "dev": "PORT7" + }, + { + "chn": "48", + "dev": "PORT8" + }, + { + "chn": "49", + "dev": "PORT9" + }, + { + "chn": "50", + "dev": "PORT10" + }, + { + "chn": "51", + "dev": "PORT11" + }, + { + "chn": "52", + "dev": "PORT12" + }, + { + "chn": "53", + "dev": "PORT13" + }, + { + "chn": "54", + "dev": "PORT14" + }, + { + "chn": "55", + "dev": "PORT15" + }, + { + "chn": "56", + "dev": "PORT16" + }, + { + "chn": "57", + "dev": "PORT17" + }, + { + "chn": "58", + "dev": "PORT18" + }, + { + "chn": "59", + "dev": "PORT19" + }, + { + "chn": "60", + "dev": "PORT20" + }, + { + "chn": "61", + "dev": "PORT21" + }, + { + "chn": "62", + "dev": "PORT22" + }, + { + "chn": "63", + "dev": "PORT23" + }, + { + "chn": "64", + "dev": "PORT24" + }, + { + "chn": "65", + "dev": "PORT25" + }, + { + "chn": "66", + "dev": "PORT26" + }, + { + "chn": "67", + "dev": "PORT27" + }, + { + "chn": "68", + "dev": "PORT28" + }, + { + "chn": "69", + "dev": "PORT29" + }, + { + "chn": "70", + "dev": "PORT30" + }, + { + "chn": "71", + "dev": "PORT31" + }, + { + "chn": "72", + "dev": "PORT32" + } + ] + }, + "gpio": { + "line0": { + "attr_list": [ + { + "offset": "0x24", + "bit": "0x0", + "direction": "0x1" + } + ] + }, + "line1": { + "attr_list": [ + { + "offset": "0x24", + "bit": "0x1", + "direction": "0x1" + } + ] + }, + "line2": { + "attr_list": [ + { + "offset": "0x24", + "bit": "0x2", + "direction": "0x0" + } + ] + }, + "line3": { + "attr_list": [ + { + "offset": "0x24", + "bit": "0x10", + "direction": "0x1" + } + ] + } + }, + "mdio": { + "dev_attr": { + "ch_base_offset": "0x4200", + "ch_size": "0x10", + "num_virt_ch": "0x10" + } + } + }, + "FAN-CTRL": { + "dev_info": { + "device_type": "FAN", + "device_name": "FAN-CTRL", + "device_parent": "MULTIFPGAPCIE1" + }, + "i2c": { + "topo_info": { + "parent_bus": "0xc", + "dev_addr": "0x8", + "dev_type": "fan_multifpgapci" + }, + "dev_attr": { + "num_fantrays": "4" + }, + "attr_list": [ + { + "attr_name": "fan1_present", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0xa4", + "attr_mask": "0x000000f0", + "attr_cmpval": "0x00000070", + "attr_len": "1" + }, + { + "attr_name": "fan2_present", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0xa4", + "attr_mask": "0x000000f0", + "attr_cmpval": "0x00000070", + "attr_len": "1" + }, + { + "attr_name": "fan3_present", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0xa4", + "attr_mask": "0x00007800", + "attr_cmpval": "0x00003800", + "attr_len": "1" + }, + { + "attr_name": "fan4_present", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0xa4", + "attr_mask": "0x00007800", + "attr_cmpval": "0x00003800", + "attr_len": "1" + }, + { + "attr_name": "fan5_present", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0xa4", + "attr_mask": "0x003c0000", + "attr_cmpval": "0x001c0000", + "attr_len": "1" + }, + { + "attr_name": "fan6_present", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0xa4", + "attr_mask": "0x003c0000", + "attr_cmpval": "0x001c0000", + "attr_len": "1" + }, + { + "attr_name": "fan7_present", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0xa4", + "attr_mask": "0x1e000000", + "attr_cmpval": "0x0e000000", + "attr_len": "1" + }, + { + "attr_name": "fan8_present", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0xa4", + "attr_mask": "0x1e000000", + "attr_cmpval": "0x0e000000", + "attr_len": "1" + }, + { + "attr_name": "fan1_direction", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0xa4", + "attr_mask": "0x000000f0", + "attr_cmpval": "0x00000070", + "attr_len": "1" + }, + { + "attr_name": "fan2_direction", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0xa4", + "attr_mask": "0x000000f0", + "attr_cmpval": "0x00000070", + "attr_len": "1" + }, + { + "attr_name": "fan3_direction", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0xa4", + "attr_mask": "0x00007800", + "attr_cmpval": "0x00003800", + "attr_len": "1" + }, + { + "attr_name": "fan4_direction", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0xa4", + "attr_mask": "0x00007800", + "attr_cmpval": "0x00003800", + "attr_len": "1" + }, + { + "attr_name": "fan5_direction", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0xa4", + "attr_mask": "0x003c0000", + "attr_cmpval": "0x001c0000", + "attr_len": "1" + }, + { + "attr_name": "fan6_direction", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0xa4", + "attr_mask": "0x003c0000", + "attr_cmpval": "0x001c0000", + "attr_len": "1" + }, + { + "attr_name": "fan7_direction", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0xa4", + "attr_mask": "0x1e000000", + "attr_cmpval": "0x0e000000", + "attr_len": "1" + }, + { + "attr_name": "fan8_direction", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0xa4", + "attr_mask": "0x1e000000", + "attr_cmpval": "0x0e000000", + "attr_len": "1" + }, + { + "attr_name": "fan1_fault", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0xa4", + "attr_mask": "0x00000100", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "fan2_fault", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0xa4", + "attr_mask": "0x00000100", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "fan3_fault", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0xa4", + "attr_mask": "0x00008000", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "fan4_fault", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0xa4", + "attr_mask": "0x00008000", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "fan5_fault", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0xa4", + "attr_mask": "0x00400000", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "fan6_fault", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0xa4", + "attr_mask": "0x00400000", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "fan7_fault", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0xa4", + "attr_mask": "0x20000000", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "fan8_fault", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0xa4", + "attr_mask": "0x20000000", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "fan1_input", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0xb0", + "attr_mask": "0xffff0000", + "attr_len": "1", + "attr_mult": "1913265", + "attr_is_divisor": "1" + }, + { + "attr_name": "fan2_input", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0xb4", + "attr_mask": "0xffff0000", + "attr_len": "1", + "attr_mult": "1913265", + "attr_is_divisor": "1" + }, + { + "attr_name": "fan3_input", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0xb8", + "attr_mask": "0xffff0000", + "attr_len": "1", + "attr_mult": "1913265", + "attr_is_divisor": "1" + }, + { + "attr_name": "fan4_input", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0xbc", + "attr_mask": "0xffff0000", + "attr_len": "1", + "attr_mult": "1913265", + "attr_is_divisor": "1" + }, + { + "attr_name": "fan5_input", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0xc0", + "attr_mask": "0xffff0000", + "attr_len": "1", + "attr_mult": "1913265", + "attr_is_divisor": "1" + }, + { + "attr_name": "fan6_input", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0xc4", + "attr_mask": "0xffff0000", + "attr_len": "1", + "attr_mult": "1913265", + "attr_is_divisor": "1" + }, + { + "attr_name": "fan7_input", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0xc8", + "attr_mask": "0xffff0000", + "attr_len": "1", + "attr_mult": "1913265", + "attr_is_divisor": "1" + }, + { + "attr_name": "fan8_input", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0xcc", + "attr_mask": "0xffff0000", + "attr_len": "1", + "attr_mult": "1913265", + "attr_is_divisor": "1" + }, + { + "attr_name": "fan1_pwm", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0xb0", + "attr_mask": "0xff", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "fan2_pwm", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0xb0", + "attr_mask": "0xff", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "fan3_pwm", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0xb8", + "attr_mask": "0xff", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "fan4_pwm", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0xb8", + "attr_mask": "0xff", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "fan5_pwm", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0xc0", + "attr_mask": "0xff", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "fan6_pwm", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0xc0", + "attr_mask": "0xff", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "fan7_pwm", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0xc8", + "attr_mask": "0xff", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "fan8_pwm", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0xc8", + "attr_mask": "0xff", + "attr_cmpval": "0x0", + "attr_len": "1" + } + ] + } + }, + "SWITCHCARD_CPLDMUX0": { + "dev_info": { + "device_type": "CPLDMUX", + "device_name": "SWITCHCARD_CPLDMUX0", + "device_parent": "MULTIFPGAPCIE1" + }, + "i2c": { + "topo_info": { + "parent_bus": "0xc", + "dev_type": "multifpgapci_mux", + "dev_id": "0" + }, + "dev_attr": { + "base_chan": "0x55", + "num_chan": "4", + "cpld_name": "SWITCHCARD_FPGA" + }, + "channel": [ + { + "chan": "0", + "dev": [ + "PSU1" + ], + "cpld_offset": "0x10", + "cpld_sel": "0x0" + }, + { + "chan": "1", + "dev": [ + "PSU2" + ], + "cpld_offset": "0x10", + "cpld_sel": "0x1" + }, + { + "chan": "2", + "dev": [], + "cpld_offset": "0x10", + "cpld_sel": "0x2" + }, + { + "chan": "3", + "dev": [], + "cpld_offset": "0x10", + "cpld_sel": "0x3" + } + ] + } + }, + "PSU1": { + "dev_info": { + "device_type": "PSU", + "device_name": "PSU 1", + "device_parent": "SWITCHCARD_CPLDMUX0" + }, + "dev_attr": { + "dev_idx": "1", + "num_psu_fans": "1", + "num_psu_thermals": "3" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PSU1-EEPROM" + }, + { + "itf": "pmbus", + "dev": "PSU1-PMBUS" + } + ] + } + }, + "PSU1-EEPROM": { + "dev_info": { + "device_type": "EEPROM", + "device_name": "PSU1-EEPROM", + "device_parent": "SWITCHCARD_CPLDMUX0", + "virt_parent": "PSU1" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x55", + "dev_addr": "0x50", + "dev_type": "24c64" + }, + "dev_attr": { + "access_mode": "BLOCK" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PSU1-PMBUS": { + "dev_info": { + "device_type": "PSU-PMBUS", + "device_name": "PSU1-PMBUS", + "device_parent": "SWITCHCARD_CPLDMUX0", + "virt_parent": "PSU1" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x55", + "dev_addr": "0x58", + "dev_type": "psu_pmbus" + }, + "attr_list": [ + { + "attr_name": "psu_present", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x98", + "attr_mask": "0x40000", + "attr_cmpval": "0x40000", + "attr_len": "1" + }, + { + "attr_name": "psu_power_good", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x98", + "attr_mask": "0x20000", + "attr_cmpval": "0x20000", + "attr_len": "1" + }, + { + "attr_name": "psu_model_name", + "attr_devaddr": "0x58", + "attr_devtype": "pmbus", + "attr_offset": "0x9a", + "attr_mask": "0x0", + "attr_cmpval": "0xff", + "attr_len": "23" + }, + { + "attr_name": "psu_serial_num", + "attr_devaddr": "0x58", + "attr_devtype": "pmbus", + "attr_offset": "0x9e", + "attr_mask": "0x0", + "attr_cmpval": "0x00", + "attr_len": "14" + }, + { + "attr_name": "psu_mfr_id", + "attr_devaddr": "0x58", + "attr_devtype": "pmbus", + "attr_offset": "0x99", + "attr_mask": "0x0", + "attr_cmpval": "0x00", + "attr_len": "11" + }, + { + "attr_name": "psu_fan_dir", + "attr_devaddr": "0x58", + "attr_devtype": "pmbus", + "attr_offset": "0x9a", + "attr_mask": "0x0", + "attr_cmpval": "0xff", + "attr_len": "23" + }, + { + "attr_name": "psu_p_out", + "attr_devaddr": "0x58", + "attr_devtype": "pmbus", + "attr_offset": "0x96", + "attr_mask": "0x0", + "attr_cmpval": "0xff", + "attr_len": "2" + }, + { + "attr_name": "psu_v_out", + "attr_devaddr": "0x58", + "attr_devtype": "pmbus", + "attr_offset": "0x8b", + "attr_mask": "0x0", + "attr_cmpval": "0xff", + "attr_data_format": "linear16", + "attr_len": "2" + }, + { + "attr_name": "psu_i_out", + "attr_devaddr": "0x58", + "attr_devtype": "pmbus", + "attr_offset": "0x8c", + "attr_mask": "0x0", + "attr_cmpval": "0xff", + "attr_len": "2" + }, + { + "attr_name": "psu_p_in", + "attr_devaddr": "0x58", + "attr_devtype": "pmbus", + "attr_offset": "0x97", + "attr_mask": "0x0", + "attr_cmpval": "0xff", + "attr_len": "2" + }, + { + "attr_name": "psu_v_in", + "attr_devaddr": "0x58", + "attr_devtype": "pmbus", + "attr_offset": "0x88", + "attr_mask": "0x0", + "attr_cmpval": "0xff", + "attr_len": "2" + }, + { + "attr_name": "psu_i_in", + "attr_devaddr": "0x58", + "attr_devtype": "pmbus", + "attr_offset": "0x89", + "attr_mask": "0x0", + "attr_cmpval": "0xff", + "attr_len": "2" + }, + { + "attr_name": "psu_fan1_speed_rpm", + "attr_devaddr": "0x58", + "attr_devtype": "pmbus", + "attr_offset": "0x90", + "attr_mask": "0x0", + "attr_cmpval": "0xff", + "attr_len": "2" + }, + { + "attr_name": "psu_temp1_input", + "attr_devaddr": "0x58", + "attr_devtype": "pmbus", + "attr_offset": "0x8f", + "attr_mask": "0x0", + "attr_cmpval": "0xff", + "attr_len": "2" + }, + { + "attr_name": "psu_temp1_high_threshold", + "attr_devaddr": "0x58", + "attr_devtype": "pmbus", + "attr_offset": "0xc2", + "attr_mask": "0x0", + "attr_cmpval": "0xff", + "attr_len": "2" + }, + { + "attr_name": "psu_temp2_input", + "attr_devaddr": "0x58", + "attr_devtype": "pmbus", + "attr_offset": "0x8e", + "attr_mask": "0x0", + "attr_cmpval": "0xff", + "attr_len": "2" + }, + { + "attr_name": "psu_temp2_high_threshold", + "attr_devaddr": "0x58", + "attr_devtype": "pmbus", + "attr_offset": "0xc1", + "attr_mask": "0x0", + "attr_cmpval": "0xff", + "attr_len": "2" + }, + { + "attr_name": "psu_temp3_input", + "attr_devaddr": "0x58", + "attr_devtype": "pmbus", + "attr_offset": "0x8d", + "attr_mask": "0x0", + "attr_cmpval": "0xff", + "attr_len": "2" + }, + { + "attr_name": "psu_temp3_high_threshold", + "attr_devaddr": "0x58", + "attr_devtype": "pmbus", + "attr_offset": "0xc0", + "attr_mask": "0x0", + "attr_cmpval": "0xff", + "attr_len": "2" + }, + { + "attr_name": "psu_v_out_max", + "attr_devaddr": "0x58", + "attr_devtype": "pmbus", + "attr_offset": "0xa5", + "attr_mask": "0x0", + "attr_cmpval": "0xff", + "attr_data_format": "linear16", + "attr_len": "2" + }, + { + "attr_name": "psu_v_out_min", + "attr_devaddr": "0x58", + "attr_devtype": "pmbus", + "attr_offset": "0xa4", + "attr_mask": "0x0", + "attr_cmpval": "0xff", + "attr_data_format": "linear16", + "attr_len": "2" + }, + { + "attr_name": "psu_p_out_max", + "attr_devaddr": "0x58", + "attr_devtype": "pmbus", + "attr_offset": "0xa7", + "attr_mask": "0x0", + "attr_cmpval": "0xff", + "attr_len": "2" + } + ] + } + }, + "PSU2": { + "dev_info": { + "device_type": "PSU", + "device_name": "PSU 2", + "device_parent": "SWITCHCARD_CPLDMUX0" + }, + "dev_attr": { + "dev_idx": "2", + "num_psu_fans": "1", + "num_psu_thermals": "3" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PSU2-EEPROM" + }, + { + "itf": "pmbus", + "dev": "PSU2-PMBUS" + } + ] + } + }, + "PSU2-EEPROM": { + "dev_info": { + "device_type": "EEPROM", + "device_name": "PSU2-EEPROM", + "device_parent": "SWITCHCARD_CPLDMUX0", + "virt_parent": "PSU2" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x56", + "dev_addr": "0x50", + "dev_type": "24c64" + }, + "dev_attr": { + "access_mode": "BLOCK" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PSU2-PMBUS": { + "dev_info": { + "device_type": "PSU-PMBUS", + "device_name": "PSU2-PMBUS", + "device_parent": "SWITCHCARD_CPLDMUX0", + "virt_parent": "PSU2" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x56", + "dev_addr": "0x58", + "dev_type": "psu_pmbus" + }, + "attr_list": [ + { + "attr_name": "psu_present", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x98", + "attr_mask": "0x400000", + "attr_cmpval": "0x400000", + "attr_len": "1" + }, + { + "attr_name": "psu_power_good", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x98", + "attr_mask": "0x200000", + "attr_cmpval": "0x200000", + "attr_len": "1" + }, + { + "attr_name": "psu_model_name", + "attr_devaddr": "0x58", + "attr_devtype": "pmbus", + "attr_offset": "0x9a", + "attr_mask": "0x0", + "attr_cmpval": "0xff", + "attr_len": "23" + }, + { + "attr_name": "psu_serial_num", + "attr_devaddr": "0x58", + "attr_devtype": "pmbus", + "attr_offset": "0x9e", + "attr_mask": "0x0", + "attr_cmpval": "0x00", + "attr_len": "14" + }, + { + "attr_name": "psu_mfr_id", + "attr_devaddr": "0x58", + "attr_devtype": "pmbus", + "attr_offset": "0x99", + "attr_mask": "0x0", + "attr_cmpval": "0x00", + "attr_len": "11" + }, + { + "attr_name": "psu_fan_dir", + "attr_devaddr": "0x58", + "attr_devtype": "pmbus", + "attr_offset": "0x9a", + "attr_mask": "0x0", + "attr_cmpval": "0xff", + "attr_len": "23" + }, + { + "attr_name": "psu_p_out", + "attr_devaddr": "0x58", + "attr_devtype": "pmbus", + "attr_offset": "0x96", + "attr_mask": "0x0", + "attr_cmpval": "0xff", + "attr_len": "2" + }, + { + "attr_name": "psu_v_out", + "attr_devaddr": "0x58", + "attr_devtype": "pmbus", + "attr_offset": "0x8b", + "attr_mask": "0x0", + "attr_cmpval": "0xff", + "attr_data_format": "linear16", + "attr_len": "2" + }, + { + "attr_name": "psu_i_out", + "attr_devaddr": "0x58", + "attr_devtype": "pmbus", + "attr_offset": "0x8c", + "attr_mask": "0x0", + "attr_cmpval": "0xff", + "attr_len": "2" + }, + { + "attr_name": "psu_p_in", + "attr_devaddr": "0x58", + "attr_devtype": "pmbus", + "attr_offset": "0x97", + "attr_mask": "0x0", + "attr_cmpval": "0xff", + "attr_len": "2" + }, + { + "attr_name": "psu_v_in", + "attr_devaddr": "0x58", + "attr_devtype": "pmbus", + "attr_offset": "0x88", + "attr_mask": "0x0", + "attr_cmpval": "0xff", + "attr_len": "2" + }, + { + "attr_name": "psu_i_in", + "attr_devaddr": "0x58", + "attr_devtype": "pmbus", + "attr_offset": "0x89", + "attr_mask": "0x0", + "attr_cmpval": "0xff", + "attr_len": "2" + }, + { + "attr_name": "psu_fan1_speed_rpm", + "attr_devaddr": "0x58", + "attr_devtype": "pmbus", + "attr_offset": "0x90", + "attr_mask": "0x0", + "attr_cmpval": "0xff", + "attr_len": "2" + }, + { + "attr_name": "psu_temp1_input", + "attr_devaddr": "0x58", + "attr_devtype": "pmbus", + "attr_offset": "0x8f", + "attr_mask": "0x0", + "attr_cmpval": "0xff", + "attr_len": "2" + }, + { + "attr_name": "psu_temp1_high_threshold", + "attr_devaddr": "0x58", + "attr_devtype": "pmbus", + "attr_offset": "0xc2", + "attr_mask": "0x0", + "attr_cmpval": "0xff", + "attr_len": "2" + }, + { + "attr_name": "psu_temp2_input", + "attr_devaddr": "0x58", + "attr_devtype": "pmbus", + "attr_offset": "0x8e", + "attr_mask": "0x0", + "attr_cmpval": "0xff", + "attr_len": "2" + }, + { + "attr_name": "psu_temp2_high_threshold", + "attr_devaddr": "0x58", + "attr_devtype": "pmbus", + "attr_offset": "0xc1", + "attr_mask": "0x0", + "attr_cmpval": "0xff", + "attr_len": "2" + }, + { + "attr_name": "psu_temp3_input", + "attr_devaddr": "0x58", + "attr_devtype": "pmbus", + "attr_offset": "0x8d", + "attr_mask": "0x0", + "attr_cmpval": "0xff", + "attr_len": "2" + }, + { + "attr_name": "psu_temp3_high_threshold", + "attr_devaddr": "0x58", + "attr_devtype": "pmbus", + "attr_offset": "0xc0", + "attr_mask": "0x0", + "attr_cmpval": "0xff", + "attr_len": "2" + }, + { + "attr_name": "psu_v_out_max", + "attr_devaddr": "0x58", + "attr_devtype": "pmbus", + "attr_offset": "0xa5", + "attr_mask": "0x0", + "attr_cmpval": "0xff", + "attr_data_format": "linear16", + "attr_len": "2" + }, + { + "attr_name": "psu_v_out_min", + "attr_devaddr": "0x58", + "attr_devtype": "pmbus", + "attr_offset": "0xa4", + "attr_mask": "0x0", + "attr_cmpval": "0xff", + "attr_data_format": "linear16", + "attr_len": "2" + }, + { + "attr_name": "psu_p_out_max", + "attr_devaddr": "0x58", + "attr_devtype": "pmbus", + "attr_offset": "0xa7", + "attr_mask": "0x0", + "attr_cmpval": "0xff", + "attr_len": "2" + } + ] + } + }, + "FAN_CARD_EEPROM": { + "dev_info": { + "device_type": "EEPROM", + "device_name": "FAN_CARD_EEPROM", + "device_parent": "MULTIFPGAPCIE1" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x58", + "dev_addr": "0x50", + "dev_type": "24c64" + }, + "dev_attr": { + "access_mode": "BLOCK" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "FAN_CARD_TMP464": { + "dev_info": { + "device_type": "TEMP_SENSOR", + "device_name": "FAN_CARD_TMP464", + "device_parent": "MULTIFPGAPCIE1" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x58", + "dev_addr": "0x48", + "dev_type": "nh_tmp464" + }, + "dev_attr": { + "access_mode": "BLOCK" + }, + "attr_list": [ + { + "attr_name": "temp1_input" + } + ] + } + }, + "SWITCHCARD_CPLDMUX1": { + "dev_info": { + "device_type": "CPLDMUX", + "device_name": "SWITCHCARD_CPLDMUX1", + "device_parent": "MULTIFPGAPCIE1" + }, + "i2c": { + "topo_info": { + "parent_bus": "0xd", + "dev_type": "multifpgapci_mux", + "dev_id": "1" + }, + "dev_attr": { + "base_chan": "0x59", + "num_chan": "4", + "cpld_name": "SWITCHCARD_FPGA" + }, + "channel": [ + { + "chan": "0", + "dev": [ + "DCDC0", + "DCDC1" + ], + "cpld_offset": "0x14", + "cpld_sel": "0x0" + }, + { + "chan": "1", + "dev": [ + "DCDC2", + "DCDC3", + "DCDC4", + "DCDC5", + "DCDC6" + ], + "cpld_offset": "0x14", + "cpld_sel": "0x1" + }, + { + "chan": "2", + "dev": [], + "cpld_offset": "0x14", + "cpld_sel": "0x2" + }, + { + "chan": "3", + "dev": [], + "cpld_offset": "0x14", + "cpld_sel": "0x3" + } + ] + } + }, + "MEZZCARD_CPLDMUX0": { + "dev_info": { + "device_type": "CPLDMUX", + "device_name": "MEZZCARD_CPLDMUX0", + "device_parent": "MULTIFPGAPCIE1" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x32", + "dev_type": "multifpgapci_mux", + "dev_id": "2" + }, + "dev_attr": { + "base_chan": "0x5d", + "num_chan": "4", + "cpld_name": "SWITCHCARD_FPGA" + }, + "channel": [ + { + "chan": "1", + "dev": [ + "DCDC7", + "DCDC8", + "DCDC9", + "DCDC10" + ], + "cpld_offset": "0x4010", + "cpld_sel": "0x0" + }, + { + "chan": "2", + "dev": [], + "cpld_offset": "0x4010", + "cpld_sel": "0x1" + }, + { + "chan": "3", + "dev": [], + "cpld_offset": "0x4010", + "cpld_sel": "0x2" + } + ] + } + }, + "PORT65": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT65", + "device_parent": "MULTIFPGAPCIE1" + }, + "dev_attr": { + "dev_idx": "65" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT65-EEPROM" + }, + { + "itf": "control", + "dev": "PORT65-CTRL" + } + ] + } + }, + "PORT65-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT65-EEPROM", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT65" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x10", + "dev_addr": "0x50", + "dev_type": "optoe1" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT65-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT65-CTRL", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT65" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x10", + "dev_addr": "0x8", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x88", + "attr_mask": "0x0", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x88", + "attr_mask": "0x1", + "attr_cmpval": "0x1", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x8c", + "attr_mask": "0x9", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x8c", + "attr_mask": "0x8", + "attr_cmpval": "0x1", + "attr_len": "1" + } + ] + } + }, + "PORT66": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT66", + "device_parent": "MULTIFPGAPCIE1" + }, + "dev_attr": { + "dev_idx": "66" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT66-EEPROM" + }, + { + "itf": "control", + "dev": "PORT66-CTRL" + } + ] + } + }, + "PORT66-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT66-EEPROM", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT66" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x11", + "dev_addr": "0x50", + "dev_type": "optoe1" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT66-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT66-CTRL", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT66" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x11", + "dev_addr": "0x8", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x88", + "attr_mask": "0x2", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x88", + "attr_mask": "0x3", + "attr_cmpval": "0x1", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x8c", + "attr_mask": "0xb", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x8c", + "attr_mask": "0xa", + "attr_cmpval": "0x1", + "attr_len": "1" + } + ] + } + }, + "PORT1": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT1", + "device_parent": "MULTIFPGAPCIE1" + }, + "dev_attr": { + "dev_idx": "1" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT1-EEPROM" + }, + { + "itf": "control", + "dev": "PORT1-CTRL" + } + ] + } + }, + "PORT1-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT1-EEPROM", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT1" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x35", + "dev_addr": "0x50", + "dev_type": "optoe3" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT1-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT1-CTRL", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT1" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x35", + "dev_addr": "0x8", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4034", + "attr_mask": "0x0", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4038", + "attr_mask": "0x0", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x403c", + "attr_mask": "0x0", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4040", + "attr_mask": "0x0", + "attr_cmpval": "0x1", + "attr_len": "1" + } + ] + } + }, + "PORT2": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT2", + "device_parent": "MULTIFPGAPCIE1" + }, + "dev_attr": { + "dev_idx": "2" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT2-EEPROM" + }, + { + "itf": "control", + "dev": "PORT2-CTRL" + } + ] + } + }, + "PORT2-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT2-EEPROM", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT2" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x36", + "dev_addr": "0x50", + "dev_type": "optoe3" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT2-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT2-CTRL", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT2" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x36", + "dev_addr": "0x8", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4034", + "attr_mask": "0x1", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4038", + "attr_mask": "0x1", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x403c", + "attr_mask": "0x1", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4040", + "attr_mask": "0x1", + "attr_cmpval": "0x1", + "attr_len": "1" + } + ] + } + }, + "PORT3": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT3", + "device_parent": "MULTIFPGAPCIE1" + }, + "dev_attr": { + "dev_idx": "3" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT3-EEPROM" + }, + { + "itf": "control", + "dev": "PORT3-CTRL" + } + ] + } + }, + "PORT3-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT3-EEPROM", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT3" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x37", + "dev_addr": "0x50", + "dev_type": "optoe3" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT3-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT3-CTRL", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT3" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x37", + "dev_addr": "0x8", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4034", + "attr_mask": "0x2", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4038", + "attr_mask": "0x2", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x403c", + "attr_mask": "0x2", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4040", + "attr_mask": "0x2", + "attr_cmpval": "0x1", + "attr_len": "1" + } + ] + } + }, + "PORT4": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT4", + "device_parent": "MULTIFPGAPCIE1" + }, + "dev_attr": { + "dev_idx": "4" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT4-EEPROM" + }, + { + "itf": "control", + "dev": "PORT4-CTRL" + } + ] + } + }, + "PORT4-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT4-EEPROM", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT4" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x38", + "dev_addr": "0x50", + "dev_type": "optoe3" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT4-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT4-CTRL", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT4" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x38", + "dev_addr": "0x8", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4034", + "attr_mask": "0x3", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4038", + "attr_mask": "0x3", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x403c", + "attr_mask": "0x3", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4040", + "attr_mask": "0x3", + "attr_cmpval": "0x1", + "attr_len": "1" + } + ] + } + }, + "PORT5": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT5", + "device_parent": "MULTIFPGAPCIE1" + }, + "dev_attr": { + "dev_idx": "5" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT5-EEPROM" + }, + { + "itf": "control", + "dev": "PORT5-CTRL" + } + ] + } + }, + "PORT5-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT5-EEPROM", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT5" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x39", + "dev_addr": "0x50", + "dev_type": "optoe3" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT5-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT5-CTRL", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT5" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x39", + "dev_addr": "0x8", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4034", + "attr_mask": "0x4", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4038", + "attr_mask": "0x4", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x403c", + "attr_mask": "0x4", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4040", + "attr_mask": "0x4", + "attr_cmpval": "0x1", + "attr_len": "1" + } + ] + } + }, + "PORT6": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT6", + "device_parent": "MULTIFPGAPCIE1" + }, + "dev_attr": { + "dev_idx": "6" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT6-EEPROM" + }, + { + "itf": "control", + "dev": "PORT6-CTRL" + } + ] + } + }, + "PORT6-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT6-EEPROM", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT6" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x3a", + "dev_addr": "0x50", + "dev_type": "optoe3" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT6-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT6-CTRL", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT6" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x3a", + "dev_addr": "0x8", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4034", + "attr_mask": "0x5", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4038", + "attr_mask": "0x5", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x403c", + "attr_mask": "0x5", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4040", + "attr_mask": "0x5", + "attr_cmpval": "0x1", + "attr_len": "1" + } + ] + } + }, + "PORT7": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT7", + "device_parent": "MULTIFPGAPCIE1" + }, + "dev_attr": { + "dev_idx": "7" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT7-EEPROM" + }, + { + "itf": "control", + "dev": "PORT7-CTRL" + } + ] + } + }, + "PORT7-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT7-EEPROM", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT7" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x3b", + "dev_addr": "0x50", + "dev_type": "optoe3" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT7-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT7-CTRL", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT7" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x3b", + "dev_addr": "0x8", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4034", + "attr_mask": "0x6", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4038", + "attr_mask": "0x6", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x403c", + "attr_mask": "0x6", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4040", + "attr_mask": "0x6", + "attr_cmpval": "0x1", + "attr_len": "1" + } + ] + } + }, + "PORT8": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT8", + "device_parent": "MULTIFPGAPCIE1" + }, + "dev_attr": { + "dev_idx": "8" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT8-EEPROM" + }, + { + "itf": "control", + "dev": "PORT8-CTRL" + } + ] + } + }, + "PORT8-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT8-EEPROM", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT8" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x3c", + "dev_addr": "0x50", + "dev_type": "optoe3" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT8-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT8-CTRL", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT8" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x3c", + "dev_addr": "0x8", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4034", + "attr_mask": "0x7", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4038", + "attr_mask": "0x7", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x403c", + "attr_mask": "0x7", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4040", + "attr_mask": "0x7", + "attr_cmpval": "0x1", + "attr_len": "1" + } + ] + } + }, + "PORT9": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT9", + "device_parent": "MULTIFPGAPCIE1" + }, + "dev_attr": { + "dev_idx": "9" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT9-EEPROM" + }, + { + "itf": "control", + "dev": "PORT9-CTRL" + } + ] + } + }, + "PORT9-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT9-EEPROM", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT9" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x3d", + "dev_addr": "0x50", + "dev_type": "optoe3" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT9-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT9-CTRL", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT9" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x3d", + "dev_addr": "0x8", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4034", + "attr_mask": "0x8", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4038", + "attr_mask": "0x8", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x403c", + "attr_mask": "0x8", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4040", + "attr_mask": "0x8", + "attr_cmpval": "0x1", + "attr_len": "1" + } + ] + } + }, + "PORT10": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT10", + "device_parent": "MULTIFPGAPCIE1" + }, + "dev_attr": { + "dev_idx": "10" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT10-EEPROM" + }, + { + "itf": "control", + "dev": "PORT10-CTRL" + } + ] + } + }, + "PORT10-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT10-EEPROM", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT10" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x3e", + "dev_addr": "0x50", + "dev_type": "optoe3" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT10-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT10-CTRL", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT10" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x3e", + "dev_addr": "0x8", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4034", + "attr_mask": "0x9", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4038", + "attr_mask": "0x9", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x403c", + "attr_mask": "0x9", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4040", + "attr_mask": "0x9", + "attr_cmpval": "0x1", + "attr_len": "1" + } + ] + } + }, + "PORT11": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT11", + "device_parent": "MULTIFPGAPCIE1" + }, + "dev_attr": { + "dev_idx": "11" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT11-EEPROM" + }, + { + "itf": "control", + "dev": "PORT11-CTRL" + } + ] + } + }, + "PORT11-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT11-EEPROM", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT11" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x3f", + "dev_addr": "0x50", + "dev_type": "optoe3" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT11-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT11-CTRL", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT11" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x3f", + "dev_addr": "0x8", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4034", + "attr_mask": "0xa", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4038", + "attr_mask": "0xa", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x403c", + "attr_mask": "0xa", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4040", + "attr_mask": "0xa", + "attr_cmpval": "0x1", + "attr_len": "1" + } + ] + } + }, + "PORT12": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT12", + "device_parent": "MULTIFPGAPCIE1" + }, + "dev_attr": { + "dev_idx": "12" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT12-EEPROM" + }, + { + "itf": "control", + "dev": "PORT12-CTRL" + } + ] + } + }, + "PORT12-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT12-EEPROM", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT12" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x40", + "dev_addr": "0x50", + "dev_type": "optoe3" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT12-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT12-CTRL", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT12" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x40", + "dev_addr": "0x8", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4034", + "attr_mask": "0xb", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4038", + "attr_mask": "0xb", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x403c", + "attr_mask": "0xb", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4040", + "attr_mask": "0xb", + "attr_cmpval": "0x1", + "attr_len": "1" + } + ] + } + }, + "PORT13": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT13", + "device_parent": "MULTIFPGAPCIE1" + }, + "dev_attr": { + "dev_idx": "13" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT13-EEPROM" + }, + { + "itf": "control", + "dev": "PORT13-CTRL" + } + ] + } + }, + "PORT13-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT13-EEPROM", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT13" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x41", + "dev_addr": "0x50", + "dev_type": "optoe3" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT13-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT13-CTRL", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT13" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x41", + "dev_addr": "0x8", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4034", + "attr_mask": "0xc", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4038", + "attr_mask": "0xc", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x403c", + "attr_mask": "0xc", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4040", + "attr_mask": "0xc", + "attr_cmpval": "0x1", + "attr_len": "1" + } + ] + } + }, + "PORT14": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT14", + "device_parent": "MULTIFPGAPCIE1" + }, + "dev_attr": { + "dev_idx": "14" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT14-EEPROM" + }, + { + "itf": "control", + "dev": "PORT14-CTRL" + } + ] + } + }, + "PORT14-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT14-EEPROM", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT14" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x42", + "dev_addr": "0x50", + "dev_type": "optoe3" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT14-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT14-CTRL", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT14" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x42", + "dev_addr": "0x8", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4034", + "attr_mask": "0xd", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4038", + "attr_mask": "0xd", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x403c", + "attr_mask": "0xd", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4040", + "attr_mask": "0xd", + "attr_cmpval": "0x1", + "attr_len": "1" + } + ] + } + }, + "PORT15": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT15", + "device_parent": "MULTIFPGAPCIE1" + }, + "dev_attr": { + "dev_idx": "15" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT15-EEPROM" + }, + { + "itf": "control", + "dev": "PORT15-CTRL" + } + ] + } + }, + "PORT15-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT15-EEPROM", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT15" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x43", + "dev_addr": "0x50", + "dev_type": "optoe3" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT15-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT15-CTRL", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT15" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x43", + "dev_addr": "0x8", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4034", + "attr_mask": "0xe", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4038", + "attr_mask": "0xe", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x403c", + "attr_mask": "0xe", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4040", + "attr_mask": "0xe", + "attr_cmpval": "0x1", + "attr_len": "1" + } + ] + } + }, + "PORT16": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT16", + "device_parent": "MULTIFPGAPCIE1" + }, + "dev_attr": { + "dev_idx": "16" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT16-EEPROM" + }, + { + "itf": "control", + "dev": "PORT16-CTRL" + } + ] + } + }, + "PORT16-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT16-EEPROM", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT16" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x44", + "dev_addr": "0x50", + "dev_type": "optoe3" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT16-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT16-CTRL", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT16" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x44", + "dev_addr": "0x8", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4034", + "attr_mask": "0xf", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4038", + "attr_mask": "0xf", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x403c", + "attr_mask": "0xf", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4040", + "attr_mask": "0xf", + "attr_cmpval": "0x1", + "attr_len": "1" + } + ] + } + }, + "PORT17": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT17", + "device_parent": "MULTIFPGAPCIE1" + }, + "dev_attr": { + "dev_idx": "17" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT17-EEPROM" + }, + { + "itf": "control", + "dev": "PORT17-CTRL" + } + ] + } + }, + "PORT17-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT17-EEPROM", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT17" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x45", + "dev_addr": "0x50", + "dev_type": "optoe3" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + 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"attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4054", + "attr_mask": "0x0", + "attr_cmpval": "0x1", + "attr_len": "1" + } + ] + } + }, + "PORT18": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT18", + "device_parent": "MULTIFPGAPCIE1" + }, + "dev_attr": { + "dev_idx": "18" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT18-EEPROM" + }, + { + "itf": "control", + "dev": "PORT18-CTRL" + } + ] + } + }, + "PORT18-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT18-EEPROM", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT18" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x46", + "dev_addr": "0x50", + "dev_type": "optoe3" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT18-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT18-CTRL", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT18" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x46", + "dev_addr": "0x8", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4048", + "attr_mask": "0x1", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x404c", + "attr_mask": "0x1", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4050", + "attr_mask": "0x1", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4054", + "attr_mask": "0x1", + "attr_cmpval": "0x1", + "attr_len": "1" + } + ] + } + }, + "PORT19": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT19", + "device_parent": "MULTIFPGAPCIE1" + }, + "dev_attr": { + "dev_idx": "19" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT19-EEPROM" + }, + { + "itf": "control", + "dev": "PORT19-CTRL" + } + ] + } + }, + "PORT19-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT19-EEPROM", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT19" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x47", + "dev_addr": "0x50", + "dev_type": "optoe3" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT19-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT19-CTRL", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT19" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x47", + "dev_addr": "0x8", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4048", + "attr_mask": "0x2", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x404c", + "attr_mask": "0x2", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4050", + "attr_mask": "0x2", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4054", + "attr_mask": "0x2", + "attr_cmpval": "0x1", + "attr_len": "1" + } + ] + } + }, + "PORT20": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT20", + "device_parent": "MULTIFPGAPCIE1" + }, + "dev_attr": { + "dev_idx": "20" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT20-EEPROM" + }, + { + "itf": "control", + "dev": "PORT20-CTRL" + } + ] + } + }, + "PORT20-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT20-EEPROM", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT20" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x48", + "dev_addr": "0x50", + "dev_type": "optoe3" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT20-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT20-CTRL", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT20" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x48", + "dev_addr": "0x8", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4048", + "attr_mask": "0x3", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x404c", + "attr_mask": "0x3", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4050", + "attr_mask": "0x3", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4054", + "attr_mask": "0x3", + "attr_cmpval": "0x1", + "attr_len": "1" + } + ] + } + }, + "PORT21": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT21", + "device_parent": "MULTIFPGAPCIE1" + }, + "dev_attr": { + "dev_idx": "21" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT21-EEPROM" + }, + { + "itf": "control", + "dev": "PORT21-CTRL" + } + ] + } + }, + "PORT21-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT21-EEPROM", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT21" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x49", + "dev_addr": "0x50", + "dev_type": "optoe3" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT21-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT21-CTRL", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT21" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x49", + "dev_addr": "0x8", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4048", + "attr_mask": "0x4", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x404c", + "attr_mask": "0x4", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4050", + "attr_mask": "0x4", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4054", + "attr_mask": "0x4", + "attr_cmpval": "0x1", + "attr_len": "1" + } + ] + } + }, + "PORT22": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT22", + "device_parent": "MULTIFPGAPCIE1" + }, + "dev_attr": { + "dev_idx": "22" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT22-EEPROM" + }, + { + "itf": "control", + "dev": "PORT22-CTRL" + } + ] + } + }, + "PORT22-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT22-EEPROM", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT22" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x4a", + "dev_addr": "0x50", + "dev_type": "optoe3" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT22-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT22-CTRL", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT22" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x4a", + "dev_addr": "0x8", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4048", + "attr_mask": "0x5", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x404c", + "attr_mask": "0x5", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4050", + "attr_mask": "0x5", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4054", + "attr_mask": "0x5", + "attr_cmpval": "0x1", + "attr_len": "1" + } + ] + } + }, + "PORT23": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT23", + "device_parent": "MULTIFPGAPCIE1" + }, + "dev_attr": { + "dev_idx": "23" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT23-EEPROM" + }, + { + "itf": "control", + "dev": "PORT23-CTRL" + } + ] + } + }, + "PORT23-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT23-EEPROM", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT23" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x4b", + "dev_addr": "0x50", + "dev_type": "optoe3" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT23-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT23-CTRL", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT23" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x4b", + "dev_addr": "0x8", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4048", + "attr_mask": "0x6", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x404c", + "attr_mask": "0x6", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4050", + "attr_mask": "0x6", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4054", + "attr_mask": "0x6", + "attr_cmpval": "0x1", + "attr_len": "1" + } + ] + } + }, + "PORT24": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT24", + "device_parent": "MULTIFPGAPCIE1" + }, + "dev_attr": { + "dev_idx": "24" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT24-EEPROM" + }, + { + "itf": "control", + "dev": "PORT24-CTRL" + } + ] + } + }, + "PORT24-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT24-EEPROM", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT24" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x4c", + "dev_addr": "0x50", + "dev_type": "optoe3" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT24-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT24-CTRL", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT24" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x4c", + "dev_addr": "0x8", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4048", + "attr_mask": "0x7", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x404c", + "attr_mask": "0x7", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4050", + "attr_mask": "0x7", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4054", + "attr_mask": "0x7", + "attr_cmpval": "0x1", + "attr_len": "1" + } + ] + } + }, + "PORT25": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT25", + "device_parent": "MULTIFPGAPCIE1" + }, + "dev_attr": { + "dev_idx": "25" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT25-EEPROM" + }, + { + "itf": "control", + "dev": "PORT25-CTRL" + } + ] + } + }, + "PORT25-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT25-EEPROM", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT25" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x4d", + "dev_addr": "0x50", + "dev_type": "optoe3" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT25-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT25-CTRL", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT25" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x4d", + "dev_addr": "0x8", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4048", + "attr_mask": "0x8", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x404c", + "attr_mask": "0x8", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4050", + "attr_mask": "0x8", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4054", + "attr_mask": "0x8", + "attr_cmpval": "0x1", + "attr_len": "1" + } + ] + } + }, + "PORT26": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT26", + "device_parent": "MULTIFPGAPCIE1" + }, + "dev_attr": { + "dev_idx": "26" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT26-EEPROM" + }, + { + "itf": "control", + "dev": "PORT26-CTRL" + } + ] + } + }, + "PORT26-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT26-EEPROM", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT26" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x4e", + "dev_addr": "0x50", + "dev_type": "optoe3" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT26-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT26-CTRL", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT26" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x4e", + "dev_addr": "0x8", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4048", + "attr_mask": "0x9", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x404c", + "attr_mask": "0x9", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4050", + "attr_mask": "0x9", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4054", + "attr_mask": "0x9", + "attr_cmpval": "0x1", + "attr_len": "1" + } + ] + } + }, + "PORT27": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT27", + "device_parent": "MULTIFPGAPCIE1" + }, + "dev_attr": { + "dev_idx": "27" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT27-EEPROM" + }, + { + "itf": "control", + "dev": "PORT27-CTRL" + } + ] + } + }, + "PORT27-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT27-EEPROM", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT27" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x4f", + "dev_addr": "0x50", + "dev_type": "optoe3" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT27-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT27-CTRL", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT27" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x4f", + "dev_addr": "0x8", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4048", + "attr_mask": "0xa", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x404c", + "attr_mask": "0xa", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4050", + "attr_mask": "0xa", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4054", + "attr_mask": "0xa", + "attr_cmpval": "0x1", + "attr_len": "1" + } + ] + } + }, + "PORT28": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT28", + "device_parent": "MULTIFPGAPCIE1" + }, + "dev_attr": { + "dev_idx": "28" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT28-EEPROM" + }, + { + "itf": "control", + "dev": "PORT28-CTRL" + } + ] + } + }, + "PORT28-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT28-EEPROM", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT28" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x50", + "dev_addr": "0x50", + "dev_type": "optoe3" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT28-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT28-CTRL", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT28" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x50", + "dev_addr": "0x8", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4048", + "attr_mask": "0xb", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x404c", + "attr_mask": "0xb", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4050", + "attr_mask": "0xb", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4054", + "attr_mask": "0xb", + "attr_cmpval": "0x1", + "attr_len": "1" + } + ] + } + }, + "PORT29": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT29", + "device_parent": "MULTIFPGAPCIE1" + }, + "dev_attr": { + "dev_idx": "29" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT29-EEPROM" + }, + { + "itf": "control", + "dev": "PORT29-CTRL" + } + ] + } + }, + "PORT29-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT29-EEPROM", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT29" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x51", + "dev_addr": "0x50", + "dev_type": "optoe3" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT29-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT29-CTRL", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT29" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x51", + "dev_addr": "0x8", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4048", + "attr_mask": "0xc", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x404c", + "attr_mask": "0xc", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4050", + "attr_mask": "0xc", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4054", + "attr_mask": "0xc", + "attr_cmpval": "0x1", + "attr_len": "1" + } + ] + } + }, + "PORT30": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT30", + "device_parent": "MULTIFPGAPCIE1" + }, + "dev_attr": { + "dev_idx": "30" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT30-EEPROM" + }, + { + "itf": "control", + "dev": "PORT30-CTRL" + } + ] + } + }, + "PORT30-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT30-EEPROM", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT30" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x52", + "dev_addr": "0x50", + "dev_type": "optoe3" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT30-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT30-CTRL", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT30" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x52", + "dev_addr": "0x8", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4048", + "attr_mask": "0xd", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x404c", + "attr_mask": "0xd", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4050", + "attr_mask": "0xd", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4054", + "attr_mask": "0xd", + "attr_cmpval": "0x1", + "attr_len": "1" + } + ] + } + }, + "PORT31": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT31", + "device_parent": "MULTIFPGAPCIE1" + }, + "dev_attr": { + "dev_idx": "31" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT31-EEPROM" + }, + { + "itf": "control", + "dev": "PORT31-CTRL" + } + ] + } + }, + "PORT31-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT31-EEPROM", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT31" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x53", + "dev_addr": "0x50", + "dev_type": "optoe3" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT31-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT31-CTRL", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT31" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x53", + "dev_addr": "0x8", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4048", + "attr_mask": "0xe", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x404c", + "attr_mask": "0xe", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4050", + "attr_mask": "0xe", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4054", + "attr_mask": "0xe", + "attr_cmpval": "0x1", + "attr_len": "1" + } + ] + } + }, + "PORT32": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT32", + "device_parent": "MULTIFPGAPCIE1" + }, + "dev_attr": { + "dev_idx": "32" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT32-EEPROM" + }, + { + "itf": "control", + "dev": "PORT32-CTRL" + } + ] + } + }, + "PORT32-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT32-EEPROM", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT32" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x54", + "dev_addr": "0x50", + "dev_type": "optoe3" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT32-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT32-CTRL", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT32" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x54", + "dev_addr": "0x8", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4048", + "attr_mask": "0xf", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x404c", + "attr_mask": "0xf", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4050", + "attr_mask": "0xf", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4054", + "attr_mask": "0xf", + "attr_cmpval": "0x1", + "attr_len": "1" + } + ] + } + }, + "PORT33": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT33", + "device_parent": "MULTIFPGAPCIE1" + }, + "dev_attr": { + "dev_idx": "33" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT33-EEPROM" + }, + { + "itf": "control", + "dev": "PORT33-CTRL" + } + ] + } + }, + "PORT33-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT33-EEPROM", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT33" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x12", + "dev_addr": "0x50", + "dev_type": "optoe3" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT33-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT33-CTRL", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT33" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x12", + "dev_addr": "0x8", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x34", + "attr_mask": "0x0", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x38", + "attr_mask": "0x0", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x3c", + "attr_mask": "0x0", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x40", + "attr_mask": "0x0", + "attr_cmpval": "0x1", + "attr_len": "1" + } + ] + } + }, + "PORT34": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT34", + "device_parent": "MULTIFPGAPCIE1" + }, + "dev_attr": { + "dev_idx": "34" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT34-EEPROM" + }, + { + "itf": "control", + "dev": "PORT34-CTRL" + } + ] + } + }, + "PORT34-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT34-EEPROM", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT34" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x13", + "dev_addr": "0x50", + "dev_type": "optoe3" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT34-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT34-CTRL", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT34" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x13", + "dev_addr": "0x8", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x34", + "attr_mask": "0x1", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x38", + "attr_mask": "0x1", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x3c", + "attr_mask": "0x1", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x40", + "attr_mask": "0x1", + "attr_cmpval": "0x1", + "attr_len": "1" + } + ] + } + }, + "PORT35": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT35", + "device_parent": "MULTIFPGAPCIE1" + }, + "dev_attr": { + "dev_idx": "35" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT35-EEPROM" + }, + { + "itf": "control", + "dev": "PORT35-CTRL" + } + ] + } + }, + "PORT35-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT35-EEPROM", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT35" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x14", + "dev_addr": "0x50", + "dev_type": "optoe3" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + 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"attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x40", + "attr_mask": "0x2", + "attr_cmpval": "0x1", + "attr_len": "1" + } + ] + } + }, + "PORT36": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT36", + "device_parent": "MULTIFPGAPCIE1" + }, + "dev_attr": { + "dev_idx": "36" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT36-EEPROM" + }, + { + "itf": "control", + "dev": "PORT36-CTRL" + } + ] + } + }, + "PORT36-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT36-EEPROM", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT36" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x15", + "dev_addr": "0x50", + "dev_type": "optoe3" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT36-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT36-CTRL", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT36" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x15", + "dev_addr": "0x8", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x34", + "attr_mask": "0x3", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x38", + "attr_mask": "0x3", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x3c", + "attr_mask": "0x3", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x40", + "attr_mask": "0x3", + "attr_cmpval": "0x1", + "attr_len": "1" + } + ] + } + }, + "PORT37": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT37", + "device_parent": "MULTIFPGAPCIE1" + }, + "dev_attr": { + "dev_idx": "37" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT37-EEPROM" + }, + { + "itf": "control", + "dev": "PORT37-CTRL" + } + ] + } + }, + "PORT37-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT37-EEPROM", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT37" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x16", + "dev_addr": "0x50", + "dev_type": "optoe3" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT37-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT37-CTRL", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT37" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x16", + "dev_addr": "0x8", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x34", + "attr_mask": "0x4", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x38", + "attr_mask": "0x4", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x3c", + "attr_mask": "0x4", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x40", + "attr_mask": "0x4", + "attr_cmpval": "0x1", + "attr_len": "1" + } + ] + } + }, + "PORT38": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT38", + "device_parent": "MULTIFPGAPCIE1" + }, + "dev_attr": { + "dev_idx": "38" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT38-EEPROM" + }, + { + "itf": "control", + "dev": "PORT38-CTRL" + } + ] + } + }, + "PORT38-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT38-EEPROM", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT38" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x17", + "dev_addr": "0x50", + "dev_type": "optoe3" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT38-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT38-CTRL", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT38" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x17", + "dev_addr": "0x8", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x34", + "attr_mask": "0x5", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x38", + "attr_mask": "0x5", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x3c", + "attr_mask": "0x5", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x40", + "attr_mask": "0x5", + "attr_cmpval": "0x1", + "attr_len": "1" + } + ] + } + }, + "PORT39": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT39", + "device_parent": "MULTIFPGAPCIE1" + }, + "dev_attr": { + "dev_idx": "39" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT39-EEPROM" + }, + { + "itf": "control", + "dev": "PORT39-CTRL" + } + ] + } + }, + "PORT39-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT39-EEPROM", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT39" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x18", + "dev_addr": "0x50", + "dev_type": "optoe3" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT39-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT39-CTRL", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT39" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x18", + "dev_addr": "0x8", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x34", + "attr_mask": "0x6", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x38", + "attr_mask": "0x6", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x3c", + "attr_mask": "0x6", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x40", + "attr_mask": "0x6", + "attr_cmpval": "0x1", + "attr_len": "1" + } + ] + } + }, + "PORT40": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT40", + "device_parent": "MULTIFPGAPCIE1" + }, + "dev_attr": { + "dev_idx": "40" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT40-EEPROM" + }, + { + "itf": "control", + "dev": "PORT40-CTRL" + } + ] + } + }, + "PORT40-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT40-EEPROM", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT40" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x19", + "dev_addr": "0x50", + "dev_type": "optoe3" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT40-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT40-CTRL", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT40" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x19", + "dev_addr": "0x8", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x34", + "attr_mask": "0x7", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x38", + "attr_mask": "0x7", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": 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"attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x40", + "attr_mask": "0x8", + "attr_cmpval": "0x1", + "attr_len": "1" + } + ] + } + }, + "PORT42": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT42", + "device_parent": "MULTIFPGAPCIE1" + }, + "dev_attr": { + "dev_idx": "42" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT42-EEPROM" + }, + { + "itf": "control", + "dev": "PORT42-CTRL" + } + ] + } + }, + "PORT42-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT42-EEPROM", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT42" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x1b", + "dev_addr": "0x50", + "dev_type": "optoe3" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT42-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT42-CTRL", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT42" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x1b", + "dev_addr": "0x8", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x34", + "attr_mask": "0x9", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x38", + "attr_mask": "0x9", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x3c", + "attr_mask": "0x9", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x40", + "attr_mask": "0x9", + "attr_cmpval": "0x1", + "attr_len": "1" + } + ] + } + }, + "PORT43": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT43", + "device_parent": "MULTIFPGAPCIE1" + }, + "dev_attr": { + "dev_idx": "43" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT43-EEPROM" + }, + { + "itf": "control", + "dev": "PORT43-CTRL" + } + ] + } + }, + "PORT43-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT43-EEPROM", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT43" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x1c", + "dev_addr": "0x50", + "dev_type": "optoe3" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT43-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT43-CTRL", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT43" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x1c", + "dev_addr": "0x8", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x34", + "attr_mask": "0xa", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x38", + "attr_mask": "0xa", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x3c", + "attr_mask": "0xa", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x40", + "attr_mask": "0xa", + "attr_cmpval": "0x1", + "attr_len": "1" + } + ] + } + }, + "PORT44": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT44", + "device_parent": "MULTIFPGAPCIE1" + }, + "dev_attr": { + "dev_idx": "44" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT44-EEPROM" + }, + { + "itf": "control", + "dev": "PORT44-CTRL" + } + ] + } + }, + "PORT44-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT44-EEPROM", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT44" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x1d", + "dev_addr": "0x50", + "dev_type": "optoe3" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT44-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT44-CTRL", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT44" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x1d", + "dev_addr": "0x8", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x34", + "attr_mask": "0xb", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x38", + "attr_mask": "0xb", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x3c", + "attr_mask": "0xb", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x40", + "attr_mask": "0xb", + "attr_cmpval": "0x1", + "attr_len": "1" + } + ] + } + }, + "PORT45": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT45", + "device_parent": "MULTIFPGAPCIE1" + }, + "dev_attr": { + "dev_idx": "45" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT45-EEPROM" + }, + { + "itf": "control", + "dev": "PORT45-CTRL" + } + ] + } + }, + "PORT45-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT45-EEPROM", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT45" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x1e", + "dev_addr": "0x50", + "dev_type": "optoe3" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT45-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT45-CTRL", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT45" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x1e", + "dev_addr": "0x8", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x34", + "attr_mask": "0xc", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x38", + "attr_mask": "0xc", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x3c", + "attr_mask": "0xc", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x40", + "attr_mask": "0xc", + "attr_cmpval": "0x1", + "attr_len": "1" + } + ] + } + }, + "PORT46": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT46", + "device_parent": "MULTIFPGAPCIE1" + }, + "dev_attr": { + "dev_idx": "46" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT46-EEPROM" + }, + { + "itf": "control", + "dev": "PORT46-CTRL" + } + ] + } + }, + "PORT46-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT46-EEPROM", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT46" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x1f", + "dev_addr": "0x50", + "dev_type": "optoe3" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT46-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT46-CTRL", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT46" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x1f", + "dev_addr": "0x8", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x34", + "attr_mask": "0xd", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x38", + "attr_mask": "0xd", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x3c", + "attr_mask": "0xd", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x40", + "attr_mask": "0xd", + "attr_cmpval": "0x1", + "attr_len": "1" + } + ] + } + }, + "PORT47": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT47", + "device_parent": "MULTIFPGAPCIE1" + }, + "dev_attr": { + "dev_idx": "47" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT47-EEPROM" + }, + { + "itf": "control", + "dev": "PORT47-CTRL" + } + ] + } + }, + "PORT47-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT47-EEPROM", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT47" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x20", + "dev_addr": "0x50", + "dev_type": "optoe3" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT47-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT47-CTRL", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT47" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x20", + "dev_addr": "0x8", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x34", + "attr_mask": "0xe", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x38", + "attr_mask": "0xe", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x3c", + "attr_mask": "0xe", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x40", + "attr_mask": "0xe", + "attr_cmpval": "0x1", + "attr_len": "1" + } + ] + } + }, + "PORT48": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT48", + "device_parent": "MULTIFPGAPCIE1" + }, + "dev_attr": { + "dev_idx": "48" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT48-EEPROM" + }, + { + "itf": "control", + "dev": "PORT48-CTRL" + } + ] + } + }, + "PORT48-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT48-EEPROM", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT48" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x21", + "dev_addr": "0x50", + "dev_type": "optoe3" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT48-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT48-CTRL", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT48" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x21", + "dev_addr": "0x8", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x34", + "attr_mask": "0xf", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x38", + "attr_mask": "0xf", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x3c", + "attr_mask": "0xf", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x40", + "attr_mask": "0xf", + "attr_cmpval": "0x1", + "attr_len": "1" + } + ] + } + }, + "PORT49": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT49", + "device_parent": "MULTIFPGAPCIE1" + }, + "dev_attr": { + "dev_idx": "49" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT49-EEPROM" + }, + { + "itf": "control", + "dev": "PORT49-CTRL" + } + ] + } + }, + "PORT49-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT49-EEPROM", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT49" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x22", + "dev_addr": "0x50", + "dev_type": "optoe3" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT49-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT49-CTRL", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT49" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x22", + "dev_addr": "0x8", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x48", + "attr_mask": "0x0", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4c", + "attr_mask": "0x0", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x50", + "attr_mask": "0x0", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x54", + "attr_mask": "0x0", + "attr_cmpval": "0x1", + "attr_len": "1" + } + ] + } + }, + "PORT50": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT50", + "device_parent": "MULTIFPGAPCIE1" + }, + "dev_attr": { + "dev_idx": "50" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT50-EEPROM" + }, + { + "itf": "control", + "dev": "PORT50-CTRL" + } + ] + } + }, + "PORT50-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT50-EEPROM", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT50" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x23", + "dev_addr": "0x50", + "dev_type": "optoe3" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT50-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT50-CTRL", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT50" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x23", + "dev_addr": "0x8", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x48", + "attr_mask": "0x1", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4c", + "attr_mask": "0x1", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x50", + "attr_mask": "0x1", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x54", + "attr_mask": "0x1", + "attr_cmpval": "0x1", + "attr_len": "1" + } + ] + } + }, + "PORT51": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT51", + "device_parent": "MULTIFPGAPCIE1" + }, + "dev_attr": { + "dev_idx": "51" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT51-EEPROM" + }, + { + "itf": "control", + "dev": "PORT51-CTRL" + } + ] + } + }, + "PORT51-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT51-EEPROM", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT51" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x24", + "dev_addr": "0x50", + "dev_type": "optoe3" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT51-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT51-CTRL", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT51" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x24", + "dev_addr": "0x8", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x48", + "attr_mask": "0x2", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4c", + "attr_mask": "0x2", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x50", + "attr_mask": "0x2", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x54", + "attr_mask": "0x2", + "attr_cmpval": "0x1", + "attr_len": "1" + } + ] + } + }, + "PORT52": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT52", + "device_parent": "MULTIFPGAPCIE1" + }, + "dev_attr": { + "dev_idx": "52" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT52-EEPROM" + }, + { + "itf": "control", + "dev": "PORT52-CTRL" + } + ] + } + }, + "PORT52-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT52-EEPROM", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT52" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x25", + "dev_addr": "0x50", + "dev_type": "optoe3" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT52-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT52-CTRL", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT52" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x25", + "dev_addr": "0x8", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x48", + "attr_mask": "0x3", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4c", + "attr_mask": "0x3", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": 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"PORT53-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT53-CTRL", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT53" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x26", + "dev_addr": "0x8", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x48", + "attr_mask": "0x4", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4c", + "attr_mask": "0x4", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x50", + "attr_mask": "0x4", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x54", + "attr_mask": "0x4", + "attr_cmpval": "0x1", + "attr_len": "1" + } + ] + } + }, + "PORT54": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT54", + "device_parent": "MULTIFPGAPCIE1" + }, + "dev_attr": { + "dev_idx": "54" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT54-EEPROM" + }, + { + "itf": "control", + "dev": "PORT54-CTRL" + } + ] + } + }, + "PORT54-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT54-EEPROM", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT54" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x27", + "dev_addr": "0x50", + "dev_type": "optoe3" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT54-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT54-CTRL", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT54" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x27", + "dev_addr": "0x8", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x48", + "attr_mask": "0x5", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4c", + "attr_mask": "0x5", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x50", + "attr_mask": "0x5", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x54", + "attr_mask": "0x5", + "attr_cmpval": "0x1", + "attr_len": "1" + } + ] + } + }, + "PORT55": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT55", + "device_parent": "MULTIFPGAPCIE1" + }, + "dev_attr": { + "dev_idx": "55" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT55-EEPROM" + }, + { + "itf": "control", + "dev": "PORT55-CTRL" + } + ] + } + }, + "PORT55-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT55-EEPROM", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT55" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x28", + "dev_addr": "0x50", + "dev_type": "optoe3" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT55-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT55-CTRL", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT55" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x28", + "dev_addr": "0x8", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x48", + "attr_mask": "0x6", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4c", + "attr_mask": "0x6", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x50", + "attr_mask": "0x6", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x54", + "attr_mask": "0x6", + "attr_cmpval": "0x1", + "attr_len": "1" + } + ] + } + }, + "PORT56": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT56", + "device_parent": "MULTIFPGAPCIE1" + }, + "dev_attr": { + "dev_idx": "56" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT56-EEPROM" + }, + { + "itf": "control", + "dev": "PORT56-CTRL" + } + ] + } + }, + "PORT56-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT56-EEPROM", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT56" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x29", + "dev_addr": "0x50", + "dev_type": "optoe3" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT56-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT56-CTRL", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT56" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x29", + "dev_addr": "0x8", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x48", + "attr_mask": "0x7", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4c", + "attr_mask": "0x7", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x50", + "attr_mask": "0x7", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x54", + "attr_mask": "0x7", + "attr_cmpval": "0x1", + "attr_len": "1" + } + ] + } + }, + "PORT57": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT57", + "device_parent": "MULTIFPGAPCIE1" + }, + "dev_attr": { + "dev_idx": "57" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT57-EEPROM" + }, + { + "itf": "control", + "dev": "PORT57-CTRL" + } + ] + } + }, + "PORT57-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT57-EEPROM", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT57" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x2a", + "dev_addr": "0x50", + "dev_type": "optoe3" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT57-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT57-CTRL", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT57" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x2a", + "dev_addr": "0x8", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x48", + "attr_mask": "0x8", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4c", + "attr_mask": "0x8", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x50", + "attr_mask": "0x8", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x54", + "attr_mask": "0x8", + "attr_cmpval": "0x1", + "attr_len": "1" + } + ] + } + }, + "PORT58": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT58", + "device_parent": "MULTIFPGAPCIE1" + }, + "dev_attr": { + "dev_idx": "58" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT58-EEPROM" + }, + { + "itf": "control", + "dev": "PORT58-CTRL" + } + ] + } + }, + "PORT58-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT58-EEPROM", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT58" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x2b", + "dev_addr": "0x50", + "dev_type": "optoe3" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT58-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT58-CTRL", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT58" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x2b", + "dev_addr": "0x8", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x48", + "attr_mask": "0x9", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4c", + "attr_mask": "0x9", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x50", + "attr_mask": "0x9", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x54", + "attr_mask": "0x9", + "attr_cmpval": "0x1", + "attr_len": "1" + } + ] + } + }, + "PORT59": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT59", + "device_parent": "MULTIFPGAPCIE1" + }, + "dev_attr": { + "dev_idx": "59" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT59-EEPROM" + }, + { + "itf": "control", + "dev": "PORT59-CTRL" + } + ] + } + }, + "PORT59-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT59-EEPROM", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT59" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x2c", + "dev_addr": "0x50", + "dev_type": "optoe3" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT59-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT59-CTRL", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT59" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x2c", + "dev_addr": "0x8", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x48", + "attr_mask": "0xa", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4c", + "attr_mask": "0xa", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x50", + "attr_mask": "0xa", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x54", + "attr_mask": "0xa", + "attr_cmpval": "0x1", + "attr_len": "1" + } + ] + } + }, + "PORT60": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT60", + "device_parent": "MULTIFPGAPCIE1" + }, + "dev_attr": { + "dev_idx": "60" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT60-EEPROM" + }, + { + "itf": "control", + "dev": "PORT60-CTRL" + } + ] + } + }, + "PORT60-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT60-EEPROM", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT60" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x2d", + "dev_addr": "0x50", + "dev_type": "optoe3" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT60-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT60-CTRL", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT60" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x2d", + "dev_addr": "0x8", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x48", + "attr_mask": "0xb", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4c", + "attr_mask": "0xb", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x50", + "attr_mask": "0xb", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x54", + "attr_mask": "0xb", + "attr_cmpval": "0x1", + "attr_len": "1" + } + ] + } + }, + "PORT61": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT61", + "device_parent": "MULTIFPGAPCIE1" + }, + "dev_attr": { + "dev_idx": "61" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT61-EEPROM" + }, + { + "itf": "control", + "dev": "PORT61-CTRL" + } + ] + } + }, + "PORT61-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT61-EEPROM", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT61" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x2e", + "dev_addr": "0x50", + "dev_type": "optoe3" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT61-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT61-CTRL", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT61" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x2e", + "dev_addr": "0x8", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x48", + "attr_mask": "0xc", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4c", + "attr_mask": "0xc", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x50", + "attr_mask": "0xc", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x54", + "attr_mask": "0xc", + "attr_cmpval": "0x1", + "attr_len": "1" + } + ] + } + }, + "PORT62": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT62", + "device_parent": "MULTIFPGAPCIE1" + }, + "dev_attr": { + "dev_idx": "62" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT62-EEPROM" + }, + { + "itf": "control", + "dev": "PORT62-CTRL" + } + ] + } + }, + "PORT62-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT62-EEPROM", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT62" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x2f", + "dev_addr": "0x50", + "dev_type": "optoe3" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT62-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT62-CTRL", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT62" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x2f", + "dev_addr": "0x8", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x48", + "attr_mask": "0xd", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4c", + "attr_mask": "0xd", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x50", + "attr_mask": "0xd", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x54", + "attr_mask": "0xd", + "attr_cmpval": "0x1", + "attr_len": "1" + } + ] + } + }, + "PORT63": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT63", + "device_parent": "MULTIFPGAPCIE1" + }, + "dev_attr": { + "dev_idx": "63" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT63-EEPROM" + }, + { + "itf": "control", + "dev": "PORT63-CTRL" + } + ] + } + }, + "PORT63-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT63-EEPROM", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT63" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x30", + "dev_addr": "0x50", + "dev_type": "optoe3" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT63-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT63-CTRL", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT63" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x30", + "dev_addr": "0x8", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x48", + "attr_mask": "0xe", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4c", + "attr_mask": "0xe", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x50", + "attr_mask": "0xe", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x54", + "attr_mask": "0xe", + "attr_cmpval": "0x1", + "attr_len": "1" + } + ] + } + }, + "PORT64": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT64", + "device_parent": "MULTIFPGAPCIE1" + }, + "dev_attr": { + "dev_idx": "64" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT64-EEPROM" + }, + { + "itf": "control", + "dev": "PORT64-CTRL" + } + ] + } + }, + "PORT64-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT64-EEPROM", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT64" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x31", + "dev_addr": "0x50", + "dev_type": "optoe3" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT64-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT64-CTRL", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "PORT64" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x31", + "dev_addr": "0x8", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x48", + "attr_mask": "0xf", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x4c", + "attr_mask": "0xf", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x50", + "attr_mask": "0xf", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x0", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "attr_offset": "0x54", + "attr_mask": "0xf", + "attr_cmpval": "0x1", + "attr_len": "1" + } + ] + } + }, + "PORT_LED_1": { + "dev_info": { + "device_type": "LED", + "device_name": "PORT_LED_1" + }, + "dev_attr": { + "index": "0" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "yellow", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "3:0", + "descr": "yellow", + "value": "0x1", + "swpld_addr": "0x4060", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "green", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "3:0", + "descr": "green", + "value": "0x2", + "swpld_addr": "0x4060", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "off", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "3:0", + "descr": "off", + "value": "0x0", + "swpld_addr": "0x4060", + "swpld_addr_offset": "0x0" + } + ] + } + }, + "PORT_LED_2": { + "dev_info": { + "device_type": "LED", + "device_name": "PORT_LED_2" + }, + "dev_attr": { + "index": "1" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "yellow", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "7:4", + "descr": "yellow", + "value": "0x1", + "swpld_addr": "0x4060", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "green", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "7:4", + "descr": "green", + "value": "0x2", + "swpld_addr": "0x4060", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "off", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "7:4", + "descr": "off", + "value": "0x0", + "swpld_addr": "0x4060", + "swpld_addr_offset": "0x0" + } + ] + } + }, + "PORT_LED_3": { + "dev_info": { + "device_type": "LED", + "device_name": "PORT_LED_3" + }, + "dev_attr": { + "index": "2" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "yellow", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "b:8", + "descr": "yellow", + "value": "0x1", + "swpld_addr": "0x4060", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "green", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "b:8", + "descr": "green", + "value": "0x2", + "swpld_addr": "0x4060", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "off", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "b:8", + "descr": "off", + "value": "0x0", + "swpld_addr": "0x4060", + "swpld_addr_offset": "0x0" + } + ] + } + }, + "PORT_LED_4": { + "dev_info": { + "device_type": "LED", + "device_name": "PORT_LED_4" + }, + "dev_attr": { + "index": "3" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "yellow", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "f:c", + "descr": "yellow", + "value": "0x1", + "swpld_addr": "0x4060", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "green", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "f:c", + "descr": "green", + "value": "0x2", + "swpld_addr": "0x4060", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "off", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "f:c", + "descr": "off", + "value": "0x0", + "swpld_addr": "0x4060", + "swpld_addr_offset": "0x0" + } + ] + } + }, + "PORT_LED_5": { + "dev_info": { + "device_type": "LED", + "device_name": "PORT_LED_5" + }, + "dev_attr": { + "index": "4" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "yellow", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "13:10", + "descr": "yellow", + "value": "0x1", + "swpld_addr": "0x4060", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "green", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "13:10", + "descr": "green", + "value": "0x2", + "swpld_addr": "0x4060", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "off", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "13:10", + "descr": "off", + "value": "0x0", + "swpld_addr": "0x4060", + "swpld_addr_offset": "0x0" + } + ] + } + }, + "PORT_LED_6": { + "dev_info": { + "device_type": "LED", + "device_name": "PORT_LED_6" + }, + "dev_attr": { + "index": "5" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "yellow", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "17:14", + "descr": "yellow", + "value": "0x1", + "swpld_addr": "0x4060", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "green", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "17:14", + "descr": "green", + "value": "0x2", + "swpld_addr": "0x4060", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "off", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "17:14", + "descr": "off", + "value": "0x0", + "swpld_addr": "0x4060", + "swpld_addr_offset": "0x0" + } + ] + } + }, + "PORT_LED_7": { + "dev_info": { + "device_type": "LED", + "device_name": "PORT_LED_7" + }, + "dev_attr": { + "index": "6" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "yellow", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "1b:18", + "descr": "yellow", + "value": "0x1", + "swpld_addr": "0x4060", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "green", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "1b:18", + "descr": "green", + "value": "0x2", + "swpld_addr": "0x4060", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "off", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "1b:18", + "descr": "off", + "value": "0x0", + "swpld_addr": "0x4060", + "swpld_addr_offset": "0x0" + } + ] + } + }, + "PORT_LED_8": { + "dev_info": { + "device_type": "LED", + "device_name": "PORT_LED_8" + }, + "dev_attr": { + "index": "7" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "yellow", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "1f:1c", + "descr": "yellow", + "value": "0x1", + "swpld_addr": "0x4060", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "green", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "1f:1c", + "descr": "green", + "value": "0x2", + "swpld_addr": "0x4060", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "off", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "1f:1c", + "descr": "off", + "value": "0x0", + "swpld_addr": "0x4060", + "swpld_addr_offset": "0x0" + } + ] + } + }, + "PORT_LED_9": { + "dev_info": { + "device_type": "LED", + "device_name": "PORT_LED_9" + }, + "dev_attr": { + "index": "8" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "yellow", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "3:0", + "descr": "yellow", + "value": "0x1", + "swpld_addr": "0x4064", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "green", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "3:0", + "descr": "green", + "value": "0x2", + "swpld_addr": "0x4064", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "off", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "3:0", + "descr": "off", + "value": "0x0", + "swpld_addr": "0x4064", + "swpld_addr_offset": "0x0" + } + ] + } + }, + "PORT_LED_10": { + "dev_info": { + "device_type": "LED", + "device_name": "PORT_LED_10" + }, + "dev_attr": { + "index": "9" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "yellow", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "7:4", + "descr": "yellow", + "value": "0x1", + "swpld_addr": "0x4064", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "green", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "7:4", + "descr": "green", + "value": "0x2", + "swpld_addr": "0x4064", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "off", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "7:4", + "descr": "off", + "value": "0x0", + "swpld_addr": "0x4064", + "swpld_addr_offset": "0x0" + } + ] + } + }, + "PORT_LED_11": { + "dev_info": { + "device_type": "LED", + "device_name": "PORT_LED_11" + }, + "dev_attr": { + "index": "10" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "yellow", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "b:8", + "descr": "yellow", + "value": "0x1", + "swpld_addr": "0x4064", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "green", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "b:8", + "descr": "green", + "value": "0x2", + "swpld_addr": "0x4064", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "off", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "b:8", + "descr": "off", + "value": "0x0", + "swpld_addr": "0x4064", + "swpld_addr_offset": "0x0" + } + ] + } + }, + "PORT_LED_12": { + "dev_info": { + "device_type": "LED", + "device_name": "PORT_LED_12" + }, + "dev_attr": { + "index": "11" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "yellow", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "f:c", + "descr": "yellow", + "value": "0x1", + "swpld_addr": "0x4064", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "green", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "f:c", + "descr": "green", + "value": "0x2", + "swpld_addr": "0x4064", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "off", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "f:c", + "descr": "off", + "value": "0x0", + "swpld_addr": "0x4064", + "swpld_addr_offset": "0x0" + } + ] + } + }, + "PORT_LED_13": { + "dev_info": { + "device_type": "LED", + "device_name": "PORT_LED_13" + }, + "dev_attr": { + "index": "12" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "yellow", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "13:10", + "descr": "yellow", + "value": "0x1", + "swpld_addr": "0x4064", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "green", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "13:10", + "descr": "green", + "value": "0x2", + "swpld_addr": "0x4064", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "off", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "13:10", + "descr": "off", + "value": "0x0", + "swpld_addr": "0x4064", + "swpld_addr_offset": "0x0" + } + ] + } + }, + "PORT_LED_14": { + "dev_info": { + "device_type": "LED", + "device_name": "PORT_LED_14" + }, + "dev_attr": { + "index": "13" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "yellow", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "17:14", + "descr": "yellow", + "value": "0x1", + "swpld_addr": "0x4064", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "green", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "17:14", + "descr": "green", + "value": "0x2", + "swpld_addr": "0x4064", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "off", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "17:14", + "descr": "off", + "value": "0x0", + "swpld_addr": "0x4064", + "swpld_addr_offset": "0x0" + } + ] + } + }, + "PORT_LED_15": { + "dev_info": { + "device_type": "LED", + "device_name": "PORT_LED_15" + }, + "dev_attr": { + "index": "14" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "yellow", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "1b:18", + "descr": "yellow", + "value": "0x1", + "swpld_addr": "0x4064", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "green", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "1b:18", + "descr": "green", + "value": "0x2", + "swpld_addr": "0x4064", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "off", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "1b:18", + "descr": "off", + "value": "0x0", + "swpld_addr": "0x4064", + "swpld_addr_offset": "0x0" + } + ] + } + }, + "PORT_LED_16": { + "dev_info": { + "device_type": "LED", + "device_name": "PORT_LED_16" + }, + "dev_attr": { + "index": "15" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "yellow", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "1f:1c", + "descr": "yellow", + "value": "0x1", + "swpld_addr": "0x4064", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "green", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "1f:1c", + "descr": "green", + "value": "0x2", + "swpld_addr": "0x4064", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "off", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "1f:1c", + "descr": "off", + "value": "0x0", + "swpld_addr": "0x4064", + "swpld_addr_offset": "0x0" + } + ] + } + }, + "PORT_LED_17": { + "dev_info": { + "device_type": "LED", + "device_name": "PORT_LED_17" + }, + "dev_attr": { + "index": "16" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "yellow", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "3:0", + "descr": "yellow", + "value": "0x1", + "swpld_addr": "0x4070", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "green", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "3:0", + "descr": "green", + "value": "0x2", + "swpld_addr": "0x4070", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "off", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "3:0", + "descr": "off", + "value": "0x0", + "swpld_addr": "0x4070", + "swpld_addr_offset": "0x0" + } + ] + } + }, + "PORT_LED_18": { + "dev_info": { + "device_type": "LED", + "device_name": "PORT_LED_18" + }, + "dev_attr": { + "index": "17" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "yellow", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "7:4", + "descr": "yellow", + "value": "0x1", + "swpld_addr": "0x4070", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "green", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "7:4", + "descr": "green", + "value": "0x2", + "swpld_addr": "0x4070", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "off", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "7:4", + "descr": "off", + "value": "0x0", + "swpld_addr": "0x4070", + "swpld_addr_offset": "0x0" + } + ] + } + }, + "PORT_LED_19": { + "dev_info": { + "device_type": "LED", + "device_name": "PORT_LED_19" + }, + "dev_attr": { + "index": "18" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "yellow", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "b:8", + "descr": "yellow", + "value": "0x1", + "swpld_addr": "0x4070", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "green", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "b:8", + "descr": "green", + "value": "0x2", + "swpld_addr": "0x4070", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "off", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "b:8", + "descr": "off", + "value": "0x0", + "swpld_addr": "0x4070", + "swpld_addr_offset": "0x0" + } + ] + } + }, + "PORT_LED_20": { + "dev_info": { + "device_type": "LED", + "device_name": "PORT_LED_20" + }, + "dev_attr": { + "index": "19" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "yellow", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "f:c", + "descr": "yellow", + "value": "0x1", + "swpld_addr": "0x4070", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "green", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "f:c", + "descr": "green", + "value": "0x2", + "swpld_addr": "0x4070", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "off", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "f:c", + "descr": "off", + "value": "0x0", + "swpld_addr": "0x4070", + "swpld_addr_offset": "0x0" + } + ] + } + }, + "PORT_LED_21": { + "dev_info": { + "device_type": "LED", + "device_name": "PORT_LED_21" + }, + "dev_attr": { + "index": "20" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "yellow", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "13:10", + "descr": "yellow", + "value": "0x1", + "swpld_addr": "0x4070", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "green", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "13:10", + "descr": "green", + "value": "0x2", + "swpld_addr": "0x4070", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "off", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "13:10", + "descr": "off", + "value": "0x0", + "swpld_addr": "0x4070", + "swpld_addr_offset": "0x0" + } + ] + } + }, + "PORT_LED_22": { + "dev_info": { + "device_type": "LED", + "device_name": "PORT_LED_22" + }, + "dev_attr": { + "index": "21" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "yellow", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "17:14", + "descr": "yellow", + "value": "0x1", + "swpld_addr": "0x4070", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "green", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "17:14", + "descr": "green", + "value": "0x2", + "swpld_addr": "0x4070", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "off", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "17:14", + "descr": "off", + "value": "0x0", + "swpld_addr": "0x4070", + "swpld_addr_offset": "0x0" + } + ] + } + }, + "PORT_LED_23": { + "dev_info": { + "device_type": "LED", + "device_name": "PORT_LED_23" + }, + "dev_attr": { + "index": "22" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "yellow", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "1b:18", + "descr": "yellow", + "value": "0x1", + "swpld_addr": "0x4070", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "green", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "1b:18", + "descr": "green", + "value": "0x2", + "swpld_addr": "0x4070", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "off", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "1b:18", + "descr": "off", + "value": "0x0", + "swpld_addr": "0x4070", + "swpld_addr_offset": "0x0" + } + ] + } + }, + "PORT_LED_24": { + "dev_info": { + "device_type": "LED", + "device_name": "PORT_LED_24" + }, + "dev_attr": { + "index": "23" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "yellow", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "1f:1c", + "descr": "yellow", + "value": "0x1", + "swpld_addr": "0x4070", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "green", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "1f:1c", + "descr": "green", + "value": "0x2", + "swpld_addr": "0x4070", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "off", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "1f:1c", + "descr": "off", + "value": "0x0", + "swpld_addr": "0x4070", + "swpld_addr_offset": "0x0" + } + ] + } + }, + "PORT_LED_25": { + "dev_info": { + "device_type": "LED", + "device_name": "PORT_LED_25" + }, + "dev_attr": { + "index": "24" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "yellow", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "3:0", + "descr": "yellow", + "value": "0x1", + "swpld_addr": "0x4074", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "green", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "3:0", + "descr": "green", + "value": "0x2", + "swpld_addr": "0x4074", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "off", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "3:0", + "descr": "off", + "value": "0x0", + "swpld_addr": "0x4074", + "swpld_addr_offset": "0x0" + } + ] + } + }, + "PORT_LED_26": { + "dev_info": { + "device_type": "LED", + "device_name": "PORT_LED_26" + }, + "dev_attr": { + "index": "25" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "yellow", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "7:4", + "descr": "yellow", + "value": "0x1", + "swpld_addr": "0x4074", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "green", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "7:4", + "descr": "green", + "value": "0x2", + "swpld_addr": "0x4074", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "off", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "7:4", + "descr": "off", + "value": "0x0", + "swpld_addr": "0x4074", + "swpld_addr_offset": "0x0" + } + ] + } + }, + "PORT_LED_27": { + "dev_info": { + "device_type": "LED", + "device_name": "PORT_LED_27" + }, + "dev_attr": { + "index": "26" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "yellow", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "b:8", + "descr": "yellow", + "value": "0x1", + "swpld_addr": "0x4074", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "green", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "b:8", + "descr": "green", + "value": "0x2", + "swpld_addr": "0x4074", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "off", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "b:8", + "descr": "off", + "value": "0x0", + "swpld_addr": "0x4074", + "swpld_addr_offset": "0x0" + } + ] + } + }, + "PORT_LED_28": { + "dev_info": { + "device_type": "LED", + "device_name": "PORT_LED_28" + }, + "dev_attr": { + "index": "27" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "yellow", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "f:c", + "descr": "yellow", + "value": "0x1", + "swpld_addr": "0x4074", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "green", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "f:c", + "descr": "green", + "value": "0x2", + "swpld_addr": "0x4074", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "off", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "f:c", + "descr": "off", + "value": "0x0", + "swpld_addr": "0x4074", + "swpld_addr_offset": "0x0" + } + ] + } + }, + "PORT_LED_29": { + "dev_info": { + "device_type": "LED", + "device_name": "PORT_LED_29" + }, + "dev_attr": { + "index": "28" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "yellow", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "13:10", + "descr": "yellow", + "value": "0x1", + "swpld_addr": "0x4074", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "green", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "13:10", + "descr": "green", + "value": "0x2", + "swpld_addr": "0x4074", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "off", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "13:10", + "descr": "off", + "value": "0x0", + "swpld_addr": "0x4074", + "swpld_addr_offset": "0x0" + } + ] + } + }, + "PORT_LED_30": { + "dev_info": { + "device_type": "LED", + "device_name": "PORT_LED_30" + }, + "dev_attr": { + "index": "29" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "yellow", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "17:14", + "descr": "yellow", + "value": "0x1", + "swpld_addr": "0x4074", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "green", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "17:14", + "descr": "green", + "value": "0x2", + "swpld_addr": "0x4074", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "off", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "17:14", + "descr": "off", + "value": "0x0", + "swpld_addr": "0x4074", + "swpld_addr_offset": "0x0" + } + ] + } + }, + "PORT_LED_31": { + "dev_info": { + "device_type": "LED", + "device_name": "PORT_LED_31" + }, + "dev_attr": { + "index": "30" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "yellow", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "1b:18", + "descr": "yellow", + "value": "0x1", + "swpld_addr": "0x4074", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "green", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "1b:18", + "descr": "green", + "value": "0x2", + "swpld_addr": "0x4074", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "off", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "1b:18", + "descr": "off", + "value": "0x0", + "swpld_addr": "0x4074", + "swpld_addr_offset": "0x0" + } + ] + } + }, + "PORT_LED_32": { + "dev_info": { + "device_type": "LED", + "device_name": "PORT_LED_32" + }, + "dev_attr": { + "index": "31" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "yellow", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "1f:1c", + "descr": "yellow", + "value": "0x1", + "swpld_addr": "0x4074", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "green", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "1f:1c", + "descr": "green", + "value": "0x2", + "swpld_addr": "0x4074", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "off", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "1f:1c", + "descr": "off", + "value": "0x0", + "swpld_addr": "0x4074", + "swpld_addr_offset": "0x0" + } + ] + } + }, + "PORT_LED_33": { + "dev_info": { + "device_type": "LED", + "device_name": "PORT_LED_33" + }, + "dev_attr": { + "index": "32" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "yellow", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "3:0", + "descr": "yellow", + "value": "0x1", + "swpld_addr": "0x60", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "green", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "3:0", + "descr": "green", + "value": "0x2", + "swpld_addr": "0x60", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "off", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "3:0", + "descr": "off", + "value": "0x0", + "swpld_addr": "0x60", + "swpld_addr_offset": "0x0" + } + ] + } + }, + "PORT_LED_34": { + "dev_info": { + "device_type": "LED", + "device_name": "PORT_LED_34" + }, + "dev_attr": { + "index": "33" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "yellow", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "7:4", + "descr": "yellow", + "value": "0x1", + "swpld_addr": "0x60", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "green", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "7:4", + "descr": "green", + "value": "0x2", + "swpld_addr": "0x60", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "off", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "7:4", + "descr": "off", + "value": "0x0", + "swpld_addr": "0x60", + "swpld_addr_offset": "0x0" + } + ] + } + }, + "PORT_LED_35": { + "dev_info": { + "device_type": "LED", + "device_name": "PORT_LED_35" + }, + "dev_attr": { + "index": "34" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "yellow", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "b:8", + "descr": "yellow", + "value": "0x1", + "swpld_addr": "0x60", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "green", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "b:8", + "descr": "green", + "value": "0x2", + "swpld_addr": "0x60", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "off", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "b:8", + "descr": "off", + "value": "0x0", + "swpld_addr": "0x60", + "swpld_addr_offset": "0x0" + } + ] + } + }, + "PORT_LED_36": { + "dev_info": { + "device_type": "LED", + "device_name": "PORT_LED_36" + }, + "dev_attr": { + "index": "35" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "yellow", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "f:c", + "descr": "yellow", + "value": "0x1", + "swpld_addr": "0x60", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "green", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "f:c", + "descr": "green", + "value": "0x2", + "swpld_addr": "0x60", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "off", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "f:c", + "descr": "off", + "value": "0x0", + "swpld_addr": "0x60", + "swpld_addr_offset": "0x0" + } + ] + } + }, + "PORT_LED_37": { + "dev_info": { + "device_type": "LED", + "device_name": "PORT_LED_37" + }, + "dev_attr": { + "index": "36" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "yellow", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "13:10", + "descr": "yellow", + "value": "0x1", + "swpld_addr": "0x60", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "green", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "13:10", + "descr": "green", + "value": "0x2", + "swpld_addr": "0x60", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "off", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "13:10", + "descr": "off", + "value": "0x0", + "swpld_addr": "0x60", + "swpld_addr_offset": "0x0" + } + ] + } + }, + "PORT_LED_38": { + "dev_info": { + "device_type": "LED", + "device_name": "PORT_LED_38" + }, + "dev_attr": { + "index": "37" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "yellow", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "17:14", + "descr": "yellow", + "value": "0x1", + "swpld_addr": "0x60", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "green", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "17:14", + "descr": "green", + "value": "0x2", + "swpld_addr": "0x60", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "off", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "17:14", + "descr": "off", + "value": "0x0", + "swpld_addr": "0x60", + "swpld_addr_offset": "0x0" + } + ] + } + }, + "PORT_LED_39": { + "dev_info": { + "device_type": "LED", + "device_name": "PORT_LED_39" + }, + "dev_attr": { + "index": "38" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "yellow", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "1b:18", + "descr": "yellow", + "value": "0x1", + "swpld_addr": "0x60", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "green", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "1b:18", + "descr": "green", + "value": "0x2", + "swpld_addr": "0x60", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "off", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "1b:18", + "descr": "off", + "value": "0x0", + "swpld_addr": "0x60", + "swpld_addr_offset": "0x0" + } + ] + } + }, + "PORT_LED_40": { + "dev_info": { + "device_type": "LED", + "device_name": "PORT_LED_40" + }, + "dev_attr": { + "index": "39" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "yellow", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "1f:1c", + "descr": "yellow", + "value": "0x1", + "swpld_addr": "0x60", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "green", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "1f:1c", + "descr": "green", + "value": "0x2", + "swpld_addr": "0x60", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "off", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "1f:1c", + "descr": "off", + "value": "0x0", + "swpld_addr": "0x60", + "swpld_addr_offset": "0x0" + } + ] + } + }, + "PORT_LED_41": { + "dev_info": { + "device_type": "LED", + "device_name": "PORT_LED_41" + }, + "dev_attr": { + "index": "40" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "yellow", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "3:0", + "descr": "yellow", + "value": "0x1", + "swpld_addr": "0x64", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "green", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "3:0", + "descr": "green", + "value": "0x2", + "swpld_addr": "0x64", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "off", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "3:0", + "descr": "off", + "value": "0x0", + "swpld_addr": "0x64", + "swpld_addr_offset": "0x0" + } + ] + } + }, + "PORT_LED_42": { + "dev_info": { + "device_type": "LED", + "device_name": "PORT_LED_42" + }, + "dev_attr": { + "index": "41" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "yellow", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "7:4", + "descr": "yellow", + "value": "0x1", + "swpld_addr": "0x64", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "green", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "7:4", + "descr": "green", + "value": "0x2", + "swpld_addr": "0x64", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "off", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "7:4", + "descr": "off", + "value": "0x0", + "swpld_addr": "0x64", + "swpld_addr_offset": "0x0" + } + ] + } + }, + "PORT_LED_43": { + "dev_info": { + "device_type": "LED", + "device_name": "PORT_LED_43" + }, + "dev_attr": { + "index": "42" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "yellow", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "b:8", + "descr": "yellow", + "value": "0x1", + "swpld_addr": "0x64", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "green", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "b:8", + "descr": "green", + "value": "0x2", + "swpld_addr": "0x64", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "off", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "b:8", + "descr": "off", + "value": "0x0", + "swpld_addr": "0x64", + "swpld_addr_offset": "0x0" + } + ] + } + }, + "PORT_LED_44": { + "dev_info": { + "device_type": "LED", + "device_name": "PORT_LED_44" + }, + "dev_attr": { + "index": "43" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "yellow", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "f:c", + "descr": "yellow", + "value": "0x1", + "swpld_addr": "0x64", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "green", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "f:c", + "descr": "green", + "value": "0x2", + "swpld_addr": "0x64", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "off", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "f:c", + "descr": "off", + "value": "0x0", + "swpld_addr": "0x64", + "swpld_addr_offset": "0x0" + } + ] + } + }, + "PORT_LED_45": { + "dev_info": { + "device_type": "LED", + "device_name": "PORT_LED_45" + }, + "dev_attr": { + "index": "44" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "yellow", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "13:10", + "descr": "yellow", + "value": "0x1", + "swpld_addr": "0x64", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "green", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "13:10", + "descr": "green", + "value": "0x2", + "swpld_addr": "0x64", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "off", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "13:10", + "descr": "off", + "value": "0x0", + "swpld_addr": "0x64", + "swpld_addr_offset": "0x0" + } + ] + } + }, + "PORT_LED_46": { + "dev_info": { + "device_type": "LED", + "device_name": "PORT_LED_46" + }, + "dev_attr": { + "index": "45" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "yellow", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "17:14", + "descr": "yellow", + "value": "0x1", + "swpld_addr": "0x64", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "green", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "17:14", + "descr": "green", + "value": "0x2", + "swpld_addr": "0x64", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "off", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "17:14", + "descr": "off", + "value": "0x0", + "swpld_addr": "0x64", + "swpld_addr_offset": "0x0" + } + ] + } + }, + "PORT_LED_47": { + "dev_info": { + "device_type": "LED", + "device_name": "PORT_LED_47" + }, + "dev_attr": { + "index": "46" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "yellow", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "1b:18", + "descr": "yellow", + "value": "0x1", + "swpld_addr": "0x64", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "green", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "1b:18", + "descr": "green", + "value": "0x2", + "swpld_addr": "0x64", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "off", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "1b:18", + "descr": "off", + "value": "0x0", + "swpld_addr": "0x64", + "swpld_addr_offset": "0x0" + } + ] + } + }, + "PORT_LED_48": { + "dev_info": { + "device_type": "LED", + "device_name": "PORT_LED_48" + }, + "dev_attr": { + "index": "47" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "yellow", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "1f:1c", + "descr": "yellow", + "value": "0x1", + "swpld_addr": "0x64", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "green", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "1f:1c", + "descr": "green", + "value": "0x2", + "swpld_addr": "0x64", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "off", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "1f:1c", + "descr": "off", + "value": "0x0", + "swpld_addr": "0x64", + "swpld_addr_offset": "0x0" + } + ] + } + }, + "PORT_LED_49": { + "dev_info": { + "device_type": "LED", + "device_name": "PORT_LED_49" + }, + "dev_attr": { + "index": "48" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "yellow", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "3:0", + "descr": "yellow", + "value": "0x1", + "swpld_addr": "0x70", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "green", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "3:0", + "descr": "green", + "value": "0x2", + "swpld_addr": "0x70", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "off", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "3:0", + "descr": "off", + "value": "0x0", + "swpld_addr": "0x70", + "swpld_addr_offset": "0x0" + } + ] + } + }, + "PORT_LED_50": { + "dev_info": { + "device_type": "LED", + "device_name": "PORT_LED_50" + }, + "dev_attr": { + "index": "49" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "yellow", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "7:4", + "descr": "yellow", + "value": "0x1", + "swpld_addr": "0x70", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "green", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "7:4", + "descr": "green", + "value": "0x2", + "swpld_addr": "0x70", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "off", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "7:4", + "descr": "off", + "value": "0x0", + "swpld_addr": "0x70", + "swpld_addr_offset": "0x0" + } + ] + } + }, + "PORT_LED_51": { + "dev_info": { + "device_type": "LED", + "device_name": "PORT_LED_51" + }, + "dev_attr": { + "index": "50" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "yellow", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "b:8", + "descr": "yellow", + "value": "0x1", + "swpld_addr": "0x70", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "green", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "b:8", + "descr": "green", + "value": "0x2", + "swpld_addr": "0x70", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "off", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "b:8", + "descr": "off", + "value": "0x0", + "swpld_addr": "0x70", + "swpld_addr_offset": "0x0" + } + ] + } + }, + "PORT_LED_52": { + "dev_info": { + "device_type": "LED", + "device_name": "PORT_LED_52" + }, + "dev_attr": { + "index": "51" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "yellow", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "f:c", + "descr": "yellow", + "value": "0x1", + "swpld_addr": "0x70", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "green", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "f:c", + "descr": "green", + "value": "0x2", + "swpld_addr": "0x70", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "off", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "f:c", + "descr": "off", + "value": "0x0", + "swpld_addr": "0x70", + "swpld_addr_offset": "0x0" + } + ] + } + }, + "PORT_LED_53": { + "dev_info": { + "device_type": "LED", + "device_name": "PORT_LED_53" + }, + "dev_attr": { + "index": "52" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "yellow", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "13:10", + "descr": "yellow", + "value": "0x1", + "swpld_addr": "0x70", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "green", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "13:10", + "descr": "green", + "value": "0x2", + "swpld_addr": "0x70", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "off", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "13:10", + "descr": "off", + "value": "0x0", + "swpld_addr": "0x70", + "swpld_addr_offset": "0x0" + } + ] + } + }, + "PORT_LED_54": { + "dev_info": { + "device_type": "LED", + "device_name": "PORT_LED_54" + }, + "dev_attr": { + "index": "53" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "yellow", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "17:14", + "descr": "yellow", + "value": "0x1", + "swpld_addr": "0x70", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "green", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "17:14", + "descr": "green", + "value": "0x2", + "swpld_addr": "0x70", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "off", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "17:14", + "descr": "off", + "value": "0x0", + "swpld_addr": "0x70", + "swpld_addr_offset": "0x0" + } + ] + } + }, + "PORT_LED_55": { + "dev_info": { + "device_type": "LED", + "device_name": "PORT_LED_55" + }, + "dev_attr": { + "index": "54" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "yellow", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "1b:18", + "descr": "yellow", + "value": "0x1", + "swpld_addr": "0x70", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "green", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "1b:18", + "descr": "green", + "value": "0x2", + "swpld_addr": "0x70", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "off", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "1b:18", + "descr": "off", + "value": "0x0", + "swpld_addr": "0x70", + "swpld_addr_offset": "0x0" + } + ] + } + }, + "PORT_LED_56": { + "dev_info": { + "device_type": "LED", + "device_name": "PORT_LED_56" + }, + "dev_attr": { + "index": "55" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "yellow", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "1f:1c", + "descr": "yellow", + "value": "0x1", + "swpld_addr": "0x70", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "green", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "1f:1c", + "descr": "green", + "value": "0x2", + "swpld_addr": "0x70", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "off", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "1f:1c", + "descr": "off", + "value": "0x0", + "swpld_addr": "0x70", + "swpld_addr_offset": "0x0" + } + ] + } + }, + "PORT_LED_57": { + "dev_info": { + "device_type": "LED", + "device_name": "PORT_LED_57" + }, + "dev_attr": { + "index": "56" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "yellow", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "3:0", + "descr": "yellow", + "value": "0x1", + "swpld_addr": "0x74", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "green", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "3:0", + "descr": "green", + "value": "0x2", + "swpld_addr": "0x74", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "off", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "3:0", + "descr": "off", + "value": "0x0", + "swpld_addr": "0x74", + "swpld_addr_offset": "0x0" + } + ] + } + }, + "PORT_LED_58": { + "dev_info": { + "device_type": "LED", + "device_name": "PORT_LED_58" + }, + "dev_attr": { + "index": "57" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "yellow", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "7:4", + "descr": "yellow", + "value": "0x1", + "swpld_addr": "0x74", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "green", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "7:4", + "descr": "green", + "value": "0x2", + "swpld_addr": "0x74", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "off", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "7:4", + "descr": "off", + "value": "0x0", + "swpld_addr": "0x74", + "swpld_addr_offset": "0x0" + } + ] + } + }, + "PORT_LED_59": { + "dev_info": { + "device_type": "LED", + "device_name": "PORT_LED_59" + }, + "dev_attr": { + "index": "58" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "yellow", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "b:8", + "descr": "yellow", + "value": "0x1", + "swpld_addr": "0x74", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "green", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "b:8", + "descr": "green", + "value": "0x2", + "swpld_addr": "0x74", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "off", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "b:8", + "descr": "off", + "value": "0x0", + "swpld_addr": "0x74", + "swpld_addr_offset": "0x0" + } + ] + } + }, + "PORT_LED_60": { + "dev_info": { + "device_type": "LED", + "device_name": "PORT_LED_60" + }, + "dev_attr": { + "index": "59" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "yellow", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "f:c", + "descr": "yellow", + "value": "0x1", + "swpld_addr": "0x74", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "green", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "f:c", + "descr": "green", + "value": "0x2", + "swpld_addr": "0x74", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "off", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "f:c", + "descr": "off", + "value": "0x0", + "swpld_addr": "0x74", + "swpld_addr_offset": "0x0" + } + ] + } + }, + "PORT_LED_61": { + "dev_info": { + "device_type": "LED", + "device_name": "PORT_LED_61" + }, + "dev_attr": { + "index": "60" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "yellow", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "13:10", + "descr": "yellow", + "value": "0x1", + "swpld_addr": "0x74", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "green", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "13:10", + "descr": "green", + "value": "0x2", + "swpld_addr": "0x74", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "off", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "13:10", + "descr": "off", + "value": "0x0", + "swpld_addr": "0x74", + "swpld_addr_offset": "0x0" + } + ] + } + }, + "PORT_LED_62": { + "dev_info": { + "device_type": "LED", + "device_name": "PORT_LED_62" + }, + "dev_attr": { + "index": "61" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "yellow", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "17:14", + "descr": "yellow", + "value": "0x1", + "swpld_addr": "0x74", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "green", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "17:14", + "descr": "green", + "value": "0x2", + "swpld_addr": "0x74", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "off", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "17:14", + "descr": "off", + "value": "0x0", + "swpld_addr": "0x74", + "swpld_addr_offset": "0x0" + } + ] + } + }, + "PORT_LED_63": { + "dev_info": { + "device_type": "LED", + "device_name": "PORT_LED_63" + }, + "dev_attr": { + "index": "62" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "yellow", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "1b:18", + "descr": "yellow", + "value": "0x1", + "swpld_addr": "0x74", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "green", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "1b:18", + "descr": "green", + "value": "0x2", + "swpld_addr": "0x74", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "off", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "1b:18", + "descr": "off", + "value": "0x0", + "swpld_addr": "0x74", + "swpld_addr_offset": "0x0" + } + ] + } + }, + "PORT_LED_64": { + "dev_info": { + "device_type": "LED", + "device_name": "PORT_LED_64" + }, + "dev_attr": { + "index": "63" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "yellow", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "1f:1c", + "descr": "yellow", + "value": "0x1", + "swpld_addr": "0x74", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "green", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "1f:1c", + "descr": "green", + "value": "0x2", + "swpld_addr": "0x74", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "off", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "1f:1c", + "descr": "off", + "value": "0x0", + "swpld_addr": "0x74", + "swpld_addr_offset": "0x0" + } + ] + } + }, + "PORT_LED_65": { + "dev_info": { + "device_type": "LED", + "device_name": "PORT_LED_65" + }, + "dev_attr": { + "index": "64" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "yellow", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "13:10", + "descr": "yellow", + "value": "0x1", + "swpld_addr": "0x84", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "green", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "13:10", + "descr": "green", + "value": "0x2", + "swpld_addr": "0x84", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "off", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "13:10", + "descr": "off", + "value": "0x0", + "swpld_addr": "0x84", + "swpld_addr_offset": "0x0" + } + ] + } + }, + "PORT_LED_66": { + "dev_info": { + "device_type": "LED", + "device_name": "PORT_LED_66" + }, + "dev_attr": { + "index": "65" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "yellow", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "17:14", + "descr": "yellow", + "value": "0x1", + "swpld_addr": "0x84", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "green", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "17:14", + "descr": "green", + "value": "0x2", + "swpld_addr": "0x84", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "off", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "17:14", + "descr": "off", + "value": "0x0", + "swpld_addr": "0x84", + "swpld_addr_offset": "0x0" + } + ] + } + }, + "SYS_LED": { + "dev_info": { + "device_type": "LED", + "device_name": "SYS_LED" + }, + "dev_attr": { + "index": "0" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "green", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "b:8", + "descr": "green", + "value": "0x2", + "swpld_addr": "0x84", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "green_blink", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "b:8", + "descr": "green_blink", + "value": "0x6", + "swpld_addr": "0x84", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "red", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "b:8", + "descr": "red", + "value": "0x1", + "swpld_addr": "0x84", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "amber", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "b:8", + "descr": "amber", + "value": "0x3", + "swpld_addr": "0x84", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "off", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "b:8", + "descr": "off", + "value": "0x0", + "swpld_addr": "0x84", + "swpld_addr_offset": "0x0" + } + ] + } + }, + "LOC_LED": { + "dev_info": { + "device_type": "LED", + "device_name": "LOC_LED" + }, + "dev_attr": { + "index": "0" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "blue_blink", + "attr_devtype": "multifpgapci", + "attr_devname": "CPUCARD_FPGA", + "bits": "13:10", + "descr": "blue_blink", + "value": "0x5", + "swpld_addr": "0x48", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "blue", + "attr_devtype": "multifpgapci", + "attr_devname": "CPUCARD_FPGA", + "bits": "13:10", + "descr": "blue", + "value": "0x1", + "swpld_addr": "0x48", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "off", + "attr_devtype": "multifpgapci", + "attr_devname": "CPUCARD_FPGA", + "bits": "13:10", + "descr": "off", + "value": "0x0", + "swpld_addr": "0x48", + "swpld_addr_offset": "0x0" + } + ] + } + }, + "FAN_LED": { + "dev_info": { + "device_type": "LED", + "device_name": "FAN_LED" + }, + "dev_attr": { + "index": "0" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "green", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "7:4", + "descr": "green", + "value": "0x2", + "swpld_addr": "0x84", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "red", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "7:4", + "descr": "red", + "value": "0x1", + "swpld_addr": "0x84", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "amber", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "7:4", + "descr": "amber", + "value": "0x3", + "swpld_addr": "0x84", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "off", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "7:4", + "descr": "off", + "value": "0x0", + "swpld_addr": "0x84", + "swpld_addr_offset": "0x0" + } + ] + } + }, + "PSU_LED": { + "dev_info": { + "device_type": "LED", + "device_name": "PSU_LED" + }, + "dev_attr": { + "index": "0" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "green", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "3:0", + "descr": "green", + "value": "0x2", + "swpld_addr": "0x84", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "red", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "3:0", + "descr": "red", + "value": "0x1", + "swpld_addr": "0x84", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "amber", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "3:0", + "descr": "amber", + "value": "0x3", + "swpld_addr": "0x84", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "off", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "3:0", + "descr": "off", + "value": "0x0", + "swpld_addr": "0x84", + "swpld_addr_offset": "0x0" + } + ] + } + }, + "FANTRAY1_LED": { + "dev_info": { + "device_type": "LED", + "device_name": "FANTRAY_LED" + }, + "dev_attr": { + "index": "0" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "green", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "1:0", + "descr": "green", + "value": "0x2", + "swpld_addr": "0xa0", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "red", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "1:0", + "descr": "red", + "value": "0x1", + "swpld_addr": "0xa0", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "off", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "1:0", + "descr": "off", + "value": "0x0", + "swpld_addr": "0xa0", + "swpld_addr_offset": "0x0" + } + ] + } + }, + "FANTRAY2_LED": { + "dev_info": { + "device_type": "LED", + "device_name": "FANTRAY_LED" + }, + "dev_attr": { + "index": "1" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "green", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "3:2", + "descr": "green", + "value": "0x2", + "swpld_addr": "0xa0", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "red", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "3:2", + "descr": "red", + "value": "0x1", + "swpld_addr": "0xa0", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "off", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "3:2", + "descr": "off", + "value": "0x0", + "swpld_addr": "0xa0", + "swpld_addr_offset": "0x0" + } + ] + } + }, + "FANTRAY3_LED": { + "dev_info": { + "device_type": "LED", + "device_name": "FANTRAY_LED" + }, + "dev_attr": { + "index": "2" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "green", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "5:4", + "descr": "green", + "value": "0x2", + "swpld_addr": "0xa0", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "red", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "5:4", + "descr": "red", + "value": "0x1", + "swpld_addr": "0xa0", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "off", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "5:4", + "descr": "off", + "value": "0x0", + "swpld_addr": "0xa0", + "swpld_addr_offset": "0x0" + } + ] + } + }, + "FANTRAY4_LED": { + "dev_info": { + "device_type": "LED", + "device_name": "FANTRAY_LED" + }, + "dev_attr": { + "index": "3" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "green", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "7:6", + "descr": "green", + "value": "0x2", + "swpld_addr": "0xa0", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "red", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "7:6", + "descr": "red", + "value": "0x1", + "swpld_addr": "0xa0", + "swpld_addr_offset": "0x0" + }, + { + "attr_name": "off", + "attr_devtype": "multifpgapci", + "attr_devname": "SWITCHCARD_FPGA", + "bits": "7:6", + "descr": "off", + "value": "0x0", + "swpld_addr": "0xa0", + "swpld_addr_offset": "0x0" + } + ] + } + }, + "DPM1": { + "dev_info": { + "device_type": "DPM", + "device_name": "DPM1", + "device_parent": "MULTIFPGAPCIE0" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x7", + "dev_addr": "0x41", + "dev_type": "adm1266" + } + } + }, + "DPM2": { + "dev_info": { + "device_type": "DPM", + "device_name": "DPM2", + "device_parent": "MULTIFPGAPCIE0" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x9", + "dev_addr": "0x41", + "dev_type": "adm1266" + } + } + }, + "DPM3": { + "dev_info": { + "device_type": "DPM", + "device_name": "DPM3", + "device_parent": "MULTIFPGAPCIE0" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x9", + "dev_addr": "0x43", + "dev_type": "adm1266" + } + } + }, + "DPM4": { + "dev_info": { + "device_type": "DPM", + "device_name": "DPM4", + "device_parent": "MULTIFPGAPCIE0" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x9", + "dev_addr": "0x45", + "dev_type": "adm1266" + } + } + }, + "VOLTAGE1": { + "dev_info": { + "device_type": "VOLTAGE_SENSOR", + "device_name": "DPM1-RAIL1", + "device_parent": "MULTIFPGAPCIE0", + "virt_parent": "DPM1" + }, + "dev_attr": { + "display_name": "POS12V0_DPM1" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "volt1_input", + "drv_attr_name": "in1_input" + }, + { + "attr_name": "volt1_high_threshold", + "drv_attr_name": "in1_max" + }, + { + "attr_name": "volt1_low_threshold", + "drv_attr_name": "in1_min" + }, + { + "attr_name": "volt1_crit_high_threshold", + "drv_attr_name": "in1_crit" + }, + { + "attr_name": "volt1_crit_low_threshold", + "drv_attr_name": "in1_lcrit" + } + ] + } + }, + "VOLTAGE2": { + "dev_info": { + "device_type": "VOLTAGE_SENSOR", + "device_name": "DPM1-RAIL2", + "device_parent": "MULTIFPGAPCIE0", + "virt_parent": "DPM1" + }, + "dev_attr": { + "display_name": "POS5V0_DPM1" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "volt1_input", + "drv_attr_name": "in2_input" + }, + { + "attr_name": "volt1_high_threshold", + "drv_attr_name": "in2_max" + }, + { + "attr_name": "volt1_low_threshold", + "drv_attr_name": "in2_min" + }, + { + "attr_name": "volt1_crit_high_threshold", + "drv_attr_name": "in2_crit" + }, + { + "attr_name": "volt1_crit_low_threshold", + "drv_attr_name": "in2_lcrit" + } + ] + } + }, + "VOLTAGE3": { + "dev_info": { + "device_type": "VOLTAGE_SENSOR", + "device_name": "DPM1-RAIL3", + "device_parent": "MULTIFPGAPCIE0", + "virt_parent": "DPM1" + }, + "dev_attr": { + "display_name": "POS5V0_S0_DPM1" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "volt1_input", + "drv_attr_name": "in4_input" + }, + { + "attr_name": "volt1_high_threshold", + "drv_attr_name": "in4_max" + }, + { + "attr_name": "volt1_low_threshold", + "drv_attr_name": "in4_min" + }, + { + "attr_name": "volt1_crit_high_threshold", + "drv_attr_name": "in4_crit" + }, + { + "attr_name": "volt1_crit_low_threshold", + "drv_attr_name": "in4_lcrit" + } + ] + } + }, + "VOLTAGE4": { + "dev_info": { + "device_type": "VOLTAGE_SENSOR", + "device_name": "DPM1-RAIL4", + "device_parent": "MULTIFPGAPCIE0", + "virt_parent": "DPM1" + }, + "dev_attr": { + "display_name": "POS1V0_A7_DPM1" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "volt1_input", + "drv_attr_name": "in5_input" + }, + { + "attr_name": "volt1_high_threshold", + "drv_attr_name": "in5_max" + }, + { + "attr_name": "volt1_low_threshold", + "drv_attr_name": "in5_min" + }, + { + "attr_name": "volt1_crit_high_threshold", + "drv_attr_name": "in5_crit" + }, + { + "attr_name": "volt1_crit_low_threshold", + "drv_attr_name": "in5_lcrit" + } + ] + } + }, + "VOLTAGE5": { + "dev_info": { + "device_type": "VOLTAGE_SENSOR", + "device_name": "DPM1-RAIL5", + "device_parent": "MULTIFPGAPCIE0", + "virt_parent": "DPM1" + }, + "dev_attr": { + "display_name": "POS1V8_A7_DPM1" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "volt1_input", + "drv_attr_name": "in6_input" + }, + { + "attr_name": "volt1_high_threshold", + "drv_attr_name": "in6_max" + }, + { + "attr_name": "volt1_low_threshold", + "drv_attr_name": "in6_min" + }, + { + "attr_name": "volt1_crit_high_threshold", + "drv_attr_name": "in6_crit" + }, + { + "attr_name": "volt1_crit_low_threshold", + "drv_attr_name": "in6_lcrit" + } + ] + } + }, + "VOLTAGE6": { + "dev_info": { + "device_type": "VOLTAGE_SENSOR", + "device_name": "DPM1-RAIL6", + "device_parent": "MULTIFPGAPCIE0", + "virt_parent": "DPM1" + }, + "dev_attr": { + "display_name": "POS3V3_DPM1" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "volt1_input", + "drv_attr_name": "in7_input" + }, + { + "attr_name": "volt1_high_threshold", + "drv_attr_name": "in7_max" + }, + { + "attr_name": "volt1_low_threshold", + "drv_attr_name": "in7_min" + }, + { + "attr_name": "volt1_crit_high_threshold", + "drv_attr_name": "in7_crit" + }, + { + "attr_name": "volt1_crit_low_threshold", + "drv_attr_name": "in7_lcrit" + } + ] + } + }, + "VOLTAGE7": { + "dev_info": { + "device_type": "VOLTAGE_SENSOR", + "device_name": "DPM1-RAIL7", + "device_parent": "MULTIFPGAPCIE0", + "virt_parent": "DPM1" + }, + "dev_attr": { + "display_name": "POS1V0_DPM1" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "volt1_input", + "drv_attr_name": "in8_input" + }, + { + "attr_name": "volt1_high_threshold", + "drv_attr_name": "in8_max" + }, + { + "attr_name": "volt1_low_threshold", + "drv_attr_name": "in8_min" + }, + { + "attr_name": "volt1_crit_high_threshold", + "drv_attr_name": "in8_crit" + }, + { + "attr_name": "volt1_crit_low_threshold", + "drv_attr_name": "in8_lcrit" + } + ] + } + }, + "VOLTAGE8": { + "dev_info": { + "device_type": "VOLTAGE_SENSOR", + "device_name": "DPM1-RAIL8", + "device_parent": "MULTIFPGAPCIE0", + "virt_parent": "DPM1" + }, + "dev_attr": { + "display_name": "POS1V2_A7_DPM1" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "volt1_input", + "drv_attr_name": "in9_input" + }, + { + "attr_name": "volt1_high_threshold", + "drv_attr_name": "in9_max" + }, + { + "attr_name": "volt1_low_threshold", + "drv_attr_name": "in9_min" + }, + { + "attr_name": "volt1_crit_high_threshold", + "drv_attr_name": "in9_crit" + }, + { + "attr_name": "volt1_crit_low_threshold", + "drv_attr_name": "in9_lcrit" + } + ] + } + }, + "VOLTAGE9": { + "dev_info": { + "device_type": "VOLTAGE_SENSOR", + "device_name": "DPM1-RAIL9", + "device_parent": "MULTIFPGAPCIE0", + "virt_parent": "DPM1" + }, + "dev_attr": { + "display_name": "POS0V75_S5_DPM1" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "volt1_input", + "drv_attr_name": "in10_input" + }, + { + "attr_name": "volt1_high_threshold", + "drv_attr_name": "in10_max" + }, + { + "attr_name": "volt1_low_threshold", + "drv_attr_name": "in10_min" + }, + { + "attr_name": "volt1_crit_high_threshold", + "drv_attr_name": "in10_crit" + }, + { + "attr_name": "volt1_crit_low_threshold", + "drv_attr_name": "in10_lcrit" + } + ] + } + }, + "VOLTAGE10": { + "dev_info": { + "device_type": "VOLTAGE_SENSOR", + "device_name": "DPM1-RAIL10", + "device_parent": "MULTIFPGAPCIE0", + "virt_parent": "DPM1" + }, + "dev_attr": { + "display_name": "POS1V8_S5_DPM1" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "volt1_input", + "drv_attr_name": "in11_input" + }, + { + "attr_name": "volt1_high_threshold", + "drv_attr_name": "in11_max" + }, + { + "attr_name": "volt1_low_threshold", + "drv_attr_name": "in11_min" + }, + { + "attr_name": "volt1_crit_high_threshold", + "drv_attr_name": "in11_crit" + }, + { + "attr_name": "volt1_crit_low_threshold", + "drv_attr_name": "in11_lcrit" + } + ] + } + }, + "VOLTAGE11": { + "dev_info": { + "device_type": "VOLTAGE_SENSOR", + "device_name": "DPM1-RAIL11", + "device_parent": "MULTIFPGAPCIE0", + "virt_parent": "DPM1" + }, + "dev_attr": { + "display_name": "POS3V3_S5_DPM1" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "volt1_input", + "drv_attr_name": "in12_input" + }, + { + "attr_name": "volt1_high_threshold", + "drv_attr_name": "in12_max" + }, + { + "attr_name": "volt1_low_threshold", + "drv_attr_name": "in12_min" + }, + { + "attr_name": "volt1_crit_high_threshold", + "drv_attr_name": "in12_crit" + }, + { + "attr_name": "volt1_crit_low_threshold", + "drv_attr_name": "in12_lcrit" + } + ] + } + }, + "VOLTAGE12": { + "dev_info": { + "device_type": "VOLTAGE_SENSOR", + "device_name": "DPM1-RAIL12", + "device_parent": "MULTIFPGAPCIE0", + "virt_parent": "DPM1" + }, + "dev_attr": { + "display_name": "POS1V1_S0_DPM1" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "volt1_input", + "drv_attr_name": "in13_input" + }, + { + "attr_name": "volt1_high_threshold", + "drv_attr_name": "in13_max" + }, + { + "attr_name": "volt1_low_threshold", + "drv_attr_name": "in13_min" + }, + { + "attr_name": "volt1_crit_high_threshold", + "drv_attr_name": "in13_crit" + }, + { + "attr_name": "volt1_crit_low_threshold", + "drv_attr_name": "in13_lcrit" + } + ] + } + }, + "VOLTAGE13": { + "dev_info": { + "device_type": "VOLTAGE_SENSOR", + "device_name": "DPM1-RAIL13", + "device_parent": "MULTIFPGAPCIE0", + "virt_parent": "DPM1" + }, + "dev_attr": { + "display_name": "POS0V78_S0_DPM1" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "volt1_input", + "drv_attr_name": "in14_input" + }, + { + "attr_name": "volt1_high_threshold", + "drv_attr_name": "in14_max" + }, + { + "attr_name": "volt1_low_threshold", + "drv_attr_name": "in14_min" + }, + { + "attr_name": "volt1_crit_high_threshold", + "drv_attr_name": "in14_crit" + }, + { + "attr_name": "volt1_crit_low_threshold", + "drv_attr_name": "in14_lcrit" + } + ] + } + }, + "VOLTAGE14": { + "dev_info": { + "device_type": "VOLTAGE_SENSOR", + "device_name": "DPM1-RAIL14", + "device_parent": "MULTIFPGAPCIE0", + "virt_parent": "DPM1" + }, + "dev_attr": { + "display_name": "POS0V75_S0_DPM1" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "volt1_input", + "drv_attr_name": "in15_input" + }, + { + "attr_name": "volt1_high_threshold", + "drv_attr_name": "in15_max" + }, + { + "attr_name": "volt1_low_threshold", + "drv_attr_name": "in15_min" + }, + { + "attr_name": "volt1_crit_high_threshold", + "drv_attr_name": "in15_crit" + }, + { + "attr_name": "volt1_crit_low_threshold", + "drv_attr_name": "in15_lcrit" + } + ] + } + }, + "VOLTAGE15": { + "dev_info": { + "device_type": "VOLTAGE_SENSOR", + "device_name": "DPM1-RAIL15", + "device_parent": "MULTIFPGAPCIE0", + "virt_parent": "DPM1" + }, + "dev_attr": { + "display_name": "POS1V8_S0_DPM1" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "volt1_input", + "drv_attr_name": "in16_input" + }, + { + "attr_name": "volt1_high_threshold", + "drv_attr_name": "in16_max" + }, + { + "attr_name": "volt1_low_threshold", + "drv_attr_name": "in16_min" + }, + { + "attr_name": "volt1_crit_high_threshold", + "drv_attr_name": "in16_crit" + }, + { + "attr_name": "volt1_crit_low_threshold", + "drv_attr_name": "in16_lcrit" + } + ] + } + }, + "VOLTAGE16": { + "dev_info": { + "device_type": "VOLTAGE_SENSOR", + "device_name": "DPM1-RAIL16", + "device_parent": "MULTIFPGAPCIE0", + "virt_parent": "DPM1" + }, + "dev_attr": { + "display_name": "POS3V3_S0_DPM1" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "volt1_input", + "drv_attr_name": "in17_input" + }, + { + "attr_name": "volt1_high_threshold", + "drv_attr_name": "in17_max" + }, + { + "attr_name": "volt1_low_threshold", + "drv_attr_name": "in17_min" + }, + { + "attr_name": "volt1_crit_high_threshold", + "drv_attr_name": "in17_crit" + }, + { + "attr_name": "volt1_crit_low_threshold", + "drv_attr_name": "in17_lcrit" + } + ] + } + }, + "VOLTAGE17": { + "dev_info": { + "device_type": "VOLTAGE_SENSOR", + "device_name": "DPM2-RAIL1", + "device_parent": "MULTIFPGAPCIE0", + "virt_parent": "DPM2" + }, + "dev_attr": { + "display_name": "POS12V0_DPM2" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "volt1_input", + "drv_attr_name": "in1_input" + }, + { + "attr_name": "volt1_high_threshold", + "drv_attr_name": "in1_max" + }, + { + "attr_name": "volt1_low_threshold", + "drv_attr_name": "in1_min" + }, + { + "attr_name": "volt1_crit_high_threshold", + "drv_attr_name": "in1_crit" + }, + { + "attr_name": "volt1_crit_low_threshold", + "drv_attr_name": "in1_lcrit" + } + ] + } + }, + "VOLTAGE18": { + "dev_info": { + "device_type": "VOLTAGE_SENSOR", + "device_name": "DPM2-RAIL2", + "device_parent": "MULTIFPGAPCIE0", + "virt_parent": "DPM2" + }, + "dev_attr": { + "display_name": "POS5V0_DPM2" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "volt1_input", + "drv_attr_name": "in2_input" + }, + { + "attr_name": "volt1_high_threshold", + "drv_attr_name": "in2_max" + }, + { + "attr_name": "volt1_low_threshold", + "drv_attr_name": "in2_min" + }, + { + "attr_name": "volt1_crit_high_threshold", + "drv_attr_name": "in2_crit" + }, + { + "attr_name": "volt1_crit_low_threshold", + "drv_attr_name": "in2_lcrit" + } + ] + } + }, + "VOLTAGE19": { + "dev_info": { + "device_type": "VOLTAGE_SENSOR", + "device_name": "DPM2-RAIL3", + "device_parent": "MULTIFPGAPCIE0", + "virt_parent": "DPM2" + }, + "dev_attr": { + "display_name": "POS1V0" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "volt1_input", + "drv_attr_name": "in3_input" + }, + { + "attr_name": "volt1_high_threshold", + "drv_attr_name": "in3_max" + }, + { + "attr_name": "volt1_low_threshold", + "drv_attr_name": "in3_min" + }, + { + "attr_name": "volt1_crit_high_threshold", + "drv_attr_name": "in3_max_alarm" + }, + { + "attr_name": "volt1_crit_low_threshold", + "drv_attr_name": "in3_min_alarm" + } + ] + } + }, + "VOLTAGE20": { + "dev_info": { + "device_type": "VOLTAGE_SENSOR", + "device_name": "DPM2-RAIL4", + "device_parent": "MULTIFPGAPCIE0", + "virt_parent": "DPM2" + }, + "dev_attr": { + "display_name": "POS1V8_CP" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "volt1_input", + "drv_attr_name": "in4_input" + }, + { + "attr_name": "volt1_high_threshold", + "drv_attr_name": "in4_max" + }, + { + "attr_name": "volt1_low_threshold", + "drv_attr_name": "in4_min" + }, + { + "attr_name": "volt1_crit_high_threshold", + "drv_attr_name": "in4_crit" + }, + { + "attr_name": "volt1_crit_low_threshold", + "drv_attr_name": "in4_lcrit" + } + ] + } + }, + "VOLTAGE21": { + "dev_info": { + "device_type": "VOLTAGE_SENSOR", + "device_name": "DPM2-RAIL5", + "device_parent": "MULTIFPGAPCIE0", + "virt_parent": "DPM2" + }, + "dev_attr": { + "display_name": "POS1V2_CP" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "volt1_input", + "drv_attr_name": "in5_input" + }, + { + "attr_name": "volt1_high_threshold", + "drv_attr_name": "in5_max" + }, + { + "attr_name": "volt1_low_threshold", + "drv_attr_name": "in5_min" + }, + { + "attr_name": "volt1_crit_high_threshold", + "drv_attr_name": "in5_crit" + }, + { + "attr_name": "volt1_crit_low_threshold", + "drv_attr_name": "in5_lcrit" + } + ] + } + }, + "VOLTAGE22": { + "dev_info": { + "device_type": "VOLTAGE_SENSOR", + "device_name": "DPM2-RAIL6", + "device_parent": "MULTIFPGAPCIE0", + "virt_parent": "DPM2" + }, + "dev_attr": { + "display_name": "POS3V3_DPM2" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "volt1_input", + "drv_attr_name": "in6_input" + }, + { + "attr_name": "volt1_high_threshold", + "drv_attr_name": "in6_max" + }, + { + "attr_name": "volt1_low_threshold", + "drv_attr_name": "in6_min" + }, + { + "attr_name": "volt1_crit_high_threshold", + "drv_attr_name": "in6_crit" + }, + { + "attr_name": "volt1_crit_low_threshold", + "drv_attr_name": "in6_lcrit" + } + ] + } + }, + "VOLTAGE23": { + "dev_info": { + "device_type": "VOLTAGE_SENSOR", + "device_name": "DPM2-RAIL7", + "device_parent": "MULTIFPGAPCIE0", + "virt_parent": "DPM2" + }, + "dev_attr": { + "display_name": "POS3V3_WEST_DPM2" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "volt1_input", + "drv_attr_name": "in7_input" + }, + { + "attr_name": "volt1_high_threshold", + "drv_attr_name": "in7_max" + }, + { + "attr_name": "volt1_low_threshold", + "drv_attr_name": "in7_min" + }, + { + "attr_name": "volt1_crit_high_threshold", + "drv_attr_name": "in7_crit" + }, + { + "attr_name": "volt1_crit_low_threshold", + "drv_attr_name": "in7_lcrit" + } + ] + } + }, + "VOLTAGE24": { + "dev_info": { + "device_type": "VOLTAGE_SENSOR", + "device_name": "DPM2-RAIL8", + "device_parent": "MULTIFPGAPCIE0", + "virt_parent": "DPM2" + }, + "dev_attr": { + "display_name": "POS3V3_EAST_DPM2" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "volt1_input", + "drv_attr_name": "in8_input" + }, + { + "attr_name": "volt1_high_threshold", + "drv_attr_name": "in8_max" + }, + { + "attr_name": "volt1_low_threshold", + "drv_attr_name": "in8_min" + }, + { + "attr_name": "volt1_crit_high_threshold", + "drv_attr_name": "in8_crit" + }, + { + "attr_name": "volt1_crit_low_threshold", + "drv_attr_name": "in8_lcrit" + } + ] + } + }, + "VOLTAGE25": { + "dev_info": { + "device_type": "VOLTAGE_SENSOR", + "device_name": "DPM2-RAIL9", + "device_parent": "MULTIFPGAPCIE0", + "virt_parent": "DPM2" + }, + "dev_attr": { + "display_name": "POS1V2_DP_DPM2" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "volt1_input", + "drv_attr_name": "in9_input" + }, + { + "attr_name": "volt1_high_threshold", + "drv_attr_name": "in9_max" + }, + { + "attr_name": "volt1_low_threshold", + "drv_attr_name": "in9_min" + }, + { + "attr_name": "volt1_crit_high_threshold", + "drv_attr_name": "in9_crit" + }, + { + "attr_name": "volt1_crit_low_threshold", + "drv_attr_name": "in9_lcrit" + } + ] + } + }, + "VOLTAGE26": { + "dev_info": { + "device_type": "VOLTAGE_SENSOR", + "device_name": "DPM2-RAIL10", + "device_parent": "MULTIFPGAPCIE0", + "virt_parent": "DPM2" + }, + "dev_attr": { + "display_name": "POS1V8_DP" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "volt1_input", + "drv_attr_name": "in10_input" + }, + { + "attr_name": "volt1_high_threshold", + "drv_attr_name": "in10_max" + }, + { + "attr_name": "volt1_low_threshold", + "drv_attr_name": "in10_min" + }, + { + "attr_name": "volt1_crit_high_threshold", + "drv_attr_name": "in10_crit" + }, + { + "attr_name": "volt1_crit_low_threshold", + "drv_attr_name": "in10_lcrit" + } + ] + } + }, + "VOLTAGE27": { + "dev_info": { + "device_type": "VOLTAGE_SENSOR", + "device_name": "DPM2-RAIL11", + "device_parent": "MULTIFPGAPCIE0", + "virt_parent": "DPM2" + }, + "dev_attr": { + "display_name": "POS0V78_VDDC_D0" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "volt1_input", + "drv_attr_name": "in11_input" + }, + { + "attr_name": "volt1_high_threshold", + "drv_attr_name": "in11_max" + }, + { + "attr_name": "volt1_low_threshold", + "drv_attr_name": "in11_min" + }, + { + "attr_name": "volt1_crit_high_threshold", + "drv_attr_name": "in11_crit" + }, + { + "attr_name": "volt1_crit_low_threshold", + "drv_attr_name": "in11_lcrit" + } + ] + } + }, + "VOLTAGE28": { + "dev_info": { + "device_type": "VOLTAGE_SENSOR", + "device_name": "DPM2-RAIL12", + "device_parent": "MULTIFPGAPCIE0", + "virt_parent": "DPM2" + }, + "dev_attr": { + "display_name": "POS0V78_VDDC_D1" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "volt1_input", + "drv_attr_name": "in12_input" + }, + { + "attr_name": "volt1_high_threshold", + "drv_attr_name": "in12_max" + }, + { + "attr_name": "volt1_low_threshold", + "drv_attr_name": "in12_min" + }, + { + "attr_name": "volt1_crit_high_threshold", + "drv_attr_name": "in12_crit" + }, + { + "attr_name": "volt1_crit_low_threshold", + "drv_attr_name": "in12_lcrit" + } + ] + } + }, + "VOLTAGE29": { + "dev_info": { + "device_type": "VOLTAGE_SENSOR", + "device_name": "DPM2-RAIL13", + "device_parent": "MULTIFPGAPCIE0", + "virt_parent": "DPM2" + }, + "dev_attr": { + "display_name": "POS0V75_TRVDD_D0_DPM2" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "volt1_input", + "drv_attr_name": "in13_input" + }, + { + "attr_name": "volt1_high_threshold", + "drv_attr_name": "in13_max" + }, + { + "attr_name": "volt1_low_threshold", + "drv_attr_name": "in13_min" + }, + { + "attr_name": "volt1_crit_high_threshold", + "drv_attr_name": "in13_crit" + }, + { + "attr_name": "volt1_crit_low_threshold", + "drv_attr_name": "in13_lcrit" + } + ] + } + }, + "VOLTAGE30": { + "dev_info": { + "device_type": "VOLTAGE_SENSOR", + "device_name": "DPM2-RAIL14", + "device_parent": "MULTIFPGAPCIE0", + "virt_parent": "DPM2" + }, + "dev_attr": { + "display_name": "POS0V75_TRVDD_D1_DPM2" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "volt1_input", + "drv_attr_name": "in14_input" + }, + { + "attr_name": "volt1_high_threshold", + "drv_attr_name": "in14_max" + }, + { + "attr_name": "volt1_low_threshold", + "drv_attr_name": "in14_min" + }, + { + "attr_name": "volt1_crit_high_threshold", + "drv_attr_name": "in14_crit" + }, + { + "attr_name": "volt1_crit_low_threshold", + "drv_attr_name": "in14_lcrit" + } + ] + } + }, + "VOLTAGE31": { + "dev_info": { + "device_type": "VOLTAGE_SENSOR", + "device_name": "DPM2-RAIL15", + "device_parent": "MULTIFPGAPCIE0", + "virt_parent": "DPM2" + }, + "dev_attr": { + "display_name": "POS0V9_PVDD_WEST" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "volt1_input", + "drv_attr_name": "in15_input" + }, + { + "attr_name": "volt1_high_threshold", + "drv_attr_name": "in15_max" + }, + { + "attr_name": "volt1_low_threshold", + "drv_attr_name": "in15_min" + }, + { + "attr_name": "volt1_crit_high_threshold", + "drv_attr_name": "in15_crit" + }, + { + "attr_name": "volt1_crit_low_threshold", + "drv_attr_name": "in15_lcrit" + } + ] + } + }, + "VOLTAGE32": { + "dev_info": { + "device_type": "VOLTAGE_SENSOR", + "device_name": "DPM2-RAIL16", + "device_parent": "MULTIFPGAPCIE0", + "virt_parent": "DPM2" + }, + "dev_attr": { + "display_name": "POS0V9_PVDD_EAST" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "volt1_input", + "drv_attr_name": "in16_input" + }, + { + "attr_name": "volt1_high_threshold", + "drv_attr_name": "in16_max" + }, + { + "attr_name": "volt1_low_threshold", + "drv_attr_name": "in16_min" + }, + { + "attr_name": "volt1_crit_high_threshold", + "drv_attr_name": "in16_crit" + }, + { + "attr_name": "volt1_crit_low_threshold", + "drv_attr_name": "in16_lcrit" + } + ] + } + }, + "DCDC0": { + "dev_info": { + "device_type": "DCDC", + "device_name": "DCDC0", + "device_parent": "MULTIFPGAPCIE1" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x59", + "dev_addr": "0x68", + "dev_type": "nh_xdpe1a2g5b" + } + } + }, + "DCDC1": { + "dev_info": { + "device_type": "DCDC", + "device_name": "DCDC1", + "device_parent": "MULTIFPGAPCIE1" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x59", + "dev_addr": "0x70", + "dev_type": "nh_xdpe1a2g5b" + } + } + }, + "VOLTAGE33": { + "dev_info": { + "device_type": "VOLTAGE_SENSOR", + "device_name": "DCDC0-RAIL1", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "DCDC0" + }, + "dev_attr": { + "display_name": "POS0V78_ASIC_1" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "volt1_input", + "drv_attr_name": "in3_input" + }, + { + "attr_name": "volt1_high_threshold", + "drv_attr_name": "in3_max" + }, + { + "attr_name": "volt1_low_threshold", + "drv_attr_name": "in3_min" + }, + { + "attr_name": "volt1_crit_high_threshold", + "drv_attr_name": "in3_crit" + }, + { + "attr_name": "volt1_crit_low_threshold", + "drv_attr_name": "in3_lcrit" + } + ] + } + }, + "TEMP17": { + "dev_info": { + "device_type": "TEMP_SENSOR", + "device_name": "DCDC0_TEMP", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent" : "DCDC0" + }, + "dev_attr": { + "display_name": "DCDC0" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "temp1_input", + "drv_attr_name": "temp1_input" + }, + { + "attr_name": "temp1_high_threshold", + "drv_attr_name": "temp1_max" + }, + { + "attr_name": "temp1_high_crit_threshold", + "drv_attr_name": "temp1_crit" + } + ] + } + }, + "VOLTAGE34": { + "dev_info": { + "device_type": "VOLTAGE_SENSOR", + "device_name": "DCDC1-RAIL1", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "DCDC1" + }, + "dev_attr": { + "display_name": "POS0V78_ASIC_2" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "volt1_input", + "drv_attr_name": "in3_input" + }, + { + "attr_name": "volt1_high_threshold", + "drv_attr_name": "in3_max" + }, + { + "attr_name": "volt1_low_threshold", + "drv_attr_name": "in3_min" + }, + { + "attr_name": "volt1_crit_high_threshold", + "drv_attr_name": "in3_crit" + }, + { + "attr_name": "volt1_crit_low_threshold", + "drv_attr_name": "in3_lcrit" + } + ] + } + }, + "TEMP18": { + "dev_info": { + "device_type": "TEMP_SENSOR", + "device_name": "DCDC1_TEMP", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent" : "DCDC1" + }, + "dev_attr": { + "display_name": "DCDC1" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "temp1_input", + "drv_attr_name": "temp1_input" + }, + { + "attr_name": "temp1_high_threshold", + "drv_attr_name": "temp1_max" + }, + { + "attr_name": "temp1_high_crit_threshold", + "drv_attr_name": "temp1_crit" + } + ] + } + }, + "VOLTAGE35": { + "dev_info": { + "device_type": "VOLTAGE_SENSOR", + "device_name": "DPM3-RAIL1", + "device_parent": "MULTIFPGAPCIE0", + "virt_parent": "DPM3" + }, + "dev_attr": { + "display_name": "POS12V0_DPM3" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "volt1_input", + "drv_attr_name": "in1_input" + }, + { + "attr_name": "volt1_high_threshold", + "drv_attr_name": "in1_max" + }, + { + "attr_name": "volt1_low_threshold", + "drv_attr_name": "in1_min" + }, + { + "attr_name": "volt1_crit_high_threshold", + "drv_attr_name": "in1_max_alarm" + }, + { + "attr_name": "volt1_crit_low_threshold", + "drv_attr_name": "in1_min_alarm" + } + ] + } + }, + "VOLTAGE36": { + "dev_info": { + "device_type": "VOLTAGE_SENSOR", + "device_name": "DPM3-RAIL2", + "device_parent": "MULTIFPGAPCIE0", + "virt_parent": "DPM3" + }, + "dev_attr": { + "display_name": "POS5V0_DPM3" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "volt1_input", + "drv_attr_name": "in2_input" + }, + { + "attr_name": "volt1_high_threshold", + "drv_attr_name": "in2_max" + }, + { + "attr_name": "volt1_low_threshold", + "drv_attr_name": "in2_min" + }, + { + "attr_name": "volt1_crit_high_threshold", + "drv_attr_name": "in2_max_alarm" + }, + { + "attr_name": "volt1_crit_low_threshold", + "drv_attr_name": "in2_min_alarm" + } + ] + } + }, + "VOLTAGE37": { + "dev_info": { + "device_type": "VOLTAGE_SENSOR", + "device_name": "DPM3-RAIL3", + "device_parent": "MULTIFPGAPCIE0", + "virt_parent": "DPM3" + }, + "dev_attr": { + "display_name": "POS0V9_TRVDD_D0_DPM3" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "volt1_input", + "drv_attr_name": "in3_input" + }, + { + "attr_name": "volt1_high_threshold", + "drv_attr_name": "in3_max" + }, + { + "attr_name": "volt1_low_threshold", + "drv_attr_name": "in3_min" + }, + { + "attr_name": "volt1_crit_high_threshold", + "drv_attr_name": "in3_max_alarm" + }, + { + "attr_name": "volt1_crit_low_threshold", + "drv_attr_name": "in3_min_alarm" + } + ] + } + }, + "VOLTAGE38": { + "dev_info": { + "device_type": "VOLTAGE_SENSOR", + "device_name": "DPM3-RAIL4", + "device_parent": "MULTIFPGAPCIE0", + "virt_parent": "DPM3" + }, + "dev_attr": { + "display_name": "POS0V9_TRVDD_D1_DPM3" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "volt1_input", + "drv_attr_name": "in4_input" + }, + { + "attr_name": "volt1_high_threshold", + "drv_attr_name": "in4_max" + }, + { + "attr_name": "volt1_low_threshold", + "drv_attr_name": "in4_min" + }, + { + "attr_name": "volt1_crit_high_threshold", + "drv_attr_name": "in4_max_alarm" + }, + { + "attr_name": "volt1_crit_low_threshold", + "drv_attr_name": "in4_min_alarm" + } + ] + } + }, + "VOLTAGE39": { + "dev_info": { + "device_type": "VOLTAGE_SENSOR", + "device_name": "DPM3-RAIL5", + "device_parent": "MULTIFPGAPCIE0", + "virt_parent": "DPM3" + }, + "dev_attr": { + "display_name": "POS0V8_AVDD" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "volt1_input", + "drv_attr_name": "in5_input" + }, + { + "attr_name": "volt1_high_threshold", + "drv_attr_name": "in5_max" + }, + { + "attr_name": "volt1_low_threshold", + "drv_attr_name": "in5_min" + }, + { + "attr_name": "volt1_crit_high_threshold", + "drv_attr_name": "in5_max_alarm" + }, + { + "attr_name": "volt1_crit_low_threshold", + "drv_attr_name": "in5_min_alarm" + } + ] + } + }, + "VOLTAGE40": { + "dev_info": { + "device_type": "VOLTAGE_SENSOR", + "device_name": "DPM3-RAIL6", + "device_parent": "MULTIFPGAPCIE0", + "virt_parent": "DPM3" + }, + "dev_attr": { + "display_name": "POS1V5_APVDD_D0" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "volt1_input", + "drv_attr_name": "in6_input" + }, + { + "attr_name": "volt1_high_threshold", + "drv_attr_name": "in6_max" + }, + { + "attr_name": "volt1_low_threshold", + "drv_attr_name": "in6_min" + }, + { + "attr_name": "volt1_crit_high_threshold", + "drv_attr_name": "in6_max_alarm" + }, + { + "attr_name": "volt1_crit_low_threshold", + "drv_attr_name": "in6_min_alarm" + } + ] + } + }, + "VOLTAGE41": { + "dev_info": { + "device_type": "VOLTAGE_SENSOR", + "device_name": "DPM3-RAIL7", + "device_parent": "MULTIFPGAPCIE0", + "virt_parent": "DPM3" + }, + "dev_attr": { + "display_name": "POS1V5_APVDD_D1" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "volt1_input", + "drv_attr_name": "in7_input" + }, + { + "attr_name": "volt1_high_threshold", + "drv_attr_name": "in7_max" + }, + { + "attr_name": "volt1_low_threshold", + "drv_attr_name": "in7_min" + }, + { + "attr_name": "volt1_crit_high_threshold", + "drv_attr_name": "in7_max_alarm" + }, + { + "attr_name": "volt1_crit_low_threshold", + "drv_attr_name": "in7_min_alarm" + } + ] + } + }, + "VOLTAGE42": { + "dev_info": { + "device_type": "VOLTAGE_SENSOR", + "device_name": "DPM3-RAIL8", + "device_parent": "MULTIFPGAPCIE0", + "virt_parent": "DPM3" + }, + "dev_attr": { + "display_name": "POS1V5_VDDH" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "volt1_input", + "drv_attr_name": "in8_input" + }, + { + "attr_name": "volt1_high_threshold", + "drv_attr_name": "in8_max" + }, + { + "attr_name": "volt1_low_threshold", + "drv_attr_name": "in8_min" + }, + { + "attr_name": "volt1_crit_high_threshold", + "drv_attr_name": "in8_max_alarm" + }, + { + "attr_name": "volt1_crit_low_threshold", + "drv_attr_name": "in8_min_alarm" + } + ] + } + }, + "VOLTAGE43": { + "dev_info": { + "device_type": "VOLTAGE_SENSOR", + "device_name": "DPM3-RAIL9", + "device_parent": "MULTIFPGAPCIE0", + "virt_parent": "DPM3" + }, + "dev_attr": { + "display_name": "POS1V5_PBU_VDDA" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "volt1_input", + "drv_attr_name": "in9_input" + }, + { + "attr_name": "volt1_high_threshold", + "drv_attr_name": "in9_max" + }, + { + "attr_name": "volt1_low_threshold", + "drv_attr_name": "in9_min" + }, + { + "attr_name": "volt1_crit_high_threshold", + "drv_attr_name": "in9_max_alarm" + }, + { + "attr_name": "volt1_crit_low_threshold", + "drv_attr_name": "in9_min_alarm" + } + ] + } + }, + "VOLTAGE44": { + "dev_info": { + "device_type": "VOLTAGE_SENSOR", + "device_name": "DPM3-RAIL10", + "device_parent": "MULTIFPGAPCIE0", + "virt_parent": "DPM3" + }, + "dev_attr": { + "display_name": "POS0V8_PB_VDD_DPM3" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "volt1_input", + "drv_attr_name": "in10_input" + }, + { + "attr_name": "volt1_high_threshold", + "drv_attr_name": "in10_max" + }, + { + "attr_name": "volt1_low_threshold", + "drv_attr_name": "in10_min" + }, + { + "attr_name": "volt1_crit_high_threshold", + "drv_attr_name": "in10_max_alarm" + }, + { + "attr_name": "volt1_crit_low_threshold", + "drv_attr_name": "in10_min_alarm" + } + ] + } + }, + "VOLTAGE45": { + "dev_info": { + "device_type": "VOLTAGE_SENSOR", + "device_name": "DPM3-RAIL11", + "device_parent": "MULTIFPGAPCIE0", + "virt_parent": "DPM3" + }, + "dev_attr": { + "display_name": "POS2V5_HBM_D0" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "volt1_input", + "drv_attr_name": "in11_input" + }, + { + "attr_name": "volt1_high_threshold", + "drv_attr_name": "in11_max" + }, + { + "attr_name": "volt1_low_threshold", + "drv_attr_name": "in11_min" + }, + { + "attr_name": "volt1_crit_high_threshold", + "drv_attr_name": "in11_max_alarm" + }, + { + "attr_name": "volt1_crit_low_threshold", + "drv_attr_name": "in11_min_alarm" + } + ] + } + }, + "VOLTAGE46": { + "dev_info": { + "device_type": "VOLTAGE_SENSOR", + "device_name": "DPM3-RAIL12", + "device_parent": "MULTIFPGAPCIE0", + "virt_parent": "DPM3" + }, + "dev_attr": { + "display_name": "POS2V5_HBM_D1" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "volt1_input", + "drv_attr_name": "in12_input" + }, + { + "attr_name": "volt1_high_threshold", + "drv_attr_name": "in12_max" + }, + { + "attr_name": "volt1_low_threshold", + "drv_attr_name": "in12_min" + }, + { + "attr_name": "volt1_crit_high_threshold", + "drv_attr_name": "in12_max_alarm" + }, + { + "attr_name": "volt1_crit_low_threshold", + "drv_attr_name": "in12_min_alarm" + } + ] + } + }, + "VOLTAGE47": { + "dev_info": { + "device_type": "VOLTAGE_SENSOR", + "device_name": "DPM3-RAIL13", + "device_parent": "MULTIFPGAPCIE0", + "virt_parent": "DPM3" + }, + "dev_attr": { + "display_name": "POS1V2_HBM_D0_DPM3" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "volt1_input", + "drv_attr_name": "in13_input" + }, + { + "attr_name": "volt1_high_threshold", + "drv_attr_name": "in13_max" + }, + { + "attr_name": "volt1_low_threshold", + "drv_attr_name": "in13_min" + }, + { + "attr_name": "volt1_crit_high_threshold", + "drv_attr_name": "in13_max_alarm" + }, + { + "attr_name": "volt1_crit_low_threshold", + "drv_attr_name": "in13_min_alarm" + } + ] + } + }, + "VOLTAGE48": { + "dev_info": { + "device_type": "VOLTAGE_SENSOR", + "device_name": "DPM3-RAIL14", + "device_parent": "MULTIFPGAPCIE0", + "virt_parent": "DPM3" + }, + "dev_attr": { + "display_name": "POS1V2_HBM_D1_DPM3" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "volt1_input", + "drv_attr_name": "in14_input" + }, + { + "attr_name": "volt1_high_threshold", + "drv_attr_name": "in14_max" + }, + { + "attr_name": "volt1_low_threshold", + "drv_attr_name": "in14_min" + }, + { + "attr_name": "volt1_crit_high_threshold", + "drv_attr_name": "in14_max_alarm" + }, + { + "attr_name": "volt1_crit_low_threshold", + "drv_attr_name": "in14_min_alarm" + } + ] + } + }, + "CURRENT1": { + "dev_info": { + "device_type": "CURRENT_SENSOR", + "device_name": "DCDC0-RAIL1", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "DCDC0" + }, + "dev_attr": { + "display_name": "POS0V78_ASIC_1" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "current1_input", + "drv_attr_name": "curr3_input" + }, + { + "attr_name": "current1_high_threshold", + "drv_attr_name": "curr3_max" + }, + { + "attr_name": "current1_crit_high_threshold", + "drv_attr_name": "curr3_crit" + } + ] + } + }, + "CURRENT2": { + "dev_info": { + "device_type": "CURRENT_SENSOR", + "device_name": "DCDC1-RAIL1", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "DCDC1" + }, + "dev_attr": { + "display_name": "POS0V78_ASIC_2" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "current1_input", + "drv_attr_name": "curr3_input" + }, + { + "attr_name": "current1_high_threshold", + "drv_attr_name": "curr3_max" + }, + { + "attr_name": "current1_crit_high_threshold", + "drv_attr_name": "curr3_crit" + } + ] + } + }, + "DCDC2": { + "dev_info": { + "device_type": "DCDC", + "device_name": "DCDC2", + "device_parent": "MULTIFPGAPCIE1" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x5a", + "dev_addr": "0x60", + "dev_type": "nh_raa228234" + } + } + }, + "DCDC3": { + "dev_info": { + "device_type": "DCDC", + "device_name": "DCDC3", + "device_parent": "MULTIFPGAPCIE1" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x5a", + "dev_addr": "0x61", + "dev_type": "nh_raa228234" + } + } + }, + "DCDC4": { + "dev_info": { + "device_type": "DCDC", + "device_name": "DCDC4", + "device_parent": "MULTIFPGAPCIE1" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x5a", + "dev_addr": "0x72", + "dev_type": "nh_raa228234" + } + } + }, + "DCDC5": { + "dev_info": { + "device_type": "DCDC", + "device_name": "DCDC5", + "device_parent": "MULTIFPGAPCIE1" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x5a", + "dev_addr": "0x75", + "dev_type": "nh_raa228234" + } + } + }, + "DCDC6": { + "dev_info": { + "device_type": "DCDC", + "device_name": "DCDC6", + "device_parent": "MULTIFPGAPCIE1" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x5a", + "dev_addr": "0x76", + "dev_type": "nh_raa228234" + } + } + }, + "VOLTAGE49": { + "dev_info": { + "device_type": "VOLTAGE_SENSOR", + "device_name": "DCDC2-RAIL1", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "DCDC2" + }, + "dev_attr": { + "display_name": "POS0V9_TRVDD_D0" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "volt1_input", + "drv_attr_name": "in3_input" + }, + { + "attr_name": "volt1_high_threshold", + "drv_attr_name": "in3_max" + }, + { + "attr_name": "volt1_low_threshold", + "drv_attr_name": "in3_min" + }, + { + "attr_name": "volt1_crit_high_threshold", + "drv_attr_name": "in3_crit" + }, + { + "attr_name": "volt1_crit_low_threshold", + "drv_attr_name": "in3_lcrit" + } + ] + } + }, + "VOLTAGE50": { + "dev_info": { + "device_type": "VOLTAGE_SENSOR", + "device_name": "DCDC2-RAIL2", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "DCDC2" + }, + "dev_attr": { + "display_name": "POS0V75_TRVDD_D0" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "volt1_input", + "drv_attr_name": "in4_input" + }, + { + "attr_name": "volt1_high_threshold", + "drv_attr_name": "in4_max" + }, + { + "attr_name": "volt1_low_threshold", + "drv_attr_name": "in4_min" + }, + { + "attr_name": "volt1_crit_high_threshold", + "drv_attr_name": "in4_crit" + }, + { + "attr_name": "volt1_crit_low_threshold", + "drv_attr_name": "in4_lcrit" + } + ] + } + }, + "CURRENT3": { + "dev_info": { + "device_type": "CURRENT_SENSOR", + "device_name": "DCDC2-RAIL1", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "DCDC2" + }, + "dev_attr": { + "display_name": "POS0V9_TRVDD_D0" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "current1_input", + "drv_attr_name": "curr3_input" + }, + { + "attr_name": "current1_high_threshold", + "drv_attr_name": "curr3_max" + }, + { + "attr_name": "current1_crit_high_threshold", + "drv_attr_name": "curr3_crit" + } + ] + } + }, + "CURRENT4": { + "dev_info": { + "device_type": "CURRENT_SENSOR", + "device_name": "DCDC2-RAIL2", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "DCDC2" + }, + "dev_attr": { + "display_name": "POS0V75_TRVDD_D0" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "current1_input", + "drv_attr_name": "curr4_input" + }, + { + "attr_name": "current1_high_threshold", + "drv_attr_name": "curr4_max" + }, + { + "attr_name": "current1_crit_high_threshold", + "drv_attr_name": "curr4_crit" + } + ] + } + }, + "TEMP19": { + "dev_info": { + "device_type": "TEMP_SENSOR", + "device_name": "DCDC2_TEMP", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent" : "DCDC2" + }, + "dev_attr": { + "display_name": "DCDC2" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "temp1_input", + "drv_attr_name": "temp1_input" + }, + { + "attr_name": "temp1_high_threshold", + "drv_attr_name": "temp1_max" + }, + { + "attr_name": "temp1_high_crit_threshold", + "drv_attr_name": "temp1_crit" + } + ] + } + }, + "VOLTAGE51": { + "dev_info": { + "device_type": "VOLTAGE_SENSOR", + "device_name": "DCDC3-RAIL1", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "DCDC3" + }, + "dev_attr": { + "display_name": "POS0V9_TRVDD_D1" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "volt1_input", + "drv_attr_name": "in3_input" + }, + { + "attr_name": "volt1_high_threshold", + "drv_attr_name": "in3_max" + }, + { + "attr_name": "volt1_low_threshold", + "drv_attr_name": "in3_min" + }, + { + "attr_name": "volt1_crit_high_threshold", + "drv_attr_name": "in3_crit" + }, + { + "attr_name": "volt1_crit_low_threshold", + "drv_attr_name": "in3_lcrit" + } + ] + } + }, + "VOLTAGE52": { + "dev_info": { + "device_type": "VOLTAGE_SENSOR", + "device_name": "DCDC3-RAIL2", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "DCDC3" + }, + "dev_attr": { + "display_name": "POS0V75_TRVDD_D1" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "volt1_input", + "drv_attr_name": "in4_input" + }, + { + "attr_name": "volt1_high_threshold", + "drv_attr_name": "in4_max" + }, + { + "attr_name": "volt1_low_threshold", + "drv_attr_name": "in4_min" + }, + { + "attr_name": "volt1_crit_high_threshold", + "drv_attr_name": "in4_crit" + }, + { + "attr_name": "volt1_crit_low_threshold", + "drv_attr_name": "in4_lcrit" + } + ] + } + }, + "CURRENT5": { + "dev_info": { + "device_type": "CURRENT_SENSOR", + "device_name": "DCDC3-RAIL1", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "DCDC3" + }, + "dev_attr": { + "display_name": "POS0V9_TRVDD_D1" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "current1_input", + "drv_attr_name": "curr3_input" + }, + { + "attr_name": "current1_high_threshold", + "drv_attr_name": "curr3_max" + }, + { + "attr_name": "current1_crit_high_threshold", + "drv_attr_name": "curr3_crit" + } + ] + } + }, + "CURRENT6": { + "dev_info": { + "device_type": "CURRENT_SENSOR", + "device_name": "DCDC3-RAIL2", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "DCDC3" + }, + "dev_attr": { + "display_name": "POS0V75_TRVDD_D1" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "current1_input", + "drv_attr_name": "curr4_input" + }, + { + "attr_name": "current1_high_threshold", + "drv_attr_name": "curr4_max" + }, + { + "attr_name": "current1_crit_high_threshold", + "drv_attr_name": "curr4_crit" + } + ] + } + }, + "TEMP20": { + "dev_info": { + "device_type": "TEMP_SENSOR", + "device_name": "DCDC3_TEMP", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent" : "DCDC3" + }, + "dev_attr": { + "display_name": "DCDC3" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "temp1_input", + "drv_attr_name": "temp1_input" + }, + { + "attr_name": "temp1_high_threshold", + "drv_attr_name": "temp1_max" + }, + { + "attr_name": "temp1_high_crit_threshold", + "drv_attr_name": "temp1_crit" + } + ] + } + }, + "VOLTAGE53": { + "dev_info": { + "device_type": "VOLTAGE_SENSOR", + "device_name": "DCDC4-RAIL1", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "DCDC4" + }, + "dev_attr": { + "display_name": "POS3V3_WEST" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "volt1_input", + "drv_attr_name": "in3_input" + }, + { + "attr_name": "volt1_high_threshold", + "drv_attr_name": "in3_max" + }, + { + "attr_name": "volt1_low_threshold", + "drv_attr_name": "in3_min" + }, + { + "attr_name": "volt1_crit_high_threshold", + "drv_attr_name": "in3_crit" + }, + { + "attr_name": "volt1_crit_low_threshold", + "drv_attr_name": "in3_lcrit" + } + ] + } + }, + "VOLTAGE54": { + "dev_info": { + "device_type": "VOLTAGE_SENSOR", + "device_name": "DCDC4-RAIL2", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "DCDC4" + }, + "dev_attr": { + "display_name": "POS1V2_HBM_D0" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "volt1_input", + "drv_attr_name": "in4_input" + }, + { + "attr_name": "volt1_high_threshold", + "drv_attr_name": "in4_max" + }, + { + "attr_name": "volt1_low_threshold", + "drv_attr_name": "in4_min" + }, + { + "attr_name": "volt1_crit_high_threshold", + "drv_attr_name": "in4_crit" + }, + { + "attr_name": "volt1_crit_low_threshold", + "drv_attr_name": "in4_lcrit" + } + ] + } + }, + "CURRENT7": { + "dev_info": { + "device_type": "CURRENT_SENSOR", + "device_name": "DCDC4-RAIL1", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "DCDC4" + }, + "dev_attr": { + "display_name": "POS3V3_WEST" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "current1_input", + "drv_attr_name": "curr3_input" + }, + { + "attr_name": "current1_high_threshold", + "drv_attr_name": "curr3_max" + }, + { + "attr_name": "current1_crit_high_threshold", + "drv_attr_name": "curr3_crit" + } + ] + } + }, + "CURRENT8": { + "dev_info": { + "device_type": "CURRENT_SENSOR", + "device_name": "DCDC4-RAIL2", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "DCDC4" + }, + "dev_attr": { + "display_name": "POS1V2_HBM_D0" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "current1_input", + "drv_attr_name": "curr4_input" + }, + { + "attr_name": "current1_high_threshold", + "drv_attr_name": "curr4_max" + }, + { + "attr_name": "current1_crit_high_threshold", + "drv_attr_name": "curr4_crit" + } + ] + } + }, + "TEMP21": { + "dev_info": { + "device_type": "TEMP_SENSOR", + "device_name": "DCDC4_TEMP", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent" : "DCDC4" + }, + "dev_attr": { + "display_name": "DCDC4" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "temp1_input", + "drv_attr_name": "temp1_input" + }, + { + "attr_name": "temp1_high_threshold", + "drv_attr_name": "temp1_max" + }, + { + "attr_name": "temp1_high_crit_threshold", + "drv_attr_name": "temp1_crit" + } + ] + } + }, + "VOLTAGE55": { + "dev_info": { + "device_type": "VOLTAGE_SENSOR", + "device_name": "DCDC5-RAIL1", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "DCDC5" + }, + "dev_attr": { + "display_name": "POS3V3_EAST" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "volt1_input", + "drv_attr_name": "in3_input" + }, + { + "attr_name": "volt1_high_threshold", + "drv_attr_name": "in3_max" + }, + { + "attr_name": "volt1_low_threshold", + "drv_attr_name": "in3_min" + }, + { + "attr_name": "volt1_crit_high_threshold", + "drv_attr_name": "in3_crit" + }, + { + "attr_name": "volt1_crit_low_threshold", + "drv_attr_name": "in3_lcrit" + } + ] + } + }, + "VOLTAGE56": { + "dev_info": { + "device_type": "VOLTAGE_SENSOR", + "device_name": "DCDC5-RAIL2", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "DCDC5" + }, + "dev_attr": { + "display_name": "POS1V2_HBM_D1" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "volt1_input", + "drv_attr_name": "in4_input" + }, + { + "attr_name": "volt1_high_threshold", + "drv_attr_name": "in4_max" + }, + { + "attr_name": "volt1_low_threshold", + "drv_attr_name": "in4_min" + }, + { + "attr_name": "volt1_crit_high_threshold", + "drv_attr_name": "in4_crit" + }, + { + "attr_name": "volt1_crit_low_threshold", + "drv_attr_name": "in4_lcrit" + } + ] + } + }, + "CURRENT9": { + "dev_info": { + "device_type": "CURRENT_SENSOR", + "device_name": "DCDC5-RAIL1", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "DCDC5" + }, + "dev_attr": { + "display_name": "POS3V3_EAST" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "current1_input", + "drv_attr_name": "curr3_input" + }, + { + "attr_name": "current1_high_threshold", + "drv_attr_name": "curr3_max" + }, + { + "attr_name": "current1_crit_high_threshold", + "drv_attr_name": "curr3_crit" + } + ] + } + }, + "CURRENT10": { + "dev_info": { + "device_type": "CURRENT_SENSOR", + "device_name": "DCDC5-RAIL2", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "DCDC5" + }, + "dev_attr": { + "display_name": "POS1V2_HBM_D1" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "current1_input", + "drv_attr_name": "curr4_input" + }, + { + "attr_name": "current1_high_threshold", + "drv_attr_name": "curr4_max" + }, + { + "attr_name": "current1_crit_high_threshold", + "drv_attr_name": "curr4_crit" + } + ] + } + }, + "TEMP22": { + "dev_info": { + "device_type": "TEMP_SENSOR", + "device_name": "DCDC5_TEMP", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent" : "DCDC5" + }, + "dev_attr": { + "display_name": "DCDC5" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "temp1_input", + "drv_attr_name": "temp1_input" + }, + { + "attr_name": "temp1_high_threshold", + "drv_attr_name": "temp1_max" + }, + { + "attr_name": "temp1_high_crit_threshold", + "drv_attr_name": "temp1_crit" + } + ] + } + }, + "VOLTAGE57": { + "dev_info": { + "device_type": "VOLTAGE_SENSOR", + "device_name": "DCDC6-RAIL1", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "DCDC6" + }, + "dev_attr": { + "display_name": "POS0V8_PB_VDD" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "volt1_input", + "drv_attr_name": "in3_input" + }, + { + "attr_name": "volt1_high_threshold", + "drv_attr_name": "in3_max" + }, + { + "attr_name": "volt1_low_threshold", + "drv_attr_name": "in3_min" + }, + { + "attr_name": "volt1_crit_high_threshold", + "drv_attr_name": "in3_crit" + }, + { + "attr_name": "volt1_crit_low_threshold", + "drv_attr_name": "in3_lcrit" + } + ] + } + }, + "VOLTAGE58": { + "dev_info": { + "device_type": "VOLTAGE_SENSOR", + "device_name": "DCDC6-RAIL2", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "DCDC6" + }, + "dev_attr": { + "display_name": "POS1V2_DP" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "volt1_input", + "drv_attr_name": "in4_input" + }, + { + "attr_name": "volt1_high_threshold", + "drv_attr_name": "in4_max" + }, + { + "attr_name": "volt1_low_threshold", + "drv_attr_name": "in4_min" + }, + { + "attr_name": "volt1_crit_high_threshold", + "drv_attr_name": "in4_crit" + }, + { + "attr_name": "volt1_crit_low_threshold", + "drv_attr_name": "in4_lcrit" + } + ] + } + }, + "CURRENT11": { + "dev_info": { + "device_type": "CURRENT_SENSOR", + "device_name": "DCDC6-RAIL1", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "DCDC6" + }, + "dev_attr": { + "display_name": "POS0V8_PB_VDD" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "current1_input", + "drv_attr_name": "curr3_input" + }, + { + "attr_name": "current1_high_threshold", + "drv_attr_name": "curr3_max" + }, + { + "attr_name": "current1_crit_high_threshold", + "drv_attr_name": "curr3_crit" + } + ] + } + }, + "CURRENT12": { + "dev_info": { + "device_type": "CURRENT_SENSOR", + "device_name": "DCDC6-RAIL2", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "DCDC6" + }, + "dev_attr": { + "display_name": "POS1V2_DP" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "current1_input", + "drv_attr_name": "curr4_input" + }, + { + "attr_name": "current1_high_threshold", + "drv_attr_name": "curr4_max" + }, + { + "attr_name": "current1_crit_high_threshold", + "drv_attr_name": "curr4_crit" + } + ] + } + }, + "TEMP23": { + "dev_info": { + "device_type": "TEMP_SENSOR", + "device_name": "DCDC6_TEMP", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent" : "DCDC6" + }, + "dev_attr": { + "display_name": "DCDC6" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "temp1_input", + "drv_attr_name": "temp1_input" + }, + { + "attr_name": "temp1_high_threshold", + "drv_attr_name": "temp1_max" + }, + { + "attr_name": "temp1_high_crit_threshold", + "drv_attr_name": "temp1_crit" + } + ] + } + }, + "TEMP24": { + "dev_info": { + "device_type": "TEMP_SENSOR", + "device_name": "TMP464-CH1", + "device_parent": "MULTIFPGAPCIE0", + "virt_parent": "TMP464" + }, + "dev_attr": { + "display_name": "Mezz Card Left Rear" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "temp1_input", + "drv_attr_name": "temp1_input" + }, + { + "attr_name": "temp1_high_threshold", + "drv_attr_name": "temp1_max" + }, + { + "attr_name": "temp1_high_crit_threshold", + "drv_attr_name": "temp1_crit" + } + ] + } + }, + "TEMP25": { + "dev_info": { + "device_type": "TEMP_SENSOR", + "device_name": "TMP464-CH2", + "device_parent": "MULTIFPGAPCIE0", + "virt_parent": "TMP464" + }, + "dev_attr": { + "display_name": "Left Upper Port Side Intake" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "temp1_input", + "drv_attr_name": "temp2_input" + }, + { + "attr_name": "temp1_high_threshold", + "drv_attr_name": "temp2_max" + }, + { + "attr_name": "temp1_high_crit_threshold", + "drv_attr_name": "temp2_crit" + } + ] + } + }, + "TEMP26": { + "dev_info": { + "device_type": "TEMP_SENSOR", + "device_name": "TMP464-CH3", + "device_parent": "MULTIFPGAPCIE0", + "virt_parent": "TMP464" + }, + "dev_attr": { + "display_name": "Mezz Card Right Rear" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "temp1_input", + "drv_attr_name": "temp3_input" + }, + { + "attr_name": "temp1_high_threshold", + "drv_attr_name": "temp3_max" + }, + { + "attr_name": "temp1_high_crit_threshold", + "drv_attr_name": "temp3_crit" + } + ] + } + }, + "TEMP27": { + "dev_info": { + "device_type": "TEMP_SENSOR", + "device_name": "TMP464-CH4", + "device_parent": "MULTIFPGAPCIE0", + "virt_parent": "TMP464" + }, + "dev_attr": { + "display_name": "Right Upper Port Side Intake" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "temp1_input", + "drv_attr_name": "temp4_input" + }, + { + "attr_name": "temp1_high_threshold", + "drv_attr_name": "temp4_max" + }, + { + "attr_name": "temp1_high_crit_threshold", + "drv_attr_name": "temp4_crit" + } + ] + } + }, + "VOLTAGE59": { + "dev_info": { + "device_type": "VOLTAGE_SENSOR", + "device_name": "DPM4-RAIL1", + "device_parent": "MULTIFPGAPCIE0", + "virt_parent": "DPM4" + }, + "dev_attr": { + "display_name": "POS12V0_DPM4" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "volt1_input", + "drv_attr_name": "in1_input" + }, + { + "attr_name": "volt1_high_threshold", + "drv_attr_name": "in1_max" + }, + { + "attr_name": "volt1_low_threshold", + "drv_attr_name": "in1_min" + }, + { + "attr_name": "volt1_crit_high_threshold", + "drv_attr_name": "in1_crit" + }, + { + "attr_name": "volt1_crit_low_threshold", + "drv_attr_name": "in1_lcrit" + } + ] + } + }, + "VOLTAGE60": { + "dev_info": { + "device_type": "VOLTAGE_SENSOR", + "device_name": "DPM4-RAIL2", + "device_parent": "MULTIFPGAPCIE0", + "virt_parent": "DPM4" + }, + "dev_attr": { + "display_name": "POS5V0_DPM4" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "volt1_input", + "drv_attr_name": "in2_input" + }, + { + "attr_name": "volt1_high_threshold", + "drv_attr_name": "in2_max" + }, + { + "attr_name": "volt1_low_threshold", + "drv_attr_name": "in2_min" + }, + { + "attr_name": "volt1_crit_high_threshold", + "drv_attr_name": "in2_crit" + }, + { + "attr_name": "volt1_crit_low_threshold", + "drv_attr_name": "in2_lcrit" + } + ] + } + }, + "VOLTAGE61": { + "dev_info": { + "device_type": "VOLTAGE_SENSOR", + "device_name": "DPM4-RAIL3", + "device_parent": "MULTIFPGAPCIE0", + "virt_parent": "DPM4" + }, + "dev_attr": { + "display_name": "POS1V0_FPGA_MC" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "volt1_input", + "drv_attr_name": "in3_input" + }, + { + "attr_name": "volt1_high_threshold", + "drv_attr_name": "in3_max" + }, + { + "attr_name": "volt1_low_threshold", + "drv_attr_name": "in3_min" + }, + { + "attr_name": "volt1_crit_high_threshold", + "drv_attr_name": "in3_max_alarm" + }, + { + "attr_name": "volt1_crit_low_threshold", + "drv_attr_name": "in3_min_alarm" + } + ] + } + }, + "VOLTAGE62": { + "dev_info": { + "device_type": "VOLTAGE_SENSOR", + "device_name": "DPM4-RAIL4", + "device_parent": "MULTIFPGAPCIE0", + "virt_parent": "DPM4" + }, + "dev_attr": { + "display_name": "POS1V8_FPGA_MC" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "volt1_input", + "drv_attr_name": "in4_input" + }, + { + "attr_name": "volt1_high_threshold", + "drv_attr_name": "in4_max" + }, + { + "attr_name": "volt1_low_threshold", + "drv_attr_name": "in4_min" + }, + { + "attr_name": "volt1_crit_high_threshold", + "drv_attr_name": "in4_crit" + }, + { + "attr_name": "volt1_crit_low_threshold", + "drv_attr_name": "in4_lcrit" + } + ] + } + }, + "VOLTAGE63": { + "dev_info": { + "device_type": "VOLTAGE_SENSOR", + "device_name": "DPM4-RAIL5", + "device_parent": "MULTIFPGAPCIE0", + "virt_parent": "DPM4" + }, + "dev_attr": { + "display_name": "POS1V2_FPGA_MC" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "volt1_input", + "drv_attr_name": "in5_input" + }, + { + "attr_name": "volt1_high_threshold", + "drv_attr_name": "in5_max" + }, + { + "attr_name": "volt1_low_threshold", + "drv_attr_name": "in5_min" + }, + { + "attr_name": "volt1_crit_high_threshold", + "drv_attr_name": "in5_crit" + }, + { + "attr_name": "volt1_crit_low_threshold", + "drv_attr_name": "in5_lcrit" + } + ] + } + }, + "VOLTAGE64": { + "dev_info": { + "device_type": "VOLTAGE_SENSOR", + "device_name": "DPM4-RAIL6", + "device_parent": "MULTIFPGAPCIE0", + "virt_parent": "DPM4" + }, + "dev_attr": { + "display_name": "POS3V3_FPGA_MC" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "volt1_input", + "drv_attr_name": "in6_input" + }, + { + "attr_name": "volt1_high_threshold", + "drv_attr_name": "in6_max" + }, + { + "attr_name": "volt1_low_threshold", + "drv_attr_name": "in6_min" + }, + { + "attr_name": "volt1_crit_high_threshold", + "drv_attr_name": "in6_crit" + }, + { + "attr_name": "volt1_crit_low_threshold", + "drv_attr_name": "in6_lcrit" + } + ] + } + }, + "VOLTAGE65": { + "dev_info": { + "device_type": "VOLTAGE_SENSOR", + "device_name": "DPM4-RAIL7", + "device_parent": "MULTIFPGAPCIE0", + "virt_parent": "DPM4" + }, + "dev_attr": { + "display_name": "POS3V3_WEST_MC_DPM4" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "volt1_input", + "drv_attr_name": "in7_input" + }, + { + "attr_name": "volt1_high_threshold", + "drv_attr_name": "in7_max" + }, + { + "attr_name": "volt1_low_threshold", + "drv_attr_name": "in7_min" + }, + { + "attr_name": "volt1_crit_high_threshold", + "drv_attr_name": "in7_crit" + }, + { + "attr_name": "volt1_crit_low_threshold", + "drv_attr_name": "in7_lcrit" + } + ] + } + }, + "VOLTAGE66": { + "dev_info": { + "device_type": "VOLTAGE_SENSOR", + "device_name": "DPM4-RAIL8", + "device_parent": "MULTIFPGAPCIE0", + "virt_parent": "DPM4" + }, + "dev_attr": { + "display_name": "POS3V3_EAST_MC_DPM4" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "volt1_input", + "drv_attr_name": "in8_input" + }, + { + "attr_name": "volt1_high_threshold", + "drv_attr_name": "in8_max" + }, + { + "attr_name": "volt1_low_threshold", + "drv_attr_name": "in8_min" + }, + { + "attr_name": "volt1_crit_high_threshold", + "drv_attr_name": "in8_crit" + }, + { + "attr_name": "volt1_crit_low_threshold", + "drv_attr_name": "in8_lcrit" + } + ] + } + }, + "VOLTAGE67": { + "dev_info": { + "device_type": "VOLTAGE_SENSOR", + "device_name": "DPM4-RAIL9", + "device_parent": "MULTIFPGAPCIE0", + "virt_parent": "DPM4" + }, + "dev_attr": { + "display_name": "POS1V5_VDDIOL" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "volt1_input", + "drv_attr_name": "in9_input" + }, + { + "attr_name": "volt1_high_threshold", + "drv_attr_name": "in9_max" + }, + { + "attr_name": "volt1_low_threshold", + "drv_attr_name": "in9_min" + }, + { + "attr_name": "volt1_crit_high_threshold", + "drv_attr_name": "in9_crit" + }, + { + "attr_name": "volt1_crit_low_threshold", + "drv_attr_name": "in9_lcrit" + } + ] + } + }, + "VOLTAGE68": { + "dev_info": { + "device_type": "VOLTAGE_SENSOR", + "device_name": "DPM4-RAIL10", + "device_parent": "MULTIFPGAPCIE0", + "virt_parent": "DPM4" + }, + "dev_attr": { + "display_name": "POS1V8_VDDIO" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "volt1_input", + "drv_attr_name": "in10_input" + }, + { + "attr_name": "volt1_high_threshold", + "drv_attr_name": "in10_max" + }, + { + "attr_name": "volt1_low_threshold", + "drv_attr_name": "in10_min" + }, + { + "attr_name": "volt1_crit_high_threshold", + "drv_attr_name": "in10_crit" + }, + { + "attr_name": "volt1_crit_low_threshold", + "drv_attr_name": "in10_lcrit" + } + ] + } + }, + "VOLTAGE69": { + "dev_info": { + "device_type": "VOLTAGE_SENSOR", + "device_name": "DPM4-RAIL11", + "device_parent": "MULTIFPGAPCIE0", + "virt_parent": "DPM4" + }, + "dev_attr": { + "display_name": "POS0V75_DVDD_WEST_MC_DPM4" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "volt1_input", + "drv_attr_name": "in11_input" + }, + { + "attr_name": "volt1_high_threshold", + "drv_attr_name": "in11_max" + }, + { + "attr_name": "volt1_low_threshold", + "drv_attr_name": "in11_min" + }, + { + "attr_name": "volt1_crit_high_threshold", + "drv_attr_name": "in11_crit" + }, + { + "attr_name": "volt1_crit_low_threshold", + "drv_attr_name": "in11_lcrit" + } + ] + } + }, + "VOLTAGE70": { + "dev_info": { + "device_type": "VOLTAGE_SENSOR", + "device_name": "DPM4-RAIL12", + "device_parent": "MULTIFPGAPCIE0", + "virt_parent": "DPM4" + }, + "dev_attr": { + "display_name": "POS0V75_DVDD_EAST_MC_DPM4" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "volt1_input", + "drv_attr_name": "in12_input" + }, + { + "attr_name": "volt1_high_threshold", + "drv_attr_name": "in12_max" + }, + { + "attr_name": "volt1_low_threshold", + "drv_attr_name": "in12_min" + }, + { + "attr_name": "volt1_crit_high_threshold", + "drv_attr_name": "in12_crit" + }, + { + "attr_name": "volt1_crit_low_threshold", + "drv_attr_name": "in12_lcrit" + } + ] + } + }, + "VOLTAGE71": { + "dev_info": { + "device_type": "VOLTAGE_SENSOR", + "device_name": "DPM4-RAIL13", + "device_parent": "MULTIFPGAPCIE0", + "virt_parent": "DPM4" + }, + "dev_attr": { + "display_name": "POS0V75_AVDDL_WEST_MC_DPM4" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "volt1_input", + "drv_attr_name": "in13_input" + }, + { + "attr_name": "volt1_high_threshold", + "drv_attr_name": "in13_max" + }, + { + "attr_name": "volt1_low_threshold", + "drv_attr_name": "in13_min" + }, + { + "attr_name": "volt1_crit_high_threshold", + "drv_attr_name": "in13_crit" + }, + { + "attr_name": "volt1_crit_low_threshold", + "drv_attr_name": "in13_lcrit" + } + ] + } + }, + "VOLTAGE72": { + "dev_info": { + "device_type": "VOLTAGE_SENSOR", + "device_name": "DPM4-RAIL14", + "device_parent": "MULTIFPGAPCIE0", + "virt_parent": "DPM4" + }, + "dev_attr": { + "display_name": "POS0V75_AVDDL_EAST_MC_DPM4" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "volt1_input", + "drv_attr_name": "in14_input" + }, + { + "attr_name": "volt1_high_threshold", + "drv_attr_name": "in14_max" + }, + { + "attr_name": "volt1_low_threshold", + "drv_attr_name": "in14_min" + }, + { + "attr_name": "volt1_crit_high_threshold", + "drv_attr_name": "in14_crit" + }, + { + "attr_name": "volt1_crit_low_threshold", + "drv_attr_name": "in14_lcrit" + } + ] + } + }, + "VOLTAGE73": { + "dev_info": { + "device_type": "VOLTAGE_SENSOR", + "device_name": "DPM4-RAIL15", + "device_parent": "MULTIFPGAPCIE0", + "virt_parent": "DPM4" + }, + "dev_attr": { + "display_name": "POS0V9_AVDDH_WEST_MC_DPM4" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "volt1_input", + "drv_attr_name": "in15_input" + }, + { + "attr_name": "volt1_high_threshold", + "drv_attr_name": "in15_max" + }, + { + "attr_name": "volt1_low_threshold", + "drv_attr_name": "in15_min" + }, + { + "attr_name": "volt1_crit_high_threshold", + "drv_attr_name": "in15_crit" + }, + { + "attr_name": "volt1_crit_low_threshold", + "drv_attr_name": "in15_lcrit" + } + ] + } + }, + "VOLTAGE74": { + "dev_info": { + "device_type": "VOLTAGE_SENSOR", + "device_name": "DPM4-RAIL16", + "device_parent": "MULTIFPGAPCIE0", + "virt_parent": "DPM4" + }, + "dev_attr": { + "display_name": "POS0V9_AVDDH_EAST_MC_DPM4" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "volt1_input", + "drv_attr_name": "in16_input" + }, + { + "attr_name": "volt1_high_threshold", + "drv_attr_name": "in16_max" + }, + { + "attr_name": "volt1_low_threshold", + "drv_attr_name": "in16_min" + }, + { + "attr_name": "volt1_crit_high_threshold", + "drv_attr_name": "in16_crit" + }, + { + "attr_name": "volt1_crit_low_threshold", + "drv_attr_name": "in16_lcrit" + } + ] + } + }, + "DCDC7": { + "dev_info": { + "device_type": "DCDC", + "device_name": "DCDC7", + "device_parent": "MULTIFPGAPCIE1" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x5e", + "dev_addr": "0x60", + "dev_type": "nh_raa228234" + } + } + }, + "VOLTAGE75": { + "dev_info": { + "device_type": "VOLTAGE_SENSOR", + "device_name": "DCDC7-RAIL1", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "DCDC7" + }, + "dev_attr": { + "display_name": "POS0V75_DVDD_WEST_MC" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "volt1_input", + "drv_attr_name": "in3_input" + }, + { + "attr_name": "volt1_high_threshold", + "drv_attr_name": "in3_max" + }, + { + "attr_name": "volt1_low_threshold", + "drv_attr_name": "in3_min" + }, + { + "attr_name": "volt1_crit_high_threshold", + "drv_attr_name": "in3_crit" + }, + { + "attr_name": "volt1_crit_low_threshold", + "drv_attr_name": "in3_lcrit" + } + ] + } + }, + "VOLTAGE76": { + "dev_info": { + "device_type": "VOLTAGE_SENSOR", + "device_name": "DCDC7-RAIL2", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "DCDC7" + }, + "dev_attr": { + "display_name": "POS0V75_AVDDL_WEST_MC" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "volt1_input", + "drv_attr_name": "in4_input" + }, + { + "attr_name": "volt1_high_threshold", + "drv_attr_name": "in4_max" + }, + { + "attr_name": "volt1_low_threshold", + "drv_attr_name": "in4_min" + }, + { + "attr_name": "volt1_crit_high_threshold", + "drv_attr_name": "in4_crit" + }, + { + "attr_name": "volt1_crit_low_threshold", + "drv_attr_name": "in4_lcrit" + } + ] + } + }, + "CURRENT13": { + "dev_info": { + "device_type": "CURRENT_SENSOR", + "device_name": "DCDC7-RAIL1", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "DCDC7" + }, + "dev_attr": { + "display_name": "POS0V75_DVDD_WEST_MC" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "current1_input", + "drv_attr_name": "curr3_input" + }, + { + "attr_name": "current1_high_threshold", + "drv_attr_name": "curr3_max" + }, + { + "attr_name": "current1_crit_high_threshold", + "drv_attr_name": "curr3_crit" + } + ] + } + }, + "CURRENT14": { + "dev_info": { + "device_type": "CURRENT_SENSOR", + "device_name": "DCDC7-RAIL2", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "DCDC7" + }, + "dev_attr": { + "display_name": "POS0V75_AVDDL_WEST_MC" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "current1_input", + "drv_attr_name": "curr4_input" + }, + { + "attr_name": "current1_high_threshold", + "drv_attr_name": "curr4_max" + }, + { + "attr_name": "current1_crit_high_threshold", + "drv_attr_name": "curr4_crit" + } + ] + } + }, + "DCDC8": { + "dev_info": { + "device_type": "DCDC", + "device_name": "DCDC8", + "device_parent": "MULTIFPGAPCIE1" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x5e", + "dev_addr": "0x61", + "dev_type": "nh_raa228234" + } + } + }, + "VOLTAGE77": { + "dev_info": { + "device_type": "VOLTAGE_SENSOR", + "device_name": "DCDC8-RAIL1", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "DCDC8" + }, + "dev_attr": { + "display_name": "POS0V75_DVDD_EAST_MC" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "volt1_input", + "drv_attr_name": "in3_input" + }, + { + "attr_name": "volt1_high_threshold", + "drv_attr_name": "in3_max" + }, + { + "attr_name": "volt1_low_threshold", + "drv_attr_name": "in3_min" + }, + { + "attr_name": "volt1_crit_high_threshold", + "drv_attr_name": "in3_crit" + }, + { + "attr_name": "volt1_crit_low_threshold", + "drv_attr_name": "in3_lcrit" + } + ] + } + }, + "VOLTAGE78": { + "dev_info": { + "device_type": "VOLTAGE_SENSOR", + "device_name": "DCDC8-RAIL2", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "DCDC8" + }, + "dev_attr": { + "display_name": "POS0V75_AVDDL_EAST_MC" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "volt1_input", + "drv_attr_name": "in4_input" + }, + { + "attr_name": "volt1_high_threshold", + "drv_attr_name": "in4_max" + }, + { + "attr_name": "volt1_low_threshold", + "drv_attr_name": "in4_min" + }, + { + "attr_name": "volt1_crit_high_threshold", + "drv_attr_name": "in4_crit" + }, + { + "attr_name": "volt1_crit_low_threshold", + "drv_attr_name": "in4_lcrit" + } + ] + } + }, + "CURRENT15": { + "dev_info": { + "device_type": "CURRENT_SENSOR", + "device_name": "DCDC8-RAIL1", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "DCDC8" + }, + "dev_attr": { + "display_name": "POS0V75_DVDD_EAST_MC" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "current1_input", + "drv_attr_name": "curr3_input" + }, + { + "attr_name": "current1_high_threshold", + "drv_attr_name": "curr3_max" + }, + { + "attr_name": "current1_crit_high_threshold", + "drv_attr_name": "curr3_crit" + } + ] + } + }, + "CURRENT16": { + "dev_info": { + "device_type": "CURRENT_SENSOR", + "device_name": "DCDC8-RAIL2", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "DCDC8" + }, + "dev_attr": { + "display_name": "POS0V75_AVDDL_EAST_MC" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "current1_input", + "drv_attr_name": "curr4_input" + }, + { + "attr_name": "current1_high_threshold", + "drv_attr_name": "curr4_max" + }, + { + "attr_name": "current1_crit_high_threshold", + "drv_attr_name": "curr4_crit" + } + ] + } + }, + "DCDC9": { + "dev_info": { + "device_type": "DCDC", + "device_name": "DCDC9", + "device_parent": "MULTIFPGAPCIE1" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x5e", + "dev_addr": "0x72", + "dev_type": "nh_raa228234" + } + } + }, + "VOLTAGE79": { + "dev_info": { + "device_type": "VOLTAGE_SENSOR", + "device_name": "DCDC9-RAIL1", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "DCDC9" + }, + "dev_attr": { + "display_name": "POS3V3_WEST_MC" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "volt1_input", + "drv_attr_name": "in3_input" + }, + { + "attr_name": "volt1_high_threshold", + "drv_attr_name": "in3_max" + }, + { + "attr_name": "volt1_low_threshold", + "drv_attr_name": "in3_min" + }, + { + "attr_name": "volt1_crit_high_threshold", + "drv_attr_name": "in3_crit" + }, + { + "attr_name": "volt1_crit_low_threshold", + "drv_attr_name": "in3_lcrit" + } + ] + } + }, + "VOLTAGE80": { + "dev_info": { + "device_type": "VOLTAGE_SENSOR", + "device_name": "DCDC9-RAIL2", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "DCDC9" + }, + "dev_attr": { + "display_name": "POS0V9_AVDDH_WEST_MC" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "volt1_input", + "drv_attr_name": "in4_input" + }, + { + "attr_name": "volt1_high_threshold", + "drv_attr_name": "in4_max" + }, + { + "attr_name": "volt1_low_threshold", + "drv_attr_name": "in4_min" + }, + { + "attr_name": "volt1_crit_high_threshold", + "drv_attr_name": "in4_crit" + }, + { + "attr_name": "volt1_crit_low_threshold", + "drv_attr_name": "in4_lcrit" + } + ] + } + }, + "CURRENT17": { + "dev_info": { + "device_type": "CURRENT_SENSOR", + "device_name": "DCDC9-RAIL1", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "DCDC9" + }, + "dev_attr": { + "display_name": "POS3V3_WEST_MC" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "current1_input", + "drv_attr_name": "curr3_input" + }, + { + "attr_name": "current1_high_threshold", + "drv_attr_name": "curr3_max" + }, + { + "attr_name": "current1_crit_high_threshold", + "drv_attr_name": "curr3_crit" + } + ] + } + }, + "CURRENT18": { + "dev_info": { + "device_type": "CURRENT_SENSOR", + "device_name": "DCDC10-RAIL2", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "DCDC10" + }, + "dev_attr": { + "display_name": "POS0V9_AVDDH_WEST_MC" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "current1_input", + "drv_attr_name": "curr4_input" + }, + { + "attr_name": "current1_high_threshold", + "drv_attr_name": "curr4_max" + }, + { + "attr_name": "current1_crit_high_threshold", + "drv_attr_name": "curr4_crit" + } + ] + } + }, + "DCDC10": { + "dev_info": { + "device_type": "DCDC", + "device_name": "DCDC10", + "device_parent": "MULTIFPGAPCIE1" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x5e", + "dev_addr": "0x75", + "dev_type": "nh_raa228234" + } + } + }, + "VOLTAGE81": { + "dev_info": { + "device_type": "VOLTAGE_SENSOR", + "device_name": "DCDC10-RAIL1", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "DCDC10" + }, + "dev_attr": { + "display_name": "POS3V3_EAST_MC" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "volt1_input", + "drv_attr_name": "in3_input" + }, + { + "attr_name": "volt1_high_threshold", + "drv_attr_name": "in3_max" + }, + { + "attr_name": "volt1_low_threshold", + "drv_attr_name": "in3_min" + }, + { + "attr_name": "volt1_crit_high_threshold", + "drv_attr_name": "in3_crit" + }, + { + "attr_name": "volt1_crit_low_threshold", + "drv_attr_name": "in3_lcrit" + } + ] + } + }, + "VOLTAGE82": { + "dev_info": { + "device_type": "VOLTAGE_SENSOR", + "device_name": "DCDC10-RAIL2", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "DCDC10" + }, + "dev_attr": { + "display_name": "POS0V9_AVDDH_EAST_MC" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "volt1_input", + "drv_attr_name": "in4_input" + }, + { + "attr_name": "volt1_high_threshold", + "drv_attr_name": "in4_max" + }, + { + "attr_name": "volt1_low_threshold", + "drv_attr_name": "in4_min" + }, + { + "attr_name": "volt1_crit_high_threshold", + "drv_attr_name": "in4_crit" + }, + { + "attr_name": "volt1_crit_low_threshold", + "drv_attr_name": "in4_lcrit" + } + ] + } + }, + "CURRENT19": { + "dev_info": { + "device_type": "CURRENT_SENSOR", + "device_name": "DCDC10-RAIL1", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "DCDC10" + }, + "dev_attr": { + "display_name": "POS3V3_EAST_MC" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "current1_input", + "drv_attr_name": "curr3_input" + }, + { + "attr_name": "current1_high_threshold", + "drv_attr_name": "curr3_max" + }, + { + "attr_name": "current1_crit_high_threshold", + "drv_attr_name": "curr3_crit" + } + ] + } + }, + "CURRENT20": { + "dev_info": { + "device_type": "CURRENT_SENSOR", + "device_name": "DCDC10-RAIL2", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent": "DCDC10" + }, + "dev_attr": { + "display_name": "POS0V9_AVDDH_EAST_MC" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "current1_input", + "drv_attr_name": "curr4_input" + }, + { + "attr_name": "current1_high_threshold", + "drv_attr_name": "curr4_max" + }, + { + "attr_name": "current1_crit_high_threshold", + "drv_attr_name": "curr4_crit" + } + ] + } + }, + "TEMP28": { + "dev_info": { + "device_type": "TEMP_SENSOR", + "device_name": "DCDC7_TEMP", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent" : "DCDC7" + }, + "dev_attr": { + "display_name": "DCDC7" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "temp1_input", + "drv_attr_name": "temp1_input" + }, + { + "attr_name": "temp1_high_threshold", + "drv_attr_name": "temp1_max" + }, + { + "attr_name": "temp1_high_crit_threshold", + "drv_attr_name": "temp1_crit" + } + ] + } + }, + "TEMP29": { + "dev_info": { + "device_type": "TEMP_SENSOR", + "device_name": "DCDC8_TEMP", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent" : "DCDC8" + }, + "dev_attr": { + "display_name": "DCDC8" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "temp1_input", + "drv_attr_name": "temp1_input" + }, + { + "attr_name": "temp1_high_threshold", + "drv_attr_name": "temp1_max" + }, + { + "attr_name": "temp1_high_crit_threshold", + "drv_attr_name": "temp1_crit" + } + ] + } + }, + "TEMP30": { + "dev_info": { + "device_type": "TEMP_SENSOR", + "device_name": "DCDC9_TEMP", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent" : "DCDC9" + }, + "dev_attr": { + "display_name": "DCDC9" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "temp1_input", + "drv_attr_name": "temp1_input" + }, + { + "attr_name": "temp1_high_threshold", + "drv_attr_name": "temp1_max" + }, + { + "attr_name": "temp1_high_crit_threshold", + "drv_attr_name": "temp1_crit" + } + ] + } + }, + "TEMP31": { + "dev_info": { + "device_type": "TEMP_SENSOR", + "device_name": "DCDC10_TEMP", + "device_parent": "MULTIFPGAPCIE1", + "virt_parent" : "DCDC10" + }, + "dev_attr": { + "display_name": "DCDC10" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "temp1_input", + "drv_attr_name": "temp1_input" + }, + { + "attr_name": "temp1_high_threshold", + "drv_attr_name": "temp1_max" + }, + { + "attr_name": "temp1_high_crit_threshold", + "drv_attr_name": "temp1_crit" + } + ] + } + }, + "WATCHDOG": { + "dev_info": { + "device_type": "WATCHDOG", + "device_parent": "MULTIFPGAPCIE1" + }, + "dev_attr": { + "event_driven_power_cycle_control_reg_offset": "0x28", + "watchdog_counter_reg_offset": "0x1E0" + } + } +} diff --git a/device/nexthop/x86_64-nexthop_5010-r0/pddf_support b/device/nexthop/x86_64-nexthop_5010-r0/pddf_support new file mode 100644 index 00000000000..e69de29bb2d diff --git a/device/nexthop/x86_64-nexthop_5010-r0/platform.json b/device/nexthop/x86_64-nexthop_5010-r0/platform.json new file mode 100644 index 00000000000..253a669b606 --- /dev/null +++ b/device/nexthop/x86_64-nexthop_5010-r0/platform.json @@ -0,0 +1,921 @@ +{ + "asic_sensors": { + "poll_interval": "10", + "poll_admin_status": "enable" + }, + "chassis": { + "name": "NH-5010-F", + "thermals": [ + { + "name": "Switch Card Left Lower Rear", + "low-threshold": false, + "low-crit-threshold": false + }, + { + "name": "Left Port Side Intake", + "low-threshold": false, + "low-crit-threshold": false + }, + { + "name": "ASIC Diode 0 PADS tsen", + "low-threshold": false, + "low-crit-threshold": false + }, + { + "name": "ASIC Diode 0 NIF0 tsen", + "low-threshold": false, + "low-crit-threshold": false + }, + { + "name": "ASIC Diode 0 CORE tsen", + "low-threshold": false, + "low-crit-threshold": false + }, + { + "name": "ASIC Diode 0 NIF1 tsen", + "low-threshold": false, + "low-crit-threshold": false + }, + { + "name": "ASIC Diode 0 HBM_PHY1 tsen", + "low-threshold": false, + "low-crit-threshold": false + }, + { + "name": "ASIC Diode 0 HBM_PHY2 tsen", + "low-threshold": false, + "low-crit-threshold": false + }, + { + "name": "Switch Card Right Lower Rear", + "low-threshold": false, + "low-crit-threshold": false + }, + { + "name": "Right Port Side Intake", + "low-threshold": false, + "low-crit-threshold": false + }, + { + "name": "ASIC Diode 1 PADS tsen", + "low-threshold": false, + "low-crit-threshold": false + }, + { + "name": "ASIC Diode 1 NIF0 tsen", + "low-threshold": false, + "low-crit-threshold": false + }, + { + "name": "ASIC Diode 1 CORE tsen", + "low-threshold": false, + "low-crit-threshold": false + }, + { + "name": "ASIC Diode 1 NIF1 tsen", + "low-threshold": false, + "low-crit-threshold": false + }, + { + "name": "ASIC Diode 1 HBM_PHY1 tsen", + "low-threshold": false, + "low-crit-threshold": false + }, + { + "name": "ASIC Diode 1 HBM_PHY2 tsen", + "low-threshold": false, + "low-crit-threshold": false + }, + { + "name": "DCDC0", + "low-threshold": false, + "low-crit-threshold": false + }, + { + "name": "DCDC1", + "low-threshold": false, + "low-crit-threshold": false + }, + { + "name": "DCDC2", + "low-threshold": false, + "low-crit-threshold": false + }, + { + "name": "DCDC3", + "low-threshold": false, + "low-crit-threshold": false + }, + { + "name": "DCDC4", + "low-threshold": false, + "low-crit-threshold": false + }, + { + "name": "DCDC5", + "low-threshold": false, + "low-crit-threshold": false + }, + { + "name": "DCDC6", + "low-threshold": false, + "low-crit-threshold": false + }, + { + "name": "Mezz Card Left Rear", + "low-threshold": false, + "low-crit-threshold": false + }, + { + "name": "Left Upper Port Side Intake", + "low-threshold": false, + "low-crit-threshold": false + }, + { + "name": "Mezz Card Right Rear", + "low-threshold": false, + "low-crit-threshold": false + }, + { + "name": "Right Upper Port Side Intake", + "low-threshold": false, + "low-crit-threshold": false + }, + { + "name": "DCDC7", + "low-threshold": false, + "low-crit-threshold": false + }, + { + "name": "DCDC8", + "low-threshold": false, + "low-crit-threshold": false + }, + { + "name": "DCDC9", + "low-threshold": false, + "low-crit-threshold": false + }, + { + "name": "DCDC10", + "low-threshold": false, + "low-crit-threshold": false + }, + { + "name": "ASIC D0_VTMON_CORE", + "low-threshold": false, + "low-crit-threshold": false, + "controllable": false + }, + { + "name": "ASIC D0_VTMON_HBM_PHY1", + "low-threshold": false, + "low-crit-threshold": false, + "controllable": false + }, + { + "name": "ASIC D0_VTMON_HBM_PHY2", + "low-threshold": false, + "low-crit-threshold": false, + "controllable": false + }, + { + "name": "ASIC D0_VTMON_NIF0", + "low-threshold": false, + "low-crit-threshold": false, + "controllable": false + }, + { + "name": "ASIC D0_VTMON_NIF1", + "low-threshold": false, + "low-crit-threshold": false, + "controllable": false + }, + { + "name": "ASIC D0_VTMON_PADS", + "low-threshold": false, + "low-crit-threshold": false, + "controllable": false + }, + { + "name": "ASIC D1_VTMON_CORE", + "low-threshold": false, + "low-crit-threshold": false, + "controllable": false + }, + { + "name": "ASIC D1_VTMON_HBM_PHY1", + "low-threshold": false, + "low-crit-threshold": false, + "controllable": false + }, + { + "name": "ASIC D1_VTMON_HBM_PHY2", + "low-threshold": false, + "low-crit-threshold": false, + "controllable": false + }, + { + "name": "ASIC D1_VTMON_NIF0", + "low-threshold": false, + "low-crit-threshold": false, + "controllable": false + }, + { + "name": "ASIC D1_VTMON_NIF1", + "low-threshold": false, + "low-crit-threshold": false, + "controllable": false + }, + { + "name": "ASIC D1_VTMON_PADS", + "low-threshold": false, + "low-crit-threshold": false, + "controllable": false + }, + { + "name": "ASIC NIF0", + "low-threshold": false, + "low-crit-threshold": false, + "controllable": false + }, + { + "name": "ASIC NIF1", + "low-threshold": false, + "low-crit-threshold": false, + "controllable": false + }, + { + "name": "ASIC NIF2", + "low-threshold": false, + "low-crit-threshold": false, + "controllable": false + }, + { + "name": "ASIC NIF3", + "low-threshold": false, + "low-crit-threshold": false, + "controllable": false + }, + { + "name": "ASIC NIF4", + "low-threshold": false, + "low-crit-threshold": false, + "controllable": false + }, + { + "name": "ASIC NIF5", + "low-threshold": false, + "low-crit-threshold": false, + "controllable": false + }, + { + "name": "ASIC NIF6", + "low-threshold": false, + "low-crit-threshold": false, + "controllable": false + }, + { + "name": "ASIC NIF7", + "low-threshold": false, + "low-crit-threshold": false, + "controllable": false + }, + { + "name": "ASIC NIF8", + "low-threshold": false, + "low-crit-threshold": false, + "controllable": false + }, + { + "name": "ASIC NIF9", + "low-threshold": false, + "low-crit-threshold": false, + "controllable": false + }, + { + "name": "ASIC NIF10", + "low-threshold": false, + "low-crit-threshold": false, + "controllable": false + }, + { + "name": "ASIC NIF11", + "low-threshold": false, + "low-crit-threshold": false, + "controllable": false + }, + { + "name": "ASIC NIF12", + "low-threshold": false, + "low-crit-threshold": false, + "controllable": false + }, + { + "name": "ASIC NIF13", + "low-threshold": false, + "low-crit-threshold": false, + "controllable": false + }, + { + "name": "ASIC NIF14", + "low-threshold": false, + "low-crit-threshold": false, + "controllable": false + }, + { + "name": "ASIC NIF15", + "low-threshold": false, + "low-crit-threshold": false, + "controllable": false + }, + { + "name": "ASIC NIF16", + "low-threshold": false, + "low-crit-threshold": false, + "controllable": false + }, + { + "name": "ASIC NIF17", + "low-threshold": false, + "low-crit-threshold": false, + "controllable": false + }, + { + "name": "ASIC NIF18", + "low-threshold": false, + "low-crit-threshold": false, + "controllable": false + }, + { + "name": "ASIC NIF19", + "low-threshold": false, + "low-crit-threshold": false, + "controllable": false + }, + { + "name": "ASIC NIF20", + "low-threshold": false, + "low-crit-threshold": false, + "controllable": false + }, + { + "name": "ASIC NIF21", + "low-threshold": false, + "low-crit-threshold": false, + "controllable": false + }, + { + "name": "ASIC NIF22", + "low-threshold": false, + "low-crit-threshold": false, + "controllable": false + }, + { + "name": "ASIC NIF23", + "low-threshold": false, + "low-crit-threshold": false, + "controllable": false + }, + { + "name": "ASIC NIF24", + "low-threshold": false, + "low-crit-threshold": false, + "controllable": false + }, + { + "name": "ASIC NIF25", + "low-threshold": false, + "low-crit-threshold": false, + "controllable": false + }, + { + "name": "ASIC NIF26", + "low-threshold": false, + "low-crit-threshold": false, + "controllable": false + }, + { + "name": "ASIC NIF27", + "low-threshold": false, + "low-crit-threshold": false, + "controllable": false + }, + { + "name": "ASIC NIF28", + "low-threshold": false, + "low-crit-threshold": false, + "controllable": false + }, + { + "name": "ASIC NIF29", + "low-threshold": false, + "low-crit-threshold": false, + "controllable": false + }, + { + "name": "ASIC NIF30", + "low-threshold": false, + "low-crit-threshold": false, + "controllable": false + }, + { + "name": "ASIC NIF31", + "low-threshold": false, + "low-crit-threshold": false, + "controllable": false + }, + { + "name": "ASIC PHY_BRIDGE0", + "low-threshold": false, + "low-crit-threshold": false, + "controllable": false + }, + { + "name": "ASIC PHY_BRIDGE1", + "low-threshold": false, + "low-crit-threshold": false, + "controllable": false + }, + { + "name": "ASIC PHY_BRIDGE2", + "low-threshold": false, + "low-crit-threshold": false, + "controllable": false + }, + { + "name": "ASIC PHY_BRIDGE3", + "low-threshold": false, + "low-crit-threshold": false, + "controllable": false + }, + { + "name": "ASIC PHY_BRIDGE4", + "low-threshold": false, + "low-crit-threshold": false, + "controllable": false + }, + { + "name": "ASIC PHY_BRIDGE5", + "low-threshold": false, + "low-crit-threshold": false, + "controllable": false + }, + { + "name": "ASIC PHY_BRIDGE6", + "low-threshold": false, + "low-crit-threshold": false, + "controllable": false + }, + { + "name": "ASIC PHY_BRIDGE7", + "low-threshold": false, + "low-crit-threshold": false, + "controllable": false + } + ], + "components": [ + { + "name": "SWITCHCARD_FPGA" + }, + { + "name": "MEZZCARD_FPGA" + }, + { + "name": "CPUCARD_FPGA" + }, + { + "name": "BIOS" + }, + { + "name": "ONIE" + }, + { + "name": "TPM" + }, + { + "name": "NVMe" + } + ], + "fans": [ + { + "name": "Fantray1_1", + "status_led": { + "available": false + } + }, + { + "name": "Fantray1_2", + "status_led": { + "available": false + } + }, + { + "name": "Fantray2_1", + "status_led": { + "available": false + } + }, + { + "name": "Fantray2_2", + "status_led": { + "available": false + } + }, + { + "name": "Fantray3_1", + "status_led": { + "available": false + } + }, + { + "name": "Fantray3_2", + "status_led": { + "available": false + } + }, + { + "name": "Fantray4_1", + "status_led": { + "available": false + } + }, + { + "name": "Fantray4_2", + "status_led": { + "available": false + } + } + ], + "fan_drawers":[ + { + "name": "Fantray1", + "num_fans" : 2, + "max_consumed_power": false, + "status_led": { + "controllable": true, + "colors": [ + "off", + "red", + "green" + ] + }, + "fans": [ + { + "name": "Fantray1_1", + "status_led": { + "available": false + } + }, + { + "name": "Fantray1_2", + "status_led": { + "available": false + } + } + ] + }, + { + "name": "Fantray2", + "num_fans" : 2, + "max_consumed_power": false, + "status_led": { + "controllable": true, + "colors": [ + "off", + "red", + "green" + ] + }, + "fans": [ + { + "name": "Fantray2_1", + "status_led": { + "available": false + } + }, + { + "name": "Fantray2_2", + "status_led": { + "available": false + } + } + ] + }, + { + "name": "Fantray3", + "num_fans" : 2, + "max_consumed_power": false, + "status_led": { + "controllable": true, + "colors": [ + "off", + "red", + "green" + ] + }, + "fans": [ + { + "name": "Fantray3_1", + "status_led": { + "available": false + } + }, + { + "name": "Fantray3_2", + "status_led": { + "available": false + } + } + ] + }, + { + "name": "Fantray4", + "num_fans" : 2, + "max_consumed_power": false, + "status_led": { + "controllable": true, + "colors": [ + "off", + "red", + "green" + ] + }, + "fans": [ + { + "name": "Fantray4_1", + "status_led": { + "available": false + } + }, + { + "name": "Fantray4_2", + "status_led": { + "available": false + } + } + ] + } + ], + "psus": [ + { + "name": "PSU1", + "status_led": { + "controllable": false + }, + "fans": [ + { + "name": "PSU1_FAN1", + "speed": { + "controllable": false + }, + "status_led": { + "controllable": false + } + } + ], + "thermals": [ + { + "name": "PSU1_TEMP1" + }, + { + "name": "PSU1_TEMP2" + }, + { + "name": "PSU1_TEMP3" + } + ] + }, + { + "name": "PSU2", + "status_led": { + "controllable": false + }, + "fans": [ + { + "name": "PSU2_FAN1", + "speed": { + "controllable": false + }, + "status_led": { + "controllable": false + } + } + ], + "thermals": [ + { + "name": "PSU2_TEMP1" + }, + { + "name": "PSU2_TEMP2" + }, + { + "name": "PSU2_TEMP3" + } + ] + } + ], + "sfps": [ + { + "name": "PORT1" + }, + { + "name": "PORT2" + }, + { + "name": "PORT3" + }, + { + "name": "PORT4" + }, + { + "name": "PORT5" + }, + { + "name": "PORT6" + }, + { + "name": "PORT7" + }, + { + "name": "PORT8" + }, + { + "name": "PORT9" + }, + { + "name": "PORT10" + }, + { + "name": "PORT11" + }, + { + "name": "PORT12" + }, + { + "name": "PORT13" + }, + { + "name": "PORT14" + }, + { + "name": "PORT15" + }, + { + "name": "PORT16" + }, + { + "name": "PORT17" + }, + { + "name": "PORT18" + }, + { + "name": "PORT19" + }, + { + "name": "PORT20" + }, + { + "name": "PORT21" + }, + { + "name": "PORT22" + }, + { + "name": "PORT23" + }, + { + "name": "PORT24" + }, + { + "name": "PORT25" + }, + { + "name": "PORT26" + }, + { + "name": "PORT27" + }, + { + "name": "PORT28" + }, + { + "name": "PORT29" + }, + { + "name": "PORT30" + }, + { + "name": "PORT31" + }, + { + "name": "PORT32" + }, + { + "name": "PORT33" + }, + { + "name": "PORT34" + }, + { + "name": "PORT35" + }, + { + "name": "PORT36" + }, + { + "name": "PORT37" + }, + { + "name": "PORT38" + }, + { + "name": "PORT39" + }, + { + "name": "PORT40" + }, + { + "name": "PORT41" + }, + { + "name": "PORT42" + }, + { + "name": "PORT43" + }, + { + "name": "PORT44" + }, + { + "name": "PORT45" + }, + { + "name": "PORT46" + }, + { + "name": "PORT47" + }, + { + "name": "PORT48" + }, + { + "name": "PORT49" + }, + { + "name": "PORT50" + }, + { + "name": "PORT51" + }, + { + "name": "PORT52" + }, + { + "name": "PORT53" + }, + { + "name": "PORT54" + }, + { + "name": "PORT55" + }, + { + "name": "PORT56" + }, + { + "name": "PORT57" + }, + { + "name": "PORT58" + }, + { + "name": "PORT59" + }, + { + "name": "PORT60" + }, + { + "name": "PORT61" + }, + { + "name": "PORT62" + }, + { + "name": "PORT63" + }, + { + "name": "PORT64" + }, + { + "name": "PORT65" + }, + { + "name": "PORT66" + } + ] + }, + "interfaces": { + } +} diff --git a/device/nexthop/x86_64-nexthop_5010-r0/platform_asic b/device/nexthop/x86_64-nexthop_5010-r0/platform_asic new file mode 100644 index 00000000000..9ba24ca3e75 --- /dev/null +++ b/device/nexthop/x86_64-nexthop_5010-r0/platform_asic @@ -0,0 +1 @@ +broadcom-dnx diff --git a/device/nexthop/x86_64-nexthop_5010-r0/platform_components.json b/device/nexthop/x86_64-nexthop_5010-r0/platform_components.json new file mode 100644 index 00000000000..2c814743a3f --- /dev/null +++ b/device/nexthop/x86_64-nexthop_5010-r0/platform_components.json @@ -0,0 +1,15 @@ +{ + "chassis": { + "NH-5010-F": { + "component": { + "SWITCHCARD_FPGA": {}, + "MEZZCARD_FPGA": {}, + "CPUCARD_FPGA": {}, + "BIOS": {}, + "ONIE": {}, + "TPM": {}, + "NVMe": {} + } + } + } +} diff --git a/device/nexthop/x86_64-nexthop_5010-r0/platform_env.conf b/device/nexthop/x86_64-nexthop_5010-r0/platform_env.conf new file mode 100644 index 00000000000..33580a92681 --- /dev/null +++ b/device/nexthop/x86_64-nexthop_5010-r0/platform_env.conf @@ -0,0 +1,4 @@ +SYNCD_SHM_SIZE=1g +macsec_enabled=1 +THERMALCTLD_THERMAL_MONITOR_UPDATE_INTERVAL=10 +THERMALCTLD_THERMAL_MONITOR_UPDATE_ELAPSED_THRESHOLD=9 diff --git a/device/nexthop/x86_64-nexthop_5010-r0/plugins/led_control.py b/device/nexthop/x86_64-nexthop_5010-r0/plugins/led_control.py new file mode 100644 index 00000000000..43494e4628b --- /dev/null +++ b/device/nexthop/x86_64-nexthop_5010-r0/plugins/led_control.py @@ -0,0 +1,9 @@ +# Copyright 2025 Nexthop Systems Inc. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +# Nexthop Port LED Policy + +try: + from nexthop.led_control import LedControl +except ImportError as e: + raise ImportError("%s - required module not found" % e) diff --git a/device/nexthop/x86_64-nexthop_5010-r0/pmon_daemon_control.json b/device/nexthop/x86_64-nexthop_5010-r0/pmon_daemon_control.json new file mode 100644 index 00000000000..26c79c86c86 --- /dev/null +++ b/device/nexthop/x86_64-nexthop_5010-r0/pmon_daemon_control.json @@ -0,0 +1,5 @@ +{ + "include_sensormond": true, + "skip_ledd": true, + "enable_xcvrd_sff_mgr": true +} diff --git a/device/nexthop/x86_64-nexthop_5010-r0/system_health_monitoring_config.json b/device/nexthop/x86_64-nexthop_5010-r0/system_health_monitoring_config.json new file mode 100644 index 00000000000..286eef80500 --- /dev/null +++ b/device/nexthop/x86_64-nexthop_5010-r0/system_health_monitoring_config.json @@ -0,0 +1,14 @@ +{ + "services_to_ignore": [], + "devices_to_ignore": [ + "PSU1_FAN1.speed", + "PSU2_FAN1.speed" + ], + "user_defined_checkers": [], + "polling_interval": 60, + "led_color": { + "fault": "red", + "normal": "green", + "booting": "green_blink" + } +} diff --git a/device/nexthop/x86_64-nexthop_5010-r0/thermal_policy.json b/device/nexthop/x86_64-nexthop_5010-r0/thermal_policy.json new file mode 100644 index 00000000000..5660f210be1 --- /dev/null +++ b/device/nexthop/x86_64-nexthop_5010-r0/thermal_policy.json @@ -0,0 +1,101 @@ +{ + "interval": 5, + "info_types": [ + { + "type": "fan_drawer_info" + }, + { + "type": "thermal_info" + }, + { + "type": "psu_info" + } + ], + "policies": [ + { + "name": "One fan drawer present", + "conditions": [ + { + "type": "fandrawer.one.present" + } + ], + "actions": [ + { + "type": "fan.set_max_speed", + "max_speed": 100 + }, + { + "type": "fan.set_speed", + "speed": 100 + } + ] + }, + { + "name": "Two fan drawers present", + "conditions": [ + { + "type": "fandrawer.two.present" + } + ], + "actions": [ + { + "type": "fan.set_max_speed", + "max_speed": 95 + }, + { + "type": "fan.set_speed", + "speed": 95 + } + ] + }, + { + "name": "Three fan drawers present", + "conditions": [ + { + "type": "fandrawer.three.present" + } + ], + "actions": [ + { + "type": "fan.set_max_speed", + "max_speed": 80 + } + ] + }, + { + "name": "Four fan drawers present", + "conditions": [ + { + "type": "fandrawer.four.present" + } + ], + "actions": [ + { + "type": "fan.set_max_speed", + "max_speed": 75 + } + ] + }, + { + "name": "thermal control algorithm", + "conditions": [ + { + "type": "default.operation" + } + ], + "actions": [ + { + "type": "thermal.control_algo", + "pid_params": { + "setpoint": 85, + "Kp": 1.0, + "Ki": 1.0, + "Kd": 1.0, + "min_speed": 50, + "max_speed": 100 + } + } + ] + } + ] +} From 64b2f7c85e7b72a80a5b72edde923d684c99e260 Mon Sep 17 00:00:00 2001 From: Roy Wen Date: Tue, 30 Sep 2025 17:21:11 -0400 Subject: [PATCH 02/13] add sonic-platform-modules-nexthop support for nh-5010 --- .../override.conf | 3 + .../system/swss.service.d/override.conf | 3 + .../system/syncd.service.d/override.conf | 3 + .../common/modules/Makefile | 1 + .../common/modules/nh_adm1266.c | 643 ++++++++++++++++++ .../common/modules/nh_isl68137.c | 4 + .../common/modules/nh_pmbus_core.c | 11 +- .../common/nexthop/eeprom_utils.py | 395 +++++++++-- .../common/nexthop/fpga_cli.py | 76 ++- .../common/nexthop/fpga_lib.py | 42 +- .../common/nexthop/pddf_config_parser.py | 113 +++ .../common/nexthop/platform_utils.py | 47 ++ .../common/service/transceiver-init.service | 2 +- .../common/sonic_platform/__init__.py | 3 +- .../common/sonic_platform/adm1266.py | 356 ++++++++++ .../common/sonic_platform/asic_thermal.py | 10 + .../common/sonic_platform/chassis.py | 14 +- .../common/sonic_platform/dpm_info.py | 47 ++ .../common/sonic_platform/fan.py | 100 +++ .../common/sonic_platform/thermal.py | 30 + .../common/sonic_platform/thermal_actions.py | 155 ++++- .../sonic_platform/thermal_conditions.py | 53 +- .../common/sonic_platform/thermal_infos.py | 18 +- .../common/utils/nh_powercycle | 89 +++ .../common/utils/pre_pddf_init.sh | 2 + .../common/utils/transceiver_init.py | 121 ++++ .../debian/control | 12 + .../debian/rules | 25 + .../sonic-platform-nexthop-4010-r0.postinst | 2 - .../sonic-platform-nexthop-5010-r0.postinst | 11 + .../komodo/utils/program_mgmt_eeprom.py | 195 ++++++ .../nh-5010/utils/asic_init.sh | 151 ++++ .../test/fixtures/adm1266_test_spec.json | 45 ++ .../test/fixtures/fake_swsscommon.py | 83 +++ .../test/fixtures/fixtures_unit_test.py | 224 +++++- .../test/fixtures/test_helpers_eeprom.py | 32 +- .../test_adm1266_chassis_integration.py | 47 ++ .../nexthop/test_eeprom_utils_integration.py | 213 ++++++ .../test/unit/nexthop/test_fpga_cli.py | 87 ++- .../test/unit/nexthop/test_fpga_lib.py | 19 +- .../unit/nexthop/test_pddf_config_parser.py | 351 ++++++++++ .../test/unit/sonic_platform/test_adm1266.py | 98 +++ .../test/unit/sonic_platform/test_fan.py | 189 +++++ .../test/unit/sonic_platform/test_thermal.py | 102 ++- 44 files changed, 4063 insertions(+), 164 deletions(-) create mode 100644 platform/broadcom/sonic-platform-modules-nexthop/common/etc/systemd/system/determine-reboot-cause.service.d/override.conf create mode 100644 platform/broadcom/sonic-platform-modules-nexthop/common/etc/systemd/system/swss.service.d/override.conf create mode 100644 platform/broadcom/sonic-platform-modules-nexthop/common/etc/systemd/system/syncd.service.d/override.conf create mode 100644 platform/broadcom/sonic-platform-modules-nexthop/common/modules/nh_adm1266.c create mode 100644 platform/broadcom/sonic-platform-modules-nexthop/common/nexthop/pddf_config_parser.py create mode 100644 platform/broadcom/sonic-platform-modules-nexthop/common/nexthop/platform_utils.py create mode 100644 platform/broadcom/sonic-platform-modules-nexthop/common/sonic_platform/adm1266.py create mode 100644 platform/broadcom/sonic-platform-modules-nexthop/common/sonic_platform/dpm_info.py create mode 100755 platform/broadcom/sonic-platform-modules-nexthop/common/utils/nh_powercycle create mode 100755 platform/broadcom/sonic-platform-modules-nexthop/common/utils/transceiver_init.py create mode 100644 platform/broadcom/sonic-platform-modules-nexthop/debian/sonic-platform-nexthop-5010-r0.postinst create mode 100644 platform/broadcom/sonic-platform-modules-nexthop/komodo/utils/program_mgmt_eeprom.py create mode 100755 platform/broadcom/sonic-platform-modules-nexthop/nh-5010/utils/asic_init.sh create mode 100644 platform/broadcom/sonic-platform-modules-nexthop/test/fixtures/adm1266_test_spec.json create mode 100644 platform/broadcom/sonic-platform-modules-nexthop/test/fixtures/fake_swsscommon.py create mode 100644 platform/broadcom/sonic-platform-modules-nexthop/test/integration/nexthop/test_adm1266_chassis_integration.py create mode 100644 platform/broadcom/sonic-platform-modules-nexthop/test/unit/nexthop/test_pddf_config_parser.py create mode 100644 platform/broadcom/sonic-platform-modules-nexthop/test/unit/sonic_platform/test_adm1266.py create mode 100644 platform/broadcom/sonic-platform-modules-nexthop/test/unit/sonic_platform/test_fan.py diff --git a/platform/broadcom/sonic-platform-modules-nexthop/common/etc/systemd/system/determine-reboot-cause.service.d/override.conf b/platform/broadcom/sonic-platform-modules-nexthop/common/etc/systemd/system/determine-reboot-cause.service.d/override.conf new file mode 100644 index 00000000000..97eb65a39b5 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-nexthop/common/etc/systemd/system/determine-reboot-cause.service.d/override.conf @@ -0,0 +1,3 @@ +[Unit] +Requires=pddf-platform-init.service +After=pddf-platform-init.service diff --git a/platform/broadcom/sonic-platform-modules-nexthop/common/etc/systemd/system/swss.service.d/override.conf b/platform/broadcom/sonic-platform-modules-nexthop/common/etc/systemd/system/swss.service.d/override.conf new file mode 100644 index 00000000000..28a84a874c7 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-nexthop/common/etc/systemd/system/swss.service.d/override.conf @@ -0,0 +1,3 @@ +[Unit] +Wants=pmon.service +After=pmon.service diff --git a/platform/broadcom/sonic-platform-modules-nexthop/common/etc/systemd/system/syncd.service.d/override.conf b/platform/broadcom/sonic-platform-modules-nexthop/common/etc/systemd/system/syncd.service.d/override.conf new file mode 100644 index 00000000000..28a84a874c7 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-nexthop/common/etc/systemd/system/syncd.service.d/override.conf @@ -0,0 +1,3 @@ +[Unit] +Wants=pmon.service +After=pmon.service diff --git a/platform/broadcom/sonic-platform-modules-nexthop/common/modules/Makefile b/platform/broadcom/sonic-platform-modules-nexthop/common/modules/Makefile index 21768fdd4e4..415298697af 100644 --- a/platform/broadcom/sonic-platform-modules-nexthop/common/modules/Makefile +++ b/platform/broadcom/sonic-platform-modules-nexthop/common/modules/Makefile @@ -3,6 +3,7 @@ obj-m += nh_tda38740.o obj-m += nh_isl68137.o obj-m += nh_pmbus_core.o obj-m += nh_tmp464.o +obj-m += nh_adm1266.o CFLAGS_pddf_custom_fpga_algo.o := -I$(M)/../../../../pddf/i2c/modules/include KBUILD_EXTRA_SYMBOLS := $(M)/../../../../pddf/i2c/Module.symvers.PDDF diff --git a/platform/broadcom/sonic-platform-modules-nexthop/common/modules/nh_adm1266.c b/platform/broadcom/sonic-platform-modules-nexthop/common/modules/nh_adm1266.c new file mode 100644 index 00000000000..2c1e24f57eb --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-nexthop/common/modules/nh_adm1266.c @@ -0,0 +1,643 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * ADM1266 - Cascadable Super Sequencer with Margin + * Control and Fault Recording + * + * Copyright 2020 Analog Devices Inc. + */ +/* + * Nexthop changes for BLACKBOX SUPPORT: + * + * Original kernel driver version: v6.16.2 + * + * Reading Blackbox: + * ----------------- + * The standard linux driver had many i2c message correctness issues while accessing + * the black box. This resulted in the driver returning -EPROTO to userspace. + * + * The Nexthop driver performs the following steps using the i2c_transfer() with + * atomic write-then-read transactions: + * - Step 1: Read blackbox info [0xE6] -> 4 bytes to get record count + * - Step 2: For each record, atomic transaction [0xDE, 0x01, index] -> 64 bytes + * + * Clear Blackbox: + * --------------- + * Added support to clear the blackbox via the standard driver. + * + * The Nexthop driver uses the following command sequence to clear blackbox entries: + * - Command: [0xDE, 0xFE, 0x00] sent via I2C transaction + * The userspace access is provided via the same nvmem sysfs interface. + * - Usage: echo "anything" > /sys/bus/nvmem/devices/7-00410/nvmem + * + * Lastly, the Nexthop driver enables 'cyclic' recording in the configuration register + * of the blackbox. This is useful when the DPM log buffer is full as new logs continue + * to be recorded. In the userspace, we need to save this setting to flash to make + * the changes permanent. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "nh_pmbus.h" +#include +#include + +#define ADM1266_BLACKBOX_CONFIG 0xD3 +#define ADM1266_PDIO_CONFIG 0xD4 +#define ADM1266_READ_STATE 0xD9 +#define ADM1266_READ_BLACKBOX 0xDE +#define ADM1266_SET_RTC 0xDF +#define ADM1266_GPIO_CONFIG 0xE1 +#define ADM1266_BLACKBOX_INFO 0xE6 +#define ADM1266_PDIO_STATUS 0xE9 +#define ADM1266_GPIO_STATUS 0xEA + +/* ADM1266 GPIO defines */ +#define ADM1266_GPIO_NR 9 +#define ADM1266_GPIO_FUNCTIONS(x) FIELD_GET(BIT(0), x) +#define ADM1266_GPIO_INPUT_EN(x) FIELD_GET(BIT(2), x) +#define ADM1266_GPIO_OUTPUT_EN(x) FIELD_GET(BIT(3), x) +#define ADM1266_GPIO_OPEN_DRAIN(x) FIELD_GET(BIT(4), x) + +/* ADM1266 PDIO defines */ +#define ADM1266_PDIO_NR 16 +#define ADM1266_PDIO_PIN_CFG(x) FIELD_GET(GENMASK(15, 13), x) +#define ADM1266_PDIO_GLITCH_FILT(x) FIELD_GET(GENMASK(12, 9), x) +#define ADM1266_PDIO_OUT_CFG(x) FIELD_GET(GENMASK(2, 0), x) + +#define ADM1266_BLACKBOX_OFFSET 0 +#define ADM1266_BLACKBOX_SIZE 64 +#define ADM1266_BLACKBOX_MAX_RECORDS 64 + +#define ADM1266_PMBUS_BLOCK_MAX 255 + +struct nh_adm1266_data { + struct pmbus_driver_info info; + struct gpio_chip gc; + const char *gpio_names[ADM1266_GPIO_NR + ADM1266_PDIO_NR]; + struct i2c_client *client; + struct dentry *debugfs_dir; + struct nvmem_config nvmem_config; + struct nvmem_device *nvmem; + u8 *dev_mem; + struct mutex buf_mutex; + u8 write_buf[ADM1266_PMBUS_BLOCK_MAX + 1] ____cacheline_aligned; + u8 read_buf[ADM1266_PMBUS_BLOCK_MAX + 1] ____cacheline_aligned; +}; + +static const struct nvmem_cell_info nh_adm1266_nvmem_cells[] = { + { + .name = "blackbox", + .offset = ADM1266_BLACKBOX_OFFSET, + .bytes = 2048, + }, +}; + +DECLARE_CRC8_TABLE(pmbus_crc_table); + +/* + * Different from Block Read as it sends data and waits for the slave to + * return a value dependent on that data. The protocol is simply a Write Block + * followed by a Read Block without the Read-Block command field and the + * Write-Block STOP bit. + */ +static int nh_adm1266_pmbus_block_xfer(struct nh_adm1266_data *data, u8 cmd, u8 w_len, u8 *data_w, + u8 *data_r) +{ + struct i2c_client *client = data->client; + struct i2c_msg msgs[2] = { + { + .addr = client->addr, + .flags = I2C_M_DMA_SAFE, + .buf = data->write_buf, + .len = w_len + 2, + }, + { + .addr = client->addr, + .flags = I2C_M_RD | I2C_M_DMA_SAFE, + .buf = data->read_buf, + .len = ADM1266_PMBUS_BLOCK_MAX + 2, + } + }; + u8 addr; + u8 crc; + int ret; + + mutex_lock(&data->buf_mutex); + + msgs[0].buf[0] = cmd; + msgs[0].buf[1] = w_len; + memcpy(&msgs[0].buf[2], data_w, w_len); + + ret = i2c_transfer(client->adapter, msgs, 2); + if (ret != 2) { + if (ret >= 0) + ret = -EPROTO; + + mutex_unlock(&data->buf_mutex); + + return ret; + } + + if (client->flags & I2C_CLIENT_PEC) { + addr = i2c_8bit_addr_from_msg(&msgs[0]); + crc = crc8(pmbus_crc_table, &addr, 1, 0); + crc = crc8(pmbus_crc_table, msgs[0].buf, msgs[0].len, crc); + + addr = i2c_8bit_addr_from_msg(&msgs[1]); + crc = crc8(pmbus_crc_table, &addr, 1, crc); + crc = crc8(pmbus_crc_table, msgs[1].buf, msgs[1].buf[0] + 1, crc); + + if (crc != msgs[1].buf[msgs[1].buf[0] + 1]) { + mutex_unlock(&data->buf_mutex); + return -EBADMSG; + } + } + + memcpy(data_r, &msgs[1].buf[1], msgs[1].buf[0]); + + ret = msgs[1].buf[0]; + mutex_unlock(&data->buf_mutex); + + return ret; +} + +static const unsigned int nh_adm1266_gpio_mapping[ADM1266_GPIO_NR][2] = { + {1, 0}, + {2, 1}, + {3, 2}, + {4, 8}, + {5, 9}, + {6, 10}, + {7, 11}, + {8, 6}, + {9, 7}, +}; + +static const char *nh_adm1266_names[ADM1266_GPIO_NR + ADM1266_PDIO_NR] = { + "GPIO1", "GPIO2", "GPIO3", "GPIO4", "GPIO5", "GPIO6", "GPIO7", "GPIO8", + "GPIO9", "PDIO1", "PDIO2", "PDIO3", "PDIO4", "PDIO5", "PDIO6", + "PDIO7", "PDIO8", "PDIO9", "PDIO10", "PDIO11", "PDIO12", "PDIO13", + "PDIO14", "PDIO15", "PDIO16", +}; + +static int nh_adm1266_gpio_get(struct gpio_chip *chip, unsigned int offset) +{ + struct nh_adm1266_data *data = gpiochip_get_data(chip); + u8 read_buf[I2C_SMBUS_BLOCK_MAX + 1]; + unsigned long pins_status; + unsigned int pmbus_cmd; + int ret; + + if (offset < ADM1266_GPIO_NR) + pmbus_cmd = ADM1266_GPIO_STATUS; + else + pmbus_cmd = ADM1266_PDIO_STATUS; + + ret = i2c_smbus_read_block_data(data->client, pmbus_cmd, read_buf); + if (ret < 0) + return ret; + + pins_status = read_buf[0] + (read_buf[1] << 8); + if (offset < ADM1266_GPIO_NR) + return test_bit(nh_adm1266_gpio_mapping[offset][1], &pins_status); + + return test_bit(offset - ADM1266_GPIO_NR, &pins_status); +} + +static int nh_adm1266_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask, + unsigned long *bits) +{ + struct nh_adm1266_data *data = gpiochip_get_data(chip); + u8 read_buf[ADM1266_PMBUS_BLOCK_MAX + 1]; + unsigned long status; + unsigned int gpio_nr; + int ret; + + ret = i2c_smbus_read_block_data(data->client, ADM1266_GPIO_STATUS, read_buf); + if (ret < 0) + return ret; + + status = read_buf[0] + (read_buf[1] << 8); + + *bits = 0; + for_each_set_bit(gpio_nr, mask, ADM1266_GPIO_NR) { + if (test_bit(nh_adm1266_gpio_mapping[gpio_nr][1], &status)) + set_bit(gpio_nr, bits); + } + + ret = i2c_smbus_read_block_data(data->client, ADM1266_PDIO_STATUS, read_buf); + if (ret < 0) + return ret; + + status = read_buf[0] + (read_buf[1] << 8); + + *bits = 0; + for_each_set_bit_from(gpio_nr, mask, ADM1266_GPIO_NR + ADM1266_PDIO_STATUS) { + if (test_bit(gpio_nr - ADM1266_GPIO_NR, &status)) + set_bit(gpio_nr, bits); + } + + return 0; +} + +static void nh_adm1266_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) +{ + struct nh_adm1266_data *data = gpiochip_get_data(chip); + u8 read_buf[ADM1266_PMBUS_BLOCK_MAX + 1]; + unsigned long gpio_config; + unsigned long pdio_config; + unsigned long pin_cfg; + u8 write_cmd; + int ret; + int i; + + for (i = 0; i < ADM1266_GPIO_NR; i++) { + write_cmd = nh_adm1266_gpio_mapping[i][1]; + ret = nh_adm1266_pmbus_block_xfer(data, ADM1266_GPIO_CONFIG, 1, &write_cmd, read_buf); + if (ret != 2) + return; + + gpio_config = read_buf[0]; + seq_puts(s, nh_adm1266_names[i]); + + seq_puts(s, " ( "); + if (!ADM1266_GPIO_FUNCTIONS(gpio_config)) { + seq_puts(s, "high-Z )\n"); + continue; + } + if (ADM1266_GPIO_INPUT_EN(gpio_config)) + seq_puts(s, "input "); + if (ADM1266_GPIO_OUTPUT_EN(gpio_config)) + seq_puts(s, "output "); + if (ADM1266_GPIO_OPEN_DRAIN(gpio_config)) + seq_puts(s, "open-drain )\n"); + else + seq_puts(s, "push-pull )\n"); + } + + write_cmd = 0xFF; + ret = nh_adm1266_pmbus_block_xfer(data, ADM1266_PDIO_CONFIG, 1, &write_cmd, read_buf); + if (ret != 32) + return; + + for (i = 0; i < ADM1266_PDIO_NR; i++) { + seq_puts(s, nh_adm1266_names[ADM1266_GPIO_NR + i]); + + pdio_config = read_buf[2 * i]; + pdio_config += (read_buf[2 * i + 1] << 8); + pin_cfg = ADM1266_PDIO_PIN_CFG(pdio_config); + + seq_puts(s, " ( "); + if (!pin_cfg || pin_cfg > 5) { + seq_puts(s, "high-Z )\n"); + continue; + } + + if (pin_cfg & BIT(0)) + seq_puts(s, "output "); + + if (pin_cfg & BIT(1)) + seq_puts(s, "input "); + + seq_puts(s, ")\n"); + } +} + +static int nh_adm1266_config_gpio(struct nh_adm1266_data *data) +{ + const char *name = dev_name(&data->client->dev); + char *gpio_name; + int ret; + int i; + + for (i = 0; i < ARRAY_SIZE(data->gpio_names); i++) { + gpio_name = devm_kasprintf(&data->client->dev, GFP_KERNEL, "nh_adm1266-%x-%x-%s", + data->client->adapter->nr, data->client->addr, nh_adm1266_names[i]); + if (!gpio_name) + return -ENOMEM; + + data->gpio_names[i] = gpio_name; + } + + data->gc.label = name; + data->gc.parent = &data->client->dev; + data->gc.owner = THIS_MODULE; + data->gc.can_sleep = true; + data->gc.base = -1; + data->gc.names = data->gpio_names; + data->gc.ngpio = ARRAY_SIZE(data->gpio_names); + data->gc.get = nh_adm1266_gpio_get; + data->gc.get_multiple = nh_adm1266_gpio_get_multiple; + data->gc.dbg_show = nh_adm1266_gpio_dbg_show; + + ret = devm_gpiochip_add_data(&data->client->dev, &data->gc, data); + if (ret) + dev_err(&data->client->dev, "GPIO registering failed (%d)\n", ret); + + return ret; +} + +static int nh_adm1266_state_read(struct seq_file *s, void *pdata) +{ + struct device *dev = s->private; + struct i2c_client *client = to_i2c_client(dev); + int ret; + + ret = i2c_smbus_read_word_data(client, ADM1266_READ_STATE); + if (ret < 0) + return ret; + + seq_printf(s, "%d\n", ret); + + return 0; +} + +static void nh_adm1266_init_debugfs(struct nh_adm1266_data *data) +{ + struct dentry *root; + + root = nh_pmbus_get_debugfs_dir(data->client); + if (!root) + return; + + data->debugfs_dir = debugfs_create_dir(data->client->name, root); + + debugfs_create_devm_seqfile(&data->client->dev, "sequencer_state", data->debugfs_dir, + nh_adm1266_state_read); +} + +static int nh_adm1266_nvmem_read_blackbox(struct nh_adm1266_data *data, u8 *read_buff) +{ + int record_count; + u8 index; + u8 buf[32]; + int ret; + struct i2c_msg msgs[2]; + u8 write_buf[3]; + + /* + * Step 1: Read blackbox info to get record count + * Reference: i2c_block_write_block_read(addr, 1, [0xE6], 4, buf) + */ + write_buf[0] = ADM1266_BLACKBOX_INFO; + + msgs[0].addr = data->client->addr; + msgs[0].flags = 0; + msgs[0].len = 1; + msgs[0].buf = write_buf; + + msgs[1].addr = data->client->addr; + msgs[1].flags = I2C_M_RD; + msgs[1].len = 5; + msgs[1].buf = buf; + + ret = i2c_transfer(data->client->adapter, msgs, 2); + if (ret != 2) { + dev_err(&data->client->dev, "Failed to read blackbox info: %d", + ret); + return ret < 0 ? ret : -EIO; + } + + /* buf[0] is length, must be 0x04 per spec */ + if (buf[0] != 0x04) { + dev_warn(&data->client->dev, + "Unexpected blackbox info len: 0x%02x", buf[0]); + return -1; + } + + index = buf[3]; + record_count = buf[4]; + + for (int count = 0; count < record_count; count++) { + u8 r_data[ADM1266_BLACKBOX_SIZE + 1]; + + write_buf[0] = ADM1266_READ_BLACKBOX; + write_buf[1] = 0x01; + write_buf[2] = index; + + msgs[0].addr = data->client->addr; + msgs[0].flags = 0; + msgs[0].len = 3; + msgs[0].buf = write_buf; + + msgs[1].addr = data->client->addr; + msgs[1].flags = I2C_M_RD; + msgs[1].len = sizeof(r_data); + msgs[1].buf = r_data; + + ret = i2c_transfer(data->client->adapter, msgs, 2); + if (ret != 2) { + dev_err(&data->client->dev, + "Failed to read record %d: %d", index, ret); + return ret < 0 ? ret : -EIO; + } + + if (r_data[0] != ADM1266_BLACKBOX_SIZE) { + dev_err(&data->client->dev, + "Invalid data length for blackbox record index=%d, len=%d", index, r_data[0]); + } else { + /* skip the first byte which is the length */ + memcpy(read_buff, r_data + 1, ADM1266_BLACKBOX_SIZE); + /* Clear unused/reserved bits */ + u8 vpx_hi_reserved = 0xE0; + + read_buff[11] &= ~vpx_hi_reserved; + read_buff[13] &= ~vpx_hi_reserved; + + u8 gpio_low_reserved = 0x38; + u8 gpio_hi_reserved = 0xf0; + + read_buff[14] &= ~gpio_low_reserved; + read_buff[15] &= ~gpio_hi_reserved; + + read_buff[16] &= ~gpio_low_reserved; + read_buff[17] &= ~gpio_hi_reserved; + + read_buff += ADM1266_BLACKBOX_SIZE; + } + index = (index - 1) & (ADM1266_BLACKBOX_MAX_RECORDS - 1); + } + + return 0; +} + +static int nh_adm1266_nvmem_read(void *priv, unsigned int offset, void *val, size_t bytes) +{ + struct nh_adm1266_data *data = priv; + int ret; + + if (offset + bytes > data->nvmem_config.size) + return -EINVAL; + + if (offset == 0) { + memset(data->dev_mem, 0, data->nvmem_config.size); + + ret = nh_adm1266_nvmem_read_blackbox(data, data->dev_mem); + if (ret) { + dev_err(&data->client->dev, "Could not read blackbox!"); + return ret; + } + } + + memcpy(val, data->dev_mem + offset, bytes); + + return 0; +} + +static int nh_adm1266_nvmem_clear(void *priv, unsigned int offset, void *val, + size_t bytes) +{ + struct nh_adm1266_data *data = priv; + int ret; + struct i2c_msg msgs[1]; + u8 write_buf[4]; + + if (data == NULL) { + return -1; + } + + write_buf[0] = ADM1266_READ_BLACKBOX; // 0xDE + write_buf[1] = 2; // The number of bytes + write_buf[2] = 0xFE; // Clear command + write_buf[3] = 0x00; // Parameter + + msgs[0].addr = data->client->addr; + msgs[0].flags = 0; + msgs[0].len = 4; + msgs[0].buf = write_buf; + + ret = i2c_transfer(data->client->adapter, msgs, 1); + if (ret != 1) { + dev_err(&data->client->dev, "Failed to clear blackbox: %d\n", + ret); + ret = ret < 0 ? ret : -EIO; + } else { + dev_info(&data->client->dev, "Blackbox cleared successfully\n"); + ret = 0; + } + return ret; +} + +static int nh_adm1266_config_nvmem(struct nh_adm1266_data *data) +{ + data->nvmem_config.name = dev_name(&data->client->dev); + data->nvmem_config.dev = &data->client->dev; + data->nvmem_config.root_only = true; + data->nvmem_config.read_only = false; /* enable clear */ + data->nvmem_config.owner = THIS_MODULE; + data->nvmem_config.reg_read = nh_adm1266_nvmem_read; + data->nvmem_config.reg_write = nh_adm1266_nvmem_clear; + data->nvmem_config.cells = nh_adm1266_nvmem_cells; + data->nvmem_config.ncells = ARRAY_SIZE(nh_adm1266_nvmem_cells); + data->nvmem_config.priv = data; + data->nvmem_config.stride = 1; + data->nvmem_config.word_size = 1; + data->nvmem_config.size = nh_adm1266_nvmem_cells[0].bytes; + + data->dev_mem = devm_kzalloc(&data->client->dev, data->nvmem_config.size, GFP_KERNEL); + if (!data->dev_mem) + return -ENOMEM; + + data->nvmem = devm_nvmem_register(&data->client->dev, &data->nvmem_config); + if (IS_ERR(data->nvmem)) { + dev_err(&data->client->dev, "Could not register nvmem!"); + return PTR_ERR(data->nvmem); + } + + return 0; +} + +static int nh_adm1266_set_rtc(struct nh_adm1266_data *data) +{ + time64_t kt; + char write_buf[6]; + int i; + + kt = ktime_get_seconds(); + + memset(write_buf, 0, sizeof(write_buf)); + + for (i = 0; i < 4; i++) + write_buf[2 + i] = (kt >> (i * 8)) & 0xFF; + + return i2c_smbus_write_block_data(data->client, ADM1266_SET_RTC, sizeof(write_buf), + write_buf); +} + +static int nh_adm1266_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct nh_adm1266_data *data; + int ret; + int i; + + data = devm_kzalloc(&client->dev, sizeof(struct nh_adm1266_data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + data->client = client; + data->info.pages = 17; + data->info.format[PSC_VOLTAGE_OUT] = linear; + for (i = 0; i < data->info.pages; i++) + data->info.func[i] = PMBUS_HAVE_VOUT | PMBUS_HAVE_STATUS_VOUT; + + crc8_populate_msb(pmbus_crc_table, 0x7); + mutex_init(&data->buf_mutex); + + ret = nh_adm1266_config_gpio(data); + if (ret < 0) + return ret; + + ret = nh_adm1266_set_rtc(data); + if (ret < 0) + return ret; + + ret = nh_adm1266_config_nvmem(data); + if (ret < 0) + return ret; + + ret = nh_pmbus_do_probe(client, &data->info); + if (ret) + return ret; + + nh_adm1266_init_debugfs(data); + + return 0; +} + +static const struct of_device_id nh_adm1266_of_match[] = { + { .compatible = "adi,nh_adm1266" }, + { } +}; +MODULE_DEVICE_TABLE(of, nh_adm1266_of_match); + +static const struct i2c_device_id nh_adm1266_id[] = { + { "nh_adm1266" }, + { } +}; +MODULE_DEVICE_TABLE(i2c, nh_adm1266_id); + +static struct i2c_driver nh_adm1266_driver = { + .driver = { + .name = "nh_adm1266", + .of_match_table = nh_adm1266_of_match, + }, + .probe = nh_adm1266_probe, + .id_table = nh_adm1266_id, +}; + +module_i2c_driver(nh_adm1266_driver); + +MODULE_AUTHOR("Alexandru Tachici "); +MODULE_DESCRIPTION("PMBus driver for Analog Devices ADM1266"); +MODULE_LICENSE("GPL v2"); +MODULE_IMPORT_NS(PMBUS); diff --git a/platform/broadcom/sonic-platform-modules-nexthop/common/modules/nh_isl68137.c b/platform/broadcom/sonic-platform-modules-nexthop/common/modules/nh_isl68137.c index 24197a5bff5..3f3c357479c 100644 --- a/platform/broadcom/sonic-platform-modules-nexthop/common/modules/nh_isl68137.c +++ b/platform/broadcom/sonic-platform-modules-nexthop/common/modules/nh_isl68137.c @@ -66,6 +66,8 @@ enum chips { raa228004, raa228006, raa228228, + raa228234, + raa228236, raa229001, raa229004, }; @@ -318,6 +320,8 @@ static const struct i2c_device_id raa_dmpvr_id[] = { {"nh_raa228004", raa_dmpvr2_hv}, {"nh_raa228006", raa_dmpvr2_hv}, {"nh_raa228228", raa_dmpvr2_2rail_nontc}, + {"nh_raa228234", raa_dmpvr2_2rail_nontc}, + {"nh_raa228236", raa_dmpvr2_2rail_nontc}, {"nh_raa229001", raa_dmpvr2_2rail}, {"nh_raa229004", raa_dmpvr2_2rail}, {} diff --git a/platform/broadcom/sonic-platform-modules-nexthop/common/modules/nh_pmbus_core.c b/platform/broadcom/sonic-platform-modules-nexthop/common/modules/nh_pmbus_core.c index 2c8b339e5a8..58019ef25f1 100644 --- a/platform/broadcom/sonic-platform-modules-nexthop/common/modules/nh_pmbus_core.c +++ b/platform/broadcom/sonic-platform-modules-nexthop/common/modules/nh_pmbus_core.c @@ -3185,9 +3185,14 @@ EXPORT_SYMBOL_NS_GPL(nh_pmbus_get_debugfs_dir, PMBUS); static int __init pmbus_core_init(void) { - pmbus_debugfs_dir = debugfs_create_dir("pmbus", NULL); - if (IS_ERR(pmbus_debugfs_dir)) - pmbus_debugfs_dir = NULL; + struct dentry *d = debugfs_lookup("pmbus", NULL); + if (!d) { + pmbus_debugfs_dir = debugfs_create_dir("pmbus", NULL); + if (IS_ERR(pmbus_debugfs_dir)) + pmbus_debugfs_dir = NULL; + } else { + dput(d); + } return 0; } diff --git a/platform/broadcom/sonic-platform-modules-nexthop/common/nexthop/eeprom_utils.py b/platform/broadcom/sonic-platform-modules-nexthop/common/nexthop/eeprom_utils.py index 6526d46bd29..a982455699c 100644 --- a/platform/broadcom/sonic-platform-modules-nexthop/common/nexthop/eeprom_utils.py +++ b/platform/broadcom/sonic-platform-modules-nexthop/common/nexthop/eeprom_utils.py @@ -5,6 +5,13 @@ import click import sys import struct +import subprocess +import errno + +from dataclasses import dataclass +from enum import Enum +from nexthop.platform_utils import run_cmd, run_and_report + try: from sonic_eeprom import eeprom_tlvinfo @@ -13,50 +20,319 @@ NEXTHOP_IANA = "63074" NEXTHOP_IANA_SIZE = 4 # IANA is 4 bytes -CUSTOM_FIELD_CODE_SIZE = 1 # Custom field code is 1 byte -CUSTOM_SECONDARY_SERIAL_NUM_CODE = 0x01 VENDOR_EXT_STR = "Vendor Extension" + +class CustomField(Enum): + """ + Enum for Nexthop custom EEPROM fields used for "Vendor Extension" + TLV programming and decoding. + """ + + SECONDARY_SERIAL_NUMBER = (0x01, "Custom Serial Number") + REGULATORY_MODEL_NUMBER = (0x02, "Regulatory Model Number") + + def __init__(self, code, display_name): + self.code = code + self.display_name = display_name + + @classmethod + def get_by_code(cls, code): + for field in cls: + if field.code == code: + return field + return None + + +@dataclass +class CustomFieldStruct: + iana: bytearray + code: int + payload: bytearray + + +def big_endian_to_int(bytes: bytearray) -> int: + return struct.unpack(">I", bytes)[0] + + +def tlv_to_custom_field_struct(t: bytearray) -> tuple[CustomFieldStruct | None, str]: + """ + Parses the given TLV in the form of bytes into a CustomFieldStruct. + Returns (None, error_message) if the given TLV bytes is not a valid Vendor Extension TLV. + + Vendor Extension TLV schema: + Byte | Name + ------------- + 0 | Type + 1 | Payload length (including IANA, Custom field code, and Custom payload) + 2-5 | IANA + 6 | Custom field code + 7+ | Custom payload (variable length) + """ + # Check minimum TLV length (1 + 1 + 4 + 1 = 7 bytes minimum) + if len(t) < 7: + return None, "Invalid format - too short" + + if t[0] != eeprom_tlvinfo.TlvInfoDecoder._TLV_CODE_VENDOR_EXT: + return None, "Not a Vendor Extension TLV" + + # Check minimum payload length (4 + 1 = 5 bytes minimum) + if t[1] < 5: + return None, "Invalid payload length - too short" + + # Parse the structure + iana_bytes = t[2:6] + custom_field_code = t[6] + payload = t[7 : 2 + t[1]] + # ============= FOR BACKWARD COMPATIBILITY ============= + # Some early units may have a garbage value at byte 2 + # of the "Custom Serial Number" (code 0x01) TLV. So, + # IANA, custom field code, and custom payload are all + # shifted right by 1 byte. This special check is so we + # can decode the "Custom Serial Number" for those units. + # Although, the value of payload length at byte 1 is + # still correct. + if ( + big_endian_to_int(iana_bytes) != int(NEXTHOP_IANA) + and len(t) >= 8 + and t[1] >= 6 + and big_endian_to_int(t[3:7]) == int(NEXTHOP_IANA) + and t[7] == CustomField.SECONDARY_SERIAL_NUMBER.code + ): + iana_bytes = t[3:7] + custom_field_code = t[7] + payload = t[8 : 2 + t[1]] + # ====================================================== + return CustomFieldStruct(iana_bytes, custom_field_code, payload), "" + + +class NexthopEepromDecodeVisitor(eeprom_tlvinfo.EepromDecodeVisitor): + """ + Custom visitor class, which lengthen the "TLV Name" column to 25 characters. + """ + def visit_header(self, eeprom_id, version, header_length): + if eeprom_id is not None: + print("TlvInfo Header:") + print(" Id String: %s" % eeprom_id) + print(" Version: %d" % version) + print(" Total Length: %d" % header_length) + print("TLV Name Code Len Value") + print("------------------------- ---- --- -----") + + def visit_tlv(self, name, code, length, value): + print("%-25s 0x%02X %3d %s" % (name, code, length, value)) + + class Eeprom(eeprom_tlvinfo.TlvInfoDecoder): def decoder(self, s, t): + # Vendor Extension TLV schema: + # Byte | Name + # ------------- + # 0 | Type + # 1 | Payload length (including IANA, Custom field code, and Custom payload) + # 2-5 | IANA + # 6 | Custom field code + # 7+ | Custom payload (variable length) if t[0] != self._TLV_CODE_VENDOR_EXT: return eeprom_tlvinfo.TlvInfoDecoder.decoder(self, s, t) - custom_data = t[2:2 + t[1]] - - # Check minimum length (1 + 4 + 1 = 6 bytes minimum) - if len(custom_data) < 6: - name = VENDOR_EXT_STR - return name, "Invalid format - too short" - # Parse the structure - iana_bytes = custom_data[1:5] # 4 bytes for IANA - custom_field_code = custom_data[5] - - # Verify IANA (convert 4 bytes to integer, big-endian) - iana_value = struct.unpack('>I', iana_bytes)[0] - expected_iana = int(NEXTHOP_IANA) + custom_field_struct, err = tlv_to_custom_field_struct(t) + if custom_field_struct is None: + name = VENDOR_EXT_STR + return name, err - if iana_value != expected_iana: + # Verify IANA + iana = big_endian_to_int(custom_field_struct.iana) + if iana != int(NEXTHOP_IANA): name = VENDOR_EXT_STR - return name, f"Invalid IANA: {iana_value}, expected {expected_iana}" + return ( + name, + f"Invalid IANA: {iana}, expected {NEXTHOP_IANA}", + ) # Verify custom field code - if custom_field_code != CUSTOM_SECONDARY_SERIAL_NUM_CODE: + custom_field = CustomField.get_by_code(custom_field_struct.code) + if custom_field is None: name = VENDOR_EXT_STR - return name, f"Invalid field code: 0x{custom_field_code:02x}" + return name, f"Invalid field code: 0x{custom_field_struct.code:02x}" # Extract and decode the actual payload - payload = custom_data[6:] - custom_value = payload.decode("utf-8", errors="replace") - name = "Custom Serial Number" + custom_value = custom_field_struct.payload.decode("utf-8", errors="replace") + name = custom_field.display_name return name, custom_value + def _encode_arg_to_tlv_bytes(self, arg: str) -> bytearray: + """ + Convert a string in the format of "{type} = {payload}", where payload is + space-separated hexidecimal numbers, to a TLV bytearray consisting of + type (1 byte) + payload length (1 byte) + payload (variable length). + """ + type, payload = arg.split("=") + type = int(type.strip(), base=0) + payload = payload.strip() + tlv = self.encoder((type,), payload) + return tlv + + def _find_tlv_vendor_ext_start_offset( + self, e: bytearray, iana: bytearray, custom_field_code: int + ) -> int | None: + """ + If exists in the given EEPROM data, returns the start index of the + Vendor Extension TLV which contains the given IANA (bytes [2,5]) and + the given custom field code (6th byte). + Returns None if not found. + """ + tlv_start = 0 + # Iterate through TLVs until we find the matching Vendor Extension TLV + while tlv_start < len(e) and self.is_valid_tlv(e[tlv_start:]): + # Check if this is the Vendor Extension TLV we're looking for. + tlv_end = tlv_start + 2 + e[tlv_start + 1] + custom_field_struct, _ = tlv_to_custom_field_struct(e[tlv_start:tlv_end]) + if ( + custom_field_struct is not None + and custom_field_struct.iana == iana + and custom_field_struct.code == custom_field_code + ): + return tlv_start + + # Move to the next TLV. + tlv_start = tlv_end + return None + + def _remove_header_and_checksum_tlv(self, e: bytearray) -> bytearray: + """ + Returns the given EEPROM data with the header and the checksum TLV removed. + """ + # Skip header. + tlv_start = 0 + if self._TLV_HDR_ENABLED: + tlv_start = self._TLV_INFO_HDR_LEN + total_length = (e[9] << 8) | e[10] + e_end = self._TLV_INFO_HDR_LEN + total_length + else: + tlv_start = self.eeprom_start + e_end = min(self._TLV_INFO_MAX_LEN, self.eeprom_max_len) + + # Include all TLVs but not the checksum TLV which is always the last TLV. + # TLV schema: + # Byte | Name + # ------------ + # 0 | Type + # 1 | Payload length + # 2+ | Payload (variable length) + new_e = bytearray() + while ( + tlv_start < len(e) + and tlv_start < e_end + and self.is_valid_tlv(e[tlv_start:]) + and e[tlv_start] != self._TLV_CODE_CRC_32 + ): + tlv_end = tlv_start + 2 + e[tlv_start + 1] + new_e += e[tlv_start:tlv_end] + tlv_start = tlv_end + return new_e + + def set_eeprom(self, e: bytearray, cmd_args: list[str]) -> bytearray: + """ + Overrides parent class method to support multiple vendor extension TLVs + with the same type (0xFD) but different IANA + custom field code. + For example, Nexthop's "Custom Serial Number" (0x01) and + "Regulatory Model Number" (0x02) can co-exist even though they + share the same type (0xFD). + + Returns the new contents of the EEPROM where the given `cmd_args` are applied + to the given EEPROM data `e`. Each command must be in the format of + "{type} = {payload}", where payload is space-separated hexidecimal numbers + and type must be parsable into an integer. + """ + # Split commands into two lists: one for vendor ext, one for everything else. + cmd_args_for_vendor_ext = [] + cmd_args_without_vendor_ext = [] + for arg_str in cmd_args: + for arg in arg_str.split(","): + tlv_bytes = self._encode_arg_to_tlv_bytes(arg) + # type is at 0th byte + if tlv_bytes[0] == self._TLV_CODE_VENDOR_EXT: + cmd_args_for_vendor_ext.append(arg) + else: + cmd_args_without_vendor_ext.append(arg) + + # Use parent class to set non-vendor ext TLV (where duplicate type is not allowed). + if cmd_args_without_vendor_ext: + click.secho("EEPROM data with updated fields:", fg="green") + e = eeprom_tlvinfo.TlvInfoDecoder.set_eeprom( + self, e, cmd_args_without_vendor_ext + ) + + if not cmd_args_for_vendor_ext: + return e + + # Remove header and checksum which will be re-calculated and re-added later + e = self._remove_header_and_checksum_tlv(e) + # Set vendor ext TLVs. Duplicate type (0xFD) is allowed, + # but duplicate (IANA + custom field code) is not allowed + # and will be overwritten. + for arg in cmd_args_for_vendor_ext: + tlv_bytes = self._encode_arg_to_tlv_bytes(arg) + old_tlv_start = self._find_tlv_vendor_ext_start_offset( + e, iana=tlv_bytes[2:6], custom_field_code=tlv_bytes[6] + ) + if old_tlv_start is not None: + # Replace existing TLV with new one + # TLV schema: + # Byte | Name + # ------------ + # 0 | Type + # 1 | Payload length + # 2+ | Payload (variable length) + old_tlv_end = old_tlv_start + 2 + e[old_tlv_start + 1] + e = e[:old_tlv_start] + tlv_bytes + e[old_tlv_end:] + else: + e += tlv_bytes + # Add back header + if self._TLV_HDR_ENABLED: + # Assuming CRC-32 is used, its length is 6 bytes (type + length + 4-byte value) + total_len = len(e) + 6 + # Header schema: + # Byte | Name + # ------------ + # 0-7 | ID String + # 8 | Header version + # 9-10 | Total length (for the bytes to follow; not including header) + e = ( + self._TLV_INFO_ID_STRING + + bytearray([self._TLV_INFO_VERSION]) + + bytearray([(total_len >> 8) & 0xFF, total_len & 0xFF]) + + e + ) + # Add back checksum TLV. We assume CRC-32 is used, so it matches the length in the header. + # Checksum is calculated from the start of header to the end of checksum TL but not V. + assert self._TLV_CODE_CRC_32 != self._TLV_CODE_UNDEFINED + e = e + bytearray([self._TLV_CODE_CRC_32]) + bytearray([4]) + e += self.encode_checksum(self.calculate_checksum(e)) + + # Print out the contents. + click.secho("EEPROM data with updated vendor extensions:", fg="green") + self.decode_eeprom(e) + + if len(e) > min(self._TLV_INFO_MAX_LEN, self.eeprom_max_len): + click.secho( + f"\nERROR: There is not enough room in the EEPROM to save data.\n", + fg="red", + ) + sys.exit(1) + + return e + + def decode_eeprom(self, e): + visitor = NexthopEepromDecodeVisitor() + self.visit_eeprom(e, visitor) + def format_vendor_ext(custom_payload, custom_field_code): """ Format vendor extension field according to Nexthop specification: - - Total bytes of custom payload (1 byte) - NEXTHOP IANA (4 bytes) - Custom field code (1 byte) - Custom payload (variable length) @@ -73,29 +349,21 @@ def format_vendor_ext(custom_payload, custom_field_code): if not isinstance(custom_payload, bytes): raise TypeError("custom_payload must be bytes") - payload_bytes = custom_payload - - # Calculate total bytes: IANA (4) + custom field code (1) + payload length - payload_len = len(payload_bytes) - # Build the vendor extension data vendor_ext_data = bytearray() - # Add total bytes (1 byte) - vendor_ext_data.append(payload_len) - # Add NEXTHOP IANA (4 bytes) - convert string to integer then to 4 bytes iana_int = int(NEXTHOP_IANA) - vendor_ext_data.extend(struct.pack('>I', iana_int)) # Big-endian 4-byte integer + vendor_ext_data.extend(struct.pack(">I", iana_int)) # Big-endian 4-byte integer # Add custom field code (1 byte) vendor_ext_data.append(custom_field_code & 0xFF) # Add custom payload - vendor_ext_data.extend(payload_bytes) + vendor_ext_data.extend(custom_payload) # Convert to hex string format expected by eeprom_tlvinfo - return ' '.join(f'0x{b:02x}' for b in vendor_ext_data) + return " ".join(f"0x{b:02x}" for b in vendor_ext_data) def get_at24_eeprom_paths(root=""): @@ -119,20 +387,30 @@ def echo_available_eeproms(): for eeprom_path in get_at24_eeprom_paths(): click.secho(f"{eeprom_path}", fg="green") + def complete_available_eeproms(ctx, args, incomplete): eeproms = get_at24_eeprom_paths() return [eeprom for eeprom in eeproms if eeprom.startswith(incomplete)] def decode_eeprom(eeprom_path: str): - eeprom_class = Eeprom( - eeprom_path, start=0, status="", ro=True - ) + eeprom_class = Eeprom(eeprom_path, start=0, status="", ro=True) eeprom = eeprom_class.read_eeprom() # will print out contents eeprom_class.decode_eeprom(eeprom) +def clear_syseeprom_cache(): + """ syseeprom cache cleanup and service restart""" + cache_path = "/var/cache/sonic/decode-syseeprom/syseeprom_cache" + + if os.path.exists(cache_path): + run_and_report("Remove syseeprom cache", f"rm {cache_path}") + + run_and_report("Remove syseeprom cache from pmon", f'docker exec pmon bash -c "rm -f {cache_path}"') + run_and_report("Restart syseepromd", 'docker exec pmon bash -c "supervisorctl restart syseepromd"') + + def check_root_privileges(): if os.getuid() != 0: click.secho("Root privileges required for this operation", fg="red") @@ -151,11 +429,10 @@ def program_eeprom( manufacturer_name, vendor_name, service_tag, - custom_serial_number + custom_serial_number, + regulatory_model_number, ): - eeprom_class = Eeprom( - eeprom_path, start=0, status="", ro=True - ) + eeprom_class = Eeprom(eeprom_path, start=0, status="", ro=True) tmp_contents = eeprom_class.read_eeprom() cmds = [] if product_name is not None: @@ -178,12 +455,20 @@ def program_eeprom( cmds.append(f"{eeprom_class._TLV_CODE_VENDOR_NAME} = {vendor_name}") if service_tag is not None: cmds.append(f"{eeprom_class._TLV_CODE_SERVICE_TAG} = {service_tag}") + + # Vendor extension fields. See Nexthop custom EEPROM fields in `CustomField` enum above. if custom_serial_number is not None: - # Format vendor_ext according to Nexthop custom serial number specification - custom_serial_number_bytes = custom_serial_number.encode('utf-8') - formatted_vendor_ext_with_custom_serial_number = \ - format_vendor_ext(custom_serial_number_bytes, CUSTOM_SECONDARY_SERIAL_NUM_CODE) - cmds.append(f"{eeprom_class._TLV_CODE_VENDOR_EXT} = {formatted_vendor_ext_with_custom_serial_number}") + payload_hex_str = format_vendor_ext( + custom_serial_number.encode("utf-8"), + CustomField.SECONDARY_SERIAL_NUMBER.code, + ) + cmds.append(f"{eeprom_class._TLV_CODE_VENDOR_EXT} = {payload_hex_str}") + if regulatory_model_number is not None: + payload_hex_str = format_vendor_ext( + regulatory_model_number.encode("utf-8"), + CustomField.REGULATORY_MODEL_NUMBER.code, + ) + cmds.append(f"{eeprom_class._TLV_CODE_VENDOR_EXT} = {payload_hex_str}") tmp_contents = eeprom_class.set_eeprom(tmp_contents, cmds) @@ -233,7 +518,16 @@ def decode_all(): @click.option("--manufacturer-name", default=None) @click.option("--vendor-name", default=None) @click.option("--service-tag", default=None) -@click.option("--custom-serial-number", default=None, help="Custom serial number embedded in vendor extension") +@click.option( + "--custom-serial-number", + default=None, + help="Custom serial number embedded in vendor extension", +) +@click.option( + "--regulatory-model-number", + default=None, + help="Regulatory model number embedded in vendor extension", +) def program( eeprom_path, product_name, @@ -246,7 +540,8 @@ def program( manufacturer_name, vendor_name, service_tag, - custom_serial_number + custom_serial_number, + regulatory_model_number, ): check_root_privileges() program_eeprom( @@ -261,8 +556,10 @@ def program( manufacturer_name, vendor_name, service_tag, - custom_serial_number + custom_serial_number, + regulatory_model_number, ) + clear_syseeprom_cache() @cli.command("clear") diff --git a/platform/broadcom/sonic-platform-modules-nexthop/common/nexthop/fpga_cli.py b/platform/broadcom/sonic-platform-modules-nexthop/common/nexthop/fpga_cli.py index 7ee63d875e8..2f6ac71904b 100644 --- a/platform/broadcom/sonic-platform-modules-nexthop/common/nexthop/fpga_cli.py +++ b/platform/broadcom/sonic-platform-modules-nexthop/common/nexthop/fpga_cli.py @@ -5,6 +5,7 @@ import re import sys import click +import json from nexthop.fpga_lib import ( find_xilinx_fpgas, @@ -13,10 +14,13 @@ max_value_for_bit_range, get_field, overwrite_field, + bdf_to_name, + name_to_bdf, ) - +from nexthop.pddf_config_parser import load_pddf_device_config def check_root_privileges(): + """Check if the current user has root privileges and exit if not.""" if os.getuid() != 0: click.secho("Root privileges required for this operation", fg="red") sys.exit(1) @@ -24,9 +28,17 @@ def check_root_privileges(): def echo_available_fpgas(): xilinx_fpgas = find_xilinx_fpgas() - click.secho("Use one of the following:", fg="cyan") - for xilinx_fpga in xilinx_fpgas: - click.secho(f"{xilinx_fpga}", fg="green") + pddf_config = load_pddf_device_config() + click.secho("Available FPGAs (you can use either NAME or PCIe ADDRESS):", fg="cyan") + click.secho(f"{'NAME':<32} PCIe ADDRESS", fg="cyan") + click.secho(f"{'-' * 32} {'-' * 13}", fg="cyan") + + for fpga_bdf in xilinx_fpgas: + device_name = bdf_to_name(fpga_bdf, pddf_config) + if device_name: + click.secho(f"{device_name:<32} {fpga_bdf}", fg="green") + else: + click.secho(f"{'UNKNOWN':<32} {fpga_bdf}", fg="yellow") def check_valid_pci_address(pci_address): @@ -105,18 +117,50 @@ def cli(): check_root_privileges() -def click_argument_pci_address(): - "Returns a click.argument with shell autocomplete to hint available FPGAs on the system." +def complete_available_fpga_names(ctx, args, incomplete): + xilinx_fpgas = find_xilinx_fpgas() + pddf_config = load_pddf_device_config() + fpga_names = [] + + for fpga_bdf in xilinx_fpgas: + device_name = bdf_to_name(fpga_bdf, pddf_config) + if device_name: + fpga_names.append(device_name) + + incomplete_lower = incomplete.lower() + return [name for name in fpga_names if name.lower().startswith(incomplete_lower)] + + +class FpgaNameOrAddress(click.ParamType): + name = "fpga_name_or_address" + + def convert(self, value, param, ctx) -> str: + # First check if it's already a valid PCI address + xilinx_fpgas = find_xilinx_fpgas() + if value in xilinx_fpgas: + return value + + # Try to convert from name to BDF + pci_address = name_to_bdf(value) + if pci_address: + return pci_address + + # If neither works, show error with available options + self.fail(f"FPGA '{value}' not found. Use 'fpga list' to see available FPGAs.", param, ctx) + + +def click_argument_target_fpga(): + "Returns a click.argument with shell autocomplete to hint available FPGA names on the system." # click version 8.0 renamed `autocompletion` to `shell_complete`. # This is to support both old versions and new versions. if hasattr(click.Parameter, "shell_complete"): - return click.argument("pci_address", shell_complete=complete_available_fpgas) + return click.argument("pci_address", type=FpgaNameOrAddress(), shell_complete=complete_available_fpga_names) else: - return click.argument("pci_address", autocompletion=complete_available_fpgas) - + return click.argument("pci_address", type=FpgaNameOrAddress(), autocompletion=complete_available_fpga_names) + @cli.command("write32") -@click_argument_pci_address() +@click_argument_target_fpga() @click.argument("offset", type=AlignedOffset()) @click.argument("value") @click.option( @@ -126,6 +170,11 @@ def click_argument_pci_address(): help="Inclusive range of bits to write to (e.g., '0:31').", ) def write32(pci_address, offset, value, bits): + """Write 32-bit value to FPGA register. + + TARGET_FPGA can be either the FPGA name (e.g., 'SWITCHCARD_FPGA') or + PCIe address (e.g., '0000:e4:00.0'). Use 'fpga list' to see available options. + """ value = int(value, 16) check_value_fits_in_bit_range(value, bits) check_valid_pci_address(pci_address) @@ -137,7 +186,7 @@ def write32(pci_address, offset, value, bits): @cli.command("read32") -@click_argument_pci_address() +@click_argument_target_fpga() @click.argument("offset", type=AlignedOffset()) @click.option( "--bits", @@ -146,6 +195,11 @@ def write32(pci_address, offset, value, bits): help="Inclusive range of bits to read from (e.g., '0:31').", ) def read32(offset, pci_address, bits): + """Read 32-bit value from FPGA register. + + TARGET_FPGA can be either the FPGA name (e.g., 'CPU_CARD_FPGA') or + PCIe address (e.g., '0000:e3:00.0'). Use 'fpga list' to see available options. + """ check_valid_pci_address(pci_address) val = read_32(pci_address, offset) val = get_field(val, bits) diff --git a/platform/broadcom/sonic-platform-modules-nexthop/common/nexthop/fpga_lib.py b/platform/broadcom/sonic-platform-modules-nexthop/common/nexthop/fpga_lib.py index 61282d7f299..7b95dbde73c 100644 --- a/platform/broadcom/sonic-platform-modules-nexthop/common/nexthop/fpga_lib.py +++ b/platform/broadcom/sonic-platform-modules-nexthop/common/nexthop/fpga_lib.py @@ -4,7 +4,44 @@ import ctypes import mmap import os +import json + from typing import Union +from nexthop.pddf_config_parser import load_pddf_device_config + + +def bdf_to_name(device_bdf, pddf_config=None): + """ Get device name for a given BDF address """ + + if pddf_config is None: + pddf_config = load_pddf_device_config() + + for device_config in pddf_config.values(): + if isinstance(device_config, dict) and 'dev_info' in device_config: + dev_info = device_config['dev_info'] + + if (dev_info.get('device_type') == 'MULTIFPGAPCIE' and + dev_info.get('device_bdf') == device_bdf): + return dev_info.get('device_name') + + return None + + +def name_to_bdf(device_name, pddf_config=None): + """ Get BDF address for a given device name """ + + if pddf_config is None: + pddf_config = load_pddf_device_config() + + for device_config in pddf_config.values(): + if isinstance(device_config, dict) and 'dev_info' in device_config: + dev_info = device_config['dev_info'] + + if (dev_info.get('device_type') == 'MULTIFPGAPCIE' and + dev_info.get('device_name') == device_name): + return dev_info.get('device_bdf') + + return None def find_pci_devices(vendor_id: int, device_id: Union[int, None], root="") -> list[str]: @@ -49,7 +86,10 @@ def write_32(pci_address: str, offset: int, val: int, root=""): aligned_offset = offset & ~(page_size - 1) offset_in_page = offset - aligned_offset mm = mmap.mmap( - f.fileno(), length=page_size, offset=aligned_offset, access=mmap.ACCESS_WRITE + f.fileno(), + length=page_size, + offset=aligned_offset, + access=mmap.ACCESS_WRITE, ) mm_buf = (ctypes.c_char * page_size).from_buffer(mm) base_ptr = ctypes.cast(mm_buf, ctypes.POINTER(ctypes.c_uint32)) diff --git a/platform/broadcom/sonic-platform-modules-nexthop/common/nexthop/pddf_config_parser.py b/platform/broadcom/sonic-platform-modules-nexthop/common/nexthop/pddf_config_parser.py new file mode 100644 index 00000000000..0249c2ca5fe --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-nexthop/common/nexthop/pddf_config_parser.py @@ -0,0 +1,113 @@ +#!/usr/bin/env python3 + +""" +PDDF config extraction utilities +This module provides functions to extract information from PDDF configuration +""" + +import json +import re + +from dataclasses import dataclass +from enum import Enum + +PDDF_DEVICE_JSON_PATH = "/usr/share/sonic/platform/pddf/pddf-device.json" + + +class FpgaDeviceName(str, Enum): + CPU_CARD = "CPUCARD_FPGA" + SWITCHCARD = "SWITCHCARD_FPGA" + + +@dataclass +class FpgaDevAttrs: + pwr_cycle_reg_offset: int + pwr_cycle_enable_word: int + + +def load_pddf_device_config(): + """Load and parse pddf-device.json configuration. Raises exception on error.""" + with open(PDDF_DEVICE_JSON_PATH, "r") as f: + config = json.load(f) + return config + + +def extract_fpga_attrs(config, fpga_types): + """Extract fpga attrs information from PDDF config. Raise exception on error.""" + fpga_attrs = {} + for device_name, device_config in config.items(): + if not isinstance(device_config, dict) or "dev_info" not in device_config: + continue + + dev_info = device_config["dev_info"] + if "device_type" not in dev_info or dev_info["device_type"] != "MULTIFPGAPCIE": + continue + + device_name = dev_info["device_name"] + if device_name not in fpga_types: + continue + + # Exceptions thrown here since FPGAs should have these attributes + # past this point. + dev_attrs = device_config["dev_attr"] + + fpga_attrs[device_name] = FpgaDevAttrs( + pwr_cycle_reg_offset=int(dev_attrs["pwr_cycle_reg_offset"], 16), + pwr_cycle_enable_word=int(dev_attrs["pwr_cycle_enable_word"], 16), + ) + + return fpga_attrs + + +def extract_xcvr_list(config): + """Extract transceiver information for initialization from PDDF config""" + xcvr_list = [] + + port_ctrl_pattern = re.compile(r"^PORT\d+-CTRL$") + + for device_name, device_config in config.items(): + if not isinstance(device_config, dict): + continue + + # Check if device name matches PORT\d+-CTRL pattern + if not port_ctrl_pattern.match(device_name): + continue + + # Check if device has i2c section + if "i2c" not in device_config: + continue + + i2c_config = device_config["i2c"] + + # Check if attr_list exists and contains required attributes + attr_list = i2c_config.get("attr_list", []) + has_reset = False + has_lpmode = False + + for attr in attr_list: + if isinstance(attr, dict): + attr_name = attr.get("attr_name", "") + if attr_name == "xcvr_reset": + has_reset = True + elif attr_name == "xcvr_lpmode": + has_lpmode = True + + # Only include devices that have both required attributes + if not (has_reset and has_lpmode): + continue + + # Extract bus and address from topo_info + topo_info = i2c_config.get("topo_info", {}) + bus = topo_info.get("parent_bus") + addr = topo_info.get("dev_addr") + + if bus and addr: + xcvr_list.append( + { + "name": device_name, + "bus": int(bus, 16), + "addr": f"{int(addr, 16):04x}", + } + ) + + return xcvr_list diff --git a/platform/broadcom/sonic-platform-modules-nexthop/common/nexthop/platform_utils.py b/platform/broadcom/sonic-platform-modules-nexthop/common/nexthop/platform_utils.py new file mode 100644 index 00000000000..28564a101c5 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-nexthop/common/nexthop/platform_utils.py @@ -0,0 +1,47 @@ +import subprocess +import click +import os +import sys + + +def run_cmd(cmd, check_exit=True): + """ + Run a command and return the output + Args: + cmd (str): The command to run + check_exit (bool): Whether to check the exit code and raise an exception if it's non-zero + Returns: + str: The output of the command (stdout) + Raises: + subprocess.CalledProcessError: If check_exit is True and command fails + subprocess.SubprocessError: If there's an error running the command + OSError: If there's an OS-level error + """ + try: + result = subprocess.run( + cmd, shell=True, capture_output=True, text=True, check=check_exit + ) + return result.stdout.strip() + except subprocess.CalledProcessError as e: + # Re-raise with more context + raise subprocess.CalledProcessError( + e.returncode, cmd, output=e.stdout, stderr=e.stderr + ) + except (subprocess.SubprocessError, OSError): + raise + + +def run_and_report(description, command): + """ + Run a command and report the result with colored output. + + Args: + description (str): Description of the operation being performed + command (str): The command to execute + """ + click.secho(f"{description}:", fg="cyan") + try: + run_cmd(command) + click.secho(f"Successfully {description.lower()}", fg="green") + except (subprocess.CalledProcessError, subprocess.SubprocessError, OSError): + click.secho(f"Failed to {description.lower()}", fg="red") \ No newline at end of file diff --git a/platform/broadcom/sonic-platform-modules-nexthop/common/service/transceiver-init.service b/platform/broadcom/sonic-platform-modules-nexthop/common/service/transceiver-init.service index fcdec6e31dc..a18341d42d0 100644 --- a/platform/broadcom/sonic-platform-modules-nexthop/common/service/transceiver-init.service +++ b/platform/broadcom/sonic-platform-modules-nexthop/common/service/transceiver-init.service @@ -6,7 +6,7 @@ DefaultDependencies=no [Service] Type=oneshot -ExecStart=/usr/local/bin/transceiver_init.sh +ExecStart=/usr/local/bin/transceiver_init.py RemainAfterExit=yes [Install] diff --git a/platform/broadcom/sonic-platform-modules-nexthop/common/sonic_platform/__init__.py b/platform/broadcom/sonic-platform-modules-nexthop/common/sonic_platform/__init__.py index 2fd1a29b267..88dbe605174 100644 --- a/platform/broadcom/sonic-platform-modules-nexthop/common/sonic_platform/__init__.py +++ b/platform/broadcom/sonic-platform-modules-nexthop/common/sonic_platform/__init__.py @@ -2,6 +2,7 @@ # SPDX-License-Identifier: Apache-2.0 # All the derived classes for PDDF -__all__ = ["platform", "chassis", "component", "sfp", "psu", "thermal", "thermal_manager", "thermal_conditions", "thermal_actions", "thermal_infos"] +__all__ = ["platform", "chassis", "component", "sfp", "psu", "thermal", "thermal_manager", "thermal_conditions", + "thermal_actions", "thermal_infos", "adm1266"] from sonic_platform import * diff --git a/platform/broadcom/sonic-platform-modules-nexthop/common/sonic_platform/adm1266.py b/platform/broadcom/sonic-platform-modules-nexthop/common/sonic_platform/adm1266.py new file mode 100644 index 00000000000..0605216ea46 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-nexthop/common/sonic_platform/adm1266.py @@ -0,0 +1,356 @@ +# Copyright 2025 Nexthop Systems Inc. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + + +import json +from typing import List, Dict, Callable, Any + + +# Rendering helpers (no hardware-width assumptions) + +def binw(val, width): + return f"0b{val:0{width}b}" + +def hex_value(_key: str, val: int) -> str: + return f"0x{val:x}" + +def time_since(_key: str, data: bytes) -> str: + """ + Convert an 8-byte ADM1266 blackbox timestamp into a human-readable + elapsed time since power-on, preserving fractional seconds. + + :param data: 8-byte timestamp from ADM1266 + :return: Human-readable string like "0 Day(s) 0 Hour(s) 3 Minute(s) 2.518700 Second(s)" + """ + if not isinstance(data, (bytes, bytearray)) or len(data) != 8: + return '' + if data == b'\x00' * 8 or data == b'\xff' * 8: + return '' + + # Extract integer seconds from bytes [2:6] (little-endian) + secs = int.from_bytes(data[2:6], 'little') + + # Extract fractional seconds from bytes [0:2] (16-bit fraction) + frac = int.from_bytes(data[0:2], 'little') / 65536.0 + + total_seconds = secs + frac + + # Compute years, days, hours, minutes, seconds + minutes_total, seconds = divmod(total_seconds, 60) + hours_total, minutes = divmod(minutes_total, 60) + days_total, hours = divmod(hours_total, 24) + years, days = divmod(days_total, 365) + + # Helper to format singular/plural + def fmt(value, name): + if value == 0: + return '' + return f"{int(value)} {name}" + ('s' if int(value) != 1 else '') + + parts = [ + fmt(years, "year"), + fmt(days, "day"), + fmt(hours, "hour"), + fmt(minutes, "minute") + ] + parts = [p for p in parts if p] # remove empty + parts.append(f"{seconds:.6f} second" + ('' if abs(seconds - 1.0) < 1e-6 else 's')) + return " ".join(parts) + " after power-on" + +# Channel naming: derive names from bit positions; use per-key prefix (no fixed widths) +CHANNEL_PREFIX: Dict[str, str] = { + 'vhx': 'VH', + 'vp_ov': 'VP', 'vp_uv': 'VP', + 'gpio_in': 'GPIO', 'gpio_out': 'GPIO', + 'pdio_in': 'PDIO', 'pdio_out': 'PDIO', +} + +CHANNEL_WIDTH: Dict[str, int] = { + 'vhx': 8, + 'vp_ov': 16, + 'vp_uv': 16, + 'gpio_in': 16, + 'gpio_out': 16, + 'pdio_in': 16, + 'pdio_out': 16, +} + +def channel_names(key: str, value: int) -> str: + prefix = CHANNEL_PREFIX.get(key) + if prefix is None: + return hex_value(key, value) + names = [] + idx = 1 + mask = value + while mask: + if mask & 1: + names.append(f"{prefix}{idx}") + mask >>= 1 + idx += 1 + width = CHANNEL_WIDTH.get(key) + if not len(names): + return binw(value, width) + return ','.join(names) + " (" + binw(value, width) + ")" + +# Renderer map: defaults to hex; override specific keys +RENDER: Dict[str, Callable[[str, int], str]] = {} +for k in ['uid','powerup','action','rule','current','last', + 'vhx','vp_ov','vp_uv','gpio_in','gpio_out','pdio_in','pdio_out']: + RENDER[k] = hex_value +RENDER['timestamp'] = time_since + +# dpm_fault and power_fault_cause are string labels; render as-is when present +RENDER['dpm_fault'] = lambda _k, v: v if isinstance(v, str) else hex_value(_k, v) +RENDER['power_fault_cause'] = lambda _k, v: v if isinstance(v, str) else hex_value(_k, v) +RENDER['power_fault_cause'] = lambda _k, v: v if isinstance(v, str) else hex_value(_k, v) + +# Channel keys use channel_names (more human friendly); keep raw hex available via get_blackbox_records +for k in ['vhx','vp_ov','vp_uv','gpio_in','gpio_out','pdio_in','pdio_out']: + RENDER[k] = channel_names + +# Fixed output key order for human-friendly view +OUTPUT_ORDER = [ + 'fault_uid','powerup','action','rule','current','last', + 'vhx','vp_ov','vp_uv','gpio_in','gpio_out','pdio_in','pdio_out', + 'dpm_fault','power_fault_cause','timestamp' +] + +def find_power_loss(input_bits: int, output_bits: int, + mapping: Dict[int, Dict[str, Any]]) -> str: + """ + Return a terse rail name (e.g., "POS5V0_S0") if any input bit AND its mapped + output bit are both 1. Otherwise return an empty string. + All bit indices are zero-based. + """ + reason = "" + for in_idx, pdio_desc in mapping.items(): + out_idx = pdio_desc.get("pdio") + desc = pdio_desc.get("rail") + if ((input_bits >> in_idx) & 1) and ((output_bits >> out_idx) & 1): + if reason: + reason += ", " + reason += desc + return reason + +def determine_power_loss(vp_to_pdio_desc: Dict[int, Dict[str, Any]], + vh_to_pdio_desc: Dict[int, Dict[str, Any]], + vh: int, vp_uv: int, pdio_out: int) -> str: + reason = find_power_loss(vh, pdio_out, vh_to_pdio_desc) + if reason: + return reason + return find_power_loss(vp_uv, pdio_out, vp_to_pdio_desc) + +def decode_dpm_fault(dpm_table: Dict[int, str], dpm_bits: Dict[int, int], + pdio_in: int) -> str: + code = 0 + for pdio_bit, fault_pos in dpm_bits.items(): + code |= ((pdio_in >> pdio_bit) & 1) << fault_pos + return dpm_table.get(code, f"code={code}") if code != 0 else "" # empty string for zero + +def decode_power_fault_cause(power_fault_cause: Dict[int, Dict[str, str]], pdio_in: int) -> str: + """Return the first asserted power fault cause description based on pdio_in.""" + # Iterate in the table's order (dict preserves insertion order in Python 3.7+) + for idx, cause_dict in power_fault_cause.items(): + if ((pdio_in >> idx) & 1): + return cause_dict.get("cause") + " (" + cause_dict.get("desc") + ")" + return "" + +class Adm1266: + def __init__(self, dpm_info): + self.dpm_info = dpm_info + self.nvmem_path = self.dpm_info.get_nvmem_path() + + def read_blackbox(self) -> bytes: + """Read the entire blackbox data blob from the nvmem sysfs file""" + with open(self.nvmem_path, 'rb') as f: + return f.read() + + def get_fault_record(self, data: bytes) -> Dict: + """Parse a 64-byte record (ADM1266 Table 79).""" + if len(data) != 64: + return {} + + def u16(off: int) -> int: + return data[off] | (data[off + 1] << 8) + + empty = data[2] & 0x01 + + rec = { + 'uid': u16(0), + 'empty': empty, + 'action': data[3], + 'rule': data[4], + 'vhx': data[5], # VHx_OV status byte + 'current': u16(6), # current state + 'last': u16(8), # last state + 'vp_ov': u16(10), + 'vp_uv': u16(12), + 'gpio_in': u16(14), + 'gpio_out': u16(16), + 'pdio_in': u16(18), + 'pdio_out': u16(20), + 'powerup': u16(22), + 'timestamp': data[24:32], # 8 bytes + 'crc': data[63], + } + return rec + + def parse_blackbox(self, data: bytes) -> List[Dict]: + """Parse blackbox data and return structured list of valid (non-empty) faults. + + - Skips records that are all 0xFF (erased) or all 0x00 (empty area) + - Uses the 'empty' bit parsed from byte 2 to keep only valid records + """ + faults: List[Dict] = [] + if not len(data): + return faults + + fault_size = 64 + num_records = len(data) // fault_size + for i in range(num_records): + start = i * fault_size + rec = data[start:start + fault_size] + # Skip cleared and erased records + if all(b == 0x00 for b in rec) or all(b == 0xFF for b in rec): + continue + fault_record = self.get_fault_record(rec) + if (fault_record['empty'] & 0x01) == 0: + fault_record['record_index'] = i + faults.append(fault_record) + return faults + + def get_blackbox_records(self) -> List[Dict]: + """Get reboot causes from blackbox faults read via sysfs.""" + blackbox_data = self.read_blackbox() + faults = self.parse_blackbox(blackbox_data) + + records: List[Dict] = [] + for fault in faults: + rec_idx = fault.get('record_index') + record = { + 'fault_uid': fault['uid'], + 'gpio_in': fault['gpio_in'], + 'gpio_out': fault['gpio_out'], + 'powerup': fault['powerup'], + 'timestamp': fault['timestamp'], + 'action': fault['action'], + 'rule': fault['rule'], + 'vhx': fault['vhx'], + 'vp_ov': fault['vp_ov'], + 'vp_uv': fault['vp_uv'], + 'current': fault['current'], + 'last': fault['last'], + 'pdio_in': fault['pdio_in'], + 'pdio_out': fault['pdio_out'], + 'record_index': rec_idx, + } + # Attach raw 64-byte chunk for this record if index is known + if isinstance(rec_idx, int) and rec_idx >= 0: + start = rec_idx * 64 + record['raw'] = blackbox_data[start:start+64] + # Decode DPM fault (from pdio_in) and add a terse label + dpm = decode_dpm_fault(self.dpm_info.get_dpm_table(), + self.dpm_info.get_dpm_signals(), + record['pdio_in']) + if dpm: + record['dpm_fault'] = dpm + # Decode Power Fault Cause bits (from pdio_in) and add the first matching description + pf = decode_power_fault_cause(self.dpm_info.get_power_fault_cause(), record['pdio_in']) + if pf: + record['power_fault_cause'] = pf + record['dpm_name'] = self.dpm_info.get_name() + records.append(record) + return records + + def get_reboot_causes(self) -> List[Dict]: + records = self.get_blackbox_records() + + rendered: List[Dict] = [] + for rec in records: + out: Dict[str, str] = {} + out['dpm_name'] = rec.get('dpm_name', '') + for key in OUTPUT_ORDER: + renderer = RENDER.get(key, hex_value) + out[key] = renderer(key, rec.get(key, 0)) + # Compute a terse power-loss reason (if any) and attach it + ploss = determine_power_loss(self.dpm_info.get_vp_to_pdio_desc(), + self.dpm_info.get_vh_to_pdio_desc(), + rec.get('vhx', 0), + rec.get('vp_uv', 0), + rec.get('pdio_out', 0)) + if ploss: + out['power_loss'] = ploss + # Add raw 64-byte record as 8 rows of 8 bytes each (hex) + raw = rec.get('raw') + if isinstance(raw, (bytes, bytearray)) and len(raw) == 64: + rows = [] + for i in range(0, 64, 8): + chunk = raw[i:i+8] + rows.append(' '.join(f"{b:02x}" for b in chunk)) + out['raw'] = '\n'.join(rows) + rendered.append(out) + return rendered + + def get_reboot_cause(self): + """Return a single string each reboot cause separated by a newline. + It preserves the order from the driver (newest -> oldest). + """ + causes = self.get_reboot_causes() + msg_order = [ + 'dpm_name', 'fault_uid', 'power_loss', 'dpm_fault', 'power_fault_cause', + 'powerup', 'timestamp', 'current', 'last', 'action', + 'rule', 'vhx', 'vp_ov', 'vp_uv', + 'gpio_in', 'gpio_out', 'pdio_in', 'pdio_out', + 'raw', + ] + + messages: List[str] = [] + for c in causes: + rendered_items = [] + for k in msg_order: + v = c.get(k) + if v is None: + continue + if isinstance(v, str) and (v == '' or v == '0x0'): + continue + rendered_items.append((k, v)) + if not rendered_items: + messages.append("") + continue + max_key = max(len(k) for k, _ in rendered_items) + lines: List[str] = [] + for k, v in rendered_items: + prefix = f" {k.ljust(max_key)} = " + if isinstance(v, str) and ('\n' in v): + indented = v.replace('\n', '\n' + ' ' * len(prefix)) + lines.append(prefix + indented) + else: + lines.append(prefix + str(v)) + # Prepend a newline to the first attribute so each block starts on a new line + lines[0] = "\n" + lines[0] + messages.append("\n".join(lines)) + if not messages: + return "" + return "\n".join(messages) + + def clear_blackbox(self): + with open(self.nvmem_path, 'w') as f: + f.write("1") + +def get_reboot_cause(): + messages = [] + from sonic_platform.dpm_info import DpmInfo + with open('/usr/share/sonic/platform/pddf/pd-plugin.json') as pd: + pddf_plugin_data = json.load(pd) + + adms = pddf_plugin_data.get("DPM", {}) + for adm in adms: + dpm_info = DpmInfo(adm, pddf_plugin_data) + adm = Adm1266(dpm_info) + message = adm.get_reboot_cause() + if message: + adm.clear_blackbox() + messages.append(message) + if len(messages): + return "REBOOT_CAUSE_HARDWARE_OTHER", "\n".join(messages) + return "REBOOT_CAUSE_UNKNOWN", "" diff --git a/platform/broadcom/sonic-platform-modules-nexthop/common/sonic_platform/asic_thermal.py b/platform/broadcom/sonic-platform-modules-nexthop/common/sonic_platform/asic_thermal.py index 8ba0cf6a5a3..ecf096cc6df 100644 --- a/platform/broadcom/sonic-platform-modules-nexthop/common/sonic_platform/asic_thermal.py +++ b/platform/broadcom/sonic-platform-modules-nexthop/common/sonic_platform/asic_thermal.py @@ -28,3 +28,13 @@ def get_temperature(self): temp = super().get_temperature() self._update_min_max_temp(temp) return temp + + def get_minimum_recorded(self): + # Make sure temp is recorded at least once. + self.get_temperature() + return MinMaxTempMixin.get_minimum_recorded(self) + + def get_maximum_recorded(self): + # Make sure temp is recorded at least once. + self.get_temperature() + return MinMaxTempMixin.get_maximum_recorded(self) diff --git a/platform/broadcom/sonic-platform-modules-nexthop/common/sonic_platform/chassis.py b/platform/broadcom/sonic-platform-modules-nexthop/common/sonic_platform/chassis.py index 89ac0bdbc5a..81b4edd2ca1 100644 --- a/platform/broadcom/sonic-platform-modules-nexthop/common/sonic_platform/chassis.py +++ b/platform/broadcom/sonic-platform-modules-nexthop/common/sonic_platform/chassis.py @@ -16,6 +16,7 @@ from sonic_platform.thermal import NexthopFpgaAsicThermal from sonic_platform.watchdog import Watchdog +from sonic_platform.adm1266 import get_reboot_cause try: from sonic_platform_pddf_base.pddf_chassis import PddfChassis @@ -165,14 +166,22 @@ def get_reboot_cause(self): to pass a description of the reboot cause. """ - reboot_cause_path = self.plugin_data['REBOOT_CAUSE']['reboot_cause_file'] + # First check for hardware specific causes + hw_cause, hw_description = get_reboot_cause() + if hw_cause != "REBOOT_CAUSE_UNKNOWN": + return (hw_cause, hw_description) + + # Fall back to software reboot cause file + reboot_cause_path = self.plugin_data["REBOOT_CAUSE"]["reboot_cause_file"] try: - with open(reboot_cause_path, 'r', errors='replace') as fd: + with open(reboot_cause_path, "r", errors="replace") as fd: data = fd.read() sw_reboot_cause = data.strip() + return ("REBOOT_CAUSE_NON_HARDWARE", sw_reboot_cause) except IOError: sw_reboot_cause = "Unknown" + return ("REBOOT_CAUSE_UNKNOWN", "Unknown") return ('REBOOT_CAUSE_NON_HARDWARE', sw_reboot_cause) @@ -210,4 +219,5 @@ def get_watchdog(self) -> Watchdog | None: def get_thermal_manager(self): from .thermal_manager import ThermalManager + return ThermalManager diff --git a/platform/broadcom/sonic-platform-modules-nexthop/common/sonic_platform/dpm_info.py b/platform/broadcom/sonic-platform-modules-nexthop/common/sonic_platform/dpm_info.py new file mode 100644 index 00000000000..7eeefc594cf --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-nexthop/common/sonic_platform/dpm_info.py @@ -0,0 +1,47 @@ +# Copyright 2025 Nexthop Systems Inc. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +from typing import Dict, Any + +class DpmInfo: + def __init__(self, name, pddf_plugin_data): + self.name = name + dpm_info = pddf_plugin_data["DPM"][name] + self.nvmem_path = dpm_info["nvmem_path"] + + self.vp_to_pdio_desc: Dict[int, Dict[str, Any]] = { + int(k): v for k, v in dpm_info["vp_to_pdio_desc"].items() + } + self.vh_to_pdio_desc: Dict[int, Dict[int, Any]] = { + int(k): v for k, v in dpm_info["vh_to_pdio_desc"].items() + } + self.dpm_signals: Dict[int, int] = { + int(k): v for k, v in dpm_info["dpm_signals"].items() + } + self.dpm_table: Dict[int, str] = { + int(k): v for k, v in dpm_info["dpm_table"].items() + } + self.power_fault_cause: Dict[int, Dict[str, str]] = { + int(k): v for k, v in dpm_info["power_fault_cause"].items() + } + + def get_vp_to_pdio_desc(self): + return self.vp_to_pdio_desc + + def get_vh_to_pdio_desc(self): + return self.vh_to_pdio_desc + + def get_dpm_signals(self): + return self.dpm_signals + + def get_dpm_table(self): + return self.dpm_table + + def get_power_fault_cause(self): + return self.power_fault_cause + + def get_nvmem_path(self): + return self.nvmem_path + + def get_name(self): + return self.name diff --git a/platform/broadcom/sonic-platform-modules-nexthop/common/sonic_platform/fan.py b/platform/broadcom/sonic-platform-modules-nexthop/common/sonic_platform/fan.py index 85f98c2802e..2f525318f45 100644 --- a/platform/broadcom/sonic-platform-modules-nexthop/common/sonic_platform/fan.py +++ b/platform/broadcom/sonic-platform-modules-nexthop/common/sonic_platform/fan.py @@ -7,11 +7,38 @@ from sonic_platform_pddf_base.pddf_fan import PddfFan except ImportError as e: raise ImportError(str(e) + "- required module not found") +from sonic_py_common import syslogger +from swsscommon import swsscommon +_FAN_INFO_TABLE_NAME = "FAN_INFO" +_STATE_MAX_SPEED_KEY = "max_speed" + +SYSLOG_IDENTIFIER = "sonic_platform.fan" +logger = syslogger.SysLogger(SYSLOG_IDENTIFIER) + +def _try_get_state_db_table(table_name) -> swsscommon.Table | None: + """ + Attempts to establish a connection to STATE_DB and returns the table. + + If failed, it is likely that redis-server is not up yet, especially + when SONiC Platform is initialized by some services early after boot. + Ignore the error and return None to not break fan initialization, as + we will retry later when needed by the runtime operations (and we expect + redis-server to already be up by then, e.g. when utilized by pmon container). + """ + try: + state_db = swsscommon.DBConnector("STATE_DB", 0) + except Exception as e: + logger.log_warning(f"Failed to connect to STATE_DB: {e}. Ignoring.") + return None + return swsscommon.Table(state_db, table_name) class Fan(PddfFan): """PDDF Platform-Specific Fan class""" + # Default maximum speed if not specified in STATE_DB + _DEFAULT_MAX_SPEED = 75.0 + def __init__( self, tray_idx, @@ -25,6 +52,7 @@ def __init__( PddfFan.__init__( self, tray_idx, fan_idx, pddf_data, pddf_plugin_data, is_psu_fan, psu_index ) + self._state_fan_tbl = _try_get_state_db_table(_FAN_INFO_TABLE_NAME) def get_model(self): if self.get_presence() and not self.is_psu_fan: @@ -58,3 +86,75 @@ def get_presence(self): if self.is_psu_fan: return self.get_psu_presence() return PddfFan.get_presence(self) + + def set_speed(self, speed): + max_speed = self.get_max_speed() + if speed > max_speed: + logger.log_warning( + f"Requested fan speed {speed}% exceeds current max {max_speed}%; " + "capping to max." + ) + speed = max_speed + return PddfFan.set_speed(self, speed) + + def get_max_speed(self): + """ + Gets maximum speed for this fan from STATE_DB's FAN_INFO table. + + If the key doesn't exist in the DB, return the default maximum speed of 75%. + + Returns: + Maximum speed for this fan in percent (0-100) + """ + if self._state_fan_tbl is None: + self._state_fan_tbl = _try_get_state_db_table(_FAN_INFO_TABLE_NAME) + if self._state_fan_tbl is None: + logger.log_error( + "Can't connect to 'STATE_DB:FAN_INFO' table; " + f"fallback to default max_speed={self._DEFAULT_MAX_SPEED}%." + ) + return self._DEFAULT_MAX_SPEED + + fan_name = PddfFan.get_name(self) + found, data = self._state_fan_tbl.get(fan_name) + if not found: + logger.log_error( + f"'STATE_DB:FAN_INFO|{fan_name}' not found; " + f"fallback to default max_speed={self._DEFAULT_MAX_SPEED}%" + ) + return self._DEFAULT_MAX_SPEED + + data_dict = dict(data) + if _STATE_MAX_SPEED_KEY not in data_dict: + logger.log_error( + f"max_speed not found in 'STATE_DB:FAN_INFO|{fan_name}'; " + f"fallback to default={self._DEFAULT_MAX_SPEED}%." + ) + return self._DEFAULT_MAX_SPEED + return float(data_dict[_STATE_MAX_SPEED_KEY]) + + def set_max_speed(self, max_speed): + """ + Sets maximum speed for this fan into STATE_DB's FAN_INFO table. + + We write it onto the DB so that Fan instances across containers will see the same value. + + Args: + max_speed: Maximum speed in percent (0-100) + + Returns: + True if the maximum speed is stored successfully, False otherwise. + """ + if self._state_fan_tbl is None: + self._state_fan_tbl = _try_get_state_db_table(_FAN_INFO_TABLE_NAME) + if self._state_fan_tbl is None: + logger.log_error( + "Can't connect to 'STATE_DB:FAN_INFO' table; " + f"ignore writing max_speed={self._DEFAULT_MAX_SPEED}% " + f"for {self.get_name()}." + ) + return False + + fvp = swsscommon.FieldValuePairs([(_STATE_MAX_SPEED_KEY, str(max_speed))]) + self._state_fan_tbl.set(PddfFan.get_name(self), fvp) + return True diff --git a/platform/broadcom/sonic-platform-modules-nexthop/common/sonic_platform/thermal.py b/platform/broadcom/sonic-platform-modules-nexthop/common/sonic_platform/thermal.py index 1d2105280f0..57ab0a18d2a 100644 --- a/platform/broadcom/sonic-platform-modules-nexthop/common/sonic_platform/thermal.py +++ b/platform/broadcom/sonic-platform-modules-nexthop/common/sonic_platform/thermal.py @@ -113,6 +113,16 @@ def get_temperature(self): self._update_min_max_temp(temp) return temp + def get_minimum_recorded(self): + # Make sure temp is recorded at least once. + self.get_temperature() + return MinMaxTempMixin.get_minimum_recorded(self) + + def get_maximum_recorded(self): + # Make sure temp is recorded at least once. + self.get_temperature() + return MinMaxTempMixin.get_maximum_recorded(self) + class NexthopFpgaAsicThermal(ThermalBase, MinMaxTempMixin, PidThermalMixin): """ASIC temperature sensor read from the FPGA register""" @@ -217,6 +227,16 @@ def get_high_critical_threshold(self): return float(val) return None + def get_minimum_recorded(self): + # Make sure temp is recorded at least once. + self.get_temperature() + return MinMaxTempMixin.get_minimum_recorded(self) + + def get_maximum_recorded(self): + # Make sure temp is recorded at least once. + self.get_temperature() + return MinMaxTempMixin.get_maximum_recorded(self) + class SfpThermal(ThermalBase, MinMaxTempMixin, PidThermalMixin): """SFP thermal interface class""" @@ -308,6 +328,16 @@ def set_high_critical_threshold(self, temperature): def set_low_critical_threshold(self, temperature): return False + + def get_minimum_recorded(self): + # Make sure temp is recorded at least once. + self.get_temperature() + return MinMaxTempMixin.get_minimum_recorded(self) + + def get_maximum_recorded(self): + # Make sure temp is recorded at least once. + self.get_temperature() + return MinMaxTempMixin.get_maximum_recorded(self) def get_pid_setpoint(self): setpoint = super().get_pid_setpoint() diff --git a/platform/broadcom/sonic-platform-modules-nexthop/common/sonic_platform/thermal_actions.py b/platform/broadcom/sonic-platform-modules-nexthop/common/sonic_platform/thermal_actions.py index 9da9e497bc9..c44f4297d32 100644 --- a/platform/broadcom/sonic-platform-modules-nexthop/common/sonic_platform/thermal_actions.py +++ b/platform/broadcom/sonic-platform-modules-nexthop/common/sonic_platform/thermal_actions.py @@ -13,10 +13,10 @@ if TYPE_CHECKING: from sonic_platform_base.fan_base import Fan -from sonic_platform.thermal_infos import FanInfo, ThermalInfo +from sonic_platform.thermal_infos import FanDrawerInfo, ThermalInfo from sonic_platform.syslog import SYSLOG_IDENTIFIER_THERMAL, NhLoggerMixin -# Fan speed constants (percentage) +# Default range of fan speed (percentage) that PID controller can produce. FAN_MIN_SPEED: float = 30.0 FAN_MAX_SPEED: float = 100.0 @@ -89,8 +89,72 @@ def execute(self, thermal_info_dict: Dict[str, Any]) -> None: Args: thermal_info_dict: Dictionary containing thermal information """ - fan_info = thermal_info_dict.get(FanInfo.INFO_TYPE) - set_all_fan_speeds(self, fan_info.get_fans(), self._speed) + fan_drawer_info = thermal_info_dict.get(FanDrawerInfo.INFO_TYPE) + set_all_fan_speeds(self, fan_drawer_info.get_fans(), self._speed) + +@thermal_json_object('fan.set_max_speed') +class FanSetMaxSpeedAction(ThermalPolicyActionBase, NhLoggerMixin): + """Thermal action to set fan speed to a specific percentage.""" + + JSON_FIELD_MAX_SPEED: str = 'max_speed' + + def __init__(self) -> None: + """Initialize FanSetSpeedAction.""" + ThermalPolicyActionBase.__init__(self) + NhLoggerMixin.__init__(self, SYSLOG_IDENTIFIER_THERMAL) + self._max_speed: Optional[float] = None + self.log_debug("Initialized") + + def load_from_json(self, set_max_speed_json: Dict[str, Any]) -> None: + """ + Load configuration from JSON. + + Args: + set_max_speed_json: JSON object with 'max_speed' field (0-100) + + Raises: + KeyError: If 'max_speed' field is missing + ValueError: If max_speed value is invalid + """ + try: + self._max_speed = float(set_max_speed_json[self.JSON_FIELD_MAX_SPEED]) + self._validate_json(set_max_speed_json) + self.log_info(f"Loaded with max_speed: {self._max_speed}%") + except (KeyError, ValueError, TypeError) as e: + self.log_error(f"Failed to load from JSON: {e}") + raise + + def _validate_json(self, set_max_speed_json: Dict[str, Any]) -> None: + """ + Validate loaded JSON configuration. + + Raises: + ValueError: If configuration is invalid + """ + if self._max_speed is None: + raise ValueError("No max_speed defined in JSON policy file") + if self._max_speed < FAN_MIN_SPEED or self._max_speed > FAN_MAX_SPEED: + raise ValueError(f"Max speed {self._max_speed} is out of range [{FAN_MIN_SPEED}, {FAN_MAX_SPEED}]") + + def execute(self, thermal_info_dict: Dict[str, Any]) -> None: + """ + Set maximum speed for all present fans. + + Args: + thermal_info_dict: Dictionary containing thermal information + """ + fan_drawer_info = thermal_info_dict.get(FanDrawerInfo.INFO_TYPE) + if not fan_drawer_info: + raise ValueError("No fan drawer info available in thermal_info_dict") + + fans = fan_drawer_info.get_fans() + if not fans: + self.log_error("No fans available to set max_speed") + raise FanException("No fans available to set max_speed") + + for fan in fans: + fan.set_max_speed(self._max_speed) + self.log_info(f"Applied max_speed {self._max_speed:.1f}% to {len(fans)} fans") @thermal_json_object('thermal.control_algo') class ThermalControlAlgorithmAction(ThermalPolicyActionBase, NhLoggerMixin): @@ -154,13 +218,10 @@ def validate_json(self) -> None: if not self._fan_limits: raise ValueError("No fan limits defined in JSON policy file") min_limit = self._fan_limits.get('min') - max_limit = self._fan_limits.get('max') - if min_limit is None or max_limit is None: - raise ValueError("No min/max fan limits defined in JSON policy file") - if min_limit > max_limit: - raise ValueError(f"Min fan limit {min_limit} is greater than max fan limit {max_limit}") - if min_limit < FAN_MIN_SPEED or max_limit > FAN_MAX_SPEED: - raise ValueError(f"Fan limits {min_limit}-{max_limit} are out of range [{FAN_MIN_SPEED}, {FAN_MAX_SPEED}]") + if min_limit is None: + raise ValueError("No min fan limits defined in JSON policy file") + if min_limit < FAN_MIN_SPEED or min_limit > FAN_MAX_SPEED: + raise ValueError(f"Min fan limit {min_limit} is out of range [{FAN_MIN_SPEED}, {FAN_MAX_SPEED}]") if not self._constants.get('interval'): raise ValueError("Interval must be defined in JSON policy file") @@ -190,11 +251,17 @@ def _execute_raise_on_error(self, thermal_info_dict: Dict[str, Any]) -> None: thermal_info = thermal_info_dict.get(ThermalInfo.INFO_TYPE) if not thermal_info: raise ValueError("No thermal info available in thermal_info_dict") + fan_drawer_info = thermal_info_dict.get(FanDrawerInfo.INFO_TYPE) + if not fan_drawer_info: + raise ValueError("No fan drawer info available in thermal_info_dict") + + # Fan's max speed limit can change at runtime, so retrieve it every time + fan_max_speed = self._get_fan_max_speed(fan_drawer_info) # Initialize PID controllers if needed if not self._pidControllers: dt = thermal_info.get_thermal_manager().get_interval() - self._initialize_pid_controllers(dt) + self._initialize_pid_controllers(dt, fan_max_speed) # Get all thermals and group by PID domain thermals = thermal_info.get_thermals() @@ -204,7 +271,9 @@ def _execute_raise_on_error(self, thermal_info_dict: Dict[str, Any]) -> None: pid_outputs = {} max_error_thermals = {} for domain, domain_thermal_list in domain_thermals.items(): - pid_output, max_error_thermal = self._compute_domain_pid_output(domain, domain_thermal_list) + pid_output, max_error_thermal = self._compute_domain_pid_output( + domain, domain_thermal_list, fan_max_speed + ) pid_outputs[domain] = pid_output max_error_thermals[domain] = max_error_thermal.get_name() if max_error_thermal else "None" @@ -216,7 +285,7 @@ def _execute_raise_on_error(self, thermal_info_dict: Dict[str, Any]) -> None: max_domain = max(pid_outputs, key=pid_outputs.get) # Convert PID output to fan speed percentage - final_speed = self._convert_pid_output_to_speed(max_output) + final_speed = self._convert_pid_output_to_speed(max_output, fan_max_speed) self.log_info(f"Max PID output: {max_output:.3f} from domain '{max_domain}', " f"setting fan speed to {final_speed:.1f}%") @@ -224,12 +293,13 @@ def _execute_raise_on_error(self, thermal_info_dict: Dict[str, Any]) -> None: # Set all fan speeds self._set_all_fan_speeds(thermal_info_dict, final_speed) - def _initialize_pid_controllers(self, interval: int) -> None: + def _initialize_pid_controllers(self, interval: int, fan_max_speed: float) -> None: """ Initialize PID controllers for each domain. Args: interval: Control loop interval in seconds + fan_max_speed: Maximum fan speed in percentage (0-100) Raises: ValueError: If interval doesn't match configuration @@ -246,7 +316,7 @@ def _initialize_pid_controllers(self, interval: int) -> None: integral_gain=domain_config['KI'], derivative_gain=domain_config['KD'], output_min=self._fan_limits.get('min', FAN_MIN_SPEED), - output_max=self._fan_limits.get('max', FAN_MAX_SPEED) + output_max=fan_max_speed ) self._pidControllers[domain] = controller self._extra_setpoint_margin[domain] = domain_config.get('extra_setpoint_margin', 0) @@ -284,19 +354,25 @@ def _group_thermals_by_domain(self, thermals: List[Any]) -> Dict[str, List[Any]] self.log_debug(f"Grouped thermals by domain: {[(d, len(ts)) for d, ts in domain_thermals.items()]}") return domain_thermals - def _compute_domain_pid_output(self, domain: str, domain_thermals: List[Any]) -> tuple[float, Any]: + def _compute_domain_pid_output( + self, domain: str, domain_thermals: List[Any], fan_max_speed: float + ) -> tuple[float, Any]: """ Compute PID output using thermal with largest error in domain. Args: domain: PID domain name domain_thermals: List of thermal objects in this domain + fan_max_speed: Maximum fan speed in percentage (0-100) Returns: Tuple of (PID output value, max error thermal object) """ controller = self._pidControllers[domain] + # Fan's max speed limit can change at runtime, so update it first + controller.set_output_max(fan_max_speed) + # Find thermal with largest error (current temp - setpoint) max_error = None max_error_thermal = None @@ -330,20 +406,46 @@ def _compute_domain_pid_output(self, domain: str, domain_thermals: List[Any]) -> pid_output = controller.compute(max_error) return pid_output, max_error_thermal - def _convert_pid_output_to_speed(self, pid_output: float) -> float: + def _convert_pid_output_to_speed(self, pid_output: float, max_speed: float) -> float: """ Convert PID output to fan speed percentage. Args: pid_output: Raw PID controller output + max_speed: Maximum fan speed in percentage (0-100) Returns: Fan speed percentage saturated to configured limits """ min_speed = self._fan_limits.get('min', FAN_MIN_SPEED) - max_speed = self._fan_limits.get('max', FAN_MAX_SPEED) return max(min_speed, min(max_speed, pid_output)) + def _get_fan_max_speed(self, fan_drawer_info: FanDrawerInfo) -> float: + """ + Gets fan speed limit that satisfy all fans. + + If the value is out of range ([self._fan_limits['min'], FAN_MAX_SPEED]), + clamps it into the range. + + Args: + thermal_info_dict: Dictionary containing thermal information + + Returns: + Max speed for all fans, saturated to the configured limits + """ + fans = fan_drawer_info.get_fans() + if not fans: + raise FanException("No fans available to get max speed") + fan_max_speed = min(fan.get_max_speed() for fan in fans) + fan_min_speed = self._fan_limits.get('min', FAN_MIN_SPEED) + if fan_max_speed < fan_min_speed or fan_max_speed > FAN_MAX_SPEED: + self.log_error( + f"Fan max speed {fan_max_speed} is out of range [{fan_min_speed}, {FAN_MAX_SPEED}]. " + "Clamping it into the range." + ) + fan_max_speed = max(fan_min_speed, min(fan_max_speed, FAN_MAX_SPEED)) + return fan_max_speed + def _set_all_fan_speeds(self, thermal_info_dict: Dict[str, Any], speed: float) -> None: """ Set speed for all fans. @@ -352,7 +454,7 @@ def _set_all_fan_speeds(self, thermal_info_dict: Dict[str, Any], speed: float) - thermal_info_dict: Dictionary containing thermal information speed: Target fan speed percentage """ - set_all_fan_speeds(self, thermal_info_dict.get(FanInfo.INFO_TYPE).get_fans(), speed) + set_all_fan_speeds(self, thermal_info_dict.get(FanDrawerInfo.INFO_TYPE).get_fans(), speed) class PIDController(NhLoggerMixin): def __init__(self, @@ -404,6 +506,19 @@ def __init__(self, def log(self, priority: Any, msg: str, also_print_to_console: bool = False) -> None: super().log(priority, f"[{self._domain}] {msg}", also_print_to_console) + def set_output_max(self, output_max: float) -> None: + """Updates the maximum output value (fan speed %) as this can change at runtime.""" + if output_max < self._output_min: + self.log_error( + f"PIDController for domain '{self._domain}': " + f"attempting to set output_max={output_max}, " + f"which is below output_min={self._output_min}. " + f"Ignoring." + ) + return + self._output_max = output_max + self.log_info(f"PIDController for domain '{self._domain}': updated output_range=[{self._output_min}, {self._output_max}]") + def compute(self, error: float) -> float: """ Compute PID output. diff --git a/platform/broadcom/sonic-platform-modules-nexthop/common/sonic_platform/thermal_conditions.py b/platform/broadcom/sonic-platform-modules-nexthop/common/sonic_platform/thermal_conditions.py index 494d2ff0f89..a61128b855a 100644 --- a/platform/broadcom/sonic-platform-modules-nexthop/common/sonic_platform/thermal_conditions.py +++ b/platform/broadcom/sonic-platform-modules-nexthop/common/sonic_platform/thermal_conditions.py @@ -5,30 +5,57 @@ from sonic_platform_base.sonic_thermal_control.thermal_condition_base import ThermalPolicyConditionBase from sonic_platform_base.sonic_thermal_control.thermal_json_object import thermal_json_object -from .thermal_infos import FanInfo +from .thermal_infos import FanDrawerInfo -class FanCondition(ThermalPolicyConditionBase): - def get_fan_info(self, thermal_info_dict) -> FanInfo: +class FanDrawerCondition(ThermalPolicyConditionBase): + def get_fan_drawer_info(self, thermal_info_dict) -> FanDrawerInfo: """ Get fan info from thermal dict to determine if a fan condition matches """ - return thermal_info_dict.get(FanInfo.INFO_TYPE) + return thermal_info_dict.get(FanDrawerInfo.INFO_TYPE) -@thermal_json_object('fan.two.or.fewer.present') -class FanTwoOrFewerPresentCondition(FanCondition): +@thermal_json_object('fandrawer.one.present') +class FanDrawerOnePresentCondition(FanDrawerCondition): """ - Condition if two or fewer fantray fans are present + Condition if one fan drawer is present """ def is_match(self, thermal_info_dict: dict) -> bool: - fan_info = self.get_fan_info(thermal_info_dict) - return fan_info.get_num_present_fans() <= 2 + fan_drawer_info = self.get_fan_drawer_info(thermal_info_dict) + return fan_drawer_info.get_num_present_fan_drawers() == 1 + +@thermal_json_object('fandrawer.two.present') +class FanDrawerTwoPresentCondition(FanDrawerCondition): + """ + Condition if two fan drawers are present + """ + def is_match(self, thermal_info_dict: dict) -> bool: + fan_drawer_info = self.get_fan_drawer_info(thermal_info_dict) + return fan_drawer_info.get_num_present_fan_drawers() == 2 + +@thermal_json_object('fandrawer.three.present') +class FanDrawerThreePresentCondition(FanDrawerCondition): + """ + Condition if three fan drawers are present + """ + def is_match(self, thermal_info_dict: dict) -> bool: + fan_drawer_info = self.get_fan_drawer_info(thermal_info_dict) + return fan_drawer_info.get_num_present_fan_drawers() == 3 + +@thermal_json_object('fandrawer.four.present') +class FanDrawerFourPresentCondition(FanDrawerCondition): + """ + Condition if four fan drawers are present + """ + def is_match(self, thermal_info_dict: dict) -> bool: + fan_drawer_info = self.get_fan_drawer_info(thermal_info_dict) + return fan_drawer_info.get_num_present_fan_drawers() == 4 @thermal_json_object('default.operation') -class ThermalControlAlgorithmCondition(FanCondition): +class ThermalControlAlgorithmCondition(FanDrawerCondition): """ - Default case, will be the complement of all other conditions + Default case when more than two fan drawers are present """ def is_match(self, thermal_info_dict): - fan_info = self.get_fan_info(thermal_info_dict) - return fan_info.get_num_present_fans() > 2 \ No newline at end of file + fan_drawer_info = self.get_fan_drawer_info(thermal_info_dict) + return fan_drawer_info.get_num_present_fan_drawers() > 2 \ No newline at end of file diff --git a/platform/broadcom/sonic-platform-modules-nexthop/common/sonic_platform/thermal_infos.py b/platform/broadcom/sonic-platform-modules-nexthop/common/sonic_platform/thermal_infos.py index cd3234071cf..8e3d1597e3b 100644 --- a/platform/broadcom/sonic-platform-modules-nexthop/common/sonic_platform/thermal_infos.py +++ b/platform/broadcom/sonic-platform-modules-nexthop/common/sonic_platform/thermal_infos.py @@ -11,23 +11,29 @@ from .thermal import Thermal from .thermal_manager import ThermalManager from .fan import Fan +from .fan_drawer import FanDrawer from .psu import Psu -@thermal_json_object('fan_info') -class FanInfo(ThermalPolicyInfoBase): +@thermal_json_object('fan_drawer_info') +class FanDrawerInfo(ThermalPolicyInfoBase): """Fan information for all fan drawers""" - INFO_TYPE = 'fan_info' + INFO_TYPE = 'fan_drawer_info' def __init__(self): self._fans = [] + self._fan_drawers = [] def collect(self, chassis: Chassis): self._fans = chassis.get_all_fans()[:] - + self._fan_drawers = chassis.get_all_fan_drawers()[:] + def get_fans(self)->list[Fan]: return self._fans + + def get_fan_drawers(self)->list[FanDrawer]: + return self._fan_drawers - def get_num_present_fans(self): - return sum([fan.get_presence() for fan in self._fans]) + def get_num_present_fan_drawers(self): + return sum([fan_drawer.get_presence() for fan_drawer in self._fan_drawers]) @thermal_json_object('thermal_info') class ThermalInfo(ThermalPolicyInfoBase): diff --git a/platform/broadcom/sonic-platform-modules-nexthop/common/utils/nh_powercycle b/platform/broadcom/sonic-platform-modules-nexthop/common/utils/nh_powercycle new file mode 100755 index 00000000000..bb59d18addc --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-nexthop/common/utils/nh_powercycle @@ -0,0 +1,89 @@ +#!/usr/bin/python3 + +import os +import sys +import time + +from nexthop.pddf_config_parser import ( + load_pddf_device_config, + extract_fpga_attrs, + FpgaDeviceName, +) +from nexthop.fpga_lib import write_32 +from nexthop.pcie_lib import get_cpu_card_fpga_bdf, get_switchcard_fpga_bdf +from sonic_py_common import logger + +REBOOT_DELAY_MS = 1000 + +sonic_logger = logger.Logger(os.path.basename(__file__)) +sonic_logger.set_min_log_priority_info() + + +def log_error(msg: str): + sonic_logger.log_error(msg) + + +def main(): + try: + config = load_pddf_device_config() + except Exception as e: + log_error(f"Failed to load PDDF configuration: {str(e)}") + return 1 + + fpga_types = (FpgaDeviceName.CPU_CARD.value, FpgaDeviceName.SWITCHCARD.value) + try: + fpga_attrs = extract_fpga_attrs(config, fpga_types) + except Exception as e: + log_error( + f"Failed to extract FPGA attributes from PDDF configuration: {str(e)}" + ) + return 1 + + if not fpga_attrs: + log_error("No FPGA attributes found in PDDF configuration") + return 1 + + try: + sonic_logger.log_info( + "Writing to CPU card FPGA power cycle control register to initiate reboot" + ) + bdf = None + attrs = fpga_attrs[FpgaDeviceName.CPU_CARD.value] + bdf = get_cpu_card_fpga_bdf() + write_32(bdf, attrs.pwr_cycle_reg_offset, attrs.pwr_cycle_enable_word) + except Exception as e: + log_error( + "Error attempting power cycle via control register on CPU FPGA" + f" {bdf if bdf else ''}: {str(e)}, trying switchcard FPGA" + ) + time.sleep(REBOOT_DELAY_MS / 1000) + + try: + bdf = None + attrs = fpga_attrs[FpgaDeviceName.SWITCHCARD.value] + bdf = get_switchcard_fpga_bdf() + write_32(bdf, attrs.pwr_cycle_reg_offset, attrs.pwr_cycle_enable_word) + except Exception as e: + log_error( + "Error attempting power cycle via control register on switchcard FPGA" + f" {bdf if bdf else ''}: {str(e)}" + ) + + time.sleep(REBOOT_DELAY_MS / 1000) + + # If we reach here, we silently failed to reboot the dataplane! + log_error( + "Failed to initiate reboot, the control plane will reboot and" + " leave the dataplane in an undefined state" + ) + return 1 + + +if __name__ == "__main__": + # Systemd calls this script with one of 4 arguments. "poweroff" and "halt" we don't expect. + # A cold reboot will pass "reboot". In the first 3 cases, we continue with the powercycle. + # Warm reboots will use kexec and will pass "kexec" as the first argument, therefore we + # must skip the powercycle in that case. + if len(sys.argv) > 1 and sys.argv[1] == "kexec": + sys.exit(0) + sys.exit(main()) diff --git a/platform/broadcom/sonic-platform-modules-nexthop/common/utils/pre_pddf_init.sh b/platform/broadcom/sonic-platform-modules-nexthop/common/utils/pre_pddf_init.sh index 600ec7dde07..967158ed838 100755 --- a/platform/broadcom/sonic-platform-modules-nexthop/common/utils/pre_pddf_init.sh +++ b/platform/broadcom/sonic-platform-modules-nexthop/common/utils/pre_pddf_init.sh @@ -27,4 +27,6 @@ else log -p warning "$ASIC_INIT_PATH not found." fi +echo "blacklist adm1266" > /etc/modprobe.d/blacklist-adm1266.conf + exit 0 diff --git a/platform/broadcom/sonic-platform-modules-nexthop/common/utils/transceiver_init.py b/platform/broadcom/sonic-platform-modules-nexthop/common/utils/transceiver_init.py new file mode 100755 index 00000000000..a2cf8b6241a --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-nexthop/common/utils/transceiver_init.py @@ -0,0 +1,121 @@ +#!/usr/bin/env python3 + +""" +Transceiver initialization script +This script deasserts reset and disables low power mode for all transceivers specified in pddf-device.json +""" + +import sys +import time +from pathlib import Path +from sonic_py_common import logger +from nexthop.pddf_config_parser import load_pddf_device_config, extract_xcvr_list + +SYSLOG_IDENTIFIER = "transceiver-init" +MAX_WAIT_TIME = 30 # Maximum time to wait for transceiver control in seconds + +# Initialize logger +sonic_logger = logger.Logger(SYSLOG_IDENTIFIER) +sonic_logger.set_min_log_priority_info() + + +def log_info(message): + sonic_logger.log_info(message) + + +def log_error(message): + sonic_logger.log_error(message) + + +def wait_for(function, max_wait_time, description): + log_info(f"Waiting for {description}.") + for elapsed_time in range(max_wait_time): + if function(): + return True + time.sleep(1) + + log_error(f"Timed out waiting for {description}.") + return False + + +def is_xcvr_control_available(xcvr_list): + """Check if transceiver control files are available""" + for xcvr in xcvr_list: + bus = xcvr["bus"] + addr = xcvr["addr"] + lpmode_path = Path(f"/sys/bus/i2c/devices/{bus}-{addr}/xcvr_lpmode") + reset_path = Path(f"/sys/bus/i2c/devices/{bus}-{addr}/xcvr_reset") + + if not lpmode_path.exists() or not reset_path.exists(): + return False + return True + + +def init_xcvrs(xcvr_list): + """Initialize transceivers by deasserting reset and disabling low power mode""" + status = True + + log_info( + f"Deasserting reset and disabling low power mode for {len(xcvr_list)} transceivers." + ) + + for xcvr in xcvr_list: + bus = xcvr["bus"] + addr = xcvr["addr"] + name = xcvr["name"] + + # Deassert reset (write 0) + try: + with open(f"/sys/bus/i2c/devices/{bus}-{addr}/xcvr_reset", "w") as f: + f.write("0") + except Exception: + log_error(f"Failed to disable {name} xcvr reset for bus {bus}.") + status = False + continue + + # Disable low power mode (write 0) + try: + with open(f"/sys/bus/i2c/devices/{bus}-{addr}/xcvr_lpmode", "w") as f: + f.write("0") + except Exception: + log_error(f"Failed to disable {name} xcvr low power mode for bus {bus}.") + status = False + continue + + return status + + +def main(): + log_info("Starting transceiver initialization") + + try: + config = load_pddf_device_config() + except Exception as e: + log_error(f"Failed to load PDDF configuration: {str(e)}") + sys.exit(1) + + # Extract transceiver information + xcvr_list = extract_xcvr_list(config) + if not xcvr_list: + log_error("No transceiver information found in PDDF configuration") + sys.exit(1) + log_info(f"Found {len(xcvr_list)} transceivers in configuration") + + # Wait for transceiver control to be available + if not wait_for( + lambda: is_xcvr_control_available(xcvr_list), + MAX_WAIT_TIME, + "transceiver control", + ): + sys.exit(1) + + # Initialize transceivers + if not init_xcvrs(xcvr_list): + sys.exit(1) + + log_info("Transceiver initialization completed successfully") + sys.exit(0) + + +if __name__ == "__main__": + main() diff --git a/platform/broadcom/sonic-platform-modules-nexthop/debian/control b/platform/broadcom/sonic-platform-modules-nexthop/debian/control index f5b2dd55e0f..3c3a4ad2c63 100755 --- a/platform/broadcom/sonic-platform-modules-nexthop/debian/control +++ b/platform/broadcom/sonic-platform-modules-nexthop/debian/control @@ -26,6 +26,13 @@ Depends: ${misc:Depends}, sonic-platform-nexthop-komodo Description: Modules for all revisions of NH-4010 +Package: sonic-platform-nexthop-5010 +Architecture: amd64 +Depends: ${misc:Depends}, + sonic-platform-nexthop-common, + sonic-platform-nexthop-komodo +Description: Modules for all revisions of NH-5010 + Package: sonic-platform-nexthop-4010-r0 Architecture: amd64 Depends: ${misc:Depends}, @@ -44,3 +51,8 @@ Depends: ${misc:Depends}, sonic-platform-nexthop-4010 Description: Modules for NH-4020 r0 +Package: sonic-platform-nexthop-5010-r0 +Architecture: amd64 +Depends: ${misc:Depends}, + sonic-platform-nexthop-5010 +Description: Modules for NH-5010 r0 diff --git a/platform/broadcom/sonic-platform-modules-nexthop/debian/rules b/platform/broadcom/sonic-platform-modules-nexthop/debian/rules index cc4eaad1944..3f57ad2a32c 100755 --- a/platform/broadcom/sonic-platform-modules-nexthop/debian/rules +++ b/platform/broadcom/sonic-platform-modules-nexthop/debian/rules @@ -16,6 +16,7 @@ MODULE_DIRS += common MODULE_DIRS += komodo # SKU MODULE_DIRS += nh-4010 +MODULE_DIRS += nh-5010 SERVICE_DIR := service SYSTEM_DIR := etc/systemd/system @@ -103,6 +104,30 @@ override_dh_auto_install: --root=$(MOD_SRC_DIR)/debian/$(PACKAGE_PRE_NAME)-common \ --install-layout=deb +override_dh_install: + set -e + # Get all package names from debian/control + (for pkg_name in $$(dh_listpackages); do \ + set -e; \ + case "$${pkg_name}" in \ + *-r[0-9]*) \ + if [ -f sonic_platform-1.0-py3-none-any.whl ]; then \ + platform_suffix="$${pkg_name#$(PACKAGE_PRE_NAME)-}"; \ + sku="$${platform_suffix%-r[0-9]*}"; \ + revision="$${platform_suffix#$$sku}"; \ + fixed_sku=$$(echo "$$sku" | sed 's/-/_/g'); \ + device_name="x86_64-nexthop_$${fixed_sku}$${revision}"; \ + dh_install -p$${pkg_name} sonic_platform-1.0-py3-none-any.whl \ + usr/share/sonic/device/$${device_name}/pddf/; \ + fi; \ + if [ -f common/utils/nh_powercycle ]; then \ + dh_install -p$${pkg_name} common/utils/nh_powercycle \ + usr/lib/systemd/system-shutdown/; \ + fi; \ + ;; \ + esac; \ + done) + override_dh_clean: set -e dh_clean diff --git a/platform/broadcom/sonic-platform-modules-nexthop/debian/sonic-platform-nexthop-4010-r0.postinst b/platform/broadcom/sonic-platform-modules-nexthop/debian/sonic-platform-nexthop-4010-r0.postinst index 09534229d26..b953150c82b 100644 --- a/platform/broadcom/sonic-platform-modules-nexthop/debian/sonic-platform-nexthop-4010-r0.postinst +++ b/platform/broadcom/sonic-platform-modules-nexthop/debian/sonic-platform-nexthop-4010-r0.postinst @@ -9,5 +9,3 @@ systemctl enable system-ledd.service systemctl start --no-block system-ledd.service systemctl enable transceiver-init.service systemctl start transceiver-init.service -systemctl enable asic-temp-sensor-enable.service -systemctl start --no-block asic-temp-sensor-enable.service diff --git a/platform/broadcom/sonic-platform-modules-nexthop/debian/sonic-platform-nexthop-5010-r0.postinst b/platform/broadcom/sonic-platform-modules-nexthop/debian/sonic-platform-nexthop-5010-r0.postinst new file mode 100644 index 00000000000..b953150c82b --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-nexthop/debian/sonic-platform-nexthop-5010-r0.postinst @@ -0,0 +1,11 @@ +depmod -a +systemctl enable rename-mgmt-interface.service +systemctl start rename-mgmt-interface.service +systemctl enable pddf-platform-init.service +systemctl start pddf-platform-init.service +systemctl enable port-ledd.service +systemctl start --no-block port-ledd.service +systemctl enable system-ledd.service +systemctl start --no-block system-ledd.service +systemctl enable transceiver-init.service +systemctl start transceiver-init.service diff --git a/platform/broadcom/sonic-platform-modules-nexthop/komodo/utils/program_mgmt_eeprom.py b/platform/broadcom/sonic-platform-modules-nexthop/komodo/utils/program_mgmt_eeprom.py new file mode 100644 index 00000000000..fb7608708fd --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-nexthop/komodo/utils/program_mgmt_eeprom.py @@ -0,0 +1,195 @@ +# Copyright 2025 Nexthop Systems Inc. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +import mmap +import time + +BYTE_SIZE = 4 +ENDIAN = 'little' + +class MgmtSwitchEepromProgrammer: + """ + A class for programming the BCM53134 management ethernet switch EEPROM. + + To create an instance of the class: + import program_mgmt_eeprom + e = program_mgmt_eeprom.MgmtSwitchEepromProgrammer() + + To read individual EEPROM addresses: + e.init_spi_master() + e.read_word(
) + + To write individual EEPROM addresses: + e.init_spi_master() + e.stage_write_enable() + e.launch_write_operation() + e.read_received_data() + e.write_word(
, , ) + + To bring up the management interface (eth0): + e.program_all() + """ + + def __init__(self, offset=0xb0c00000): + self.init_mmap(offset) + + def init_mmap(self, offset): + size=0x100000 + with open('/dev/mem', 'r+b') as f: + mm = mmap.mmap(f.fileno(), size, access=mmap.ACCESS_WRITE, offset=offset) + self.mm = mm + + def read_reg(self, offset): + time.sleep(0.05) + value = int.from_bytes(self.mm[offset:offset+BYTE_SIZE], ENDIAN) + print("READ " + hex(offset) + " : " + hex(value)) + + def write_reg(self, offset, value): + time.sleep(0.05) + self.mm[offset:offset+BYTE_SIZE] = value.to_bytes(BYTE_SIZE, ENDIAN) + print("WRITE " + hex(offset) + " : " + hex(value)) + + def read_status_reg(self): + self.read_reg(0x50864) # read status register + self.read_reg(0x50874) # read Tx FIFO occupancy register + self.read_reg(0x50878) # read Rx FIFO occupancy register + + def slave_select_mgmt_eeprom(self): + self.write_reg(0x50870, 0xFFFFFFFE) # bit 3 + + def slave_deselect_mgmt_eeprom(self): + self.write_reg(0x50870, 0xFFFFFFFF) + + def init_spi_master(self): + self.write_reg(0x0c, 0x06) # MSWT EEPROM select, disable write protect + self.write_reg(0x00068, 0x00000003) # mask first 3 SPI_CLK out of 8 per Mwire spec + self.write_reg(0x00080, 0xA0000000) + self.write_reg(0x00080, 0xA000000F) # skip every other write/read, arm logic analyzer + self.write_reg(0x50840, 0x0000000A) # soft reset SPI master + self.write_reg(0x50860, 0x000001E6) # inhibit Tx, manual CS_N, Tx/Rx FIFO reset, master, enable + self.write_reg(0x50860, 0x00000186) # deassert Tx/Rx FIFO reset + + def stage_write_enable(self): + self.slave_deselect_mgmt_eeprom() + self.write_reg(0x50860, 0x00000186) # disable Tx output + self.write_reg(0x50868, 0x000000f3) # write Tx FIFO, {3'b0, opcode[12:8]} = 0x13 + self.write_reg(0x50868, 0x00000000) # write Tx FIFO, opcode[7:0] = 0x00 + + def launch_read_operation(self): + self.slave_select_mgmt_eeprom() + self.write_reg(0x00068, 0x00000013) # special read bit + self.write_reg(0x50860, 0x00000096) # enable Tx output, launch transaction + + def launch_write_operation(self): + self.slave_select_mgmt_eeprom() + self.write_reg(0x50860, 0x00000086) # enable Tx output, launch transaction + + def stage_word_read(self, address): + self.slave_deselect_mgmt_eeprom() + + self.write_reg(0x50860, 0x00000196) # disable Tx output + + self.write_reg(0x50868, 0xf0) # start bit (1) + opcode (read: 10) + self.write_reg(0x50868, address << 1) + self.write_reg(0x50868, 0x00) + self.write_reg(0x50868, 0x00) + + def read_received_data(self): + self.slave_deselect_mgmt_eeprom() + + self.write_reg(0x00068, 0x00000003) # reset special read bit + self.write_reg(0x50860, 0x00000196) # disable Tx output + + self.read_reg(0x5086c) # read Rx FIFO, expect dummy byte 0, discard + self.read_reg(0x5086c) # read Rx FIFO, expect dummy byte 1, discard + self.read_reg(0x5086c) # read data [15:8] + self.read_reg(0x5086c) # read data [7:0] + + def stage_word_write(self, address, byte1, byte0): + self.slave_deselect_mgmt_eeprom() + + self.write_reg(0x50860, 0x00000186) # disable Tx output + + # The EEPROM is a Microwire 93LC86C (16Kb) -- the word size is 16-bits + self.write_reg(0x50868, 0xf4) # start bit (1) + opcode (write: 01) + self.write_reg(0x50868, address) # address + self.write_reg(0x50868, byte1) # data [15:8] + self.write_reg(0x50868, byte0) # data [7:0] + + def write_word(self, address, byte1, byte0): + self.stage_word_write(address, byte1, byte0) + time.sleep(0.1) + self.launch_write_operation() + time.sleep(0.1) + self.read_received_data() + time.sleep(0.1) + + def write_read_word(self, address, byte1, byte0): + self.stage_word_write(address, byte1, byte0) + time.sleep(0.1) + self.launch_write_operation() + time.sleep(0.1) + self.read_received_data() + time.sleep(0.1) + + self.stage_word_read(address) + time.sleep(0.1) + self.launch_read_operation() + time.sleep(0.1) + self.read_received_data() + + def read_word(self, address): + self.stage_word_read(address) + time.sleep(0.1) + self.launch_read_operation() + time.sleep(0.1) + self.read_received_data() + + def program_all(self): + # Initial setup + self.init_spi_master() + self.stage_write_enable() + self.launch_write_operation() + self.read_received_data() + + # Program the EEPROM contents + # Configure Port 5 (SGMII) as 1G + AN disabled + self.write_word(0x0, 0xa8, 0x20) + self.write_word(0x1, 0xff, 0x01) + self.write_word(0x2, 0x00, 0xe6) + self.write_word(0x3, 0x00, 0x01) + self.write_word(0x4, 0x00, 0x01) + self.write_word(0x5, 0xff, 0x01) + self.write_word(0x6, 0x00, 0x14) + self.write_word(0x7, 0x3e, 0x01) + self.write_word(0x8, 0x80, 0x00) + self.write_word(0x9, 0x20, 0x01) + self.write_word(0xa, 0x0c, 0x2f) + self.write_word(0xb, 0x3e, 0x01) + self.write_word(0xc, 0x83, 0x00) + self.write_word(0xd, 0x20, 0x01) + self.write_word(0xe, 0x01, 0x0d) + self.write_word(0xf, 0x3e, 0x01) + self.write_word(0x10, 0x84, 0x70) + self.write_word(0x11, 0x26, 0x01) + self.write_word(0x12, 0x12, 0x51) + self.write_word(0x13, 0x3e, 0x01) + self.write_word(0x14, 0x83, 0x40) + self.write_word(0x15, 0x34, 0x01) + self.write_word(0x16, 0x00, 0x03) + self.write_word(0x17, 0x3e, 0x01) + self.write_word(0x18, 0x80, 0x00) + self.write_word(0x19, 0x00, 0x01) + self.write_word(0x1a, 0x01, 0x40) + self.write_word(0x1b, 0x20, 0x01) + self.write_word(0x1c, 0x2c, 0x2f) + self.write_word(0x1d, 0xff, 0x01) + self.write_word(0x1e, 0x00, 0x00) + self.write_word(0x1f, 0x5d, 0x01) + self.write_word(0x20, 0x00, 0x4b) + + def stage_erase_all(self): + self.slave_deselect_mgmt_eeprom() + self.write_reg(0x50860, 0x00000186) # disable Tx output + self.write_reg(0x50868, 0x000000f2) # write Tx FIFO, {3'b0, opcode[12:8]} = 0x12 + self.write_reg(0x50868, 0x00000000) # write Tx FIFO, opcode[7:0] = 0x00 diff --git a/platform/broadcom/sonic-platform-modules-nexthop/nh-5010/utils/asic_init.sh b/platform/broadcom/sonic-platform-modules-nexthop/nh-5010/utils/asic_init.sh new file mode 100755 index 00000000000..11da39ea6ff --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-nexthop/nh-5010/utils/asic_init.sh @@ -0,0 +1,151 @@ +#!/bin/bash + +LOCKFD=200 +LOCKFILE="/var/run/nexthop-asic-init.lock" +FPGA_BDF=$(setpci -s 00:02.2 0x19.b | xargs printf '0000:%s:00.0') +KOMODO_FPGA_BDF=$(setpci -s 00:02.1 0x19.b | xargs printf '0000:%s:00.0') +LOG_TAG="asic_init" + +fpga_write() { + local offset="$1" + local value="$2" + + fpga write32 "$FPGA_BDF" "$offset" "$value" + if [ $? -ne 0 ]; then + logger -t $LOG_TAG -p error "Error writing $value to reg $offset on fpga $FPGA_BDF" + exit 1 + fi +} + +komodo_fpga_read() { + local offset="$1" + fpga read32 "$KOMODO_FPGA_BDF" "$offset" + if [ $? -ne 0 ]; then + logger -t $LOG_TAG -p error "Error reading from reg $offset on fpga $KOMODO_FPGA_BDF" + exit 1 + fi +} + +function acquire_lock() { + if [[ ! -f $LOCKFILE ]]; then + touch $LOCKFILE + fi + + logger -t $LOG_TAG "Acquiring ${LOCKFILE}" + + exec {LOCKFD}>${LOCKFILE} + /usr/bin/flock -x ${LOCKFD} + trap "/usr/bin/flock -u ${LOCKFD}" EXIT + + logger -t $LOG_TAG "Acquired ${LOCKFILE}" +} + +function release_lock() { + /usr/bin/flock -u ${LOCKFD} + logger -t $LOG_TAG "Released ${LOCKFILE}" +} + +function enable_phy() { + #Put PHYs in reset + fpga_write 0x4090 0xFFFF2000 + fpga_write 0x4094 0xFFFF2000 + sleep 1 + + #Enable PHY clocks + fpga_write 0x4090 0xFFFF2100 + fpga_write 0x4094 0xFFFF2100 + sleep 1 + + #PHYs out of reset and SERBOOT set to SPI boot + fpga_write 0x4090 0xFFFF3FFF + fpga_write 0x4094 0xFFFF3FFF +} + +function clear_sticky_bits() { + # This function clears all the sticky bits (Clear On Write) for various + # power monitoring and other status registers in the switch/mezz card FPGAs. + + ### Switch Card + # Shift Chains Status + fpga_write 0xf0 0xffffffff + # Input Status State Change Flags + fpga_write 0x120 0xffffffff + # Q3D GPIO State Change Flags + fpga_write 0x124 0xffffffff + # Q3D TS I/F GPIO State Change Flags + fpga_write 0x128 0xffffffff + # Port 33-48 Mod Present Change Flags + fpga_write 0x1a0 0xffffffff + # Port 33-48 Interrupt Change Flags + fpga_write 0x1a4 0xffffffff + # Port 33-48 Power Good Change Flags + fpga_write 0x1a8 0xffffffff + # Port 49-64 Mod Present Change Flags + fpga_write 0x1ac 0xffffffff + # Port 49-64 Interrupt Change Flags + fpga_write 0x1b0 0xffffffff + # Port 49-64 Power Good Change Flags + fpga_write 0x1b4 0xffffffff + # CPU-Switch Card Status Change Flags + fpga_write 0x1b8 0xffffffff + # SFP Mgmt Card Status Change Flags + fpga_write 0x1bc 0xffffffff + # Miscellaneous Status 0 Change Flags + fpga_write 0x1c0 0xffffffff + # Miscellaneous Status 1 Change Flags + fpga_write 0x1c4 0xffffffff + # Fan Card Status Change Flags + fpga_write 0x1c8 0xffffffff + # Mezz-Switch Card Status Change Flags + fpga_write 0x1cc 0xffffffff + + ### Mezz Card + # Shift Chains Status + fpga_write 0x40f0 0xffffffff + # Input Status State Change Flags + fpga_write 0x4120 0xffffffff + # Port 1-16 Mod Present Change Flags + fpga_write 0x41a0 0xffffffff + # Port 1-16 Interrupt Change Flags + fpga_write 0x41a4 0xffffffff + # Port 1-16 Power Good Change Flags + fpga_write 0x41a8 0xffffffff + # Port 17-32 Mod Present Change Flags + fpga_write 0x41ac 0xffffffff + # Port 17-32 Interrupt Change Flags + fpga_write 0x41b0 0xffffffff + # Port 17-32 Power Good Change Flags + fpga_write 0x41b4 0xffffffff + # Miscellaneous Status West Change Flags + fpga_write 0x41c0 0xffffffff + # Miscellaneous Status East Change Flags + fpga_write 0x41c4 0xffffffff + # Mezz-Switch Card Status Change Flags + fpga_write 0x41cc 0xffffffff +} + +if [ -f /disable_asic ]; then + logger -p user.warning -t $LOG_TAG "ASIC init disabled due to /disable_asic file" + exit 0 +fi + +acquire_lock + +# Per HW, do this right before taking the ASIC out of reset. +clear_sticky_bits + +# Switchcard revision is in Komodo FPGA register 0x44 bottom 4 bits +switchcard_revision=$(($(komodo_fpga_read 0x44) & 0xF)) + +# Take the asic out of reset +fpga_write 0x8 0x112 +sleep 2 +fpga_write 0x8 0x102 +sleep 0.2 +fpga_write 0x8 0x502 + +enable_phy + +release_lock + +exit 0 diff --git a/platform/broadcom/sonic-platform-modules-nexthop/test/fixtures/adm1266_test_spec.json b/platform/broadcom/sonic-platform-modules-nexthop/test/fixtures/adm1266_test_spec.json new file mode 100644 index 00000000000..6f45f6a1d79 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-nexthop/test/fixtures/adm1266_test_spec.json @@ -0,0 +1,45 @@ +{ + "description": "Self-contained ADM1266 test vector using embedded hexdump lines; only hex byte pairs kept", + "hexdump_lines": [ + "23 00 02 01 00 10 0c 00 0b 00 00 00 00 00 1f 3c", + "f9 32 00 00 fc 1f 4d 11 79 2e ee 02 00 00 00 00", + "ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff", + "ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff d2", + "22 00 02 01 00 10 0c 00 0b 00 00 00 00 00 1f 3c", + "f9 32 00 00 fc 1f 4c 11 38 cc 80 02 00 00 00 00", + "ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff", + "ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff d0", + "21 00 02 01 00 10 0c 00 0b 00 00 00 00 00 1f 3c", + "f9 32 00 00 fc 1f 4b 11 63 42 a8 02 00 00 00 00", + "ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff", + "ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 6d" + ], + "expected_blackbox_records": [ + { "fault_uid": 35, "action": 1, "rule": 0, "vhx": 16, "current": 12, "last": 11, "vp_ov": 0, "vp_uv": 0, "gpio_in": 15391, "gpio_out": 13049, "pdio_in": 0, "pdio_out": 8188, "powerup": 4429 }, + { "fault_uid": 34, "action": 1, "rule": 0, "vhx": 16, "current": 12, "last": 11, "vp_ov": 0, "vp_uv": 0, "gpio_in": 15391, "gpio_out": 13049, "pdio_in": 0, "pdio_out": 8188, "powerup": 4428 }, + { "fault_uid": 33, "action": 1, "rule": 0, "vhx": 16, "current": 12, "last": 11, "vp_ov": 0, "vp_uv": 0, "gpio_in": 15391, "gpio_out": 13049, "pdio_in": 0, "pdio_out": 8188, "powerup": 4427 } + ], + "expected_reboot_causes": [ + { "fault_uid": "0x23", "powerup": "0x114d", "action": "0x1", "rule": "0x0", "current": "0xc", "last": "0xb", + "vhx": "VH5 (0b00010000)", "vp_ov": "0b0000000000000000", "vp_uv": "0b0000000000000000", + "gpio_in": "GPIO1,GPIO2,GPIO3,GPIO4,GPIO5,GPIO11,GPIO12,GPIO13,GPIO14 (0b0011110000011111)", + "gpio_out": "GPIO1,GPIO4,GPIO5,GPIO6,GPIO7,GPIO8,GPIO10,GPIO13,GPIO14 (0b0011001011111001)", + "pdio_in": "0b0000000000000000", + "pdio_out": "PDIO3,PDIO4,PDIO5,PDIO6,PDIO7,PDIO8,PDIO9,PDIO10,PDIO11,PDIO12,PDIO13 (0b0001111111111100)", + "timestamp": "12 minutes 30.181534 seconds after power-on" }, + { "fault_uid": "0x22", "powerup": "0x114c", "action": "0x1", "rule": "0x0", "current": "0xc", "last": "0xb", + "vhx": "VH5 (0b00010000)", "vp_ov": "0b0000000000000000", "vp_uv": "0b0000000000000000", + "gpio_in": "GPIO1,GPIO2,GPIO3,GPIO4,GPIO5,GPIO11,GPIO12,GPIO13,GPIO14 (0b0011110000011111)", + "gpio_out": "GPIO1,GPIO4,GPIO5,GPIO6,GPIO7,GPIO8,GPIO10,GPIO13,GPIO14 (0b0011001011111001)", + "pdio_in": "0b0000000000000000", + "pdio_out": "PDIO3,PDIO4,PDIO5,PDIO6,PDIO7,PDIO8,PDIO9,PDIO10,PDIO11,PDIO12,PDIO13 (0b0001111111111100)", + "timestamp": "10 minutes 40.797729 seconds after power-on" }, + { "fault_uid": "0x21", "powerup": "0x114b", "action": "0x1", "rule": "0x0", "current": "0xc", "last": "0xb", + "vhx": "VH5 (0b00010000)", "vp_ov": "0b0000000000000000", "vp_uv": "0b0000000000000000", + "gpio_in": "GPIO1,GPIO2,GPIO3,GPIO4,GPIO5,GPIO11,GPIO12,GPIO13,GPIO14 (0b0011110000011111)", + "gpio_out": "GPIO1,GPIO4,GPIO5,GPIO6,GPIO7,GPIO8,GPIO10,GPIO13,GPIO14 (0b0011001011111001)", + "pdio_in": "0b0000000000000000", + "pdio_out": "PDIO3,PDIO4,PDIO5,PDIO6,PDIO7,PDIO8,PDIO9,PDIO10,PDIO11,PDIO12,PDIO13 (0b0001111111111100)", + "timestamp": "11 minutes 20.259323 seconds after power-on"} + ] +} diff --git a/platform/broadcom/sonic-platform-modules-nexthop/test/fixtures/fake_swsscommon.py b/platform/broadcom/sonic-platform-modules-nexthop/test/fixtures/fake_swsscommon.py new file mode 100644 index 00000000000..af96e3cb766 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-nexthop/test/fixtures/fake_swsscommon.py @@ -0,0 +1,83 @@ +#!/usr/bin/env python + +# Copyright 2025 Nexthop Systems Inc. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +""" +Shared fake implementation of swsscommon for unit testings. + +The real swsscommon module has external dependencies that are +difficult to meet in a unit testing environment. This fake +implementation provides the minimum functionality of the database +required by the platform modules for unit tests. + +Call setup_fake_swsscommon() from a pytest fixture to inject +the fake swsscommon module. +""" + +import sys + +from unittest.mock import Mock + + +class FakeDBConnector: + """Fake implementation of swsscommon.DBConnector for testing.""" + + def __init__(self, db_name: str, retry: int): + self.db_name = db_name + + +class FakeFieldValuePairs: + """Fake implementation of swsscommon.FieldValuePairs for testing.""" + + def __init__(self, fvs: list[tuple[str, str]]): + self.dict = dict(fvs) + + +class FakeTable: + """Fake implementation of swsscommon.Table for testing.""" + + # Global in-memory DB. Shared across all FakeTable instances. + # + # Key: db_name, Value: table data + # Example: + # { + # "STATE_DB": { + # "FAN_INFO": { + # "Fantray1_1": {"max_speed": "75"} + # "Fantray1_2": {"max_speed": "75"} + # } + # } + # } + _global_db = {} + + def __init__(self, db_connector: FakeDBConnector, table_name: str): + self.db_name = db_connector.db_name + self.table_name = table_name + if self.db_name not in self._global_db: + self._global_db[self.db_name] = {} + if table_name not in self._global_db[self.db_name]: + self._global_db[self.db_name][table_name] = {} + + def set(self, key: str, fvp: FakeFieldValuePairs) -> None: + if key not in self._global_db[self.db_name][self.table_name]: + self._global_db[self.db_name][self.table_name][key] = {} + self._global_db[self.db_name][self.table_name][key].update(fvp.dict) + + def get(self, key: str) -> tuple[bool, dict]: + if key in self._global_db[self.db_name][self.table_name]: + return True, self._global_db[self.db_name][self.table_name][key] + else: + return False, {} + + +def setup_fake_swsscommon(): + """ + Sets up mock swsscommon module that contains a fake, simpliflied + implementation of the database using an in-memory dictionary. + """ + swsscommon = Mock() + swsscommon.swsscommon.DBConnector = FakeDBConnector + swsscommon.swsscommon.FieldValuePairs = FakeFieldValuePairs + swsscommon.swsscommon.Table = FakeTable + sys.modules["swsscommon"] = swsscommon diff --git a/platform/broadcom/sonic-platform-modules-nexthop/test/fixtures/fixtures_unit_test.py b/platform/broadcom/sonic-platform-modules-nexthop/test/fixtures/fixtures_unit_test.py index c1ac62de3a0..4a33f27d18e 100644 --- a/platform/broadcom/sonic-platform-modules-nexthop/test/fixtures/fixtures_unit_test.py +++ b/platform/broadcom/sonic-platform-modules-nexthop/test/fixtures/fixtures_unit_test.py @@ -13,7 +13,7 @@ import importlib.util from unittest.mock import Mock import pytest - +import tempfile class PddfChassisMock: """Mock implementation of PddfChassis for testing.""" @@ -38,6 +38,203 @@ def set_system_led(self, led_name, color): def get_system_led(self, led_name): return "green" +def process_input(json_file): + """Load a JSON test spec and return (blackbox_data, expected_records, expected_causes). + + The JSON must contain: + - hexdump_lines: array of hexdump lines (strings) + Optionally: + - expected_records: list[dict] of raw numeric expectations + - expected_causes: list[dict] of rendered string expectations + """ + import json + + def parse_hexdump_lines(lines): + bb = bytearray() + hexchars = set("0123456789abcdefABCDEF") + for line in lines: + for tok in line.split(): + if len(tok) == 2 and all(c in hexchars for c in tok): + bb.append(int(tok, 16)) + return bytes(bb) + + with open(json_file, 'r') as f: + spec = json.load(f) + + if 'hexdump_lines' not in spec: + raise ValueError('JSON must include hexdump_lines') + blackbox_data = parse_hexdump_lines(spec['hexdump_lines']) + expected_records = spec.get('expected_blackbox_records') + expected_causes = spec.get('expected_reboot_causes') + + return blackbox_data, expected_records, expected_causes + +class DpmInfoMock: + def __init__(self): + # Carelessly made up stuff - Not accurate for any HW platform + + self.dpm_signals = { + 1 : 2, # PDIO bit 0 - Fault code bit 2 + 14 : 0, # PDIO bit 13 - Fault code bit 0 + 15 : 1 # PDIO bit 14 - Fault code bit 1 + } + self.dpm_table = { + 0 : "", + 1 : "THERMTRIP_L: CPU has exceeded Tdie,shutdown", + 2 : "CPU_PWR_CYC_REQ", + 3 : "BMC_PWR_CYC_REQ", + 4 : "FPGA_PWR_CYC_REQ", + 5 : "Switch Card CP power bad" + } + self.power_fault_cause = { + 0: ("PSU_VIN_LOSS", "Both PSUs lost input power"), # PDIO1 (0) + 1: ("OVER_TEMP", "Switch card temp sensor OT)"), # PDIO2 (1) + 2: ("CPU_PWR_BAD", "CPU card power bad"), # PDIO3 (2) + 3: ("WACHDOG", "FPGA watchdog expired"), # PDIO4 (3) + 4: ("ASIC_OT", "ASIC MAX_TEMP exceeded OT threshold"), # PDIO5 (4) + 5: ("NO_FAN_PRSNT", "All 4 fans have same ID=0xf"), # PDIO6 (5) + 6: ("CMD_PWR_CYC", "Software commanded power cycle"), # PDIO7 (6) + 7: ("DP_PWR_ON", "P2 only: from shift chain; not used on P1"), # PDIO8 (7) + 9: ("FPGA_CMD_PCYC", "FPGA commanded power cycle"), # PDIO10 (9) + 10:("CMD_ASIC_PWR_OFF", "FPGA command ASIC power off"), # PDIO11 (10) + } + + self.vp_to_pdio_desc = { + 5: { "pdio": 2, "rail": "POS0V75_S5" }, # VP6 -> PDIO3 + 6: { "pdio": 3, "rail": "POS1V8_S5" }, # VP7 -> PDIO4 + 7: { "pdio": 4, "rail": "POS3V3_S5" }, # VP8 -> PDIO5 + 8: { "pdio": 6, "rail": "POS1V1_S0" }, # VP9 -> PDIO7 + 9: { "pdio": 7, "rail": "POS0V78_S0" }, # VP10 -> PDIO8 + 10: { "pdio": 8, "rail": "POS0V75_S0" }, # VP11 -> PDIO9 + 11: { "pdio": 9, "rail": "POS1V8_S0" }, # VP12 -> PDIO10 + 12: { "pdio": 10, "rail": "POS3V3_S0" }, # VP13 -> PDIO11 + } + + self.vh_to_pdio_desc = { + 4: { "pdio": 5, "rail": "POS5V0_S0" }, # VH4_UV (bit 4) -> PDIO6 (bit 5) + } + self._create_nvmem_path() + + def get_vp_to_pdio_desc(self): + return self.vp_to_pdio_desc + + def get_vh_to_pdio_desc(self): + return self.vh_to_pdio_desc + + def get_dpm_signals(self): + return self.dpm_signals + + def get_dpm_table(self): + return self.dpm_table + + def get_power_fault_cause(self): + return self.power_fault_cause + + def get_nvmem_path(self): + return self.nvmem_path + + def get_name(self): + return "dpm-mock" + + def _create_nvmem_path(self): + """Create temporary file with binary data and return path""" + nvmem_file = tempfile.NamedTemporaryFile(delete=False) + nvmem_file.close() + self.nvmem_path = nvmem_file.name + + def __del__(self): + """Clean up temporary file""" + if os.path.exists(self.nvmem_path): + os.unlink(self.nvmem_path) + +class Adm1266Mock: + """ + Mock implementation of ADM1266 for unit testing. + Reads test data from provided file paths. + """ + def __init__(self): + os.path.dirname(__file__), + + json_file = os.path.join(os.path.dirname(__file__), "adm1266_test_spec.json") + data, records, causes = process_input(json_file) + self.blackbox_input = data + self.expected_records = records + self.expected_causes = causes + + self.dpm_info = DpmInfoMock() + + # Load the adm1266 module directly from file path + test_dir = os.path.dirname(os.path.realpath(__file__)) + adm1266_path = os.path.join(test_dir, "../../common/sonic_platform/adm1266.py") + + spec = importlib.util.spec_from_file_location("adm1266", adm1266_path) + adm1266_module = importlib.util.module_from_spec(spec) + spec.loader.exec_module(adm1266_module) + self.adm = adm1266_module.Adm1266(self.dpm_info) + + self._setup_nvmem_file(data) + + def _setup_nvmem_file(self, binary_data): + """Populate nvmem file with binary data """ + with open(self.dpm_info.get_nvmem_path(), 'wb') as nvmem_file: + nvmem_file.write(binary_data) + + def get_blackbox_input(self): + return self.blackbox_input + + def get_expected_records(self): + return self.expected_records + + def get_expected_causes(self): + return self.expected_causes + + def read_blackbox(self): + return self.adm.read_blackbox() + + def get_blackbox_records(self): + return self.adm.get_blackbox_records() + + def get_reboot_causes(self): + return self.adm.get_reboot_causes() + + def parse_blackbox(self, data): + return self.adm.parse_blackbox(data) + + def get_reboot_cause(self): + return self.adm.get_reboot_cause() + + def clear_blackbox(self): + self.adm.clear_blackbox() + self.blackbox_cleared = True + + +class WatchdogBaseMock: + """Mock of WatchdogBase for testing.""" + + def arm(self, seconds): + raise NotImplementedError + + def disarm(self): + raise NotImplementedError + + def is_armed(self): + raise NotImplementedError + + def get_remaining_time(self): + raise NotImplementedError + + +class WatchdogMock(WatchdogBaseMock): + def __init__( + self, + fpga_pci_addr: str, + event_driven_power_cycle_control_reg_offset: int, + watchdog_counter_reg_offset: int, + ): + self.fpga_pci_addr: str = fpga_pci_addr + self.event_driven_power_cycle_control_reg_offset: int = event_driven_power_cycle_control_reg_offset + self.watchdog_counter_reg_offset: int = watchdog_counter_reg_offset + class WatchdogBaseMock: """Mock of WatchdogBase for testing.""" @@ -137,6 +334,31 @@ def watchdog(mock_pddf_data): ) +@pytest.fixture +def watchdog(mock_pddf_data): + """ + Fixture providing a Watchdog instance for testing. + """ + # Set up the specific WatchdogBase mock with our test implementation + watchdog_base_mock = Mock() + watchdog_base_mock.WatchdogBase = WatchdogBaseMock + sys.modules["sonic_platform_base.watchdog_base"] = watchdog_base_mock + + # Load the module directly from file path + test_dir = os.path.dirname(os.path.realpath(__file__)) + watchdog_path = os.path.join(test_dir, "../../common/sonic_platform/watchdog.py") + + spec = importlib.util.spec_from_file_location("watchdog", watchdog_path) + watchdog_module = importlib.util.module_from_spec(spec) + spec.loader.exec_module(watchdog_module) + + return watchdog_module.Watchdog( + fpga_pci_addr="FAKE_FPGA_PCI_ADDR", + event_driven_power_cycle_control_reg_offset=0x28, + watchdog_counter_reg_offset=0x1E0, + ) + + @pytest.fixture def mock_sfps(chassis): """ diff --git a/platform/broadcom/sonic-platform-modules-nexthop/test/fixtures/test_helpers_eeprom.py b/platform/broadcom/sonic-platform-modules-nexthop/test/fixtures/test_helpers_eeprom.py index 66d1f46fd3c..aa71046fb4d 100644 --- a/platform/broadcom/sonic-platform-modules-nexthop/test/fixtures/test_helpers_eeprom.py +++ b/platform/broadcom/sonic-platform-modules-nexthop/test/fixtures/test_helpers_eeprom.py @@ -116,6 +116,7 @@ def get_standard_eeprom_program_data() -> dict: "vendor_name": "Nexthop", "service_tag": "www.nexthop.ai", "custom_serial_number": "123", + "regulatory_model_number": "NH99-99", } @staticmethod @@ -130,21 +131,22 @@ def get_expected_tlv_output() -> str: TlvInfo Header: Id String: TlvInfo Version: 1 - Total Length: 109 -TLV Name Code Len Value --------------------- ---- --- ----- -Product Name 0x21 7 NH-4010 -Part Number 0x22 3 ABC -Serial Number 0x23 3 XYZ -Base MAC Address 0x24 6 00:E1:4C:68:00:C4 -Device Version 0x26 1 0 -Label Revision 0x27 2 P0 -Platform Name 0x28 22 x86_64-nexthop_4010-r0 -Manufacturer 0x2B 7 Nexthop -Vendor Name 0x2D 7 Nexthop -Service Tag 0x2F 14 www.nexthop.ai -Custom Serial Number 0xFD 9 123 -CRC-32 0xFE 4 0xB5306162 + Total Length: 122 +TLV Name Code Len Value +------------------------- ---- --- ----- +Product Name 0x21 7 NH-4010 +Part Number 0x22 3 ABC +Serial Number 0x23 3 XYZ +Base MAC Address 0x24 6 00:E1:4C:68:00:C4 +Device Version 0x26 1 0 +Label Revision 0x27 2 P0 +Platform Name 0x28 22 x86_64-nexthop_4010-r0 +Manufacturer 0x2B 7 Nexthop +Vendor Name 0x2D 7 Nexthop +Service Tag 0x2F 14 www.nexthop.ai +Custom Serial Number 0xFD 8 123 +Regulatory Model Number 0xFD 12 NH99-99 +CRC-32 0xFE 4 0x368C1825 """ diff --git a/platform/broadcom/sonic-platform-modules-nexthop/test/integration/nexthop/test_adm1266_chassis_integration.py b/platform/broadcom/sonic-platform-modules-nexthop/test/integration/nexthop/test_adm1266_chassis_integration.py new file mode 100644 index 00000000000..2a9b17a1291 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-nexthop/test/integration/nexthop/test_adm1266_chassis_integration.py @@ -0,0 +1,47 @@ +#!/usr/bin/env python + +import pytest +import sys +from unittest.mock import Mock, patch, mock_open +import os + +# Import test fixtures +sys.path.insert(0, '../../fixtures') +from fixtures_unit_test import Adm1266Mock + + +@pytest.fixture +def chassis(): + """Create a mock chassis for integration testing.""" + from unittest.mock import Mock + + chassis_mock = Mock() + chassis_mock._blackbox = None # Will be set by individual tests + + def mock_get_reboot_cause(): + if chassis_mock._blackbox is None: + return ('REBOOT_CAUSE_NON_HARDWARE', 'Unknown') + + # Delegate to the ADM1266 mock + return chassis_mock._blackbox.get_reboot_cause() + + chassis_mock.get_reboot_cause = mock_get_reboot_cause + return chassis_mock + + +class TestAdm1266ChassisIntegration: + """Integration tests for ADM1266 with chassis - reboot cause only.""" + + def test_clear_blackbox_integration(self, chassis): + """Test blackbox clearing through chassis interface.""" + chassis._blackbox = Adm1266Mock() + + # Initially has faults + fault_data = chassis.get_reboot_cause() + assert len(fault_data), "no fault data" + + # Clear blackbox + chassis._blackbox.clear_blackbox() + + # Should now show cleared state + assert chassis._blackbox.blackbox_cleared == True diff --git a/platform/broadcom/sonic-platform-modules-nexthop/test/integration/nexthop/test_eeprom_utils_integration.py b/platform/broadcom/sonic-platform-modules-nexthop/test/integration/nexthop/test_eeprom_utils_integration.py index 1246b2a7dfa..5a0050d1317 100644 --- a/platform/broadcom/sonic-platform-modules-nexthop/test/integration/nexthop/test_eeprom_utils_integration.py +++ b/platform/broadcom/sonic-platform-modules-nexthop/test/integration/nexthop/test_eeprom_utils_integration.py @@ -39,6 +39,7 @@ decode_eeprom, get_at24_eeprom_paths, program_eeprom, + Eeprom, ) @@ -64,6 +65,218 @@ def test_program_and_decode(self, capsys): out, _ = capsys.readouterr() assert expected in out + def test_decode_known_buggy_custom_serial_number(self, capsys): + """ + Under full SONiC environment, + Test decoding and reprogramming EEPROM data when "Custom Serial Number" + TLV has a known bug, where byte 2 of the TLV contains a garbage value. + """ + # Given + root = tempfile.mktemp() + os.makedirs(root) + eeprom_path = os.path.join(root, "eeprom") + self.create_fake_eeprom(eeprom_path) + + # When + program_data = self.get_standard_eeprom_program_data() + for k in program_data: + program_data[k] = None + program_data["custom_serial_number"] = "123" + program_eeprom(eeprom_path=eeprom_path, **program_data) + + # Then + expected = """\ +TlvInfo Header: + Id String: TlvInfo + Version: 1 + Total Length: 16 +TLV Name Code Len Value +------------------------- ---- --- ----- +Custom Serial Number 0xFD 8 123 +CRC-32 0xFE 4 0x8F92A23C +""" + decode_eeprom(eeprom_path) + out, _ = capsys.readouterr() + assert expected in out + + # But When + # Byte 2 of the "Custom Serial Number" TLV contains a garbage value + with open(eeprom_path, "rb") as f: + e = bytearray(f.read()) + csn_tlv_start = Eeprom._TLV_INFO_HDR_LEN + e = e[:csn_tlv_start + 2] + bytearray([0xff]) + e[csn_tlv_start + 2:] + # Increment payload length by 1 + e[csn_tlv_start + 1] += 1 + # Increment total EEPROM data length by 1 + total_length = e[9] << 8 | e[10] + total_length += 1 + e[9] = (total_length >> 8) & 0xFF + e[10] = total_length & 0xFF + # Write the modified EEPROM data back to file + with open(eeprom_path, "wb") as f: + f.write(e) + + # Then can still decode + expected = """\ +TlvInfo Header: + Id String: TlvInfo + Version: 1 + Total Length: 17 +TLV Name Code Len Value +------------------------- ---- --- ----- +Custom Serial Number 0xFD 9 123 +CRC-32 0xFE 4 0x8F92A23C +""" + decode_eeprom(eeprom_path) + out, _ = capsys.readouterr() + assert expected in out + + # And When programming EEPROM again + program_eeprom(eeprom_path=eeprom_path, **program_data) + + # Then the good format is restored + expected = """\ +TlvInfo Header: + Id String: TlvInfo + Version: 1 + Total Length: 16 +TLV Name Code Len Value +------------------------- ---- --- ----- +Custom Serial Number 0xFD 8 123 +CRC-32 0xFE 4 0x8F92A23C +""" + decode_eeprom(eeprom_path) + out, _ = capsys.readouterr() + assert expected in out + + def test_decode_buggy_regulatory_model_number(self, capsys): + """ + Under full SONiC environment, + Test decoding EEPROM data gives invalid output when the known bug + (byte 2 of the TLV contains a garbage value) is applied on other + Nexthop custom fields, e.g. "Regulatory Model Number". + """ + # Given + root = tempfile.mktemp() + os.makedirs(root) + eeprom_path = os.path.join(root, "eeprom") + self.create_fake_eeprom(eeprom_path) + + # When + program_data = self.get_standard_eeprom_program_data() + for k in program_data: + program_data[k] = None + program_data["regulatory_model_number"] = "123" + program_eeprom(eeprom_path=eeprom_path, **program_data) + + # Then + expected = """\ +TlvInfo Header: + Id String: TlvInfo + Version: 1 + Total Length: 16 +TLV Name Code Len Value +------------------------- ---- --- ----- +Regulatory Model Number 0xFD 8 123 +CRC-32 0xFE 4 0x0906D092 +""" + decode_eeprom(eeprom_path) + out, _ = capsys.readouterr() + assert expected in out + + # But When + # Byte 2 of the "Regulatory Model Number" TLV contains a garbage value + with open(eeprom_path, "rb") as f: + e = bytearray(f.read()) + csn_tlv_start = Eeprom._TLV_INFO_HDR_LEN + e = e[:csn_tlv_start + 2] + bytearray([0xff]) + e[csn_tlv_start + 2:] + # Increment payload length by 1 + e[csn_tlv_start + 1] += 1 + # Increment total EEPROM data length by 1 + total_length = e[9] << 8 | e[10] + total_length += 1 + e[9] = (total_length >> 8) & 0xFF + e[10] = total_length & 0xFF + # Write the modified EEPROM data back to file + with open(eeprom_path, "wb") as f: + f.write(e) + + # Then + expected = """\ +TlvInfo Header: + Id String: TlvInfo + Version: 1 + Total Length: 17 +TLV Name Code Len Value +------------------------- ---- --- ----- +Vendor Extension 0xFD 9 Invalid IANA: 4278190326, expected 63074 +CRC-32 0xFE 4 0x0906D092 +""" + decode_eeprom(eeprom_path) + out, _ = capsys.readouterr() + assert expected in out + + def test_program_replace_nh_custom_fields(self, capsys): + """ + Under full SONiC environment, + Test re-programming EEPROM data with Nexthop custom fields being replaced. + """ + # Given + root = tempfile.mktemp() + os.makedirs(root) + eeprom_path = os.path.join(root, "eeprom") + self.create_fake_eeprom(eeprom_path) + + # When + program_data = self.get_standard_eeprom_program_data() + for k in program_data: + program_data[k] = None + program_data["product_name"] = "NH-9999" + program_data["custom_serial_number"] = "111" + program_data["regulatory_model_number"] = "AAA" + program_eeprom(eeprom_path=eeprom_path, **program_data) + + expected = self.get_expected_tlv_output() + + # Then + expected = """\ +TlvInfo Header: + Id String: TlvInfo + Version: 1 + Total Length: 35 +TLV Name Code Len Value +------------------------- ---- --- ----- +Product Name 0x21 7 NH-9999 +Custom Serial Number 0xFD 8 111 +Regulatory Model Number 0xFD 8 AAA +CRC-32 0xFE 4 0xB6CE81FB +""" + decode_eeprom(eeprom_path) + out, _ = capsys.readouterr() + assert expected in out + + # And When programming EEPROM again with different values + program_data["custom_serial_number"] = "222" + program_data["regulatory_model_number"] = "BBB" + program_eeprom(eeprom_path=eeprom_path, **program_data) + + # Then the values are replaced + expected = """\ +TlvInfo Header: + Id String: TlvInfo + Version: 1 + Total Length: 35 +TLV Name Code Len Value +------------------------- ---- --- ----- +Product Name 0x21 7 NH-9999 +Custom Serial Number 0xFD 8 222 +Regulatory Model Number 0xFD 8 BBB +CRC-32 0xFE 4 0x314BC9F0 +""" + decode_eeprom(eeprom_path) + out, _ = capsys.readouterr() + assert expected in out + def test_clear(self, capsys): """Test clearing EEPROM data with full SONiC environment.""" # Given diff --git a/platform/broadcom/sonic-platform-modules-nexthop/test/unit/nexthop/test_fpga_cli.py b/platform/broadcom/sonic-platform-modules-nexthop/test/unit/nexthop/test_fpga_cli.py index 2709d3a91de..712d84e202e 100644 --- a/platform/broadcom/sonic-platform-modules-nexthop/test/unit/nexthop/test_fpga_cli.py +++ b/platform/broadcom/sonic-platform-modules-nexthop/test/unit/nexthop/test_fpga_cli.py @@ -5,6 +5,12 @@ from nexthop.fpga_cli import ( read32, write32, + echo_available_fpgas, +) + +from nexthop.fpga_lib import ( + name_to_bdf, + bdf_to_name, ) @@ -18,7 +24,8 @@ def test_read32_valid_args(pci_address, offset, bits): @pytest.mark.parametrize("offset", ["0x1", "0x2", "0x3", "0xbeef"]) -def test_read32_unaligned_offset(offset): +def test_read32_unaligned_offset(offset, monkeypatch): + monkeypatch.setattr("nexthop.fpga_cli.find_xilinx_fpgas", lambda: ["0000:00:02.0"]) runner = CliRunner() result = runner.invoke(read32, ["0000:00:02.0", offset]) assert f"Offset ({offset}) must be 4 byte aligned" in result.output @@ -26,7 +33,8 @@ def test_read32_unaligned_offset(offset): @pytest.mark.parametrize("offset", ["0xg", "0x", "0xcoffee"]) -def test_read32_bad_hex_offset(offset): +def test_read32_bad_hex_offset(offset, monkeypatch): + monkeypatch.setattr("nexthop.fpga_cli.find_xilinx_fpgas", lambda: ["0000:00:02.0"]) runner = CliRunner() result = runner.invoke(read32, ["0000:00:02.0", offset]) assert f"Offset ({offset}) must be a valid hex number" in result.output @@ -67,7 +75,8 @@ def test_write32_valid_args(pci_address, offset, bits): @pytest.mark.parametrize("offset", ["0x1", "0x2", "0x3", "0xbeef"]) -def test_write32_unaligned_offset(offset): +def test_write32_unaligned_offset(offset, monkeypatch): + monkeypatch.setattr("nexthop.fpga_cli.find_xilinx_fpgas", lambda: ["0000:00:02.0"]) runner = CliRunner() result = runner.invoke(write32, ["0000:00:02.0", offset, "0xdeadbeef"]) assert f"Offset ({offset}) must be 4 byte aligned" in result.output @@ -75,7 +84,8 @@ def test_write32_unaligned_offset(offset): @pytest.mark.parametrize("offset", ["0xg", "0x", "0xcoffee"]) -def test_write32_bad_hex_offset(offset): +def test_write32_bad_hex_offset(offset, monkeypatch): + monkeypatch.setattr("nexthop.fpga_cli.find_xilinx_fpgas", lambda: ["0000:00:02.0"]) runner = CliRunner() result = runner.invoke(write32, ["0000:00:02.0", offset, "0xdeadbeef"]) assert f"Offset ({offset}) must be a valid hex number" in result.output @@ -110,8 +120,75 @@ def test_write32_invalid_start_bits(): assert result.exit_code == BadParameter.exit_code -def test_write32_value_exceeds_bits(): +def test_write32_value_exceeds_bits(monkeypatch): + monkeypatch.setattr("nexthop.fpga_cli.find_xilinx_fpgas", lambda: ["0000:00:02.0"]) runner = CliRunner() result = runner.invoke(write32, ["0000:00:02.0", "0x0", "0x10", "--bits=1:4"]) assert f"value (0x10) must be smaller than or equal to 0xf" in result.output assert result.exit_code == BadParameter.exit_code + + +def test_read32_with_fpga_name(monkeypatch): + monkeypatch.setattr("nexthop.fpga_cli.find_xilinx_fpgas", lambda: ["0000:e3:00.0"]) + monkeypatch.setattr("nexthop.fpga_cli.name_to_bdf", lambda name: "0000:e3:00.0" if name == "CPU_CARD_FPGA" else None) + + runner = CliRunner() + result = runner.invoke(read32, ["CPU_CARD_FPGA", "0x0"]) + assert result.exit_code != BadParameter.exit_code + + +def test_write32_with_fpga_name(monkeypatch): + monkeypatch.setattr("nexthop.fpga_cli.find_xilinx_fpgas", lambda: ["0000:e3:00.0"]) + monkeypatch.setattr("nexthop.fpga_cli.name_to_bdf", lambda name: "0000:e3:00.0" if name == "SWITCHCARD_FPGA" else None) + + runner = CliRunner() + result = runner.invoke(write32, ["SWITCHCARD_FPGA", "0x0", "0xdeadbeef"]) + assert result.exit_code != BadParameter.exit_code + + +def test_invalid_fpga_name_error_message(monkeypatch): + monkeypatch.setattr("nexthop.fpga_cli.find_xilinx_fpgas", lambda: ["0000:e3:00.0"]) + monkeypatch.setattr("nexthop.fpga_cli.name_to_bdf", lambda name: None) + + runner = CliRunner() + result = runner.invoke(read32, ["INVALID_FPGA", "0x0"]) + assert "FPGA 'INVALID_FPGA' not found" in result.output + assert "Use 'fpga list' to see available FPGAs" in result.output + assert result.exit_code == BadParameter.exit_code + + result = runner.invoke(write32, ["INVALID_FPGA", "0x0", "0xdeadbeef"]) + assert "FPGA 'INVALID_FPGA' not found" in result.output + assert "Use 'fpga list' to see available FPGAs" in result.output + assert result.exit_code == BadParameter.exit_code + + +def test_echo_available_fpgas(monkeypatch, capsys): + mock_pddf_config = { + "MULTIFPGAPCIE0": { + "dev_info": { + "device_type": "MULTIFPGAPCIE", + "device_name": "CPUCARD_FPGA", + "device_bdf": "0000:30:00.0", + } + }, + "MULTIFPGAPCIE1": { + "dev_info": { + "device_type": "MULTIFPGAPCIE", + "device_name": "SWITCHCARD_FPGA", + "device_bdf": "0000:e4:00.0", + } + } + } + + monkeypatch.setattr("nexthop.fpga_cli.load_pddf_device_config", lambda: mock_pddf_config) + monkeypatch.setattr("nexthop.fpga_lib.load_pddf_device_config", lambda: mock_pddf_config) + + echo_available_fpgas() + captured = capsys.readouterr() + print(f"Captured output: '{captured.out}'") + print(f"Captured error: '{captured.err}'") + assert "Available FPGAs" in captured.out + assert "NAME" in captured.out + assert "PCIe ADDRESS" in captured.out + assert bdf_to_name("0000:30:00.0") == "CPUCARD_FPGA" + assert bdf_to_name("0000:e4:00.0") == "SWITCHCARD_FPGA" \ No newline at end of file diff --git a/platform/broadcom/sonic-platform-modules-nexthop/test/unit/nexthop/test_fpga_lib.py b/platform/broadcom/sonic-platform-modules-nexthop/test/unit/nexthop/test_fpga_lib.py index 0b6b3118ce1..e4d5d37899a 100644 --- a/platform/broadcom/sonic-platform-modules-nexthop/test/unit/nexthop/test_fpga_lib.py +++ b/platform/broadcom/sonic-platform-modules-nexthop/test/unit/nexthop/test_fpga_lib.py @@ -1,11 +1,12 @@ import os import sys import shutil -from typing import Counter import pytest import tempfile + from dataclasses import dataclass +from typing import Counter from nexthop.fpga_lib import ( find_pci_devices, @@ -153,21 +154,21 @@ def do_test_read_write(root: str): assert read_32(pci_address, offset=0x0, root=root) == 0 assert read_32(pci_address, offset=0x4, root=root) == 0 assert read_32(pci_address, offset=0x8, root=root) == 0 - assert read_32(pci_address, offset=0xc, root=root) == 0 + assert read_32(pci_address, offset=0xC, root=root) == 0 write_32(pci_address, offset=0x100000 - 4, val=1, root=root) write_32(pci_address, offset=0x0, val=2, root=root) write_32(pci_address, offset=0x4, val=3, root=root) write_32(pci_address, offset=0x8, val=4, root=root) - with pytest.raises(ValueError): # Unaligned writes not allowed. - write_32(pci_address, offset=0xc - 1, val=0xdeadbeef, root=root) - write_32(pci_address, offset=0xc, val=0xdeadbeef, root=root) + with pytest.raises(ValueError): # Unaligned writes not allowed. + write_32(pci_address, offset=0xC - 1, val=0xDEADBEEF, root=root) + write_32(pci_address, offset=0xC, val=0xDEADBEEF, root=root) assert read_32(pci_address, offset=0x100000 - 4, root=root) == 1 assert read_32(pci_address, offset=0x0, root=root) == 2 assert read_32(pci_address, offset=0x4, root=root) == 3 assert read_32(pci_address, offset=0x8, root=root) == 4 - assert read_32(pci_address, offset=0xc, root=root) == 0xdeadbeef + assert read_32(pci_address, offset=0xC, root=root) == 0xDEADBEEF def test_read_write(): @@ -177,13 +178,13 @@ def test_read_write(): except AssertionError: resource0_path = get_resource_0_path("0000:00:02.0", root=root) print(f"\nHexdump of {resource0_path}:") - with open(resource0_path, 'rb') as f: + with open(resource0_path, "rb") as f: content = f.read() skip = False for i in range(0, len(content), 16): - chunk = content[i:i+16] + chunk = content[i : i + 16] if any(b != 0 for b in chunk): - hex_str = ' '.join(f'{b:02x}' for b in chunk) + hex_str = " ".join(f"{b:02x}" for b in chunk) print(f"{i:08x}: {hex_str}") skip = False elif not skip: diff --git a/platform/broadcom/sonic-platform-modules-nexthop/test/unit/nexthop/test_pddf_config_parser.py b/platform/broadcom/sonic-platform-modules-nexthop/test/unit/nexthop/test_pddf_config_parser.py new file mode 100644 index 00000000000..84cc3508a15 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-nexthop/test/unit/nexthop/test_pddf_config_parser.py @@ -0,0 +1,351 @@ +#!/usr/bin/env python + +# Copyright 2025 Nexthop Systems Inc. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +""" +Unit tests for the pddf_config_parser module. +""" + +import sys +import os +import json +import pytest +from unittest.mock import MagicMock +from nexthop.pddf_config_parser import ( + extract_xcvr_list, + extract_fpga_attrs, + FpgaDeviceName, + FpgaDevAttrs, +) + +# Mock sonic_py_common if not available +try: + import sonic_py_common +except ImportError: + sys.modules["sonic_py_common"] = MagicMock() + sys.modules["sonic_py_common.logger"] = MagicMock() + +CWD = os.path.dirname(os.path.realpath(__file__)) +BASE_PLATFORM_PDDF_PATH = "../../../../../../device/nexthop/{}/pddf" + + +def find_pddf_device_json(platform_variant): + """Find the pddf-device.json file for the given platform variant.""" + # First try to find pddf-device.json.j2 which dynamically generates pddf-device.json at runtime. + platform_pddf_path = os.path.join( + CWD, BASE_PLATFORM_PDDF_PATH.format(platform_variant) + ) + pddf_template_path = os.path.join(platform_pddf_path, "pddf-device.json.j2") + # If all else fails, fallback to pddf-device.json + fallback_path = os.path.join(platform_pddf_path, "pddf-device.json") + if os.path.exists(pddf_template_path): + return pddf_template_path + else: + return fallback_path + + +class TestExtractXcvrList: + """Test class for 'extract_xcvr_list' function.""" + + def test_extract_xcvr_list(self): + """Test extract_xcvr_list with a sample configuration.""" + # Sample PDDF config + config = { + "PORT1-CTRL": { + "i2c": { + "topo_info": {"parent_bus": "0x0f", "dev_addr": "0x08"}, + "attr_list": [ + {"attr_name": "xcvr_reset"}, + {"attr_name": "xcvr_lpmode"}, + {"attr_name": "xcvr_present"}, + ], + } + }, + "PORT32-CTRL": { + "i2c": { + "topo_info": {"parent_bus": "0x2e", "dev_addr": "0x08"}, + "attr_list": [ + {"attr_name": "xcvr_reset"}, + {"attr_name": "xcvr_lpmode"}, + ], + } + }, + "PORT33-CTRL": { + "i2c": { + "topo_info": {"parent_bus": "0x35", "dev_addr": "0x08"}, + "attr_list": [ + {"attr_name": "xcvr_reset"}, + {"attr_name": "xcvr_lpmode"}, + ], + } + }, + "PORTMGMT-CTRL": { + "i2c": { + "topo_info": {"parent_bus": "0x36", "dev_addr": "0x09"}, + "attr_list": [ + {"attr_name": "xcvr_reset"}, + {"attr_name": "xcvr_lpmode"}, + ], + } + }, + "SOME_OTHER_DEVICE": { + "i2c": {"topo_info": {"parent_bus": "0x01", "dev_addr": "0x50"}} + }, + } + + # When + xcvr_list = extract_xcvr_list(config) + + # Then + expected = [ + {"name": "PORT1-CTRL", "bus": 15, "addr": "0008"}, + {"name": "PORT32-CTRL", "bus": 46, "addr": "0008"}, + {"name": "PORT33-CTRL", "bus": 53, "addr": "0008"}, + ] + + assert len(xcvr_list) == 3 + for expected_xcvr in expected: + assert expected_xcvr in xcvr_list + + def test_extract_xcvr_list_missing_required_attrs(self): + """Test that devices without both xcvr_reset and xcvr_lpmode are filtered out.""" + config = { + "PORT1-CTRL": { + "i2c": { + "topo_info": {"parent_bus": "0x0f", "dev_addr": "0x08"}, + "attr_list": [ + {"attr_name": "xcvr_reset"} + # Missing xcvr_lpmode + ], + } + }, + "PORT2-CTRL": { + "i2c": { + "topo_info": {"parent_bus": "0x10", "dev_addr": "0x08"}, + "attr_list": [ + {"attr_name": "xcvr_lpmode"} + # Missing xcvr_reset + ], + } + }, + "PORT3-CTRL": { + "i2c": { + "topo_info": {"parent_bus": "0x11", "dev_addr": "0x08"}, + "attr_list": [ + {"attr_name": "xcvr_reset"}, + {"attr_name": "xcvr_lpmode"}, + ], + } + }, + } + + # When + xcvr_list = extract_xcvr_list(config) + + # Then - only PORT3-CTRL should be included + assert len(xcvr_list) == 1 + assert xcvr_list[0]["name"] == "PORT3-CTRL" + + def test_extract_xcvr_list_non_port_ctrl_devices(self): + """Test that non-PORT*-CTRL devices are filtered out.""" + config = { + "PORT1-CTRL": { + "i2c": { + "topo_info": {"parent_bus": "0x0f", "dev_addr": "0x08"}, + "attr_list": [ + {"attr_name": "xcvr_reset"}, + {"attr_name": "xcvr_lpmode"}, + ], + } + }, + "SOME_FAN": { + "i2c": { + "topo_info": {"parent_bus": "0x10", "dev_addr": "0x08"}, + "attr_list": [ + {"attr_name": "xcvr_reset"}, + {"attr_name": "xcvr_lpmode"}, + ], + } + }, + "PORT_INVALID": { + "i2c": { + "topo_info": {"parent_bus": "0x11", "dev_addr": "0x08"}, + "attr_list": [ + {"attr_name": "xcvr_reset"}, + {"attr_name": "xcvr_lpmode"}, + ], + } + }, + } + + # When + xcvr_list = extract_xcvr_list(config) + + # Then - only PORT1-CTRL should be included + assert len(xcvr_list) == 1 + assert xcvr_list[0]["name"] == "PORT1-CTRL" + + def test_extract_xcvr_list_missing_i2c_section(self): + """Test that devices without i2c section are filtered out.""" + config = { + "PORT1-CTRL": { + "some_other_section": {} + # Missing i2c section + }, + "PORT2-CTRL": { + "i2c": { + "topo_info": {"parent_bus": "0x10", "dev_addr": "0x08"}, + "attr_list": [ + {"attr_name": "xcvr_reset"}, + {"attr_name": "xcvr_lpmode"}, + ], + } + }, + } + + # When + xcvr_list = extract_xcvr_list(config) + + # Then - only PORT2-CTRL should be included + assert len(xcvr_list) == 1 + assert xcvr_list[0]["name"] == "PORT2-CTRL" + + def test_extract_xcvr_list_empty_config(self): + """Test extract_xcvr_list with empty configuration.""" + # When + xcvr_list = extract_xcvr_list({}) + + # Then + assert xcvr_list == [] + + @pytest.mark.parametrize( + "platform_variant", + ["x86_64-nexthop_4010-r0", "x86_64-nexthop_4010-r1"], + ) + def test_extract_xcvr_list_real_40x0_config(self, platform_variant): + """Test extract_xcvr_list with real NH-40x0 pddf-device.json configuration.""" + # Path to the real pddf-device.json file + config_path = find_pddf_device_json(platform_variant) + + # Load the real configuration + with open(config_path, "r") as f: + config = json.load(f) + + # When + xcvr_list = extract_xcvr_list(config) + + # Then - validate the results + assert isinstance(xcvr_list, list) + + # NH-40x0 should have 64 OSFP transceivers + assert len(xcvr_list) == 64 + + # First port starts at bus 23 + xcvr_port1 = next(xcvr for xcvr in xcvr_list if xcvr["name"] == "PORT1-CTRL") + assert xcvr_port1["bus"] == 23 + assert xcvr_port1["addr"] == "0008" + + # Verify all entries have unique names and bus numbers + names = [xcvr["name"] for xcvr in xcvr_list] + buses = [xcvr["bus"] for xcvr in xcvr_list] + assert len(names) == len(set(names)), "All transceiver names should be unique" + assert len(buses) == len(set(buses)), "All bus numbers should be unique" + + def test_extract_xcvr_list_real_5010_config(self): + """Test extract_xcvr_list with real NH-5010 pddf-device.json configuration.""" + # Path to the real pddf-device.json file + config_path = find_pddf_device_json("x86_64-nexthop_5010-r0") + + # Load the real configuration + with open(config_path, "r") as f: + config = json.load(f) + + # When + xcvr_list = extract_xcvr_list(config) + + # Then - validate the results + assert isinstance(xcvr_list, list) + + # NH-5010 should have 32 QSFP-DD, 32 QSFP112, and 2 QSFP28 transceivers + assert len(xcvr_list) == 32 + 32 + 2 + + # First QSFP-DD starts at bus 53 + xcvr_port1 = next(xcvr for xcvr in xcvr_list if xcvr["name"] == "PORT1-CTRL") + assert xcvr_port1["bus"] == 53 + assert xcvr_port1["addr"] == "0008" + # First QSFP112 starts at bus 18 + xcvr_port33 = next(xcvr for xcvr in xcvr_list if xcvr["name"] == "PORT33-CTRL") + assert xcvr_port33["bus"] == 18 + assert xcvr_port33["addr"] == "0008" + + # Verify all entries have unique names and bus numbers + names = [xcvr["name"] for xcvr in xcvr_list] + buses = [xcvr["bus"] for xcvr in xcvr_list] + assert len(names) == len(set(names)), "All transceiver names should be unique" + assert len(buses) == len(set(buses)), "All bus numbers should be unique" + + +class TestExtractFpgaDevAttrs: + FPGA_TYPES = (FpgaDeviceName.CPU_CARD.value, FpgaDeviceName.SWITCHCARD.value) + + def test_extract_fpga_attrs_malformed_config(self): + bad_configs = [] + no_dev_attr_config = { + "MULTIFPGAPCIE0": { + "dev_info": { + "device_name": "CPUCARD_FPGA", + "device_type": "MULTIFPGAPCIE", + } + } + } + bad_configs.append(no_dev_attr_config) + + no_pwr_cycle_config_reg_config = { + "MULTIFPGAPCIE0": { + "dev_info": { + "device_name": "SWITCHCARD_FPGA", + "device_type": "MULTIFPGAPCIE", + }, + "dev_attr": { + "pwr_cycle_enable_word": "0xDEADBEEF", + }, + } + } + bad_configs.append(no_pwr_cycle_config_reg_config) + + for config in bad_configs: + with pytest.raises(Exception): + extract_fpga_attrs(config, self.FPGA_TYPES) + + @pytest.mark.parametrize( + "platform_variant", + [ + "x86_64-nexthop_4010-r0", + "x86_64-nexthop_4010-r1", + "x86_64-nexthop_5010-r0", + ], + ) + def test_extract_fpga_attrs(self, platform_variant): + """Test extract_fpga_attrs with real NH pddf-device.json configuration.""" + # Path to the real pddf-device.json file + config_path = find_pddf_device_json(platform_variant) + + # Load the real configuration + with open(config_path, "r") as f: + config = json.load(f) + + # When + fpga_attrs = extract_fpga_attrs(config, self.FPGA_TYPES) + + # Then + assert fpga_attrs == { + FpgaDeviceName.CPU_CARD.value: FpgaDevAttrs( + pwr_cycle_reg_offset=0x8, + pwr_cycle_enable_word=0xDEADBEEF, + ), + FpgaDeviceName.SWITCHCARD.value: FpgaDevAttrs( + pwr_cycle_reg_offset=0x4, + pwr_cycle_enable_word=0xDEADBEEF, + ), + } diff --git a/platform/broadcom/sonic-platform-modules-nexthop/test/unit/sonic_platform/test_adm1266.py b/platform/broadcom/sonic-platform-modules-nexthop/test/unit/sonic_platform/test_adm1266.py new file mode 100644 index 00000000000..4be21ef1243 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-nexthop/test/unit/sonic_platform/test_adm1266.py @@ -0,0 +1,98 @@ +#!/usr/bin/env python + +import pytest +import sys +import tempfile +import os +from unittest.mock import Mock, patch, mock_open + +# Import test fixtures +sys.path.insert(0, '../../fixtures') +from fixtures_unit_test import Adm1266Mock + +class TestAdm1266Basic: + """Test ADM1266 basic properties and interface.""" + def test_read_blackbox(self): + """Test read_blackbox method""" + + adm = Adm1266Mock() + blackbox_input = adm.get_blackbox_input() + expected_records = adm.get_expected_records() + expected_causes = adm.get_expected_causes() + + print("\n--- Testing read_blackbox ---") + blackbox_data = adm.read_blackbox() + assert len(blackbox_data) == len(blackbox_input), \ + "Size mismatch: {len(blackbox_data)} != {len(blackbox_input)}" + assert blackbox_data == blackbox_input, "Blackbox Data mismatch" + print(" Passed") + + def test_parse_blackbox(self): + """Test parse_blackbox method""" + print("\n--- Testing parse_blackbox ---") + adm = Adm1266Mock() + blackbox_input = adm.get_blackbox_input() + expected_records = adm.get_expected_records() + expected_causes = adm.get_expected_causes() + + blackbox_data = adm.read_blackbox() + faults = adm.parse_blackbox(blackbox_data) + exp = expected_records + assert exp is not None, "expected_records not provided" + assert len(faults) == len(exp), f"Fault count mismatch: {len(faults)} != {len(exp)}" + for i, e in enumerate(exp): + a = faults[i] + for k, v in e.items(): + ak = 'uid' if k == 'fault_uid' else k + assert ak in a, f"[{i}] missing '{ak}' in parsed fault" + assert a[ak] == v, f"[{i}] {ak} mismatch: {a[ak]} != {v}" + print(" Passed") + + def test_get_blackbox_records(self): + """Integration test for Adm1266.get_blackbox_records with optional JSON expectations.""" + print("\n--- Testing get_blackbox_records ---") + + adm = Adm1266Mock() + blackbox_input = adm.get_blackbox_input() + expected_records = adm.get_expected_records() + expected_causes = adm.get_expected_causes() + + + records = adm.get_blackbox_records() + assert len(records) == len(expected_records),\ + f"Count mismatch: {len(records)} != {len(expected_records)}" + + for i, exp in enumerate(expected_records): + a = records[i] + for k, v in exp.items(): + assert k in a, f"[{i}] missing '{k}'" + assert a[k] == v, f"[{i}] {k}: {a[k]} != {v}" + print(" Passed") + + def test_get_reboot_causes(self): + """Test Adm1266.get_reboot_causes by rendering expected numerics with same RENDERers. + + We reuse expected_causes (numeric) and render them using RENDER to compare with + the human-friendly output, avoiding spec duplication. + """ + print("\n--- Testing get_reboot_causes ---") + + adm = Adm1266Mock() + blackbox_input = adm.get_blackbox_input() + expected_records = adm.get_expected_records() + expected_causes = adm.get_expected_causes() + + causes = adm.get_reboot_causes() + exp = expected_causes + assert exp is not None, "expected_causes not provided" + assert len(causes) == len(exp), f"Count mismatch: {len(causes)} != {len(exp)}" + + print(f"expected_causes: {expected_causes}") + print(f"actual_causes: {causes}") + + for i, e in enumerate(exp): + a = causes[i] + for k, v in e.items(): + assert k in a, f"[{i}] missing '{k}' in reboot cause" + assert a[k] == v, f"[{i}] {k}: {a[k]} != {v}" + print(" Passed") diff --git a/platform/broadcom/sonic-platform-modules-nexthop/test/unit/sonic_platform/test_fan.py b/platform/broadcom/sonic-platform-modules-nexthop/test/unit/sonic_platform/test_fan.py new file mode 100644 index 00000000000..5dd352f1d44 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-nexthop/test/unit/sonic_platform/test_fan.py @@ -0,0 +1,189 @@ +#!/usr/bin/env python + +# Copyright 2025 Nexthop Systems Inc. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +""" +Unit tests for the sonic_platform fan module. +These tests run in isolation from the SONiC environment using pytest: +python -m pytest test/unit/sonic_platform/test_fan.py -v +""" + +import importlib.util +import pytest +import os +import sys + +from fixtures.fake_swsscommon import FakeDBConnector, FakeTable, setup_fake_swsscommon +from unittest.mock import Mock, patch, call + + +@pytest.fixture(scope="session", autouse=True) +def setup_fan_unit_tests(): + setup_fake_swsscommon() + yield + + +class MockPddfFan: + """Mock implemnentation of PddfFan for testing.""" + + # mock methods + get_presence = Mock() + set_speed = Mock(return_value=True) + + def __init__( + self, + tray_idx, + fan_idx, + pddf_data, + pddf_plugin_data, + is_psu_fan, + psu_index, + ): + self.tray_idx = tray_idx + 1 + self.fan_index = fan_idx + 1 + self.pddf_data = pddf_data + self.pddf_plugin_data = pddf_plugin_data + self.is_psu_fan = is_psu_fan + if self.is_psu_fan: + self.fans_psu_index = psu_index + + def get_name(self): + return f"Fantray{self.tray_idx}_{self.fan_index}" + + +@pytest.fixture(scope="session") +def mock_pddf_fan(): + """Fixture providing a mock PddfFan instance for testing.""" + return MockPddfFan + + +@pytest.fixture(scope="session") +def fan(mock_pddf_fan): + """ + Fixture providing a Fan instance for testing. + This fixture loads the fan module directly to avoid package import issues. + """ + # Set up the PddfFan mock + pddf_fan_module = Mock() + pddf_fan_module.PddfFan = mock_pddf_fan + sys.modules["sonic_platform_pddf_base.pddf_fan"] = pddf_fan_module + + # Load the fan module directly from file path + test_dir = os.path.dirname(os.path.realpath(__file__)) + fan_path = os.path.join(test_dir, "../../../common/sonic_platform/fan.py") + + spec = importlib.util.spec_from_file_location("fan", fan_path) + fan_module = importlib.util.module_from_spec(spec) + spec.loader.exec_module(fan_module) + + return fan_module.Fan(tray_idx=0, fan_idx=0) + + +class TestFan: + """Test class for Fan functionality.""" + + def test_get_presence(self, fan, mock_pddf_fan): + """Test get_presence.""" + mock_pddf_fan.get_presence.return_value = True + assert fan.get_presence() is True + + mock_pddf_fan.get_presence.return_value = False + assert fan.get_presence() is False + + def test_get_model_for_present_non_psu_fan(self, fan, mock_pddf_fan): + """Test get_model for present non-PSU fan.""" + mock_pddf_fan.get_presence.return_value = True + assert fan.get_model() == "FAN-80G1-F" + + def test_get_model_for_non_present_fan(self, fan, mock_pddf_fan): + """Test get_model for non-present non-PSU fan.""" + mock_pddf_fan.get_presence.return_value = False + assert fan.get_model() == "N/A" + + def test_fan_init_ok_when_db_conn_fails(self, mock_pddf_fan): + """Test Fan initialization is ok when DB connection fails.""" + # Given + with patch.object( + FakeDBConnector, + "__init__", + Mock(side_effect=RuntimeError) + ): + # When + test_fan = fan.__wrapped__(mock_pddf_fan) + # Then + assert test_fan._state_fan_tbl is None + + def test_get_max_speed_default(self, fan): + """Test get_max_speed when it hasn't been set.""" + assert fan.get_max_speed() == fan._DEFAULT_MAX_SPEED + + def test_set_max_speed(self, fan): + """Test set_max_speed writes data to STATE_DB.""" + fan.set_max_speed(60.99) + assert ( + FakeTable._global_db["STATE_DB"]["FAN_INFO"][fan.get_name()]["max_speed"] + == "60.99" + ) + + def test_set_and_get_max_speed(self, fan): + """Test setting and getting max speed.""" + fan.set_max_speed(60.99) + assert fan.get_max_speed() == 60.99 + + def test_set_speed_is_clamped_by_max_speed(self, fan, mock_pddf_fan): + """Test set_speed is clamped by the previously set max_speed.""" + # Given + fan.set_max_speed(60) + + # When + fan.set_speed(61) + fan.set_speed(100) + fan.set_speed(59) + fan.set_speed(30) + + # Then + mock_pddf_fan.set_speed.assert_has_calls( + [ + # Clamped to max speed + call(fan, 60), + call(fan, 60), + # Within max speed + call(fan, 59), + call(fan, 30), + ], + any_order=False, + ) + + def test_set_and_get_max_speed_when_db_conn_fails(self, mock_pddf_fan): + """Test set_max_speed and get_max_speed change nothing when DB connection fails.""" + # Given + with patch.object( + FakeDBConnector, + "__init__", + Mock(side_effect=RuntimeError) + ): + test_fan = fan.__wrapped__(mock_pddf_fan) + # When/Then + assert test_fan.set_max_speed(60.99) == False + assert test_fan.get_max_speed() == test_fan._DEFAULT_MAX_SPEED + + def test_set_and_get_max_speed_when_db_conn_resumes(self, mock_pddf_fan): + """Test set_max_speed and get_max_speed working when DB connection resumes.""" + # Given - Inject a failed DB connection + old_init = FakeDBConnector.__init__ + FakeDBConnector.__init__ = Mock(side_effect=RuntimeError) + test_fan = fan.__wrapped__(mock_pddf_fan) + assert test_fan._state_fan_tbl is None + + # When - Revive the DB connector + FakeDBConnector.__init__ = old_init + + # Then - Perform set/get max speed should work + test_fan.set_max_speed(60.99) + assert test_fan._state_fan_tbl is not None + assert ( + FakeTable._global_db["STATE_DB"]["FAN_INFO"][test_fan.get_name()]["max_speed"] + == "60.99" + ) + assert test_fan.get_max_speed() == 60.99 diff --git a/platform/broadcom/sonic-platform-modules-nexthop/test/unit/sonic_platform/test_thermal.py b/platform/broadcom/sonic-platform-modules-nexthop/test/unit/sonic_platform/test_thermal.py index 0a8c6308755..bca995564c1 100644 --- a/platform/broadcom/sonic-platform-modules-nexthop/test/unit/sonic_platform/test_thermal.py +++ b/platform/broadcom/sonic-platform-modules-nexthop/test/unit/sonic_platform/test_thermal.py @@ -54,7 +54,7 @@ def log(self, priority, msg, also_print_to_console=False): pass # Create mock modules for the local dependencies mock_thermal_infos = Mock() - mock_thermal_infos.FanInfo = type('FanInfo', (), {'INFO_TYPE': 'fan_info'}) + mock_thermal_infos.FanDrawerInfo = type('FanDrawerInfo', (), {'INFO_TYPE': 'fan_drawer_info'}) mock_thermal_infos.ThermalInfo = type('ThermalInfo', (), {'INFO_TYPE': 'thermal_info'}) mock_syslog = Mock() @@ -540,11 +540,11 @@ def mock_fans(self): @pytest.fixture def mock_thermal_info_dict(self, thermal_actions_module, mock_fans): """Fixture providing mock thermal info dictionary.""" - fan_info = Mock() - fan_info.get_fans = Mock(return_value=mock_fans) + fan_drawer_info = Mock() + fan_drawer_info.get_fans = Mock(return_value=mock_fans) return { - thermal_actions_module.FanInfo.INFO_TYPE: fan_info + thermal_actions_module.FanDrawerInfo.INFO_TYPE: fan_drawer_info } def test_fan_set_speed_action_initialization(self, fan_set_speed_action): @@ -575,6 +575,70 @@ def test_fan_set_speed_action_execute(self, fan_set_speed_action, mock_thermal_i fan.set_speed.assert_called_once_with(75) +class TestFanSetMaxSpeedAction: + """Test class for FanSetMaxSpeedAction functionality.""" + + @pytest.fixture + def fan_set_max_speed_action(self, thermal_actions_module): + """Fixture providing a FanSetMaxSpeedAction instance.""" + return thermal_actions_module.FanSetMaxSpeedAction() + + @pytest.fixture + def mock_fans(self): + """Fixture providing mock fan objects.""" + fans = [] + for _ in range(3): + fan = Mock() + fan.set_speed = Mock(return_value=True) + fans.append(fan) + return fans + + @pytest.fixture + def mock_thermal_info_dict(self, thermal_actions_module, mock_fans): + """Fixture providing mock thermal info dictionary.""" + fan_drawer_info = Mock() + fan_drawer_info.get_fans = Mock(return_value=mock_fans) + + return { + thermal_actions_module.FanDrawerInfo.INFO_TYPE: fan_drawer_info + } + + def test_fan_set_max_speed_action_initialization(self, fan_set_max_speed_action): + """Test FanSetMaxSpeedAction initialization.""" + assert fan_set_max_speed_action._max_speed is None + + def test_fan_set_max_speed_action_load_from_json_valid(self, fan_set_max_speed_action): + """Test loading valid JSON configuration.""" + json_config = {'max_speed': 75} + fan_set_max_speed_action.load_from_json(json_config) + assert fan_set_max_speed_action._max_speed == 75 + + def test_fan_set_max_speed_action_load_from_json_invalid(self, fan_set_max_speed_action): + """Test loading invalid JSON configuration.""" + with pytest.raises(KeyError): + fan_set_max_speed_action.load_from_json({}) # Missing max_speed field + + def test_fan_set_max_speed_action_load_from_json_range_validation(self, fan_set_max_speed_action): + """Test max_speed range validation during JSON loading.""" + with pytest.raises(ValueError, match="Max speed 5.0 is out of range"): + fan_set_max_speed_action.load_from_json({'max_speed': 5}) + + with pytest.raises(ValueError, match="Max speed 105.0 is out of range"): + fan_set_max_speed_action.load_from_json({'max_speed': 105}) + + def test_fan_set_max_speed_action_execute(self, fan_set_max_speed_action, mock_thermal_info_dict, mock_fans): + """Test FanSetMaxSpeedAction execution.""" + # Configure action + fan_set_max_speed_action.load_from_json({'max_speed': 75}) + + # Execute action + fan_set_max_speed_action.execute(mock_thermal_info_dict) + + # Verify all fans were set to correct max speed + for fan in mock_fans: + fan.set_max_speed.assert_called_once_with(75) + + class TestThermalControlAlgorithmAction: """Test class for ThermalControlAlgorithmAction functionality.""" @@ -595,8 +659,7 @@ def valid_json_config(self): 'extra_setpoint_margin': {'cpu': 2.0} }, 'fan_limits': { - 'min': 30, - 'max': 100 + 'min': 30 } } @@ -628,7 +691,7 @@ def test_thermal_control_action_pid_controller_creation(self, thermal_control_ac thermal_control_action.load_from_json(valid_json_config) # Initialize PID controllers - thermal_control_action._initialize_pid_controllers(5) + thermal_control_action._initialize_pid_controllers(interval=5, fan_max_speed=100) # Verify controller was created for the domain assert 'cpu' in thermal_control_action._pidControllers @@ -648,7 +711,7 @@ def test_thermal_control_action_interval_mismatch(self, thermal_control_action, # Try to initialize with different interval with pytest.raises(ValueError, match="Interval 10 does not match interval 5"): - thermal_control_action._initialize_pid_controllers(10) + thermal_control_action._initialize_pid_controllers(interval=10, fan_max_speed=100) def test_thermal_control_action_convert_pid_output_to_speed(self, thermal_control_action, valid_json_config): """Test PID output to fan speed conversion with precise validation.""" @@ -664,7 +727,7 @@ def test_thermal_control_action_convert_pid_output_to_speed(self, thermal_contro ] for pid_output, expected_speed in test_cases: - speed = thermal_control_action._convert_pid_output_to_speed(pid_output) + speed = thermal_control_action._convert_pid_output_to_speed(pid_output, max_speed=100) assert speed == expected_speed, f"PID output {pid_output} should convert to {expected_speed}, got {speed}" def test_thermal_control_action_multiple_domains(self, thermal_actions_module): @@ -682,13 +745,12 @@ def test_thermal_control_action_multiple_domains(self, thermal_actions_module): 'extra_setpoint_margin': {'cpu': 2.0, 'switch': 3.0, 'ambient': 1.0} }, 'fan_limits': { - 'min': 35, - 'max': 95 + 'min': 35 } } action.load_from_json(multi_domain_config) - action._initialize_pid_controllers(5) + action._initialize_pid_controllers(interval=5, fan_max_speed=95) # Verify all controllers were created assert len(action._pidControllers) == 3 @@ -712,28 +774,18 @@ def test_thermal_control_action_fan_limits_validation(self, thermal_control_acti invalid_config = { 'pid_domains': {'cpu': {'KP': 1.0, 'KI': 0.5, 'KD': 0.1}}, 'constants': {'interval': 5, 'extra_setpoint_margin': {'cpu': 2.0}}, - 'fan_limits': {'min': 5, 'max': 150} # Out of valid range + 'fan_limits': {'min': 5} # Out of valid range } - with pytest.raises(ValueError, match="Fan limits 5-150 are out of range"): + with pytest.raises(ValueError, match="Min fan limit 5 is out of range"): thermal_control_action.load_from_json(invalid_config) - # Test invalid fan limits (min > max) - invalid_config2 = { - 'pid_domains': {'cpu': {'KP': 1.0, 'KI': 0.5, 'KD': 0.1}}, - 'constants': {'interval': 5, 'extra_setpoint_margin': {'cpu': 2.0}}, - 'fan_limits': {'min': 80, 'max': 60} # min > max - } - - with pytest.raises(ValueError, match="Min fan limit 80 is greater than max fan limit 60"): - thermal_control_action.load_from_json(invalid_config2) - def test_thermal_control_action_missing_interval(self, thermal_control_action): """Test that missing interval raises ValueError.""" invalid_config = { 'pid_domains': {'cpu': {'KP': 1.0, 'KI': 0.5, 'KD': 0.1}}, 'constants': {'extra_setpoint_margin': {'cpu': 2.0}}, # Missing interval - 'fan_limits': {'min': 30, 'max': 100} + 'fan_limits': {'min': 30} } with pytest.raises(ValueError, match="Interval must be defined"): From 42cb8adf57b4450d33873b79204d2ae2db8657e5 Mon Sep 17 00:00:00 2001 From: Roy Wen Date: Tue, 7 Oct 2025 16:11:16 -0400 Subject: [PATCH 03/13] more nh-5010 device dir changes --- .../NH-5010-F-O32-C32/gearbox_config.json | 16 +++ .../NH-5010-F-O64/gearbox_config.json | 16 +++ .../x86_64-nexthop_5010-r0/installer.conf | 2 +- .../nexthop/x86_64-nexthop_5010-r0/pcie.yaml | 2 +- .../pddf/pddf-device.json | 4 +- .../pddf/pddf-device.json.j2 | 120 +++++++++--------- .../x86_64-nexthop_5010-r0/platform_env.conf | 2 - .../plugins/led_control.py | 10 +- .../pmon_daemon_control.json | 6 +- .../x86_64-nexthop_5010-r0/sensors.conf | 89 +++++++++++++ .../system_health_monitoring_config.json | 15 +-- 11 files changed, 187 insertions(+), 95 deletions(-) mode change 100644 => 120000 device/nexthop/x86_64-nexthop_5010-r0/installer.conf mode change 100644 => 120000 device/nexthop/x86_64-nexthop_5010-r0/pcie.yaml mode change 100644 => 120000 device/nexthop/x86_64-nexthop_5010-r0/pddf/pddf-device.json mode change 100644 => 120000 device/nexthop/x86_64-nexthop_5010-r0/plugins/led_control.py mode change 100644 => 120000 device/nexthop/x86_64-nexthop_5010-r0/pmon_daemon_control.json create mode 100644 device/nexthop/x86_64-nexthop_5010-r0/sensors.conf mode change 100644 => 120000 device/nexthop/x86_64-nexthop_5010-r0/system_health_monitoring_config.json diff --git a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/gearbox_config.json b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/gearbox_config.json index 9003187a182..3b7e7808fde 100644 --- a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/gearbox_config.json +++ b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/gearbox_config.json @@ -11,6 +11,7 @@ "phy_access": "mdio", "bus_id": 0, "context_id": 1, + "macsec_supported": false, "hwinfo": "0" }, { @@ -24,6 +25,7 @@ "phy_access": "mdio", "bus_id": 0, "context_id": 1, + "macsec_supported": false, "hwinfo": "1" }, { @@ -37,6 +39,7 @@ "phy_access": "mdio", "bus_id": 0, "context_id": 1, + "macsec_supported": false, "hwinfo": "2" }, { @@ -50,6 +53,7 @@ "phy_access": "mdio", "bus_id": 0, "context_id": 1, + "macsec_supported": false, "hwinfo": "3" }, { @@ -63,6 +67,7 @@ "phy_access": "mdio", "bus_id": 0, "context_id": 1, + "macsec_supported": false, "hwinfo": "4" }, { @@ -76,6 +81,7 @@ "phy_access": "mdio", "bus_id": 0, "context_id": 1, + "macsec_supported": false, "hwinfo": "5" }, { @@ -89,6 +95,7 @@ "phy_access": "mdio", "bus_id": 0, "context_id": 1, + "macsec_supported": false, "hwinfo": "6" }, { @@ -102,6 +109,7 @@ "phy_access": "mdio", "bus_id": 0, "context_id": 1, + "macsec_supported": false, "hwinfo": "7" }, { @@ -115,6 +123,7 @@ "phy_access": "mdio", "bus_id": 0, "context_id": 1, + "macsec_supported": false, "hwinfo": "8" }, { @@ -128,6 +137,7 @@ "phy_access": "mdio", "bus_id": 0, "context_id": 1, + "macsec_supported": false, "hwinfo": "9" }, { @@ -141,6 +151,7 @@ "phy_access": "mdio", "bus_id": 0, "context_id": 1, + "macsec_supported": false, "hwinfo": "10" }, { @@ -154,6 +165,7 @@ "phy_access": "mdio", "bus_id": 0, "context_id": 1, + "macsec_supported": false, "hwinfo": "11" }, { @@ -167,6 +179,7 @@ "phy_access": "mdio", "bus_id": 0, "context_id": 1, + "macsec_supported": false, "hwinfo": "12" }, { @@ -180,6 +193,7 @@ "phy_access": "mdio", "bus_id": 0, "context_id": 1, + "macsec_supported": false, "hwinfo": "13" }, { @@ -193,6 +207,7 @@ "phy_access": "mdio", "bus_id": 0, "context_id": 1, + "macsec_supported": false, "hwinfo": "14" }, { @@ -206,6 +221,7 @@ "phy_access": "mdio", "bus_id": 0, "context_id": 1, + "macsec_supported": false, "hwinfo": "15" } ], diff --git a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/gearbox_config.json b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/gearbox_config.json index a60e21c62ba..5f96924fe1a 100644 --- a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/gearbox_config.json +++ b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/gearbox_config.json @@ -11,6 +11,7 @@ "phy_access": "mdio", "bus_id": 0, "context_id": 1, + "macsec_supported": false, "hwinfo": "0" }, { @@ -24,6 +25,7 @@ "phy_access": "mdio", "bus_id": 0, "context_id": 1, + "macsec_supported": false, "hwinfo": "1" }, { @@ -37,6 +39,7 @@ "phy_access": "mdio", "bus_id": 0, "context_id": 1, + "macsec_supported": false, "hwinfo": "2" }, { @@ -50,6 +53,7 @@ "phy_access": "mdio", "bus_id": 0, "context_id": 1, + "macsec_supported": false, "hwinfo": "3" }, { @@ -63,6 +67,7 @@ "phy_access": "mdio", "bus_id": 0, "context_id": 1, + "macsec_supported": false, "hwinfo": "4" }, { @@ -76,6 +81,7 @@ "phy_access": "mdio", "bus_id": 0, "context_id": 1, + "macsec_supported": false, "hwinfo": "5" }, { @@ -89,6 +95,7 @@ "phy_access": "mdio", "bus_id": 0, "context_id": 1, + "macsec_supported": false, "hwinfo": "6" }, { @@ -102,6 +109,7 @@ "phy_access": "mdio", "bus_id": 0, "context_id": 1, + "macsec_supported": false, "hwinfo": "7" }, { @@ -115,6 +123,7 @@ "phy_access": "mdio", "bus_id": 0, "context_id": 1, + "macsec_supported": false, "hwinfo": "8" }, { @@ -128,6 +137,7 @@ "phy_access": "mdio", "bus_id": 0, "context_id": 1, + "macsec_supported": false, "hwinfo": "9" }, { @@ -141,6 +151,7 @@ "phy_access": "mdio", "bus_id": 0, "context_id": 1, + "macsec_supported": false, "hwinfo": "10" }, { @@ -154,6 +165,7 @@ "phy_access": "mdio", "bus_id": 0, "context_id": 1, + "macsec_supported": false, "hwinfo": "11" }, { @@ -167,6 +179,7 @@ "phy_access": "mdio", "bus_id": 0, "context_id": 1, + "macsec_supported": false, "hwinfo": "12" }, { @@ -180,6 +193,7 @@ "phy_access": "mdio", "bus_id": 0, "context_id": 1, + "macsec_supported": false, "hwinfo": "13" }, { @@ -193,6 +207,7 @@ "phy_access": "mdio", "bus_id": 0, "context_id": 1, + "macsec_supported": false, "hwinfo": "14" }, { @@ -206,6 +221,7 @@ "phy_access": "mdio", "bus_id": 0, "context_id": 1, + "macsec_supported": false, "hwinfo": "15" } ], diff --git a/device/nexthop/x86_64-nexthop_5010-r0/installer.conf b/device/nexthop/x86_64-nexthop_5010-r0/installer.conf deleted file mode 100644 index e172a88fc88..00000000000 --- a/device/nexthop/x86_64-nexthop_5010-r0/installer.conf +++ /dev/null @@ -1 +0,0 @@ -ONIE_PLATFORM_EXTRA_CMDLINE_LINUX="crashkernel=512M" diff --git a/device/nexthop/x86_64-nexthop_5010-r0/installer.conf b/device/nexthop/x86_64-nexthop_5010-r0/installer.conf new file mode 120000 index 00000000000..97b3314541b --- /dev/null +++ b/device/nexthop/x86_64-nexthop_5010-r0/installer.conf @@ -0,0 +1 @@ +../x86_64-nexthop_4010-r0/installer.conf \ No newline at end of file diff --git a/device/nexthop/x86_64-nexthop_5010-r0/pcie.yaml b/device/nexthop/x86_64-nexthop_5010-r0/pcie.yaml deleted file mode 100644 index 7a125466e0f..00000000000 --- a/device/nexthop/x86_64-nexthop_5010-r0/pcie.yaml +++ /dev/null @@ -1 +0,0 @@ -- description: "Generated at runtime by pcie.yaml.j2" diff --git a/device/nexthop/x86_64-nexthop_5010-r0/pcie.yaml b/device/nexthop/x86_64-nexthop_5010-r0/pcie.yaml new file mode 120000 index 00000000000..ce9ec4e0d92 --- /dev/null +++ b/device/nexthop/x86_64-nexthop_5010-r0/pcie.yaml @@ -0,0 +1 @@ +../x86_64-nexthop_4010-r0/pcie.yaml \ No newline at end of file diff --git a/device/nexthop/x86_64-nexthop_5010-r0/pddf/pddf-device.json b/device/nexthop/x86_64-nexthop_5010-r0/pddf/pddf-device.json deleted file mode 100644 index f12f708c904..00000000000 --- a/device/nexthop/x86_64-nexthop_5010-r0/pddf/pddf-device.json +++ /dev/null @@ -1,3 +0,0 @@ -{ - "description": "Generated at runtime by pddf-device.json.j2" -} diff --git a/device/nexthop/x86_64-nexthop_5010-r0/pddf/pddf-device.json b/device/nexthop/x86_64-nexthop_5010-r0/pddf/pddf-device.json new file mode 120000 index 00000000000..b941e90e610 --- /dev/null +++ b/device/nexthop/x86_64-nexthop_5010-r0/pddf/pddf-device.json @@ -0,0 +1 @@ +../../x86_64-nexthop_4010-r0/pddf/pddf-device.json \ No newline at end of file diff --git a/device/nexthop/x86_64-nexthop_5010-r0/pddf/pddf-device.json.j2 b/device/nexthop/x86_64-nexthop_5010-r0/pddf/pddf-device.json.j2 index 17265b6a6e5..e9a772366fe 100644 --- a/device/nexthop/x86_64-nexthop_5010-r0/pddf/pddf-device.json.j2 +++ b/device/nexthop/x86_64-nexthop_5010-r0/pddf/pddf-device.json.j2 @@ -569,15 +569,15 @@ "attr_list": [ { "attr_name": "temp1_input", - "drv_attr_name": "temp1_input" + "drv_attr_name": "temp2_input" }, { "attr_name": "temp1_high_threshold", - "drv_attr_name": "temp1_max" + "drv_attr_name": "temp2_max" }, { "attr_name": "temp1_high_crit_threshold", - "drv_attr_name": "temp1_crit" + "drv_attr_name": "temp2_crit" } ] } @@ -596,15 +596,15 @@ "attr_list": [ { "attr_name": "temp1_input", - "drv_attr_name": "temp2_input" + "drv_attr_name": "temp3_input" }, { "attr_name": "temp1_high_threshold", - "drv_attr_name": "temp2_max" + "drv_attr_name": "temp3_max" }, { "attr_name": "temp1_high_crit_threshold", - "drv_attr_name": "temp2_crit" + "drv_attr_name": "temp3_crit" } ] } @@ -623,15 +623,15 @@ "attr_list": [ { "attr_name": "temp1_input", - "drv_attr_name": "temp3_input" + "drv_attr_name": "temp4_input" }, { "attr_name": "temp1_high_threshold", - "drv_attr_name": "temp3_max" + "drv_attr_name": "temp4_max" }, { "attr_name": "temp1_high_crit_threshold", - "drv_attr_name": "temp3_crit" + "drv_attr_name": "temp4_crit" } ] } @@ -650,15 +650,15 @@ "attr_list": [ { "attr_name": "temp1_input", - "drv_attr_name": "temp4_input" + "drv_attr_name": "temp5_input" }, { "attr_name": "temp1_high_threshold", - "drv_attr_name": "temp4_max" + "drv_attr_name": "temp5_max" }, { "attr_name": "temp1_high_crit_threshold", - "drv_attr_name": "temp4_crit" + "drv_attr_name": "temp5_crit" } ] } @@ -677,15 +677,15 @@ "attr_list": [ { "attr_name": "temp1_input", - "drv_attr_name": "temp5_input" + "drv_attr_name": "temp6_input" }, { "attr_name": "temp1_high_threshold", - "drv_attr_name": "temp5_max" + "drv_attr_name": "temp6_max" }, { "attr_name": "temp1_high_crit_threshold", - "drv_attr_name": "temp5_crit" + "drv_attr_name": "temp6_crit" } ] } @@ -704,15 +704,15 @@ "attr_list": [ { "attr_name": "temp1_input", - "drv_attr_name": "temp6_input" + "drv_attr_name": "temp7_input" }, { "attr_name": "temp1_high_threshold", - "drv_attr_name": "temp6_max" + "drv_attr_name": "temp7_max" }, { "attr_name": "temp1_high_crit_threshold", - "drv_attr_name": "temp6_crit" + "drv_attr_name": "temp7_crit" } ] } @@ -731,15 +731,15 @@ "attr_list": [ { "attr_name": "temp1_input", - "drv_attr_name": "temp7_input" + "drv_attr_name": "temp8_input" }, { "attr_name": "temp1_high_threshold", - "drv_attr_name": "temp7_max" + "drv_attr_name": "temp8_max" }, { "attr_name": "temp1_high_crit_threshold", - "drv_attr_name": "temp7_crit" + "drv_attr_name": "temp8_crit" } ] } @@ -758,15 +758,15 @@ "attr_list": [ { "attr_name": "temp1_input", - "drv_attr_name": "temp8_input" + "drv_attr_name": "temp9_input" }, { "attr_name": "temp1_high_threshold", - "drv_attr_name": "temp8_max" + "drv_attr_name": "temp9_max" }, { "attr_name": "temp1_high_crit_threshold", - "drv_attr_name": "temp8_crit" + "drv_attr_name": "temp9_crit" } ] } @@ -785,15 +785,15 @@ "attr_list": [ { "attr_name": "temp1_input", - "drv_attr_name": "temp1_input" + "drv_attr_name": "temp2_input" }, { "attr_name": "temp1_high_threshold", - "drv_attr_name": "temp1_max" + "drv_attr_name": "temp2_max" }, { "attr_name": "temp1_high_crit_threshold", - "drv_attr_name": "temp1_crit" + "drv_attr_name": "temp2_crit" } ] } @@ -812,15 +812,15 @@ "attr_list": [ { "attr_name": "temp1_input", - "drv_attr_name": "temp2_input" + "drv_attr_name": "temp3_input" }, { "attr_name": "temp1_high_threshold", - "drv_attr_name": "temp2_max" + "drv_attr_name": "temp3_max" }, { "attr_name": "temp1_high_crit_threshold", - "drv_attr_name": "temp2_crit" + "drv_attr_name": "temp3_crit" } ] } @@ -839,15 +839,15 @@ "attr_list": [ { "attr_name": "temp1_input", - "drv_attr_name": "temp3_input" + "drv_attr_name": "temp4_input" }, { "attr_name": "temp1_high_threshold", - "drv_attr_name": "temp3_max" + "drv_attr_name": "temp4_max" }, { "attr_name": "temp1_high_crit_threshold", - "drv_attr_name": "temp3_crit" + "drv_attr_name": "temp4_crit" } ] } @@ -866,15 +866,15 @@ "attr_list": [ { "attr_name": "temp1_input", - "drv_attr_name": "temp4_input" + "drv_attr_name": "temp5_input" }, { "attr_name": "temp1_high_threshold", - "drv_attr_name": "temp4_max" + "drv_attr_name": "temp5_max" }, { "attr_name": "temp1_high_crit_threshold", - "drv_attr_name": "temp4_crit" + "drv_attr_name": "temp5_crit" } ] } @@ -893,15 +893,15 @@ "attr_list": [ { "attr_name": "temp1_input", - "drv_attr_name": "temp5_input" + "drv_attr_name": "temp6_input" }, { "attr_name": "temp1_high_threshold", - "drv_attr_name": "temp5_max" + "drv_attr_name": "temp6_max" }, { "attr_name": "temp1_high_crit_threshold", - "drv_attr_name": "temp5_crit" + "drv_attr_name": "temp6_crit" } ] } @@ -920,15 +920,15 @@ "attr_list": [ { "attr_name": "temp1_input", - "drv_attr_name": "temp6_input" + "drv_attr_name": "temp7_input" }, { "attr_name": "temp1_high_threshold", - "drv_attr_name": "temp6_max" + "drv_attr_name": "temp7_max" }, { "attr_name": "temp1_high_crit_threshold", - "drv_attr_name": "temp6_crit" + "drv_attr_name": "temp7_crit" } ] } @@ -947,15 +947,15 @@ "attr_list": [ { "attr_name": "temp1_input", - "drv_attr_name": "temp7_input" + "drv_attr_name": "temp8_input" }, { "attr_name": "temp1_high_threshold", - "drv_attr_name": "temp7_max" + "drv_attr_name": "temp8_max" }, { "attr_name": "temp1_high_crit_threshold", - "drv_attr_name": "temp7_crit" + "drv_attr_name": "temp8_crit" } ] } @@ -974,15 +974,15 @@ "attr_list": [ { "attr_name": "temp1_input", - "drv_attr_name": "temp8_input" + "drv_attr_name": "temp9_input" }, { "attr_name": "temp1_high_threshold", - "drv_attr_name": "temp8_max" + "drv_attr_name": "temp9_max" }, { "attr_name": "temp1_high_crit_threshold", - "drv_attr_name": "temp8_crit" + "drv_attr_name": "temp9_crit" } ] } @@ -15626,15 +15626,15 @@ "attr_list": [ { "attr_name": "temp1_input", - "drv_attr_name": "temp1_input" + "drv_attr_name": "temp2_input" }, { "attr_name": "temp1_high_threshold", - "drv_attr_name": "temp1_max" + "drv_attr_name": "temp2_max" }, { "attr_name": "temp1_high_crit_threshold", - "drv_attr_name": "temp1_crit" + "drv_attr_name": "temp2_crit" } ] } @@ -15653,15 +15653,15 @@ "attr_list": [ { "attr_name": "temp1_input", - "drv_attr_name": "temp2_input" + "drv_attr_name": "temp3_input" }, { "attr_name": "temp1_high_threshold", - "drv_attr_name": "temp2_max" + "drv_attr_name": "temp3_max" }, { "attr_name": "temp1_high_crit_threshold", - "drv_attr_name": "temp2_crit" + "drv_attr_name": "temp3_crit" } ] } @@ -15680,15 +15680,15 @@ "attr_list": [ { "attr_name": "temp1_input", - "drv_attr_name": "temp3_input" + "drv_attr_name": "temp4_input" }, { "attr_name": "temp1_high_threshold", - "drv_attr_name": "temp3_max" + "drv_attr_name": "temp4_max" }, { "attr_name": "temp1_high_crit_threshold", - "drv_attr_name": "temp3_crit" + "drv_attr_name": "temp4_crit" } ] } @@ -15707,15 +15707,15 @@ "attr_list": [ { "attr_name": "temp1_input", - "drv_attr_name": "temp4_input" + "drv_attr_name": "temp5_input" }, { "attr_name": "temp1_high_threshold", - "drv_attr_name": "temp4_max" + "drv_attr_name": "temp5_max" }, { "attr_name": "temp1_high_crit_threshold", - "drv_attr_name": "temp4_crit" + "drv_attr_name": "temp5_crit" } ] } diff --git a/device/nexthop/x86_64-nexthop_5010-r0/platform_env.conf b/device/nexthop/x86_64-nexthop_5010-r0/platform_env.conf index 33580a92681..b3085890288 100644 --- a/device/nexthop/x86_64-nexthop_5010-r0/platform_env.conf +++ b/device/nexthop/x86_64-nexthop_5010-r0/platform_env.conf @@ -1,4 +1,2 @@ SYNCD_SHM_SIZE=1g macsec_enabled=1 -THERMALCTLD_THERMAL_MONITOR_UPDATE_INTERVAL=10 -THERMALCTLD_THERMAL_MONITOR_UPDATE_ELAPSED_THRESHOLD=9 diff --git a/device/nexthop/x86_64-nexthop_5010-r0/plugins/led_control.py b/device/nexthop/x86_64-nexthop_5010-r0/plugins/led_control.py deleted file mode 100644 index 43494e4628b..00000000000 --- a/device/nexthop/x86_64-nexthop_5010-r0/plugins/led_control.py +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright 2025 Nexthop Systems Inc. All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -# Nexthop Port LED Policy - -try: - from nexthop.led_control import LedControl -except ImportError as e: - raise ImportError("%s - required module not found" % e) diff --git a/device/nexthop/x86_64-nexthop_5010-r0/plugins/led_control.py b/device/nexthop/x86_64-nexthop_5010-r0/plugins/led_control.py new file mode 120000 index 00000000000..4c221b4b181 --- /dev/null +++ b/device/nexthop/x86_64-nexthop_5010-r0/plugins/led_control.py @@ -0,0 +1 @@ +../../common/plugins/led_control.py \ No newline at end of file diff --git a/device/nexthop/x86_64-nexthop_5010-r0/pmon_daemon_control.json b/device/nexthop/x86_64-nexthop_5010-r0/pmon_daemon_control.json deleted file mode 100644 index 26c79c86c86..00000000000 --- a/device/nexthop/x86_64-nexthop_5010-r0/pmon_daemon_control.json +++ /dev/null @@ -1,5 +0,0 @@ -{ - "include_sensormond": true, - "skip_ledd": true, - "enable_xcvrd_sff_mgr": true -} diff --git a/device/nexthop/x86_64-nexthop_5010-r0/pmon_daemon_control.json b/device/nexthop/x86_64-nexthop_5010-r0/pmon_daemon_control.json new file mode 120000 index 00000000000..55ab421a92a --- /dev/null +++ b/device/nexthop/x86_64-nexthop_5010-r0/pmon_daemon_control.json @@ -0,0 +1 @@ +../common/pmon_daemon_control.json \ No newline at end of file diff --git a/device/nexthop/x86_64-nexthop_5010-r0/sensors.conf b/device/nexthop/x86_64-nexthop_5010-r0/sensors.conf new file mode 100644 index 00000000000..3fd9790c080 --- /dev/null +++ b/device/nexthop/x86_64-nexthop_5010-r0/sensors.conf @@ -0,0 +1,89 @@ +# libsensors configuration file +# ---------------------------------------------- +# +bus "i2c-10" "i2c-pci-10" + +chip "nh_tmp468-i2c-10-48" + ignore temp1 + + label temp2 "Switch Card Left Lower Rear" + label temp3 "Left Port Side Intake" + label temp4 "ASIC Diode0 PADS tsen" + label temp5 "ASIC Diode0 NIF0 tsen" + label temp6 "ASIC Diode0 CORE tsen" + label temp7 "ASIC Diode0 NIF1 tsen" + label temp8 "ASIC Diode0 HBM_PHY1 tsen" + label temp9 "ASIC Diode0 HBM_PHY2 tsen" + + set temp2_max 55 + set temp2_crit 56 + set temp3_max 45 + set temp3_crit 65 + set temp4_max 100 + set temp4_crit 105 + set temp5_max 100 + set temp5_crit 105 + set temp6_max 110 + set temp6_crit 115 + set temp7_max 95 + set temp7_crit 100 + set temp8_max 115 + set temp8_crit 120 + set temp9_max 115 + set temp9_crit 120 + +chip "nh_tmp468-i2c-10-49" + ignore temp1 + + label temp2 "Switch Card Right Lower Rear" + label temp3 "Right Port Side Intake" + label temp4 "ASIC Diode1 PADS tsen" + label temp5 "ASIC Diode1 NIF0 tsen" + label temp6 "ASIC Diode1 CORE tsen" + label temp7 "ASIC Diode1 NIF1 tsen" + label temp8 "ASIC Diode1 HBM_PHY1 tsen" + label temp9 "ASIC Diode1 HBM_PHY2 tsen" + + set temp2_max 55 + set temp2_crit 56 + set temp3_max 45 + set temp3_crit 65 + set temp4_max 100 + set temp4_crit 105 + set temp5_max 100 + set temp5_crit 105 + set temp6_max 110 + set temp6_crit 115 + set temp7_max 95 + set temp7_crit 100 + set temp8_max 115 + set temp8_crit 120 + set temp9_max 115 + set temp9_crit 120 + +chip "nh_tmp464-i2c-10-4a" + label temp2 "Mezz Card Left Rear" + label temp3 "Left Upper Port Side Intake" + label temp4 "Mezz Card Right Rear" + label temp5 "Right Upper Port Side Intake" + + set temp2_max 55 + set temp2_crit 56 + set temp3_max 45 + set temp3_crit 65 + set temp4_max 55 + set temp4_crit 56 + set temp5_max 45 + set temp5_crit 65 + + ignore temp6 + ignore temp7 + ignore temp8 + ignore temp9 + +# The NVME drive doesn't populate min and max temps for these sensors, ignore +# them to not get I/O errors. +chip "nvme-pci-*" + ignore temp2 + ignore temp3 + ignore temp4 diff --git a/device/nexthop/x86_64-nexthop_5010-r0/system_health_monitoring_config.json b/device/nexthop/x86_64-nexthop_5010-r0/system_health_monitoring_config.json deleted file mode 100644 index 286eef80500..00000000000 --- a/device/nexthop/x86_64-nexthop_5010-r0/system_health_monitoring_config.json +++ /dev/null @@ -1,14 +0,0 @@ -{ - "services_to_ignore": [], - "devices_to_ignore": [ - "PSU1_FAN1.speed", - "PSU2_FAN1.speed" - ], - "user_defined_checkers": [], - "polling_interval": 60, - "led_color": { - "fault": "red", - "normal": "green", - "booting": "green_blink" - } -} diff --git a/device/nexthop/x86_64-nexthop_5010-r0/system_health_monitoring_config.json b/device/nexthop/x86_64-nexthop_5010-r0/system_health_monitoring_config.json new file mode 120000 index 00000000000..d00c29791bb --- /dev/null +++ b/device/nexthop/x86_64-nexthop_5010-r0/system_health_monitoring_config.json @@ -0,0 +1 @@ +../common/system_health_monitoring_config.json \ No newline at end of file From a82f4b9b247a944471d49374b636626bb8d42c3f Mon Sep 17 00:00:00 2001 From: Roy Wen Date: Tue, 7 Oct 2025 16:33:28 -0400 Subject: [PATCH 04/13] remove eeprom utils change --- .../common/nexthop/eeprom_utils.py | 16 ------- .../common/nexthop/platform_utils.py | 47 ------------------- 2 files changed, 63 deletions(-) delete mode 100644 platform/broadcom/sonic-platform-modules-nexthop/common/nexthop/platform_utils.py diff --git a/platform/broadcom/sonic-platform-modules-nexthop/common/nexthop/eeprom_utils.py b/platform/broadcom/sonic-platform-modules-nexthop/common/nexthop/eeprom_utils.py index a982455699c..68523385dbf 100644 --- a/platform/broadcom/sonic-platform-modules-nexthop/common/nexthop/eeprom_utils.py +++ b/platform/broadcom/sonic-platform-modules-nexthop/common/nexthop/eeprom_utils.py @@ -5,13 +5,9 @@ import click import sys import struct -import subprocess -import errno from dataclasses import dataclass from enum import Enum -from nexthop.platform_utils import run_cmd, run_and_report - try: from sonic_eeprom import eeprom_tlvinfo @@ -400,17 +396,6 @@ def decode_eeprom(eeprom_path: str): eeprom_class.decode_eeprom(eeprom) -def clear_syseeprom_cache(): - """ syseeprom cache cleanup and service restart""" - cache_path = "/var/cache/sonic/decode-syseeprom/syseeprom_cache" - - if os.path.exists(cache_path): - run_and_report("Remove syseeprom cache", f"rm {cache_path}") - - run_and_report("Remove syseeprom cache from pmon", f'docker exec pmon bash -c "rm -f {cache_path}"') - run_and_report("Restart syseepromd", 'docker exec pmon bash -c "supervisorctl restart syseepromd"') - - def check_root_privileges(): if os.getuid() != 0: click.secho("Root privileges required for this operation", fg="red") @@ -559,7 +544,6 @@ def program( custom_serial_number, regulatory_model_number, ) - clear_syseeprom_cache() @cli.command("clear") diff --git a/platform/broadcom/sonic-platform-modules-nexthop/common/nexthop/platform_utils.py b/platform/broadcom/sonic-platform-modules-nexthop/common/nexthop/platform_utils.py deleted file mode 100644 index 28564a101c5..00000000000 --- a/platform/broadcom/sonic-platform-modules-nexthop/common/nexthop/platform_utils.py +++ /dev/null @@ -1,47 +0,0 @@ -import subprocess -import click -import os -import sys - - -def run_cmd(cmd, check_exit=True): - """ - Run a command and return the output - Args: - cmd (str): The command to run - check_exit (bool): Whether to check the exit code and raise an exception if it's non-zero - Returns: - str: The output of the command (stdout) - Raises: - subprocess.CalledProcessError: If check_exit is True and command fails - subprocess.SubprocessError: If there's an error running the command - OSError: If there's an OS-level error - """ - try: - result = subprocess.run( - cmd, shell=True, capture_output=True, text=True, check=check_exit - ) - return result.stdout.strip() - except subprocess.CalledProcessError as e: - # Re-raise with more context - raise subprocess.CalledProcessError( - e.returncode, cmd, output=e.stdout, stderr=e.stderr - ) - except (subprocess.SubprocessError, OSError): - raise - - -def run_and_report(description, command): - """ - Run a command and report the result with colored output. - - Args: - description (str): Description of the operation being performed - command (str): The command to execute - """ - click.secho(f"{description}:", fg="cyan") - try: - run_cmd(command) - click.secho(f"Successfully {description.lower()}", fg="green") - except (subprocess.CalledProcessError, subprocess.SubprocessError, OSError): - click.secho(f"Failed to {description.lower()}", fg="red") \ No newline at end of file From 518596cfd969f6b20dfccf49370829216a7e140b Mon Sep 17 00:00:00 2001 From: Roy Wen Date: Wed, 15 Oct 2025 13:00:49 -0400 Subject: [PATCH 05/13] additional nh platform support changes --- .../NH-5010-F-O32-C32/port_config.ini | 136 ++-- .../NH-5010-F-O64/gearbox_config.json | 512 +++++++++++++- .../NH-5010-F-O64/nh5010-default.bcm | 512 +++++++------- .../NH-5010-F-O64/port_config.ini | 136 ++-- .../x86_64-nexthop_5010-r0/installer.conf | 2 +- .../pddf/pd-plugin.json | 287 +++++++- .../pddf/pddf-device.json.j2 | 90 +-- .../x86_64-nexthop_5010-r0/sensors.conf | 91 +-- .../service/asic-temp-sensor-enable.service | 13 - .../common/sonic_platform/adm1266.py | 635 +++++++++++++----- .../sonic_platform/adm1266_platform_spec.py | 99 +++ .../common/sonic_platform/chassis.py | 72 +- .../common/sonic_platform/dpm.py | 264 ++++++++ .../common/sonic_platform/dpm_info.py | 47 -- .../common/sonic_platform/thermal.py | 145 +++- .../common/utils/asic-temp-sensor-enable.py | 27 - .../common/utils/nh_reboot_cause | 97 +++ .../debian/rules | 1 + .../sonic-platform-nexthop-4010-r0.install | 2 - .../sonic-platform-nexthop-4010-r1.install | 2 - .../sonic-platform-nexthop-4020-r0.install | 2 - .../nh-4010/utils/system_powercycle | 65 -- .../nh-4010/utils/transceiver_init.sh | 74 -- .../sign-modules.sh | 99 +++ .../test/fixtures/fixtures_unit_test.py | 281 +++++--- .../test/unit/nexthop/test_nh_reboot_cause.py | 218 ++++++ .../test/unit/sonic_platform/test_adm1266.py | 211 +++++- .../test/unit/sonic_platform/test_chassis.py | 104 +++ .../test/unit/sonic_platform/test_thermal.py | 211 +++++- 29 files changed, 3340 insertions(+), 1095 deletions(-) mode change 120000 => 100644 device/nexthop/x86_64-nexthop_5010-r0/installer.conf delete mode 100644 platform/broadcom/sonic-platform-modules-nexthop/common/service/asic-temp-sensor-enable.service create mode 100644 platform/broadcom/sonic-platform-modules-nexthop/common/sonic_platform/adm1266_platform_spec.py create mode 100644 platform/broadcom/sonic-platform-modules-nexthop/common/sonic_platform/dpm.py delete mode 100644 platform/broadcom/sonic-platform-modules-nexthop/common/sonic_platform/dpm_info.py delete mode 100755 platform/broadcom/sonic-platform-modules-nexthop/common/utils/asic-temp-sensor-enable.py create mode 100755 platform/broadcom/sonic-platform-modules-nexthop/common/utils/nh_reboot_cause delete mode 100644 platform/broadcom/sonic-platform-modules-nexthop/debian/sonic-platform-nexthop-4010-r0.install delete mode 100644 platform/broadcom/sonic-platform-modules-nexthop/debian/sonic-platform-nexthop-4010-r1.install delete mode 100644 platform/broadcom/sonic-platform-modules-nexthop/debian/sonic-platform-nexthop-4020-r0.install delete mode 100755 platform/broadcom/sonic-platform-modules-nexthop/nh-4010/utils/system_powercycle delete mode 100755 platform/broadcom/sonic-platform-modules-nexthop/nh-4010/utils/transceiver_init.sh create mode 100755 platform/broadcom/sonic-platform-modules-nexthop/sign-modules.sh create mode 100644 platform/broadcom/sonic-platform-modules-nexthop/test/unit/nexthop/test_nh_reboot_cause.py diff --git a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/port_config.ini b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/port_config.ini index 2531d610880..d016d6c14a6 100644 --- a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/port_config.ini +++ b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/port_config.ini @@ -1,68 +1,68 @@ -# name lanes alias index role speed asic_port_name core_id core_port_id num_voq -Ethernet0 96,97,98,99 Port1 1 Ext 100000 Eth0 3 1 8 -Ethernet4 100,101,102,103 Port2 2 Ext 100000 Eth4 3 5 8 -Ethernet8 104,105,106,107 Port3 3 Ext 100000 Eth8 3 9 8 -Ethernet12 108,109,110,111 Port4 4 Ext 100000 Eth12 3 13 8 -Ethernet16 112,113,114,115 Port5 5 Ext 100000 Eth16 3 17 8 -Ethernet20 116,117,118,119 Port6 6 Ext 100000 Eth20 3 21 8 -Ethernet24 120,121,122,123 Port7 7 Ext 100000 Eth24 3 25 8 -Ethernet28 124,125,126,127 Port8 8 Ext 100000 Eth28 3 29 8 -Ethernet32 56,57,58,59 Port9 9 Ext 100000 Eth32 1 25 8 -Ethernet36 60,61,62,63 Port10 10 Ext 100000 Eth36 1 29 8 -Ethernet40 48,49,50,51 Port11 11 Ext 100000 Eth40 1 17 8 -Ethernet44 52,53,54,55 Port12 12 Ext 100000 Eth44 1 21 8 -Ethernet48 40,41,42,43 Port13 13 Ext 100000 Eth48 1 9 8 -Ethernet52 44,45,46,47 Port14 14 Ext 100000 Eth52 1 13 8 -Ethernet56 32,33,34,35 Port15 15 Ext 100000 Eth56 1 1 8 -Ethernet60 36,37,38,39 Port16 16 Ext 100000 Eth60 1 5 8 -Ethernet64 128,129,130,131 Port17 17 Ext 100000 Eth64 4 1 8 -Ethernet68 132,133,134,135 Port18 18 Ext 100000 Eth68 4 5 8 -Ethernet72 136,137,138,139 Port19 19 Ext 100000 Eth72 4 9 8 -Ethernet76 140,141,142,143 Port20 20 Ext 100000 Eth76 4 13 8 -Ethernet80 144,145,146,147 Port21 21 Ext 100000 Eth80 4 17 8 -Ethernet84 148,149,150,151 Port22 22 Ext 100000 Eth84 4 21 8 -Ethernet88 152,153,154,155 Port23 23 Ext 100000 Eth88 4 25 8 -Ethernet92 156,157,158,159 Port24 24 Ext 100000 Eth92 4 29 8 -Ethernet96 216,217,218,219 Port25 25 Ext 100000 Eth96 6 25 8 -Ethernet100 220,221,222,223 Port26 26 Ext 100000 Eth100 6 29 8 -Ethernet104 208,209,210,211 Port27 27 Ext 100000 Eth108 6 17 8 -Ethernet108 212,213,214,215 Port28 28 Ext 100000 Eth108 6 21 8 -Ethernet112 200,201,202,203 Port29 29 Ext 100000 Eth112 6 9 8 -Ethernet116 204,205,206,207 Port30 30 Ext 100000 Eth116 6 13 8 -Ethernet120 192,193,194,195 Port31 31 Ext 100000 Eth120 6 1 8 -Ethernet124 196,197,198,199 Port32 32 Ext 100000 Eth124 6 5 8 -Ethernet128 64,65,66,67 Port33 33 Ext 400000 Eth128 2 1 8 -Ethernet132 68,69,70,71 Port34 34 Ext 400000 Eth132 2 5 8 -Ethernet136 72,73,74,75 Port35 35 Ext 400000 Eth136 2 9 8 -Ethernet140 76,77,78,79 Port36 36 Ext 400000 Eth140 2 13 8 -Ethernet144 80,81,82,83 Port37 37 Ext 400000 Eth144 2 17 8 -Ethernet148 84,85,86,87 Port38 38 Ext 400000 Eth148 2 21 8 -Ethernet152 88,89,90,91 Port39 39 Ext 400000 Eth152 2 25 8 -Ethernet156 92,93,94,95 Port40 40 Ext 400000 Eth156 2 29 8 -Ethernet160 24,25,26,27 Port41 41 Ext 400000 Eth160 0 25 8 -Ethernet164 28,29,30,31 Port42 42 Ext 400000 Eth164 0 29 8 -Ethernet168 16,17,18,19 Port43 43 Ext 400000 Eth168 0 17 8 -Ethernet172 20,21,22,23 Port44 44 Ext 400000 Eth172 0 21 8 -Ethernet176 8,9,10,11 Port45 45 Ext 400000 Eth176 0 9 8 -Ethernet180 12,13,14,15 Port46 46 Ext 400000 Eth180 0 13 8 -Ethernet184 0,1,2,3 Port47 47 Ext 400000 Eth184 0 1 8 -Ethernet188 4,5,6,7 Port48 48 Ext 400000 Eth188 0 5 8 -Ethernet192 160,161,162,163 Port49 49 Ext 400000 Eth192 5 1 8 -Ethernet196 164,165,166,167 Port50 50 Ext 400000 Eth196 5 5 8 -Ethernet200 168,169,170,171 Port51 51 Ext 400000 Eth200 5 9 8 -Ethernet204 172,173,174,175 Port52 52 Ext 400000 Eth204 5 13 8 -Ethernet208 176,177,178,179 Port53 53 Ext 400000 Eth208 5 17 8 -Ethernet212 180,181,182,183 Port54 54 Ext 400000 Eth212 5 21 8 -Ethernet216 184,185,186,187 Port55 55 Ext 400000 Eth216 5 25 8 -Ethernet220 188,189,190,191 Port56 56 Ext 400000 Eth220 5 29 8 -Ethernet224 248,249,250,251 Port57 57 Ext 400000 Eth224 7 25 8 -Ethernet228 252,253,254,255 Port58 58 Ext 400000 Eth228 7 29 8 -Ethernet232 240,241,242,243 Port59 59 Ext 400000 Eth232 7 17 8 -Ethernet236 244,245,246,247 Port60 60 Ext 400000 Eth236 7 21 8 -Ethernet240 232,233,234,235 Port61 61 Ext 400000 Eth240 7 9 8 -Ethernet244 236,237,238,239 Port62 62 Ext 400000 Eth244 7 13 8 -Ethernet248 224,225,226,227 Port63 63 Ext 400000 Eth248 7 1 8 -Ethernet252 228,229,230,231 Port64 64 Ext 400000 Eth252 7 5 8 -Ethernet256 256,257,258,259 Port65 65 Ext 100000 Eth256 2 33 8 -Ethernet260 260,261,262,263 Port66 66 Ext 100000 Eth260 6 33 8 -Ethernet-Rec0 621 Port67 67 Rec 400000 Rcy0 0 221 8 +# name lanes alias index role speed asic_port_name core_id core_port_id num_voq +Ethernet0 96,97,98,99 Port1 1 Ext 100000 Eth0 3 1 8 +Ethernet4 100,101,102,103 Port2 2 Ext 100000 Eth4 3 5 8 +Ethernet8 104,105,106,107 Port3 3 Ext 100000 Eth8 3 9 8 +Ethernet12 108,109,110,111 Port4 4 Ext 100000 Eth12 3 13 8 +Ethernet16 112,113,114,115 Port5 5 Ext 100000 Eth16 3 17 8 +Ethernet20 116,117,118,119 Port6 6 Ext 100000 Eth20 3 21 8 +Ethernet24 120,121,122,123 Port7 7 Ext 100000 Eth24 3 25 8 +Ethernet28 124,125,126,127 Port8 8 Ext 100000 Eth28 3 29 8 +Ethernet32 56,57,58,59 Port9 9 Ext 100000 Eth32 1 25 8 +Ethernet36 60,61,62,63 Port10 10 Ext 100000 Eth36 1 29 8 +Ethernet40 48,49,50,51 Port11 11 Ext 100000 Eth40 1 17 8 +Ethernet44 52,53,54,55 Port12 12 Ext 100000 Eth44 1 21 8 +Ethernet48 40,41,42,43 Port13 13 Ext 100000 Eth48 1 9 8 +Ethernet52 44,45,46,47 Port14 14 Ext 100000 Eth52 1 13 8 +Ethernet56 32,33,34,35 Port15 15 Ext 100000 Eth56 1 1 8 +Ethernet60 36,37,38,39 Port16 16 Ext 100000 Eth60 1 5 8 +Ethernet64 128,129,130,131 Port17 17 Ext 100000 Eth64 4 1 8 +Ethernet68 132,133,134,135 Port18 18 Ext 100000 Eth68 4 5 8 +Ethernet72 136,137,138,139 Port19 19 Ext 100000 Eth72 4 9 8 +Ethernet76 140,141,142,143 Port20 20 Ext 100000 Eth76 4 13 8 +Ethernet80 144,145,146,147 Port21 21 Ext 100000 Eth80 4 17 8 +Ethernet84 148,149,150,151 Port22 22 Ext 100000 Eth84 4 21 8 +Ethernet88 152,153,154,155 Port23 23 Ext 100000 Eth88 4 25 8 +Ethernet92 156,157,158,159 Port24 24 Ext 100000 Eth92 4 29 8 +Ethernet96 216,217,218,219 Port25 25 Ext 100000 Eth96 6 25 8 +Ethernet100 220,221,222,223 Port26 26 Ext 100000 Eth100 6 29 8 +Ethernet104 208,209,210,211 Port27 27 Ext 100000 Eth108 6 17 8 +Ethernet108 212,213,214,215 Port28 28 Ext 100000 Eth108 6 21 8 +Ethernet112 200,201,202,203 Port29 29 Ext 100000 Eth112 6 9 8 +Ethernet116 204,205,206,207 Port30 30 Ext 100000 Eth116 6 13 8 +Ethernet120 192,193,194,195 Port31 31 Ext 100000 Eth120 6 1 8 +Ethernet124 196,197,198,199 Port32 32 Ext 100000 Eth124 6 5 8 +Ethernet128 64,65,66,67 Port33 33 Ext 400000 Eth128 2 1 8 +Ethernet132 68,69,70,71 Port34 34 Ext 400000 Eth132 2 5 8 +Ethernet136 72,73,74,75 Port35 35 Ext 400000 Eth136 2 9 8 +Ethernet140 76,77,78,79 Port36 36 Ext 400000 Eth140 2 13 8 +Ethernet144 80,81,82,83 Port37 37 Ext 400000 Eth144 2 17 8 +Ethernet148 84,85,86,87 Port38 38 Ext 400000 Eth148 2 21 8 +Ethernet152 88,89,90,91 Port39 39 Ext 400000 Eth152 2 25 8 +Ethernet156 92,93,94,95 Port40 40 Ext 400000 Eth156 2 29 8 +Ethernet160 24,25,26,27 Port41 41 Ext 400000 Eth160 0 25 8 +Ethernet164 28,29,30,31 Port42 42 Ext 400000 Eth164 0 29 8 +Ethernet168 16,17,18,19 Port43 43 Ext 400000 Eth168 0 17 8 +Ethernet172 20,21,22,23 Port44 44 Ext 400000 Eth172 0 21 8 +Ethernet176 8,9,10,11 Port45 45 Ext 400000 Eth176 0 9 8 +Ethernet180 12,13,14,15 Port46 46 Ext 400000 Eth180 0 13 8 +Ethernet184 0,1,2,3 Port47 47 Ext 400000 Eth184 0 1 8 +Ethernet188 4,5,6,7 Port48 48 Ext 400000 Eth188 0 5 8 +Ethernet192 160,161,162,163 Port49 49 Ext 400000 Eth192 5 1 8 +Ethernet196 164,165,166,167 Port50 50 Ext 400000 Eth196 5 5 8 +Ethernet200 168,169,170,171 Port51 51 Ext 400000 Eth200 5 9 8 +Ethernet204 172,173,174,175 Port52 52 Ext 400000 Eth204 5 13 8 +Ethernet208 176,177,178,179 Port53 53 Ext 400000 Eth208 5 17 8 +Ethernet212 180,181,182,183 Port54 54 Ext 400000 Eth212 5 21 8 +Ethernet216 184,185,186,187 Port55 55 Ext 400000 Eth216 5 25 8 +Ethernet220 188,189,190,191 Port56 56 Ext 400000 Eth220 5 29 8 +Ethernet224 248,249,250,251 Port57 57 Ext 400000 Eth224 7 25 8 +Ethernet228 252,253,254,255 Port58 58 Ext 400000 Eth228 7 29 8 +Ethernet232 240,241,242,243 Port59 59 Ext 400000 Eth232 7 17 8 +Ethernet236 244,245,246,247 Port60 60 Ext 400000 Eth236 7 21 8 +Ethernet240 232,233,234,235 Port61 61 Ext 400000 Eth240 7 9 8 +Ethernet244 236,237,238,239 Port62 62 Ext 400000 Eth244 7 13 8 +Ethernet248 224,225,226,227 Port63 63 Ext 400000 Eth248 7 1 8 +Ethernet252 228,229,230,231 Port64 64 Ext 400000 Eth252 7 5 8 +Ethernet256 256,257,258,259 Port65 65 Ext 100000 Eth256 2 33 8 +Ethernet260 260,261,262,263 Port66 66 Ext 100000 Eth260 6 33 8 +Ethernet-Rec0 621 Port67 67 Rec 400000 Rcy0 0 221 8 diff --git a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/gearbox_config.json b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/gearbox_config.json index 5f96924fe1a..72dcdbee5b9 100644 --- a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/gearbox_config.json +++ b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/gearbox_config.json @@ -231,224 +231,672 @@ "index": 1, "phy_id": 0, "system_lanes": [20,21,22,23], - "line_lanes": [0,1,2,3,4,5,6,7] + "line_lanes": [0,1,2,3,4,5,6,7], + "system_tx_fir_pre3": [0,0,0,0], + "system_tx_fir_pre2": [0,0,0,0], + "system_tx_fir_pre1": [0,0,0,0], + "system_tx_fir_main": [128,128,128,128], + "system_tx_fir_post1": [0,0,0,0], + "system_tx_fir_post2": [0,0,0,0], + "system_tx_fir_post3": [0,0,0,0], + "line_tx_fir_pre3": [0,0,0,0,0,0,0,0], + "line_tx_fir_pre2": [0,0,0,0,0,0,0,0], + "line_tx_fir_pre1": [-20,-20,-20,-20,-20,-20,-20,-20], + "line_tx_fir_main": [140,140,140,140,140,140,140,140], + "line_tx_fir_post1": [0,0,0,0,0,0,0,0], + "line_tx_fir_post2": [0,0,0,0,0,0,0,0], + "line_tx_fir_post3": [0,0,0,0,0,0,0,0] }, { "name": "Ethernet4", "index": 2, "phy_id": 0, "system_lanes": [24,25,26,27], - "line_lanes": [8,9,10,11,12,13,14,15] + "line_lanes": [8,9,10,11,12,13,14,15], + "system_tx_fir_pre3": [0,0,0,0], + "system_tx_fir_pre2": [0,0,0,0], + "system_tx_fir_pre1": [0,0,0,0], + "system_tx_fir_main": [128,128,128,128], + "system_tx_fir_post1": [0,0,0,0], + "system_tx_fir_post2": [0,0,0,0], + "system_tx_fir_post3": [0,0,0,0], + "line_tx_fir_pre3": [0,0,0,0,0,0,0,0], + "line_tx_fir_pre2": [0,0,0,0,0,0,0,0], + "line_tx_fir_pre1": [-18,-18,-18,-18,-18,-18,-18,-18], + "line_tx_fir_main": [112,112,112,112,112,112,112,112], + "line_tx_fir_post1": [0,0,0,0,0,0,0,0], + "line_tx_fir_post2": [0,0,0,0,0,0,0,0], + "line_tx_fir_post3": [0,0,0,0,0,0,0,0] }, { "name": "Ethernet8", "index": 3, "phy_id": 1, "system_lanes": [52,53,54,55], - "line_lanes": [32,33,34,35,36,37,38,39] + "line_lanes": [32,33,34,35,36,37,38,39], + "system_tx_fir_pre3": [0,0,0,0], + "system_tx_fir_pre2": [0,0,0,0], + "system_tx_fir_pre1": [0,0,0,0], + "system_tx_fir_main": [128,128,128,128], + "system_tx_fir_post1": [0,0,0,0], + "system_tx_fir_post2": [0,0,0,0], + "system_tx_fir_post3": [0,0,0,0], + "line_tx_fir_pre3": [0,0,0,0,0,0,0,0], + "line_tx_fir_pre2": [0,0,0,0,0,0,0,0], + "line_tx_fir_pre1": [-16,-16,-16,-16,-16,-16,-16,-16], + "line_tx_fir_main": [128,128,128,128,128,128,128,128], + "line_tx_fir_post1": [-10,-10,-10,-10,-10,-10,-10,-10], + "line_tx_fir_post2": [0,0,0,0,0,0,0,0], + "line_tx_fir_post3": [0,0,0,0,0,0,0,0] }, { "name": "Ethernet12", "index": 4, "phy_id": 1, "system_lanes": [56,57,58,59], - "line_lanes": [40,41,42,43,44,45,46,47] + "line_lanes": [40,41,42,43,44,45,46,47], + "system_tx_fir_pre3": [0,0,0,0], + "system_tx_fir_pre2": [0,0,0,0], + "system_tx_fir_pre1": [0,0,0,0], + "system_tx_fir_main": [128,128,128,128], + "system_tx_fir_post1": [0,0,0,0], + "system_tx_fir_post2": [0,0,0,0], + "system_tx_fir_post3": [0,0,0,0], + "line_tx_fir_pre3": [0,0,0,0,0,0,0,0], + "line_tx_fir_pre2": [0,0,0,0,0,0,0,0], + "line_tx_fir_pre1": [-18,-18,-18,-18,-18,-18,-18,-18], + "line_tx_fir_main": [112,112,112,112,112,112,112,112], + "line_tx_fir_post1": [0,0,0,0,0,0,0,0], + "line_tx_fir_post2": [0,0,0,0,0,0,0,0], + "line_tx_fir_post3": [0,0,0,0,0,0,0,0] }, { "name": "Ethernet16", "index": 5, "phy_id": 2, "system_lanes": [84,85,86,87], - "line_lanes": [64,65,66,67,68,69,70,71] + "line_lanes": [64,65,66,67,68,69,70,71], + "system_tx_fir_pre3": [0,0,0,0], + "system_tx_fir_pre2": [0,0,0,0], + "system_tx_fir_pre1": [0,0,0,0], + "system_tx_fir_main": [128,128,128,128], + "system_tx_fir_post1": [0,0,0,0], + "system_tx_fir_post2": [0,0,0,0], + "system_tx_fir_post3": [0,0,0,0], + "line_tx_fir_pre3": [0,0,0,0,0,0,0,0], + "line_tx_fir_pre2": [0,0,0,0,0,0,0,0], + "line_tx_fir_pre1": [-20,-20,-20,-20,-20,-20,-20,-20], + "line_tx_fir_main": [100,100,100,100,100,100,100,100], + "line_tx_fir_post1": [-20,-20,-20,-20,-20,-20,-20,-20], + "line_tx_fir_post2": [0,0,0,0,0,0,0,0], + "line_tx_fir_post3": [0,0,0,0,0,0,0,0] }, { "name": "Ethernet20", "index": 6, "phy_id": 2, "system_lanes": [88,89,90,91], - "line_lanes": [72,73,74,75,76,77,78,79] + "line_lanes": [72,73,74,75,76,77,78,79], + "system_tx_fir_pre3": [0,0,0,0], + "system_tx_fir_pre2": [0,0,0,0], + "system_tx_fir_pre1": [0,0,0,0], + "system_tx_fir_main": [128,128,128,128], + "system_tx_fir_post1": [0,0,0,0], + "system_tx_fir_post2": [0,0,0,0], + "system_tx_fir_post3": [0,0,0,0], + "line_tx_fir_pre3": [0,0,0,0,0,0,0,0], + "line_tx_fir_pre2": [0,0,0,0,0,0,0,0], + "line_tx_fir_pre1": [-18,-18,-18,-18,-18,-18,-18,-18], + "line_tx_fir_main": [112,112,112,112,112,112,112,112], + "line_tx_fir_post1": [0,0,0,0,0,0,0,0], + "line_tx_fir_post2": [0,0,0,0,0,0,0,0], + "line_tx_fir_post3": [0,0,0,0,0,0,0,0] }, { "name": "Ethernet24", "index": 7, "phy_id": 3, "system_lanes": [116,117,118,119], - "line_lanes": [96,97,98,99,100,101,102,103] + "line_lanes": [96,97,98,99,100,101,102,103], + "system_tx_fir_pre3": [0,0,0,0], + "system_tx_fir_pre2": [0,0,0,0], + "system_tx_fir_pre1": [0,0,0,0], + "system_tx_fir_main": [128,128,128,128], + "system_tx_fir_post1": [0,0,0,0], + "system_tx_fir_post2": [0,0,0,0], + "system_tx_fir_post3": [0,0,0,0], + "line_tx_fir_pre3": [0,0,0,0,0,0,0,0], + "line_tx_fir_pre2": [0,0,0,0,0,0,0,0], + "line_tx_fir_pre1": [-18,-18,-18,-18,-18,-18,-18,-18], + "line_tx_fir_main": [112,112,112,112,112,112,112,112], + "line_tx_fir_post1": [0,0,0,0,0,0,0,0], + "line_tx_fir_post2": [0,0,0,0,0,0,0,0], + "line_tx_fir_post3": [0,0,0,0,0,0,0,0] }, { "name": "Ethernet28", "index": 8, "phy_id": 3, "system_lanes": [120,121,122,123], - "line_lanes": [104,105,106,107,108,109,110,111] + "line_lanes": [104,105,106,107,108,109,110,111], + "system_tx_fir_pre3": [0,0,0,0], + "system_tx_fir_pre2": [0,0,0,0], + "system_tx_fir_pre1": [0,0,0,0], + "system_tx_fir_main": [128,128,128,128], + "system_tx_fir_post1": [0,0,0,0], + "system_tx_fir_post2": [0,0,0,0], + "system_tx_fir_post3": [0,0,0,0], + "line_tx_fir_pre3": [0,0,0,0,0,0,0,0], + "line_tx_fir_pre2": [0,0,0,0,0,0,0,0], + "line_tx_fir_pre1": [-20,-20,-20,-20,-20,-20,-20,-20], + "line_tx_fir_main": [100,100,100,100,100,100,100,100], + "line_tx_fir_post1": [-20,-20,-20,-20,-20,-20,-20,-20], + "line_tx_fir_post2": [0,0,0,0,0,0,0,0], + "line_tx_fir_post3": [0,0,0,0,0,0,0,0] }, { "name": "Ethernet32", "index": 9, "phy_id": 4, "system_lanes": [148,149,150,151], - "line_lanes": [128,129,130,131,132,133,134,135] + "line_lanes": [128,129,130,131,132,133,134,135], + "system_tx_fir_pre3": [0,0,0,0], + "system_tx_fir_pre2": [0,0,0,0], + "system_tx_fir_pre1": [0,0,0,0], + "system_tx_fir_main": [128,128,128,128], + "system_tx_fir_post1": [0,0,0,0], + "system_tx_fir_post2": [0,0,0,0], + "system_tx_fir_post3": [0,0,0,0], + "line_tx_fir_pre3": [0,0,0,0,0,0,0,0], + "line_tx_fir_pre2": [0,0,0,0,0,0,0,0], + "line_tx_fir_pre1": [-18,-18,-18,-18,-18,-18,-18,-18], + "line_tx_fir_main": [112,112,112,112,112,112,112,112], + "line_tx_fir_post1": [0,0,0,0,0,0,0,0], + "line_tx_fir_post2": [0,0,0,0,0,0,0,0], + "line_tx_fir_post3": [0,0,0,0,0,0,0,0] }, { "name": "Ethernet36", "index": 10, "phy_id": 4, "system_lanes": [152,153,154,155], - "line_lanes": [136,137,138,139,140,141,142,143] + "line_lanes": [136,137,138,139,140,141,142,143], + "system_tx_fir_pre3": [0,0,0,0], + "system_tx_fir_pre2": [0,0,0,0], + "system_tx_fir_pre1": [0,0,0,0], + "system_tx_fir_main": [128,128,128,128], + "system_tx_fir_post1": [0,0,0,0], + "system_tx_fir_post2": [0,0,0,0], + "system_tx_fir_post3": [0,0,0,0], + "line_tx_fir_pre3": [0,0,0,0,0,0,0,0], + "line_tx_fir_pre2": [0,0,0,0,0,0,0,0], + "line_tx_fir_pre1": [-18,-18,-18,-18,-18,-18,-18,-18], + "line_tx_fir_main": [112,112,112,112,112,112,112,112], + "line_tx_fir_post1": [0,0,0,0,0,0,0,0], + "line_tx_fir_post2": [0,0,0,0,0,0,0,0], + "line_tx_fir_post3": [0,0,0,0,0,0,0,0] }, { "name": "Ethernet40", "index": 11, "phy_id": 5, "system_lanes": [180,181,182,183], - "line_lanes": [160,161,162,163,164,165,166,167] + "line_lanes": [160,161,162,163,164,165,166,167], + "system_tx_fir_pre3": [0,0,0,0], + "system_tx_fir_pre2": [0,0,0,0], + "system_tx_fir_pre1": [0,0,0,0], + "system_tx_fir_main": [128,128,128,128], + "system_tx_fir_post1": [0,0,0,0], + "system_tx_fir_post2": [0,0,0,0], + "system_tx_fir_post3": [0,0,0,0], + "line_tx_fir_pre3": [0,0,0,0,0,0,0,0], + "line_tx_fir_pre2": [0,0,0,0,0,0,0,0], + "line_tx_fir_pre1": [-18,-18,-18,-18,-18,-18,-18,-18], + "line_tx_fir_main": [112,112,112,112,112,112,112,112], + "line_tx_fir_post1": [0,0,0,0,0,0,0,0], + "line_tx_fir_post2": [0,0,0,0,0,0,0,0], + "line_tx_fir_post3": [0,0,0,0,0,0,0,0] }, { "name": "Ethernet44", "index": 12, "phy_id": 5, "system_lanes": [184,185,186,187], - "line_lanes": [168,169,170,171,172,173,174,175] + "line_lanes": [168,169,170,171,172,173,174,175], + "system_tx_fir_pre3": [0,0,0,0], + "system_tx_fir_pre2": [0,0,0,0], + "system_tx_fir_pre1": [0,0,0,0], + "system_tx_fir_main": [128,128,128,128], + "system_tx_fir_post1": [0,0,0,0], + "system_tx_fir_post2": [0,0,0,0], + "system_tx_fir_post3": [0,0,0,0], + "line_tx_fir_pre3": [0,0,0,0,0,0,0,0], + "line_tx_fir_pre2": [0,0,0,0,0,0,0,0], + "line_tx_fir_pre1": [-18,-18,-18,-18,-18,-18,-18,-18], + "line_tx_fir_main": [112,112,112,112,112,112,112,112], + "line_tx_fir_post1": [0,0,0,0,0,0,0,0], + "line_tx_fir_post2": [0,0,0,0,0,0,0,0], + "line_tx_fir_post3": [0,0,0,0,0,0,0,0] }, { "name": "Ethernet48", "index": 13, "phy_id": 6, "system_lanes": [212,213,214,215], - "line_lanes": [192,193,194,195,196,197,198,199] + "line_lanes": [192,193,194,195,196,197,198,199], + "system_tx_fir_pre3": [0,0,0,0], + "system_tx_fir_pre2": [0,0,0,0], + "system_tx_fir_pre1": [0,0,0,0], + "system_tx_fir_main": [128,128,128,128], + "system_tx_fir_post1": [0,0,0,0], + "system_tx_fir_post2": [0,0,0,0], + "system_tx_fir_post3": [0,0,0,0], + "line_tx_fir_pre3": [0,0,0,0,0,0,0,0], + "line_tx_fir_pre2": [0,0,0,0,0,0,0,0], + "line_tx_fir_pre1": [-18,-18,-18,-18,-18,-18,-18,-18], + "line_tx_fir_main": [112,112,112,112,112,112,112,112], + "line_tx_fir_post1": [0,0,0,0,0,0,0,0], + "line_tx_fir_post2": [0,0,0,0,0,0,0,0], + "line_tx_fir_post3": [0,0,0,0,0,0,0,0] }, { "name": "Ethernet52", "index": 14, "phy_id": 6, "system_lanes": [216,217,218,219], - "line_lanes": [200,201,202,203,204,205,206,207] + "line_lanes": [200,201,202,203,204,205,206,207], + "system_tx_fir_pre3": [0,0,0,0], + "system_tx_fir_pre2": [0,0,0,0], + "system_tx_fir_pre1": [0,0,0,0], + "system_tx_fir_main": [128,128,128,128], + "system_tx_fir_post1": [0,0,0,0], + "system_tx_fir_post2": [0,0,0,0], + "system_tx_fir_post3": [0,0,0,0], + "line_tx_fir_pre3": [0,0,0,0,0,0,0,0], + "line_tx_fir_pre2": [0,0,0,0,0,0,0,0], + "line_tx_fir_pre1": [-18,-18,-18,-18,-18,-18,-18,-18], + "line_tx_fir_main": [112,112,112,112,112,112,112,112], + "line_tx_fir_post1": [0,0,0,0,0,0,0,0], + "line_tx_fir_post2": [0,0,0,0,0,0,0,0], + "line_tx_fir_post3": [0,0,0,0,0,0,0,0] }, { "name": "Ethernet56", "index": 15, "phy_id": 7, "system_lanes": [244,245,246,247], - "line_lanes": [224,225,226,227,228,229,230,231] + "line_lanes": [224,225,226,227,228,229,230,231], + "system_tx_fir_pre3": [0,0,0,0], + "system_tx_fir_pre2": [0,0,0,0], + "system_tx_fir_pre1": [0,0,0,0], + "system_tx_fir_main": [128,128,128,128], + "system_tx_fir_post1": [0,0,0,0], + "system_tx_fir_post2": [0,0,0,0], + "system_tx_fir_post3": [0,0,0,0], + "line_tx_fir_pre3": [0,0,0,0,0,0,0,0], + "line_tx_fir_pre2": [0,0,0,0,0,0,0,0], + "line_tx_fir_pre1": [-18,-18,-18,-18,-18,-18,-18,-18], + "line_tx_fir_main": [100,100,100,100,100,100,100,100], + "line_tx_fir_post1": [-2,-2,-2,-2,-2,-2,-2,-2], + "line_tx_fir_post2": [0,0,0,0,0,0,0,0], + "line_tx_fir_post3": [0,0,0,0,0,0,0,0] }, { "name": "Ethernet60", "index": 16, "phy_id": 7, "system_lanes": [248,249,250,251], - "line_lanes": [232,233,234,235,236,237,238,239] + "line_lanes": [232,233,234,235,236,237,238,239], + "system_tx_fir_pre3": [0,0,0,0], + "system_tx_fir_pre2": [0,0,0,0], + "system_tx_fir_pre1": [0,0,0,0], + "system_tx_fir_main": [128,128,128,128], + "system_tx_fir_post1": [0,0,0,0], + "system_tx_fir_post2": [0,0,0,0], + "system_tx_fir_post3": [0,0,0,0], + "line_tx_fir_pre3": [0,0,0,0,0,0,0,0], + "line_tx_fir_pre2": [0,0,0,0,0,0,0,0], + "line_tx_fir_pre1": [-18,-18,-18,-18,-18,-18,-18,-18], + "line_tx_fir_main": [112,112,112,112,112,112,112,112], + "line_tx_fir_post1": [0,0,0,0,0,0,0,0], + "line_tx_fir_post2": [0,0,0,0,0,0,0,0], + "line_tx_fir_post3": [0,0,0,0,0,0,0,0] }, { "name": "Ethernet64", "index": 17, "phy_id": 8, "system_lanes": [276,277,278,279], - "line_lanes": [256,257,258,259,260,261,262,263] + "line_lanes": [256,257,258,259,260,261,262,263], + "system_tx_fir_pre3": [0,0,0,0], + "system_tx_fir_pre2": [0,0,0,0], + "system_tx_fir_pre1": [0,0,0,0], + "system_tx_fir_main": [128,128,128,128], + "system_tx_fir_post1": [0,0,0,0], + "system_tx_fir_post2": [0,0,0,0], + "system_tx_fir_post3": [0,0,0,0], + "line_tx_fir_pre3": [0,0,0,0,0,0,0,0], + "line_tx_fir_pre2": [0,0,0,0,0,0,0,0], + "line_tx_fir_pre1": [-18,-18,-18,-18,-18,-18,-18,-18], + "line_tx_fir_main": [112,112,112,112,112,112,112,112], + "line_tx_fir_post1": [0,0,0,0,0,0,0,0], + "line_tx_fir_post2": [0,0,0,0,0,0,0,0], + "line_tx_fir_post3": [0,0,0,0,0,0,0,0] }, { "name": "Ethernet68", "index": 18, "phy_id": 8, "system_lanes": [280,281,282,283], - "line_lanes": [264,265,266,267,268,269,270,271] + "line_lanes": [264,265,266,267,268,269,270,271], + "system_tx_fir_pre3": [0,0,0,0], + "system_tx_fir_pre2": [0,0,0,0], + "system_tx_fir_pre1": [0,0,0,0], + "system_tx_fir_main": [128,128,128,128], + "system_tx_fir_post1": [0,0,0,0], + "system_tx_fir_post2": [0,0,0,0], + "system_tx_fir_post3": [0,0,0,0], + "line_tx_fir_pre3": [0,0,0,0,0,0,0,0], + "line_tx_fir_pre2": [0,0,0,0,0,0,0,0], + "line_tx_fir_pre1": [-18,-18,-18,-18,-18,-18,-18,-18], + "line_tx_fir_main": [112,112,112,112,112,112,112,112], + "line_tx_fir_post1": [0,0,0,0,0,0,0,0], + "line_tx_fir_post2": [0,0,0,0,0,0,0,0], + "line_tx_fir_post3": [0,0,0,0,0,0,0,0] }, { "name": "Ethernet72", "index": 19, "phy_id": 9, "system_lanes": [308,309,310,311], - "line_lanes": [288,289,290,291,292,293,294,295] + "line_lanes": [288,289,290,291,292,293,294,295], + "system_tx_fir_pre3": [0,0,0,0], + "system_tx_fir_pre2": [0,0,0,0], + "system_tx_fir_pre1": [0,0,0,0], + "system_tx_fir_main": [128,128,128,128], + "system_tx_fir_post1": [0,0,0,0], + "system_tx_fir_post2": [0,0,0,0], + "system_tx_fir_post3": [0,0,0,0], + "line_tx_fir_pre3": [0,0,0,0,0,0,0,0], + "line_tx_fir_pre2": [0,0,0,0,0,0,0,0], + "line_tx_fir_pre1": [-16,-16,-16,-16,-16,-16,-16,-16], + "line_tx_fir_main": [112,112,112,112,112,112,112,112], + "line_tx_fir_post1": [0,0,0,0,0,0,0,0], + "line_tx_fir_post2": [0,0,0,0,0,0,0,0], + "line_tx_fir_post3": [0,0,0,0,0,0,0,0] }, { "name": "Ethernet76", "index": 20, "phy_id": 9, "system_lanes": [312,313,314,315], - "line_lanes": [296,297,298,299,300,301,302,303] + "line_lanes": [296,297,298,299,300,301,302,303], + "system_tx_fir_pre3": [0,0,0,0], + "system_tx_fir_pre2": [0,0,0,0], + "system_tx_fir_pre1": [0,0,0,0], + "system_tx_fir_main": [128,128,128,128], + "system_tx_fir_post1": [0,0,0,0], + "system_tx_fir_post2": [0,0,0,0], + "system_tx_fir_post3": [0,0,0,0], + "line_tx_fir_pre3": [0,0,0,0,0,0,0,0], + "line_tx_fir_pre2": [0,0,0,0,0,0,0,0], + "line_tx_fir_pre1": [-18,-18,-18,-18,-18,-18,-18,-18], + "line_tx_fir_main": [112,112,112,112,112,112,112,112], + "line_tx_fir_post1": [0,0,0,0,0,0,0,0], + "line_tx_fir_post2": [0,0,0,0,0,0,0,0], + "line_tx_fir_post3": [0,0,0,0,0,0,0,0] }, { "name": "Ethernet80", "index": 21, "phy_id": 10, "system_lanes": [340,341,342,343], - "line_lanes": [320,321,322,323,324,325,326,327] + "line_lanes": [320,321,322,323,324,325,326,327], + "system_tx_fir_pre3": [0,0,0,0], + "system_tx_fir_pre2": [0,0,0,0], + "system_tx_fir_pre1": [0,0,0,0], + "system_tx_fir_main": [128,128,128,128], + "system_tx_fir_post1": [0,0,0,0], + "system_tx_fir_post2": [0,0,0,0], + "system_tx_fir_post3": [0,0,0,0], + "line_tx_fir_pre3": [0,0,0,0,0,0,0,0], + "line_tx_fir_pre2": [0,0,0,0,0,0,0,0], + "line_tx_fir_pre1": [-18,-18,-18,-18,-18,-18,-18,-18], + "line_tx_fir_main": [112,112,112,112,112,112,112,112], + "line_tx_fir_post1": [0,0,0,0,0,0,0,0], + "line_tx_fir_post2": [0,0,0,0,0,0,0,0], + "line_tx_fir_post3": [0,0,0,0,0,0,0,0] }, { "name": "Ethernet84", "index": 22, "phy_id": 10, "system_lanes": [344,345,346,347], - "line_lanes": [328,329,330,331,332,333,334,335] + "line_lanes": [328,329,330,331,332,333,334,335], + "system_tx_fir_pre3": [0,0,0,0], + "system_tx_fir_pre2": [0,0,0,0], + "system_tx_fir_pre1": [0,0,0,0], + "system_tx_fir_main": [128,128,128,128], + "system_tx_fir_post1": [0,0,0,0], + "system_tx_fir_post2": [0,0,0,0], + "system_tx_fir_post3": [0,0,0,0], + "line_tx_fir_pre3": [0,0,0,0,0,0,0,0], + "line_tx_fir_pre2": [0,0,0,0,0,0,0,0], + "line_tx_fir_pre1": [-18,-18,-18,-18,-18,-18,-18,-18], + "line_tx_fir_main": [112,112,112,112,112,112,112,112], + "line_tx_fir_post1": [0,0,0,0,0,0,0,0], + "line_tx_fir_post2": [0,0,0,0,0,0,0,0], + "line_tx_fir_post3": [0,0,0,0,0,0,0,0] }, { "name": "Ethernet88", "index": 23, "phy_id": 11, "system_lanes": [372,373,374,375], - "line_lanes": [352,353,354,355,356,357,358,359] + "line_lanes": [352,353,354,355,356,357,358,359], + "system_tx_fir_pre3": [0,0,0,0], + "system_tx_fir_pre2": [0,0,0,0], + "system_tx_fir_pre1": [0,0,0,0], + "system_tx_fir_main": [128,128,128,128], + "system_tx_fir_post1": [0,0,0,0], + "system_tx_fir_post2": [0,0,0,0], + "system_tx_fir_post3": [0,0,0,0], + "line_tx_fir_pre3": [0,0,0,0,0,0,0,0], + "line_tx_fir_pre2": [0,0,0,0,0,0,0,0], + "line_tx_fir_pre1": [-16,-16,-16,-16,-16,-16,-16,-16], + "line_tx_fir_main": [116,116,116,116,116,116,116,116], + "line_tx_fir_post1": [-4,-4,-4,-4,-4,-4,-4,-4], + "line_tx_fir_post2": [0,0,0,0,0,0,0,0], + "line_tx_fir_post3": [0,0,0,0,0,0,0,0] }, { "name": "Ethernet92", "index": 24, "phy_id": 11, "system_lanes": [376,377,378,379], - "line_lanes": [360,361,362,363,364,365,366,367] + "line_lanes": [360,361,362,363,364,365,366,367], + "system_tx_fir_pre3": [0,0,0,0], + "system_tx_fir_pre2": [0,0,0,0], + "system_tx_fir_pre1": [0,0,0,0], + "system_tx_fir_main": [128,128,128,128], + "system_tx_fir_post1": [0,0,0,0], + "system_tx_fir_post2": [0,0,0,0], + "system_tx_fir_post3": [0,0,0,0], + "line_tx_fir_pre3": [0,0,0,0,0,0,0,0], + "line_tx_fir_pre2": [0,0,0,0,0,0,0,0], + "line_tx_fir_pre1": [-18,-18,-18,-18,-18,-18,-18,-18], + "line_tx_fir_main": [112,112,112,112,112,112,112,112], + "line_tx_fir_post1": [0,0,0,0,0,0,0,0], + "line_tx_fir_post2": [0,0,0,0,0,0,0,0], + "line_tx_fir_post3": [0,0,0,0,0,0,0,0] }, { "name": "Ethernet96", "index": 25, "phy_id": 12, "system_lanes": [404,405,406,407], - "line_lanes": [384,385,386,387,388,389,390,391] + "line_lanes": [384,385,386,387,388,389,390,391], + "system_tx_fir_pre3": [0,0,0,0], + "system_tx_fir_pre2": [0,0,0,0], + "system_tx_fir_pre1": [0,0,0,0], + "system_tx_fir_main": [128,128,128,128], + "system_tx_fir_post1": [0,0,0,0], + "system_tx_fir_post2": [0,0,0,0], + "system_tx_fir_post3": [0,0,0,0], + "line_tx_fir_pre3": [0,0,0,0,0,0,0,0], + "line_tx_fir_pre2": [0,0,0,0,0,0,0,0], + "line_tx_fir_pre1": [-18,-18,-18,-18,-18,-18,-18,-18], + "line_tx_fir_main": [100,100,100,100,100,100,100,100], + "line_tx_fir_post1": [-16,-16,-16,-16,-16,-16,-16,-16], + "line_tx_fir_post2": [0,0,0,0,0,0,0,0], + "line_tx_fir_post3": [0,0,0,0,0,0,0,0] }, { "name": "Ethernet100", "index": 26, "phy_id": 12, "system_lanes": [408,409,410,411], - "line_lanes": [392,393,394,395,396,397,398,399] + "line_lanes": [392,393,394,395,396,397,398,399], + "system_tx_fir_pre3": [0,0,0,0], + "system_tx_fir_pre2": [0,0,0,0], + "system_tx_fir_pre1": [0,0,0,0], + "system_tx_fir_main": [128,128,128,128], + "system_tx_fir_post1": [0,0,0,0], + "system_tx_fir_post2": [0,0,0,0], + "system_tx_fir_post3": [0,0,0,0], + "line_tx_fir_pre3": [0,0,0,0,0,0,0,0], + "line_tx_fir_pre2": [0,0,0,0,0,0,0,0], + "line_tx_fir_pre1": [-16,-16,-16,-16,-16,-16,-16,-16], + "line_tx_fir_main": [104,104,104,104,104,104,104,104], + "line_tx_fir_post1": [-4,-4,-4,-4,-4,-4,-4,-4], + "line_tx_fir_post2": [0,0,0,0,0,0,0,0], + "line_tx_fir_post3": [0,0,0,0,0,0,0,0] }, { "name": "Ethernet104", "index": 27, "phy_id": 13, "system_lanes": [436,437,438,439], - "line_lanes": [416,417,418,419,420,421,422,423] + "line_lanes": [416,417,418,419,420,421,422,423], + "system_tx_fir_pre3": [0,0,0,0], + "system_tx_fir_pre2": [0,0,0,0], + "system_tx_fir_pre1": [0,0,0,0], + "system_tx_fir_main": [128,128,128,128], + "system_tx_fir_post1": [0,0,0,0], + "system_tx_fir_post2": [0,0,0,0], + "system_tx_fir_post3": [0,0,0,0], + "line_tx_fir_pre3": [0,0,0,0,0,0,0,0], + "line_tx_fir_pre2": [0,0,0,0,0,0,0,0], + "line_tx_fir_pre1": [-18,-18,-18,-18,-18,-18,-18,-18], + "line_tx_fir_main": [112,112,112,112,112,112,112,112], + "line_tx_fir_post1": [0,0,0,0,0,0,0,0], + "line_tx_fir_post2": [0,0,0,0,0,0,0,0], + "line_tx_fir_post3": [0,0,0,0,0,0,0,0] }, { "name": "Ethernet108", "index": 28, "phy_id": 13, "system_lanes": [440,441,442,443], - "line_lanes": [424,425,426,427,428,429,430,431] + "line_lanes": [424,425,426,427,428,429,430,431], + "system_tx_fir_pre3": [0,0,0,0], + "system_tx_fir_pre2": [0,0,0,0], + "system_tx_fir_pre1": [0,0,0,0], + "system_tx_fir_main": [128,128,128,128], + "system_tx_fir_post1": [0,0,0,0], + "system_tx_fir_post2": [0,0,0,0], + "system_tx_fir_post3": [0,0,0,0], + "line_tx_fir_pre3": [0,0,0,0,0,0,0,0], + "line_tx_fir_pre2": [0,0,0,0,0,0,0,0], + "line_tx_fir_pre1": [-16,-16,-16,-16,-16,-16,-16,-16], + "line_tx_fir_main": [120,120,120,120,120,120,120,120], + "line_tx_fir_post1": [0,0,0,0,0,0,0,0], + "line_tx_fir_post2": [0,0,0,0,0,0,0,0], + "line_tx_fir_post3": [0,0,0,0,0,0,0,0] }, { "name": "Ethernet112", "index": 29, "phy_id": 14, "system_lanes": [468,469,470,471], - "line_lanes": [448,449,450,451,452,453,454,455] + "line_lanes": [448,449,450,451,452,453,454,455], + "system_tx_fir_pre3": [0,0,0,0], + "system_tx_fir_pre2": [0,0,0,0], + "system_tx_fir_pre1": [0,0,0,0], + "system_tx_fir_main": [128,128,128,128], + "system_tx_fir_post1": [0,0,0,0], + "system_tx_fir_post2": [0,0,0,0], + "system_tx_fir_post3": [0,0,0,0], + "line_tx_fir_pre3": [0,0,0,0,0,0,0,0], + "line_tx_fir_pre2": [0,0,0,0,0,0,0,0], + "line_tx_fir_pre1": [-18,-18,-18,-18,-18,-18,-18,-18], + "line_tx_fir_main": [112,112,112,112,112,112,112,112], + "line_tx_fir_post1": [0,0,0,0,0,0,0,0], + "line_tx_fir_post2": [0,0,0,0,0,0,0,0], + "line_tx_fir_post3": [0,0,0,0,0,0,0,0] }, { "name": "Ethernet116", "index": 30, "phy_id": 14, "system_lanes": [472,473,474,475], - "line_lanes": [456,457,458,459,460,461,462,463] + "line_lanes": [456,457,458,459,460,461,462,463], + "system_tx_fir_pre3": [0,0,0,0], + "system_tx_fir_pre2": [0,0,0,0], + "system_tx_fir_pre1": [0,0,0,0], + "system_tx_fir_main": [128,128,128,128], + "system_tx_fir_post1": [0,0,0,0], + "system_tx_fir_post2": [0,0,0,0], + "system_tx_fir_post3": [0,0,0,0], + "line_tx_fir_pre3": [0,0,0,0,0,0,0,0], + "line_tx_fir_pre2": [0,0,0,0,0,0,0,0], + "line_tx_fir_pre1": [-18,-18,-18,-18,-18,-18,-18,-18], + "line_tx_fir_main": [112,112,112,112,112,112,112,112], + "line_tx_fir_post1": [0,0,0,0,0,0,0,0], + "line_tx_fir_post2": [0,0,0,0,0,0,0,0], + "line_tx_fir_post3": [0,0,0,0,0,0,0,0] }, { "name": "Ethernet120", "index": 31, "phy_id": 15, "system_lanes": [500,501,502,503], - "line_lanes": [480,481,482,483,484,485,486,487] + "line_lanes": [480,481,482,483,484,485,486,487], + "system_tx_fir_pre3": [0,0,0,0], + "system_tx_fir_pre2": [0,0,0,0], + "system_tx_fir_pre1": [0,0,0,0], + "system_tx_fir_main": [128,128,128,128], + "system_tx_fir_post1": [0,0,0,0], + "system_tx_fir_post2": [0,0,0,0], + "system_tx_fir_post3": [0,0,0,0], + "line_tx_fir_pre3": [0,0,0,0,0,0,0,0], + "line_tx_fir_pre2": [0,0,0,0,0,0,0,0], + "line_tx_fir_pre1": [-16,-16,-16,-16,-16,-16,-16,-16], + "line_tx_fir_main": [124,124,124,124,124,124,124,124], + "line_tx_fir_post1": [0,0,0,0,0,0,0,0], + "line_tx_fir_post2": [0,0,0,0,0,0,0,0], + "line_tx_fir_post3": [0,0,0,0,0,0,0,0] }, { "name": "Ethernet124", "index": 32, "phy_id": 15, "system_lanes": [504,505,506,507], - "line_lanes": [488,489,490,491,492,493,494,495] + "line_lanes": [488,489,490,491,492,493,494,495], + "system_tx_fir_pre3": [0,0,0,0], + "system_tx_fir_pre2": [0,0,0,0], + "system_tx_fir_pre1": [0,0,0,0], + "system_tx_fir_main": [128,128,128,128], + "system_tx_fir_post1": [0,0,0,0], + "system_tx_fir_post2": [0,0,0,0], + "system_tx_fir_post3": [0,0,0,0], + "line_tx_fir_pre3": [0,0,0,0,0,0,0,0], + "line_tx_fir_pre2": [0,0,0,0,0,0,0,0], + "line_tx_fir_pre1": [-18,-18,-18,-18,-18,-18,-18,-18], + "line_tx_fir_main": [112,112,112,112,112,112,112,112], + "line_tx_fir_post1": [0,0,0,0,0,0,0,0], + "line_tx_fir_post2": [0,0,0,0,0,0,0,0], + "line_tx_fir_post3": [0,0,0,0,0,0,0,0] } ] } diff --git a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/nh5010-default.bcm b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/nh5010-default.bcm index 2d0b66812b5..a8a869a0a75 100644 --- a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/nh5010-default.bcm +++ b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/nh5010-default.bcm @@ -10,49 +10,49 @@ tm_port_header_type_out_189.BCM8887X=ETH lane_to_serdes_map_nif_lane0.BCM8887X=rx6:tx7 phy_rx_polarity_flip_phy0.BCM8887X=0 phy_tx_polarity_flip_phy0.BCM8887X=1 -serdes_tx_taps_0.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_0.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 0 lane1 lane_to_serdes_map_nif_lane1.BCM8887X=rx4:tx3 phy_rx_polarity_flip_phy1.BCM8887X=0 phy_tx_polarity_flip_phy1.BCM8887X=1 -serdes_tx_taps_1.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_1.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 0 lane2 lane_to_serdes_map_nif_lane2.BCM8887X=rx7:tx1 phy_rx_polarity_flip_phy2.BCM8887X=0 phy_tx_polarity_flip_phy2.BCM8887X=0 -serdes_tx_taps_2.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_2.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 0 lane3 lane_to_serdes_map_nif_lane3.BCM8887X=rx5:tx2 phy_rx_polarity_flip_phy3.BCM8887X=0 phy_tx_polarity_flip_phy3.BCM8887X=1 -serdes_tx_taps_3.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_3.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 0 lane4 lane_to_serdes_map_nif_lane4.BCM8887X=rx2:tx0 phy_rx_polarity_flip_phy4.BCM8887X=0 phy_tx_polarity_flip_phy4.BCM8887X=0 -serdes_tx_taps_4.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_4.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 0 lane5 lane_to_serdes_map_nif_lane5.BCM8887X=rx3:tx6 phy_rx_polarity_flip_phy5.BCM8887X=1 phy_tx_polarity_flip_phy5.BCM8887X=1 -serdes_tx_taps_5.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_5.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 0 lane6 lane_to_serdes_map_nif_lane6.BCM8887X=rx0:tx4 phy_rx_polarity_flip_phy6.BCM8887X=0 phy_tx_polarity_flip_phy6.BCM8887X=0 -serdes_tx_taps_6.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_6.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 0 lane7 lane_to_serdes_map_nif_lane7.BCM8887X=rx1:tx5 phy_rx_polarity_flip_phy7.BCM8887X=0 phy_tx_polarity_flip_phy7.BCM8887X=0 -serdes_tx_taps_7.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_7.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # ---------------------------------------------------------------------------------------------------- @@ -67,49 +67,49 @@ tm_port_header_type_out_181.BCM8887X=ETH lane_to_serdes_map_nif_lane8.BCM8887X=rx10:tx8 phy_rx_polarity_flip_phy8.BCM8887X=0 phy_tx_polarity_flip_phy8.BCM8887X=0 -serdes_tx_taps_8.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_8.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 1 lane9 lane_to_serdes_map_nif_lane9.BCM8887X=rx11:tx14 phy_rx_polarity_flip_phy9.BCM8887X=1 phy_tx_polarity_flip_phy9.BCM8887X=1 -serdes_tx_taps_9.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_9.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 1 lane10 lane_to_serdes_map_nif_lane10.BCM8887X=rx8:tx12 phy_rx_polarity_flip_phy10.BCM8887X=1 phy_tx_polarity_flip_phy10.BCM8887X=0 -serdes_tx_taps_10.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_10.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 1 lane11 lane_to_serdes_map_nif_lane11.BCM8887X=rx9:tx13 phy_rx_polarity_flip_phy11.BCM8887X=0 phy_tx_polarity_flip_phy11.BCM8887X=0 -serdes_tx_taps_11.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_11.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 1 lane12 lane_to_serdes_map_nif_lane12.BCM8887X=rx14:tx15 phy_rx_polarity_flip_phy12.BCM8887X=0 phy_tx_polarity_flip_phy12.BCM8887X=1 -serdes_tx_taps_12.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_12.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 1 lane13 lane_to_serdes_map_nif_lane13.BCM8887X=rx12:tx11 phy_rx_polarity_flip_phy13.BCM8887X=0 phy_tx_polarity_flip_phy13.BCM8887X=1 -serdes_tx_taps_13.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_13.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 1 lane14 lane_to_serdes_map_nif_lane14.BCM8887X=rx15:tx9 phy_rx_polarity_flip_phy14.BCM8887X=0 phy_tx_polarity_flip_phy14.BCM8887X=0 -serdes_tx_taps_14.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_14.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 1 lane15 lane_to_serdes_map_nif_lane15.BCM8887X=rx13:tx10 phy_rx_polarity_flip_phy15.BCM8887X=0 phy_tx_polarity_flip_phy15.BCM8887X=1 -serdes_tx_taps_15.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_15.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # ---------------------------------------------------------------------------------------------------- @@ -124,49 +124,49 @@ tm_port_header_type_out_173.BCM8887X=ETH lane_to_serdes_map_nif_lane16.BCM8887X=rx18:tx16 phy_rx_polarity_flip_phy16.BCM8887X=0 phy_tx_polarity_flip_phy16.BCM8887X=0 -serdes_tx_taps_16.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_16.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 2 lane17 lane_to_serdes_map_nif_lane17.BCM8887X=rx19:tx22 phy_rx_polarity_flip_phy17.BCM8887X=1 phy_tx_polarity_flip_phy17.BCM8887X=1 -serdes_tx_taps_17.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_17.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 2 lane18 lane_to_serdes_map_nif_lane18.BCM8887X=rx16:tx20 phy_rx_polarity_flip_phy18.BCM8887X=0 phy_tx_polarity_flip_phy18.BCM8887X=0 -serdes_tx_taps_18.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_18.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 2 lane19 lane_to_serdes_map_nif_lane19.BCM8887X=rx17:tx21 phy_rx_polarity_flip_phy19.BCM8887X=0 phy_tx_polarity_flip_phy19.BCM8887X=0 -serdes_tx_taps_19.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_19.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 2 lane20 lane_to_serdes_map_nif_lane20.BCM8887X=rx22:tx23 phy_rx_polarity_flip_phy20.BCM8887X=0 phy_tx_polarity_flip_phy20.BCM8887X=1 -serdes_tx_taps_20.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_20.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 2 lane21 lane_to_serdes_map_nif_lane21.BCM8887X=rx20:tx19 phy_rx_polarity_flip_phy21.BCM8887X=0 phy_tx_polarity_flip_phy21.BCM8887X=1 -serdes_tx_taps_21.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_21.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 2 lane22 lane_to_serdes_map_nif_lane22.BCM8887X=rx23:tx17 phy_rx_polarity_flip_phy22.BCM8887X=0 phy_tx_polarity_flip_phy22.BCM8887X=0 -serdes_tx_taps_22.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_22.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 2 lane23 lane_to_serdes_map_nif_lane23.BCM8887X=rx21:tx18 phy_rx_polarity_flip_phy23.BCM8887X=0 phy_tx_polarity_flip_phy23.BCM8887X=1 -serdes_tx_taps_23.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_23.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # ---------------------------------------------------------------------------------------------------- @@ -181,49 +181,49 @@ tm_port_header_type_out_165.BCM8887X=ETH lane_to_serdes_map_nif_lane24.BCM8887X=rx26:tx26 phy_rx_polarity_flip_phy24.BCM8887X=1 phy_tx_polarity_flip_phy24.BCM8887X=0 -serdes_tx_taps_24.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_24.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 3 lane25 lane_to_serdes_map_nif_lane25.BCM8887X=rx27:tx25 phy_rx_polarity_flip_phy25.BCM8887X=0 phy_tx_polarity_flip_phy25.BCM8887X=1 -serdes_tx_taps_25.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_25.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 3 lane26 lane_to_serdes_map_nif_lane26.BCM8887X=rx28:tx31 phy_rx_polarity_flip_phy26.BCM8887X=0 phy_tx_polarity_flip_phy26.BCM8887X=0 -serdes_tx_taps_26.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_26.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 3 lane27 lane_to_serdes_map_nif_lane27.BCM8887X=rx30:tx24 phy_rx_polarity_flip_phy27.BCM8887X=1 phy_tx_polarity_flip_phy27.BCM8887X=0 -serdes_tx_taps_27.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_27.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 3 lane28 lane_to_serdes_map_nif_lane28.BCM8887X=rx29:tx28 phy_rx_polarity_flip_phy28.BCM8887X=1 phy_tx_polarity_flip_phy28.BCM8887X=1 -serdes_tx_taps_28.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_28.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 3 lane29 lane_to_serdes_map_nif_lane29.BCM8887X=rx31:tx27 phy_rx_polarity_flip_phy29.BCM8887X=0 phy_tx_polarity_flip_phy29.BCM8887X=1 -serdes_tx_taps_29.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_29.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 3 lane30 lane_to_serdes_map_nif_lane30.BCM8887X=rx24:tx30 phy_rx_polarity_flip_phy30.BCM8887X=0 phy_tx_polarity_flip_phy30.BCM8887X=1 -serdes_tx_taps_30.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_30.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 3 lane31 lane_to_serdes_map_nif_lane31.BCM8887X=rx25:tx29 phy_rx_polarity_flip_phy31.BCM8887X=0 phy_tx_polarity_flip_phy31.BCM8887X=1 -serdes_tx_taps_31.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_31.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # ---------------------------------------------------------------------------------------------------- @@ -238,49 +238,49 @@ tm_port_header_type_out_61.BCM8887X=ETH lane_to_serdes_map_nif_lane32.BCM8887X=rx35:tx39 phy_rx_polarity_flip_phy32.BCM8887X=1 phy_tx_polarity_flip_phy32.BCM8887X=0 -serdes_tx_taps_32.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_32.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 4 lane33 lane_to_serdes_map_nif_lane33.BCM8887X=rx34:tx35 phy_rx_polarity_flip_phy33.BCM8887X=0 phy_tx_polarity_flip_phy33.BCM8887X=0 -serdes_tx_taps_33.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_33.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 4 lane34 lane_to_serdes_map_nif_lane34.BCM8887X=rx37:tx34 phy_rx_polarity_flip_phy34.BCM8887X=1 phy_tx_polarity_flip_phy34.BCM8887X=0 -serdes_tx_taps_34.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_34.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 4 lane35 lane_to_serdes_map_nif_lane35.BCM8887X=rx39:tx33 phy_rx_polarity_flip_phy35.BCM8887X=1 phy_tx_polarity_flip_phy35.BCM8887X=1 -serdes_tx_taps_35.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_35.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 4 lane36 lane_to_serdes_map_nif_lane36.BCM8887X=rx33:tx36 phy_rx_polarity_flip_phy36.BCM8887X=1 phy_tx_polarity_flip_phy36.BCM8887X=0 -serdes_tx_taps_36.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_36.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 4 lane37 lane_to_serdes_map_nif_lane37.BCM8887X=rx32:tx37 phy_rx_polarity_flip_phy37.BCM8887X=0 phy_tx_polarity_flip_phy37.BCM8887X=1 -serdes_tx_taps_37.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_37.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 4 lane38 lane_to_serdes_map_nif_lane38.BCM8887X=rx36:tx38 phy_rx_polarity_flip_phy38.BCM8887X=0 phy_tx_polarity_flip_phy38.BCM8887X=0 -serdes_tx_taps_38.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_38.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 4 lane39 lane_to_serdes_map_nif_lane39.BCM8887X=rx38:tx32 phy_rx_polarity_flip_phy39.BCM8887X=0 phy_tx_polarity_flip_phy39.BCM8887X=1 -serdes_tx_taps_39.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_39.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # ---------------------------------------------------------------------------------------------------- @@ -295,49 +295,49 @@ tm_port_header_type_out_53.BCM8887X=ETH lane_to_serdes_map_nif_lane40.BCM8887X=rx43:tx47 phy_rx_polarity_flip_phy40.BCM8887X=1 phy_tx_polarity_flip_phy40.BCM8887X=0 -serdes_tx_taps_40.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_40.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 5 lane41 lane_to_serdes_map_nif_lane41.BCM8887X=rx42:tx43 phy_rx_polarity_flip_phy41.BCM8887X=0 phy_tx_polarity_flip_phy41.BCM8887X=0 -serdes_tx_taps_41.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_41.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 5 lane42 lane_to_serdes_map_nif_lane42.BCM8887X=rx45:tx42 phy_rx_polarity_flip_phy42.BCM8887X=1 phy_tx_polarity_flip_phy42.BCM8887X=0 -serdes_tx_taps_42.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_42.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 5 lane43 lane_to_serdes_map_nif_lane43.BCM8887X=rx47:tx41 phy_rx_polarity_flip_phy43.BCM8887X=1 phy_tx_polarity_flip_phy43.BCM8887X=1 -serdes_tx_taps_43.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_43.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 5 lane44 lane_to_serdes_map_nif_lane44.BCM8887X=rx41:tx44 phy_rx_polarity_flip_phy44.BCM8887X=1 phy_tx_polarity_flip_phy44.BCM8887X=0 -serdes_tx_taps_44.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_44.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 5 lane45 lane_to_serdes_map_nif_lane45.BCM8887X=rx40:tx45 phy_rx_polarity_flip_phy45.BCM8887X=0 phy_tx_polarity_flip_phy45.BCM8887X=1 -serdes_tx_taps_45.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_45.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 5 lane46 lane_to_serdes_map_nif_lane46.BCM8887X=rx44:tx46 phy_rx_polarity_flip_phy46.BCM8887X=0 phy_tx_polarity_flip_phy46.BCM8887X=0 -serdes_tx_taps_46.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_46.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 5 lane47 lane_to_serdes_map_nif_lane47.BCM8887X=rx46:tx40 phy_rx_polarity_flip_phy47.BCM8887X=0 phy_tx_polarity_flip_phy47.BCM8887X=1 -serdes_tx_taps_47.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_47.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # ---------------------------------------------------------------------------------------------------- @@ -352,49 +352,49 @@ tm_port_header_type_out_45.BCM8887X=ETH lane_to_serdes_map_nif_lane48.BCM8887X=rx51:tx55 phy_rx_polarity_flip_phy48.BCM8887X=1 phy_tx_polarity_flip_phy48.BCM8887X=0 -serdes_tx_taps_48.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_48.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 6 lane49 lane_to_serdes_map_nif_lane49.BCM8887X=rx50:tx51 phy_rx_polarity_flip_phy49.BCM8887X=0 phy_tx_polarity_flip_phy49.BCM8887X=0 -serdes_tx_taps_49.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_49.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 6 lane50 lane_to_serdes_map_nif_lane50.BCM8887X=rx53:tx50 phy_rx_polarity_flip_phy50.BCM8887X=1 phy_tx_polarity_flip_phy50.BCM8887X=0 -serdes_tx_taps_50.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_50.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 6 lane51 lane_to_serdes_map_nif_lane51.BCM8887X=rx55:tx49 phy_rx_polarity_flip_phy51.BCM8887X=1 phy_tx_polarity_flip_phy51.BCM8887X=1 -serdes_tx_taps_51.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_51.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 6 lane52 lane_to_serdes_map_nif_lane52.BCM8887X=rx49:tx52 phy_rx_polarity_flip_phy52.BCM8887X=1 phy_tx_polarity_flip_phy52.BCM8887X=0 -serdes_tx_taps_52.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_52.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 6 lane53 lane_to_serdes_map_nif_lane53.BCM8887X=rx48:tx53 phy_rx_polarity_flip_phy53.BCM8887X=0 phy_tx_polarity_flip_phy53.BCM8887X=1 -serdes_tx_taps_53.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_53.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 6 lane54 lane_to_serdes_map_nif_lane54.BCM8887X=rx52:tx54 phy_rx_polarity_flip_phy54.BCM8887X=0 phy_tx_polarity_flip_phy54.BCM8887X=0 -serdes_tx_taps_54.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_54.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 6 lane55 lane_to_serdes_map_nif_lane55.BCM8887X=rx54:tx48 phy_rx_polarity_flip_phy55.BCM8887X=0 phy_tx_polarity_flip_phy55.BCM8887X=1 -serdes_tx_taps_55.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_55.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # ---------------------------------------------------------------------------------------------------- @@ -409,49 +409,49 @@ tm_port_header_type_out_37.BCM8887X=ETH lane_to_serdes_map_nif_lane56.BCM8887X=rx58:tx59 phy_rx_polarity_flip_phy56.BCM8887X=1 phy_tx_polarity_flip_phy56.BCM8887X=1 -serdes_tx_taps_56.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_56.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 7 lane57 lane_to_serdes_map_nif_lane57.BCM8887X=rx59:tx61 phy_rx_polarity_flip_phy57.BCM8887X=0 phy_tx_polarity_flip_phy57.BCM8887X=1 -serdes_tx_taps_57.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_57.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 7 lane58 lane_to_serdes_map_nif_lane58.BCM8887X=rx60:tx60 phy_rx_polarity_flip_phy58.BCM8887X=0 phy_tx_polarity_flip_phy58.BCM8887X=1 -serdes_tx_taps_58.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_58.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 7 lane59 lane_to_serdes_map_nif_lane59.BCM8887X=rx62:tx56 phy_rx_polarity_flip_phy59.BCM8887X=1 phy_tx_polarity_flip_phy59.BCM8887X=1 -serdes_tx_taps_59.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_59.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 7 lane60 lane_to_serdes_map_nif_lane60.BCM8887X=rx56:tx62 phy_rx_polarity_flip_phy60.BCM8887X=0 phy_tx_polarity_flip_phy60.BCM8887X=0 -serdes_tx_taps_60.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_60.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 7 lane61 lane_to_serdes_map_nif_lane61.BCM8887X=rx57:tx58 phy_rx_polarity_flip_phy61.BCM8887X=0 phy_tx_polarity_flip_phy61.BCM8887X=0 -serdes_tx_taps_61.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_61.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 7 lane62 lane_to_serdes_map_nif_lane62.BCM8887X=rx63:tx63 phy_rx_polarity_flip_phy62.BCM8887X=0 phy_tx_polarity_flip_phy62.BCM8887X=1 -serdes_tx_taps_62.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_62.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 7 lane63 lane_to_serdes_map_nif_lane63.BCM8887X=rx61:tx57 phy_rx_polarity_flip_phy63.BCM8887X=0 phy_tx_polarity_flip_phy63.BCM8887X=1 -serdes_tx_taps_63.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_63.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # ---------------------------------------------------------------------------------------------------- @@ -466,49 +466,49 @@ tm_port_header_type_out_133.BCM8887X=ETH lane_to_serdes_map_nif_lane64.BCM8887X=rx67:tx71 phy_rx_polarity_flip_phy64.BCM8887X=0 phy_tx_polarity_flip_phy64.BCM8887X=0 -serdes_tx_taps_64.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_64.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 8 lane65 lane_to_serdes_map_nif_lane65.BCM8887X=rx66:tx65 phy_rx_polarity_flip_phy65.BCM8887X=0 phy_tx_polarity_flip_phy65.BCM8887X=1 -serdes_tx_taps_65.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_65.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 8 lane66 lane_to_serdes_map_nif_lane66.BCM8887X=rx70:tx70 phy_rx_polarity_flip_phy66.BCM8887X=1 phy_tx_polarity_flip_phy66.BCM8887X=1 -serdes_tx_taps_66.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_66.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 8 lane67 lane_to_serdes_map_nif_lane67.BCM8887X=rx68:tx66 phy_rx_polarity_flip_phy67.BCM8887X=1 phy_tx_polarity_flip_phy67.BCM8887X=0 -serdes_tx_taps_67.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_67.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 8 lane68 lane_to_serdes_map_nif_lane68.BCM8887X=rx69:tx67 phy_rx_polarity_flip_phy68.BCM8887X=0 phy_tx_polarity_flip_phy68.BCM8887X=0 -serdes_tx_taps_68.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_68.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 8 lane69 lane_to_serdes_map_nif_lane69.BCM8887X=rx71:tx69 phy_rx_polarity_flip_phy69.BCM8887X=1 phy_tx_polarity_flip_phy69.BCM8887X=1 -serdes_tx_taps_69.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_69.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 8 lane70 lane_to_serdes_map_nif_lane70.BCM8887X=rx65:tx68 phy_rx_polarity_flip_phy70.BCM8887X=0 phy_tx_polarity_flip_phy70.BCM8887X=0 -serdes_tx_taps_70.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_70.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 8 lane71 lane_to_serdes_map_nif_lane71.BCM8887X=rx64:tx64 phy_rx_polarity_flip_phy71.BCM8887X=1 phy_tx_polarity_flip_phy71.BCM8887X=1 -serdes_tx_taps_71.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_71.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # ---------------------------------------------------------------------------------------------------- @@ -523,49 +523,49 @@ tm_port_header_type_out_141.BCM8887X=ETH lane_to_serdes_map_nif_lane72.BCM8887X=rx75:tx79 phy_rx_polarity_flip_phy72.BCM8887X=0 phy_tx_polarity_flip_phy72.BCM8887X=0 -serdes_tx_taps_72.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_72.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 9 lane73 lane_to_serdes_map_nif_lane73.BCM8887X=rx74:tx73 phy_rx_polarity_flip_phy73.BCM8887X=0 phy_tx_polarity_flip_phy73.BCM8887X=1 -serdes_tx_taps_73.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_73.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 9 lane74 lane_to_serdes_map_nif_lane74.BCM8887X=rx78:tx78 phy_rx_polarity_flip_phy74.BCM8887X=1 phy_tx_polarity_flip_phy74.BCM8887X=1 -serdes_tx_taps_74.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_74.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 9 lane75 lane_to_serdes_map_nif_lane75.BCM8887X=rx76:tx74 phy_rx_polarity_flip_phy75.BCM8887X=1 phy_tx_polarity_flip_phy75.BCM8887X=0 -serdes_tx_taps_75.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_75.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 9 lane76 lane_to_serdes_map_nif_lane76.BCM8887X=rx77:tx75 phy_rx_polarity_flip_phy76.BCM8887X=0 phy_tx_polarity_flip_phy76.BCM8887X=0 -serdes_tx_taps_76.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_76.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 9 lane77 lane_to_serdes_map_nif_lane77.BCM8887X=rx79:tx77 phy_rx_polarity_flip_phy77.BCM8887X=1 phy_tx_polarity_flip_phy77.BCM8887X=1 -serdes_tx_taps_77.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_77.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 9 lane78 lane_to_serdes_map_nif_lane78.BCM8887X=rx73:tx76 phy_rx_polarity_flip_phy78.BCM8887X=0 phy_tx_polarity_flip_phy78.BCM8887X=0 -serdes_tx_taps_78.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_78.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 9 lane79 lane_to_serdes_map_nif_lane79.BCM8887X=rx72:tx72 phy_rx_polarity_flip_phy79.BCM8887X=1 phy_tx_polarity_flip_phy79.BCM8887X=1 -serdes_tx_taps_79.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_79.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # ---------------------------------------------------------------------------------------------------- @@ -580,49 +580,49 @@ tm_port_header_type_out_149.BCM8887X=ETH lane_to_serdes_map_nif_lane80.BCM8887X=rx83:tx87 phy_rx_polarity_flip_phy80.BCM8887X=0 phy_tx_polarity_flip_phy80.BCM8887X=0 -serdes_tx_taps_80.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_80.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 10 lane81 lane_to_serdes_map_nif_lane81.BCM8887X=rx82:tx81 phy_rx_polarity_flip_phy81.BCM8887X=0 phy_tx_polarity_flip_phy81.BCM8887X=1 -serdes_tx_taps_81.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_81.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 10 lane82 lane_to_serdes_map_nif_lane82.BCM8887X=rx86:tx86 phy_rx_polarity_flip_phy82.BCM8887X=1 phy_tx_polarity_flip_phy82.BCM8887X=1 -serdes_tx_taps_82.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_82.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 10 lane83 lane_to_serdes_map_nif_lane83.BCM8887X=rx84:tx82 phy_rx_polarity_flip_phy83.BCM8887X=1 phy_tx_polarity_flip_phy83.BCM8887X=0 -serdes_tx_taps_83.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_83.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 10 lane84 lane_to_serdes_map_nif_lane84.BCM8887X=rx85:tx83 phy_rx_polarity_flip_phy84.BCM8887X=0 phy_tx_polarity_flip_phy84.BCM8887X=0 -serdes_tx_taps_84.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_84.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 10 lane85 lane_to_serdes_map_nif_lane85.BCM8887X=rx87:tx85 phy_rx_polarity_flip_phy85.BCM8887X=1 phy_tx_polarity_flip_phy85.BCM8887X=1 -serdes_tx_taps_85.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_85.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 10 lane86 lane_to_serdes_map_nif_lane86.BCM8887X=rx81:tx84 phy_rx_polarity_flip_phy86.BCM8887X=0 phy_tx_polarity_flip_phy86.BCM8887X=0 -serdes_tx_taps_86.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_86.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 10 lane87 lane_to_serdes_map_nif_lane87.BCM8887X=rx80:tx80 phy_rx_polarity_flip_phy87.BCM8887X=1 phy_tx_polarity_flip_phy87.BCM8887X=1 -serdes_tx_taps_87.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_87.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # ---------------------------------------------------------------------------------------------------- @@ -637,49 +637,49 @@ tm_port_header_type_out_157.BCM8887X=ETH lane_to_serdes_map_nif_lane88.BCM8887X=rx91:tx95 phy_rx_polarity_flip_phy88.BCM8887X=0 phy_tx_polarity_flip_phy88.BCM8887X=0 -serdes_tx_taps_88.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_88.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 11 lane89 lane_to_serdes_map_nif_lane89.BCM8887X=rx90:tx89 phy_rx_polarity_flip_phy89.BCM8887X=0 phy_tx_polarity_flip_phy89.BCM8887X=1 -serdes_tx_taps_89.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_89.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 11 lane90 lane_to_serdes_map_nif_lane90.BCM8887X=rx94:tx94 phy_rx_polarity_flip_phy90.BCM8887X=1 phy_tx_polarity_flip_phy90.BCM8887X=1 -serdes_tx_taps_90.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_90.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 11 lane91 lane_to_serdes_map_nif_lane91.BCM8887X=rx92:tx90 phy_rx_polarity_flip_phy91.BCM8887X=1 phy_tx_polarity_flip_phy91.BCM8887X=0 -serdes_tx_taps_91.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_91.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 11 lane92 lane_to_serdes_map_nif_lane92.BCM8887X=rx93:tx91 phy_rx_polarity_flip_phy92.BCM8887X=0 phy_tx_polarity_flip_phy92.BCM8887X=0 -serdes_tx_taps_92.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_92.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 11 lane93 lane_to_serdes_map_nif_lane93.BCM8887X=rx95:tx93 phy_rx_polarity_flip_phy93.BCM8887X=1 phy_tx_polarity_flip_phy93.BCM8887X=1 -serdes_tx_taps_93.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_93.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 11 lane94 lane_to_serdes_map_nif_lane94.BCM8887X=rx89:tx92 phy_rx_polarity_flip_phy94.BCM8887X=0 phy_tx_polarity_flip_phy94.BCM8887X=0 -serdes_tx_taps_94.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_94.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 11 lane95 lane_to_serdes_map_nif_lane95.BCM8887X=rx88:tx88 phy_rx_polarity_flip_phy95.BCM8887X=1 phy_tx_polarity_flip_phy95.BCM8887X=1 -serdes_tx_taps_95.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_95.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # ---------------------------------------------------------------------------------------------------- @@ -694,49 +694,49 @@ tm_port_header_type_out_5.BCM8887X=ETH lane_to_serdes_map_nif_lane96.BCM8887X=rx100:tx103 phy_rx_polarity_flip_phy96.BCM8887X=1 phy_tx_polarity_flip_phy96.BCM8887X=0 -serdes_tx_taps_96.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_96.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 12 lane97 lane_to_serdes_map_nif_lane97.BCM8887X=rx96:tx98 phy_rx_polarity_flip_phy97.BCM8887X=1 phy_tx_polarity_flip_phy97.BCM8887X=1 -serdes_tx_taps_97.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_97.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 12 lane98 lane_to_serdes_map_nif_lane98.BCM8887X=rx99:tx99 phy_rx_polarity_flip_phy98.BCM8887X=0 phy_tx_polarity_flip_phy98.BCM8887X=0 -serdes_tx_taps_98.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_98.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 12 lane99 lane_to_serdes_map_nif_lane99.BCM8887X=rx101:tx97 phy_rx_polarity_flip_phy99.BCM8887X=0 phy_tx_polarity_flip_phy99.BCM8887X=0 -serdes_tx_taps_99.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_99.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 12 lane100 lane_to_serdes_map_nif_lane100.BCM8887X=rx98:tx100 phy_rx_polarity_flip_phy100.BCM8887X=1 phy_tx_polarity_flip_phy100.BCM8887X=0 -serdes_tx_taps_100.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_100.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 12 lane101 lane_to_serdes_map_nif_lane101.BCM8887X=rx103:tx96 phy_rx_polarity_flip_phy101.BCM8887X=1 phy_tx_polarity_flip_phy101.BCM8887X=0 -serdes_tx_taps_101.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_101.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 12 lane102 lane_to_serdes_map_nif_lane102.BCM8887X=rx102:tx101 phy_rx_polarity_flip_phy102.BCM8887X=0 phy_tx_polarity_flip_phy102.BCM8887X=1 -serdes_tx_taps_102.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_102.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 12 lane103 lane_to_serdes_map_nif_lane103.BCM8887X=rx97:tx102 phy_rx_polarity_flip_phy103.BCM8887X=1 phy_tx_polarity_flip_phy103.BCM8887X=1 -serdes_tx_taps_103.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_103.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # ---------------------------------------------------------------------------------------------------- @@ -751,49 +751,49 @@ tm_port_header_type_out_13.BCM8887X=ETH lane_to_serdes_map_nif_lane104.BCM8887X=rx107:tx108 phy_rx_polarity_flip_phy104.BCM8887X=1 phy_tx_polarity_flip_phy104.BCM8887X=0 -serdes_tx_taps_104.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_104.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 13 lane105 lane_to_serdes_map_nif_lane105.BCM8887X=rx106:tx107 phy_rx_polarity_flip_phy105.BCM8887X=0 phy_tx_polarity_flip_phy105.BCM8887X=1 -serdes_tx_taps_105.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_105.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 13 lane106 lane_to_serdes_map_nif_lane106.BCM8887X=rx110:tx110 phy_rx_polarity_flip_phy106.BCM8887X=0 phy_tx_polarity_flip_phy106.BCM8887X=0 -serdes_tx_taps_106.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_106.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 13 lane107 lane_to_serdes_map_nif_lane107.BCM8887X=rx108:tx109 phy_rx_polarity_flip_phy107.BCM8887X=0 phy_tx_polarity_flip_phy107.BCM8887X=1 -serdes_tx_taps_107.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_107.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 13 lane108 lane_to_serdes_map_nif_lane108.BCM8887X=rx105:tx111 phy_rx_polarity_flip_phy108.BCM8887X=1 phy_tx_polarity_flip_phy108.BCM8887X=1 -serdes_tx_taps_108.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_108.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 13 lane109 lane_to_serdes_map_nif_lane109.BCM8887X=rx104:tx104 phy_rx_polarity_flip_phy109.BCM8887X=0 phy_tx_polarity_flip_phy109.BCM8887X=0 -serdes_tx_taps_109.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_109.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 13 lane110 lane_to_serdes_map_nif_lane110.BCM8887X=rx111:tx106 phy_rx_polarity_flip_phy110.BCM8887X=1 phy_tx_polarity_flip_phy110.BCM8887X=1 -serdes_tx_taps_110.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_110.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 13 lane111 lane_to_serdes_map_nif_lane111.BCM8887X=rx109:tx105 phy_rx_polarity_flip_phy111.BCM8887X=1 phy_tx_polarity_flip_phy111.BCM8887X=1 -serdes_tx_taps_111.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_111.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # ---------------------------------------------------------------------------------------------------- @@ -808,49 +808,49 @@ tm_port_header_type_out_21.BCM8887X=ETH lane_to_serdes_map_nif_lane112.BCM8887X=rx115:tx116 phy_rx_polarity_flip_phy112.BCM8887X=1 phy_tx_polarity_flip_phy112.BCM8887X=0 -serdes_tx_taps_112.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_112.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 14 lane113 lane_to_serdes_map_nif_lane113.BCM8887X=rx114:tx115 phy_rx_polarity_flip_phy113.BCM8887X=1 phy_tx_polarity_flip_phy113.BCM8887X=1 -serdes_tx_taps_113.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_113.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 14 lane114 lane_to_serdes_map_nif_lane114.BCM8887X=rx118:tx118 phy_rx_polarity_flip_phy114.BCM8887X=0 phy_tx_polarity_flip_phy114.BCM8887X=0 -serdes_tx_taps_114.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_114.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 14 lane115 lane_to_serdes_map_nif_lane115.BCM8887X=rx116:tx117 phy_rx_polarity_flip_phy115.BCM8887X=0 phy_tx_polarity_flip_phy115.BCM8887X=1 -serdes_tx_taps_115.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_115.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 14 lane116 lane_to_serdes_map_nif_lane116.BCM8887X=rx113:tx119 phy_rx_polarity_flip_phy116.BCM8887X=1 phy_tx_polarity_flip_phy116.BCM8887X=1 -serdes_tx_taps_116.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_116.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 14 lane117 lane_to_serdes_map_nif_lane117.BCM8887X=rx112:tx112 phy_rx_polarity_flip_phy117.BCM8887X=0 phy_tx_polarity_flip_phy117.BCM8887X=0 -serdes_tx_taps_117.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_117.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 14 lane118 lane_to_serdes_map_nif_lane118.BCM8887X=rx119:tx114 phy_rx_polarity_flip_phy118.BCM8887X=1 phy_tx_polarity_flip_phy118.BCM8887X=1 -serdes_tx_taps_118.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_118.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 14 lane119 lane_to_serdes_map_nif_lane119.BCM8887X=rx117:tx113 phy_rx_polarity_flip_phy119.BCM8887X=1 phy_tx_polarity_flip_phy119.BCM8887X=1 -serdes_tx_taps_119.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_119.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # ---------------------------------------------------------------------------------------------------- @@ -865,49 +865,49 @@ tm_port_header_type_out_29.BCM8887X=ETH lane_to_serdes_map_nif_lane120.BCM8887X=rx123:tx124 phy_rx_polarity_flip_phy120.BCM8887X=1 phy_tx_polarity_flip_phy120.BCM8887X=0 -serdes_tx_taps_120.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_120.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 15 lane121 lane_to_serdes_map_nif_lane121.BCM8887X=rx122:tx123 phy_rx_polarity_flip_phy121.BCM8887X=1 phy_tx_polarity_flip_phy121.BCM8887X=1 -serdes_tx_taps_121.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_121.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 15 lane122 lane_to_serdes_map_nif_lane122.BCM8887X=rx126:tx126 phy_rx_polarity_flip_phy122.BCM8887X=0 phy_tx_polarity_flip_phy122.BCM8887X=0 -serdes_tx_taps_122.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_122.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 15 lane123 lane_to_serdes_map_nif_lane123.BCM8887X=rx124:tx125 phy_rx_polarity_flip_phy123.BCM8887X=0 phy_tx_polarity_flip_phy123.BCM8887X=1 -serdes_tx_taps_123.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_123.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 15 lane124 lane_to_serdes_map_nif_lane124.BCM8887X=rx121:tx127 phy_rx_polarity_flip_phy124.BCM8887X=1 phy_tx_polarity_flip_phy124.BCM8887X=1 -serdes_tx_taps_124.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_124.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 15 lane125 lane_to_serdes_map_nif_lane125.BCM8887X=rx120:tx120 phy_rx_polarity_flip_phy125.BCM8887X=0 phy_tx_polarity_flip_phy125.BCM8887X=0 -serdes_tx_taps_125.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_125.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 15 lane126 lane_to_serdes_map_nif_lane126.BCM8887X=rx127:tx122 phy_rx_polarity_flip_phy126.BCM8887X=1 phy_tx_polarity_flip_phy126.BCM8887X=1 -serdes_tx_taps_126.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_126.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 15 lane127 lane_to_serdes_map_nif_lane127.BCM8887X=rx125:tx121 phy_rx_polarity_flip_phy127.BCM8887X=1 phy_tx_polarity_flip_phy127.BCM8887X=1 -serdes_tx_taps_127.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_127.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # ---------------------------------------------------------------------------------------------------- @@ -922,49 +922,49 @@ tm_port_header_type_out_69.BCM8887X=ETH lane_to_serdes_map_nif_lane128.BCM8887X=rx131:tx135 phy_rx_polarity_flip_phy128.BCM8887X=0 phy_tx_polarity_flip_phy128.BCM8887X=0 -serdes_tx_taps_128.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_128.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 16 lane129 lane_to_serdes_map_nif_lane129.BCM8887X=rx130:tx131 phy_rx_polarity_flip_phy129.BCM8887X=0 phy_tx_polarity_flip_phy129.BCM8887X=1 -serdes_tx_taps_129.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_129.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 16 lane130 lane_to_serdes_map_nif_lane130.BCM8887X=rx129:tx129 phy_rx_polarity_flip_phy130.BCM8887X=1 phy_tx_polarity_flip_phy130.BCM8887X=1 -serdes_tx_taps_130.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_130.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 16 lane131 lane_to_serdes_map_nif_lane131.BCM8887X=rx128:tx130 phy_rx_polarity_flip_phy131.BCM8887X=0 phy_tx_polarity_flip_phy131.BCM8887X=1 -serdes_tx_taps_131.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_131.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 16 lane132 lane_to_serdes_map_nif_lane132.BCM8887X=rx133:tx132 phy_rx_polarity_flip_phy132.BCM8887X=1 phy_tx_polarity_flip_phy132.BCM8887X=1 -serdes_tx_taps_132.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_132.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 16 lane133 lane_to_serdes_map_nif_lane133.BCM8887X=rx135:tx133 phy_rx_polarity_flip_phy133.BCM8887X=0 phy_tx_polarity_flip_phy133.BCM8887X=0 -serdes_tx_taps_133.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_133.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 16 lane134 lane_to_serdes_map_nif_lane134.BCM8887X=rx132:tx128 phy_rx_polarity_flip_phy134.BCM8887X=1 phy_tx_polarity_flip_phy134.BCM8887X=1 -serdes_tx_taps_134.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_134.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 16 lane135 lane_to_serdes_map_nif_lane135.BCM8887X=rx134:tx134 phy_rx_polarity_flip_phy135.BCM8887X=0 phy_tx_polarity_flip_phy135.BCM8887X=1 -serdes_tx_taps_135.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_135.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # ---------------------------------------------------------------------------------------------------- @@ -979,49 +979,49 @@ tm_port_header_type_out_77.BCM8887X=ETH lane_to_serdes_map_nif_lane136.BCM8887X=rx139:tx143 phy_rx_polarity_flip_phy136.BCM8887X=0 phy_tx_polarity_flip_phy136.BCM8887X=0 -serdes_tx_taps_136.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_136.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 17 lane137 lane_to_serdes_map_nif_lane137.BCM8887X=rx138:tx139 phy_rx_polarity_flip_phy137.BCM8887X=0 phy_tx_polarity_flip_phy137.BCM8887X=1 -serdes_tx_taps_137.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_137.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 17 lane138 lane_to_serdes_map_nif_lane138.BCM8887X=rx137:tx137 phy_rx_polarity_flip_phy138.BCM8887X=1 phy_tx_polarity_flip_phy138.BCM8887X=1 -serdes_tx_taps_138.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_138.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 17 lane139 lane_to_serdes_map_nif_lane139.BCM8887X=rx136:tx138 phy_rx_polarity_flip_phy139.BCM8887X=1 phy_tx_polarity_flip_phy139.BCM8887X=1 -serdes_tx_taps_139.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_139.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 17 lane140 lane_to_serdes_map_nif_lane140.BCM8887X=rx141:tx140 phy_rx_polarity_flip_phy140.BCM8887X=1 phy_tx_polarity_flip_phy140.BCM8887X=1 -serdes_tx_taps_140.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_140.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 17 lane141 lane_to_serdes_map_nif_lane141.BCM8887X=rx143:tx141 phy_rx_polarity_flip_phy141.BCM8887X=0 phy_tx_polarity_flip_phy141.BCM8887X=0 -serdes_tx_taps_141.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_141.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 17 lane142 lane_to_serdes_map_nif_lane142.BCM8887X=rx140:tx136 phy_rx_polarity_flip_phy142.BCM8887X=1 phy_tx_polarity_flip_phy142.BCM8887X=1 -serdes_tx_taps_142.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_142.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 17 lane143 lane_to_serdes_map_nif_lane143.BCM8887X=rx142:tx142 phy_rx_polarity_flip_phy143.BCM8887X=0 phy_tx_polarity_flip_phy143.BCM8887X=1 -serdes_tx_taps_143.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_143.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # ---------------------------------------------------------------------------------------------------- @@ -1036,49 +1036,49 @@ tm_port_header_type_out_85.BCM8887X=ETH lane_to_serdes_map_nif_lane144.BCM8887X=rx147:tx151 phy_rx_polarity_flip_phy144.BCM8887X=0 phy_tx_polarity_flip_phy144.BCM8887X=0 -serdes_tx_taps_144.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_144.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 18 lane145 lane_to_serdes_map_nif_lane145.BCM8887X=rx146:tx147 phy_rx_polarity_flip_phy145.BCM8887X=0 phy_tx_polarity_flip_phy145.BCM8887X=1 -serdes_tx_taps_145.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_145.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 18 lane146 lane_to_serdes_map_nif_lane146.BCM8887X=rx145:tx145 phy_rx_polarity_flip_phy146.BCM8887X=1 phy_tx_polarity_flip_phy146.BCM8887X=1 -serdes_tx_taps_146.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_146.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 18 lane147 lane_to_serdes_map_nif_lane147.BCM8887X=rx144:tx146 phy_rx_polarity_flip_phy147.BCM8887X=0 phy_tx_polarity_flip_phy147.BCM8887X=1 -serdes_tx_taps_147.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_147.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 18 lane148 lane_to_serdes_map_nif_lane148.BCM8887X=rx149:tx148 phy_rx_polarity_flip_phy148.BCM8887X=1 phy_tx_polarity_flip_phy148.BCM8887X=1 -serdes_tx_taps_148.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_148.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 18 lane149 lane_to_serdes_map_nif_lane149.BCM8887X=rx151:tx149 phy_rx_polarity_flip_phy149.BCM8887X=0 phy_tx_polarity_flip_phy149.BCM8887X=0 -serdes_tx_taps_149.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_149.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 18 lane150 lane_to_serdes_map_nif_lane150.BCM8887X=rx148:tx144 phy_rx_polarity_flip_phy150.BCM8887X=1 phy_tx_polarity_flip_phy150.BCM8887X=1 -serdes_tx_taps_150.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_150.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 18 lane151 lane_to_serdes_map_nif_lane151.BCM8887X=rx150:tx150 phy_rx_polarity_flip_phy151.BCM8887X=0 phy_tx_polarity_flip_phy151.BCM8887X=1 -serdes_tx_taps_151.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_151.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # ---------------------------------------------------------------------------------------------------- @@ -1093,49 +1093,49 @@ tm_port_header_type_out_93.BCM8887X=ETH lane_to_serdes_map_nif_lane152.BCM8887X=rx155:tx156 phy_rx_polarity_flip_phy152.BCM8887X=0 phy_tx_polarity_flip_phy152.BCM8887X=1 -serdes_tx_taps_152.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_152.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 19 lane153 lane_to_serdes_map_nif_lane153.BCM8887X=rx154:tx155 phy_rx_polarity_flip_phy153.BCM8887X=0 phy_tx_polarity_flip_phy153.BCM8887X=0 -serdes_tx_taps_153.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_153.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 19 lane154 lane_to_serdes_map_nif_lane154.BCM8887X=rx158:tx158 phy_rx_polarity_flip_phy154.BCM8887X=1 phy_tx_polarity_flip_phy154.BCM8887X=1 -serdes_tx_taps_154.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_154.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 19 lane155 lane_to_serdes_map_nif_lane155.BCM8887X=rx156:tx157 phy_rx_polarity_flip_phy155.BCM8887X=1 phy_tx_polarity_flip_phy155.BCM8887X=0 -serdes_tx_taps_155.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_155.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 19 lane156 lane_to_serdes_map_nif_lane156.BCM8887X=rx153:tx159 phy_rx_polarity_flip_phy156.BCM8887X=0 phy_tx_polarity_flip_phy156.BCM8887X=0 -serdes_tx_taps_156.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_156.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 19 lane157 lane_to_serdes_map_nif_lane157.BCM8887X=rx152:tx152 phy_rx_polarity_flip_phy157.BCM8887X=1 phy_tx_polarity_flip_phy157.BCM8887X=1 -serdes_tx_taps_157.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_157.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 19 lane158 lane_to_serdes_map_nif_lane158.BCM8887X=rx159:tx154 phy_rx_polarity_flip_phy158.BCM8887X=0 phy_tx_polarity_flip_phy158.BCM8887X=0 -serdes_tx_taps_158.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_158.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 19 lane159 lane_to_serdes_map_nif_lane159.BCM8887X=rx157:tx153 phy_rx_polarity_flip_phy159.BCM8887X=0 phy_tx_polarity_flip_phy159.BCM8887X=0 -serdes_tx_taps_159.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_159.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # ---------------------------------------------------------------------------------------------------- @@ -1150,49 +1150,49 @@ tm_port_header_type_out_197.BCM8887X=ETH lane_to_serdes_map_nif_lane160.BCM8887X=rx166:tx167 phy_rx_polarity_flip_phy160.BCM8887X=0 phy_tx_polarity_flip_phy160.BCM8887X=1 -serdes_tx_taps_160.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_160.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 20 lane161 lane_to_serdes_map_nif_lane161.BCM8887X=rx164:tx163 phy_rx_polarity_flip_phy161.BCM8887X=1 phy_tx_polarity_flip_phy161.BCM8887X=0 -serdes_tx_taps_161.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_161.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 20 lane162 lane_to_serdes_map_nif_lane162.BCM8887X=rx160:tx162 phy_rx_polarity_flip_phy162.BCM8887X=0 phy_tx_polarity_flip_phy162.BCM8887X=1 -serdes_tx_taps_162.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_162.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 20 lane163 lane_to_serdes_map_nif_lane163.BCM8887X=rx161:tx161 phy_rx_polarity_flip_phy163.BCM8887X=0 phy_tx_polarity_flip_phy163.BCM8887X=1 -serdes_tx_taps_163.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_163.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 20 lane164 lane_to_serdes_map_nif_lane164.BCM8887X=rx162:tx166 phy_rx_polarity_flip_phy164.BCM8887X=0 phy_tx_polarity_flip_phy164.BCM8887X=1 -serdes_tx_taps_164.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_164.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 20 lane165 lane_to_serdes_map_nif_lane165.BCM8887X=rx163:tx160 phy_rx_polarity_flip_phy165.BCM8887X=0 phy_tx_polarity_flip_phy165.BCM8887X=1 -serdes_tx_taps_165.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_165.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 20 lane166 lane_to_serdes_map_nif_lane166.BCM8887X=rx167:tx164 phy_rx_polarity_flip_phy166.BCM8887X=1 phy_tx_polarity_flip_phy166.BCM8887X=1 -serdes_tx_taps_166.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_166.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 20 lane167 lane_to_serdes_map_nif_lane167.BCM8887X=rx165:tx165 phy_rx_polarity_flip_phy167.BCM8887X=0 phy_tx_polarity_flip_phy167.BCM8887X=1 -serdes_tx_taps_167.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_167.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # ---------------------------------------------------------------------------------------------------- @@ -1207,49 +1207,49 @@ tm_port_header_type_out_205.BCM8887X=ETH lane_to_serdes_map_nif_lane168.BCM8887X=rx170:tx174 phy_rx_polarity_flip_phy168.BCM8887X=0 phy_tx_polarity_flip_phy168.BCM8887X=1 -serdes_tx_taps_168.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_168.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 21 lane169 lane_to_serdes_map_nif_lane169.BCM8887X=rx171:tx168 phy_rx_polarity_flip_phy169.BCM8887X=0 phy_tx_polarity_flip_phy169.BCM8887X=1 -serdes_tx_taps_169.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_169.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 21 lane170 lane_to_serdes_map_nif_lane170.BCM8887X=rx175:tx172 phy_rx_polarity_flip_phy170.BCM8887X=1 phy_tx_polarity_flip_phy170.BCM8887X=1 -serdes_tx_taps_170.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_170.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 21 lane171 lane_to_serdes_map_nif_lane171.BCM8887X=rx173:tx173 phy_rx_polarity_flip_phy171.BCM8887X=0 phy_tx_polarity_flip_phy171.BCM8887X=1 -serdes_tx_taps_171.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_171.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 21 lane172 lane_to_serdes_map_nif_lane172.BCM8887X=rx174:tx175 phy_rx_polarity_flip_phy172.BCM8887X=0 phy_tx_polarity_flip_phy172.BCM8887X=1 -serdes_tx_taps_172.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_172.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 21 lane173 lane_to_serdes_map_nif_lane173.BCM8887X=rx172:tx171 phy_rx_polarity_flip_phy173.BCM8887X=1 phy_tx_polarity_flip_phy173.BCM8887X=0 -serdes_tx_taps_173.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_173.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 21 lane174 lane_to_serdes_map_nif_lane174.BCM8887X=rx168:tx170 phy_rx_polarity_flip_phy174.BCM8887X=0 phy_tx_polarity_flip_phy174.BCM8887X=1 -serdes_tx_taps_174.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_174.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 21 lane175 lane_to_serdes_map_nif_lane175.BCM8887X=rx169:tx169 phy_rx_polarity_flip_phy175.BCM8887X=0 phy_tx_polarity_flip_phy175.BCM8887X=1 -serdes_tx_taps_175.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_175.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # ---------------------------------------------------------------------------------------------------- @@ -1264,49 +1264,49 @@ tm_port_header_type_out_213.BCM8887X=ETH lane_to_serdes_map_nif_lane176.BCM8887X=rx178:tx182 phy_rx_polarity_flip_phy176.BCM8887X=0 phy_tx_polarity_flip_phy176.BCM8887X=1 -serdes_tx_taps_176.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_176.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 22 lane177 lane_to_serdes_map_nif_lane177.BCM8887X=rx179:tx176 phy_rx_polarity_flip_phy177.BCM8887X=0 phy_tx_polarity_flip_phy177.BCM8887X=1 -serdes_tx_taps_177.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_177.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 22 lane178 lane_to_serdes_map_nif_lane178.BCM8887X=rx183:tx180 phy_rx_polarity_flip_phy178.BCM8887X=1 phy_tx_polarity_flip_phy178.BCM8887X=1 -serdes_tx_taps_178.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_178.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 22 lane179 lane_to_serdes_map_nif_lane179.BCM8887X=rx181:tx181 phy_rx_polarity_flip_phy179.BCM8887X=0 phy_tx_polarity_flip_phy179.BCM8887X=1 -serdes_tx_taps_179.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_179.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 22 lane180 lane_to_serdes_map_nif_lane180.BCM8887X=rx182:tx183 phy_rx_polarity_flip_phy180.BCM8887X=0 phy_tx_polarity_flip_phy180.BCM8887X=1 -serdes_tx_taps_180.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_180.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 22 lane181 lane_to_serdes_map_nif_lane181.BCM8887X=rx180:tx179 phy_rx_polarity_flip_phy181.BCM8887X=1 phy_tx_polarity_flip_phy181.BCM8887X=0 -serdes_tx_taps_181.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_181.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 22 lane182 lane_to_serdes_map_nif_lane182.BCM8887X=rx176:tx178 phy_rx_polarity_flip_phy182.BCM8887X=0 phy_tx_polarity_flip_phy182.BCM8887X=1 -serdes_tx_taps_182.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_182.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 22 lane183 lane_to_serdes_map_nif_lane183.BCM8887X=rx177:tx177 phy_rx_polarity_flip_phy183.BCM8887X=0 phy_tx_polarity_flip_phy183.BCM8887X=1 -serdes_tx_taps_183.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_183.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # ---------------------------------------------------------------------------------------------------- @@ -1321,49 +1321,49 @@ tm_port_header_type_out_221.BCM8887X=ETH lane_to_serdes_map_nif_lane184.BCM8887X=rx187:tx191 phy_rx_polarity_flip_phy184.BCM8887X=1 phy_tx_polarity_flip_phy184.BCM8887X=1 -serdes_tx_taps_184.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_184.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 23 lane185 lane_to_serdes_map_nif_lane185.BCM8887X=rx186:tx185 phy_rx_polarity_flip_phy185.BCM8887X=1 phy_tx_polarity_flip_phy185.BCM8887X=0 -serdes_tx_taps_185.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_185.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 23 lane186 lane_to_serdes_map_nif_lane186.BCM8887X=rx190:tx190 phy_rx_polarity_flip_phy186.BCM8887X=0 phy_tx_polarity_flip_phy186.BCM8887X=0 -serdes_tx_taps_186.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_186.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 23 lane187 lane_to_serdes_map_nif_lane187.BCM8887X=rx188:tx186 phy_rx_polarity_flip_phy187.BCM8887X=0 phy_tx_polarity_flip_phy187.BCM8887X=1 -serdes_tx_taps_187.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_187.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 23 lane188 lane_to_serdes_map_nif_lane188.BCM8887X=rx189:tx187 phy_rx_polarity_flip_phy188.BCM8887X=1 phy_tx_polarity_flip_phy188.BCM8887X=1 -serdes_tx_taps_188.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_188.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 23 lane189 lane_to_serdes_map_nif_lane189.BCM8887X=rx191:tx189 phy_rx_polarity_flip_phy189.BCM8887X=0 phy_tx_polarity_flip_phy189.BCM8887X=0 -serdes_tx_taps_189.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_189.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 23 lane190 lane_to_serdes_map_nif_lane190.BCM8887X=rx185:tx188 phy_rx_polarity_flip_phy190.BCM8887X=1 phy_tx_polarity_flip_phy190.BCM8887X=1 -serdes_tx_taps_190.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_190.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 23 lane191 lane_to_serdes_map_nif_lane191.BCM8887X=rx184:tx184 phy_rx_polarity_flip_phy191.BCM8887X=0 phy_tx_polarity_flip_phy191.BCM8887X=0 -serdes_tx_taps_191.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_191.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # ---------------------------------------------------------------------------------------------------- @@ -1378,49 +1378,49 @@ tm_port_header_type_out_125.BCM8887X=ETH lane_to_serdes_map_nif_lane192.BCM8887X=rx194:tx195 phy_rx_polarity_flip_phy192.BCM8887X=0 phy_tx_polarity_flip_phy192.BCM8887X=0 -serdes_tx_taps_192.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_192.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 24 lane193 lane_to_serdes_map_nif_lane193.BCM8887X=rx195:tx197 phy_rx_polarity_flip_phy193.BCM8887X=1 phy_tx_polarity_flip_phy193.BCM8887X=0 -serdes_tx_taps_193.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_193.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 24 lane194 lane_to_serdes_map_nif_lane194.BCM8887X=rx196:tx196 phy_rx_polarity_flip_phy194.BCM8887X=1 phy_tx_polarity_flip_phy194.BCM8887X=0 -serdes_tx_taps_194.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_194.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 24 lane195 lane_to_serdes_map_nif_lane195.BCM8887X=rx198:tx192 phy_rx_polarity_flip_phy195.BCM8887X=0 phy_tx_polarity_flip_phy195.BCM8887X=0 -serdes_tx_taps_195.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_195.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 24 lane196 lane_to_serdes_map_nif_lane196.BCM8887X=rx192:tx198 phy_rx_polarity_flip_phy196.BCM8887X=1 phy_tx_polarity_flip_phy196.BCM8887X=1 -serdes_tx_taps_196.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_196.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 24 lane197 lane_to_serdes_map_nif_lane197.BCM8887X=rx193:tx194 phy_rx_polarity_flip_phy197.BCM8887X=0 phy_tx_polarity_flip_phy197.BCM8887X=1 -serdes_tx_taps_197.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_197.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 24 lane198 lane_to_serdes_map_nif_lane198.BCM8887X=rx199:tx199 phy_rx_polarity_flip_phy198.BCM8887X=1 phy_tx_polarity_flip_phy198.BCM8887X=0 -serdes_tx_taps_198.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_198.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 24 lane199 lane_to_serdes_map_nif_lane199.BCM8887X=rx197:tx193 phy_rx_polarity_flip_phy199.BCM8887X=1 phy_tx_polarity_flip_phy199.BCM8887X=0 -serdes_tx_taps_199.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_199.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # ---------------------------------------------------------------------------------------------------- @@ -1435,49 +1435,49 @@ tm_port_header_type_out_117.BCM8887X=ETH lane_to_serdes_map_nif_lane200.BCM8887X=rx202:tx203 phy_rx_polarity_flip_phy200.BCM8887X=0 phy_tx_polarity_flip_phy200.BCM8887X=0 -serdes_tx_taps_200.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_200.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 25 lane201 lane_to_serdes_map_nif_lane201.BCM8887X=rx203:tx205 phy_rx_polarity_flip_phy201.BCM8887X=1 phy_tx_polarity_flip_phy201.BCM8887X=0 -serdes_tx_taps_201.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_201.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 25 lane202 lane_to_serdes_map_nif_lane202.BCM8887X=rx204:tx204 phy_rx_polarity_flip_phy202.BCM8887X=1 phy_tx_polarity_flip_phy202.BCM8887X=0 -serdes_tx_taps_202.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_202.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 25 lane203 lane_to_serdes_map_nif_lane203.BCM8887X=rx206:tx200 phy_rx_polarity_flip_phy203.BCM8887X=0 phy_tx_polarity_flip_phy203.BCM8887X=0 -serdes_tx_taps_203.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_203.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 25 lane204 lane_to_serdes_map_nif_lane204.BCM8887X=rx200:tx206 phy_rx_polarity_flip_phy204.BCM8887X=1 phy_tx_polarity_flip_phy204.BCM8887X=1 -serdes_tx_taps_204.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_204.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 25 lane205 lane_to_serdes_map_nif_lane205.BCM8887X=rx201:tx202 phy_rx_polarity_flip_phy205.BCM8887X=1 phy_tx_polarity_flip_phy205.BCM8887X=1 -serdes_tx_taps_205.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_205.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 25 lane206 lane_to_serdes_map_nif_lane206.BCM8887X=rx207:tx207 phy_rx_polarity_flip_phy206.BCM8887X=1 phy_tx_polarity_flip_phy206.BCM8887X=0 -serdes_tx_taps_206.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_206.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 25 lane207 lane_to_serdes_map_nif_lane207.BCM8887X=rx205:tx201 phy_rx_polarity_flip_phy207.BCM8887X=1 phy_tx_polarity_flip_phy207.BCM8887X=0 -serdes_tx_taps_207.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_207.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # ---------------------------------------------------------------------------------------------------- @@ -1492,49 +1492,49 @@ tm_port_header_type_out_109.BCM8887X=ETH lane_to_serdes_map_nif_lane208.BCM8887X=rx210:tx211 phy_rx_polarity_flip_phy208.BCM8887X=0 phy_tx_polarity_flip_phy208.BCM8887X=0 -serdes_tx_taps_208.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_208.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 26 lane209 lane_to_serdes_map_nif_lane209.BCM8887X=rx211:tx213 phy_rx_polarity_flip_phy209.BCM8887X=1 phy_tx_polarity_flip_phy209.BCM8887X=0 -serdes_tx_taps_209.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_209.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 26 lane210 lane_to_serdes_map_nif_lane210.BCM8887X=rx212:tx212 phy_rx_polarity_flip_phy210.BCM8887X=1 phy_tx_polarity_flip_phy210.BCM8887X=0 -serdes_tx_taps_210.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_210.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 26 lane211 lane_to_serdes_map_nif_lane211.BCM8887X=rx214:tx208 phy_rx_polarity_flip_phy211.BCM8887X=0 phy_tx_polarity_flip_phy211.BCM8887X=0 -serdes_tx_taps_211.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_211.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 26 lane212 lane_to_serdes_map_nif_lane212.BCM8887X=rx208:tx214 phy_rx_polarity_flip_phy212.BCM8887X=1 phy_tx_polarity_flip_phy212.BCM8887X=1 -serdes_tx_taps_212.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_212.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 26 lane213 lane_to_serdes_map_nif_lane213.BCM8887X=rx209:tx210 phy_rx_polarity_flip_phy213.BCM8887X=1 phy_tx_polarity_flip_phy213.BCM8887X=1 -serdes_tx_taps_213.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_213.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 26 lane214 lane_to_serdes_map_nif_lane214.BCM8887X=rx215:tx215 phy_rx_polarity_flip_phy214.BCM8887X=1 phy_tx_polarity_flip_phy214.BCM8887X=0 -serdes_tx_taps_214.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_214.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 26 lane215 lane_to_serdes_map_nif_lane215.BCM8887X=rx213:tx209 phy_rx_polarity_flip_phy215.BCM8887X=1 phy_tx_polarity_flip_phy215.BCM8887X=0 -serdes_tx_taps_215.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_215.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # ---------------------------------------------------------------------------------------------------- @@ -1549,49 +1549,49 @@ tm_port_header_type_out_101.BCM8887X=ETH lane_to_serdes_map_nif_lane216.BCM8887X=rx218:tx219 phy_rx_polarity_flip_phy216.BCM8887X=0 phy_tx_polarity_flip_phy216.BCM8887X=0 -serdes_tx_taps_216.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_216.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 27 lane217 lane_to_serdes_map_nif_lane217.BCM8887X=rx219:tx221 phy_rx_polarity_flip_phy217.BCM8887X=1 phy_tx_polarity_flip_phy217.BCM8887X=0 -serdes_tx_taps_217.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_217.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 27 lane218 lane_to_serdes_map_nif_lane218.BCM8887X=rx220:tx220 phy_rx_polarity_flip_phy218.BCM8887X=1 phy_tx_polarity_flip_phy218.BCM8887X=0 -serdes_tx_taps_218.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_218.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 27 lane219 lane_to_serdes_map_nif_lane219.BCM8887X=rx222:tx216 phy_rx_polarity_flip_phy219.BCM8887X=0 phy_tx_polarity_flip_phy219.BCM8887X=0 -serdes_tx_taps_219.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_219.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 27 lane220 lane_to_serdes_map_nif_lane220.BCM8887X=rx216:tx222 phy_rx_polarity_flip_phy220.BCM8887X=1 phy_tx_polarity_flip_phy220.BCM8887X=1 -serdes_tx_taps_220.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_220.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 27 lane221 lane_to_serdes_map_nif_lane221.BCM8887X=rx217:tx218 phy_rx_polarity_flip_phy221.BCM8887X=1 phy_tx_polarity_flip_phy221.BCM8887X=1 -serdes_tx_taps_221.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_221.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 27 lane222 lane_to_serdes_map_nif_lane222.BCM8887X=rx223:tx223 phy_rx_polarity_flip_phy222.BCM8887X=1 phy_tx_polarity_flip_phy222.BCM8887X=0 -serdes_tx_taps_222.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_222.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 27 lane223 lane_to_serdes_map_nif_lane223.BCM8887X=rx221:tx217 phy_rx_polarity_flip_phy223.BCM8887X=1 phy_tx_polarity_flip_phy223.BCM8887X=0 -serdes_tx_taps_223.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_223.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # ---------------------------------------------------------------------------------------------------- @@ -1606,49 +1606,49 @@ tm_port_header_type_out_253.BCM8887X=ETH lane_to_serdes_map_nif_lane224.BCM8887X=rx224:tx229 phy_rx_polarity_flip_phy224.BCM8887X=0 phy_tx_polarity_flip_phy224.BCM8887X=1 -serdes_tx_taps_224.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_224.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 28 lane225 lane_to_serdes_map_nif_lane225.BCM8887X=rx228:tx230 phy_rx_polarity_flip_phy225.BCM8887X=1 phy_tx_polarity_flip_phy225.BCM8887X=0 -serdes_tx_taps_225.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_225.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 28 lane226 lane_to_serdes_map_nif_lane226.BCM8887X=rx229:tx228 phy_rx_polarity_flip_phy226.BCM8887X=1 phy_tx_polarity_flip_phy226.BCM8887X=0 -serdes_tx_taps_226.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_226.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 28 lane227 lane_to_serdes_map_nif_lane227.BCM8887X=rx227:tx224 phy_rx_polarity_flip_phy227.BCM8887X=0 phy_tx_polarity_flip_phy227.BCM8887X=1 -serdes_tx_taps_227.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_227.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 28 lane228 lane_to_serdes_map_nif_lane228.BCM8887X=rx225:tx231 phy_rx_polarity_flip_phy228.BCM8887X=0 phy_tx_polarity_flip_phy228.BCM8887X=0 -serdes_tx_taps_228.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_228.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 28 lane229 lane_to_serdes_map_nif_lane229.BCM8887X=rx230:tx226 phy_rx_polarity_flip_phy229.BCM8887X=0 phy_tx_polarity_flip_phy229.BCM8887X=0 -serdes_tx_taps_229.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_229.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 28 lane230 lane_to_serdes_map_nif_lane230.BCM8887X=rx231:tx227 phy_rx_polarity_flip_phy230.BCM8887X=0 phy_tx_polarity_flip_phy230.BCM8887X=0 -serdes_tx_taps_230.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_230.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 28 lane231 lane_to_serdes_map_nif_lane231.BCM8887X=rx226:tx225 phy_rx_polarity_flip_phy231.BCM8887X=1 phy_tx_polarity_flip_phy231.BCM8887X=1 -serdes_tx_taps_231.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_231.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # ---------------------------------------------------------------------------------------------------- @@ -1663,49 +1663,49 @@ tm_port_header_type_out_245.BCM8887X=ETH lane_to_serdes_map_nif_lane232.BCM8887X=rx234:tx234 phy_rx_polarity_flip_phy232.BCM8887X=1 phy_tx_polarity_flip_phy232.BCM8887X=1 -serdes_tx_taps_232.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_232.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 29 lane233 lane_to_serdes_map_nif_lane233.BCM8887X=rx235:tx233 phy_rx_polarity_flip_phy233.BCM8887X=1 phy_tx_polarity_flip_phy233.BCM8887X=0 -serdes_tx_taps_233.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_233.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 29 lane234 lane_to_serdes_map_nif_lane234.BCM8887X=rx236:tx239 phy_rx_polarity_flip_phy234.BCM8887X=1 phy_tx_polarity_flip_phy234.BCM8887X=1 -serdes_tx_taps_234.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_234.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 29 lane235 lane_to_serdes_map_nif_lane235.BCM8887X=rx238:tx232 phy_rx_polarity_flip_phy235.BCM8887X=0 phy_tx_polarity_flip_phy235.BCM8887X=1 -serdes_tx_taps_235.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_235.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 29 lane236 lane_to_serdes_map_nif_lane236.BCM8887X=rx237:tx236 phy_rx_polarity_flip_phy236.BCM8887X=0 phy_tx_polarity_flip_phy236.BCM8887X=0 -serdes_tx_taps_236.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_236.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 29 lane237 lane_to_serdes_map_nif_lane237.BCM8887X=rx239:tx235 phy_rx_polarity_flip_phy237.BCM8887X=1 phy_tx_polarity_flip_phy237.BCM8887X=0 -serdes_tx_taps_237.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_237.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 29 lane238 lane_to_serdes_map_nif_lane238.BCM8887X=rx232:tx238 phy_rx_polarity_flip_phy238.BCM8887X=1 phy_tx_polarity_flip_phy238.BCM8887X=0 -serdes_tx_taps_238.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_238.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 29 lane239 lane_to_serdes_map_nif_lane239.BCM8887X=rx233:tx237 phy_rx_polarity_flip_phy239.BCM8887X=1 phy_tx_polarity_flip_phy239.BCM8887X=0 -serdes_tx_taps_239.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_239.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # ---------------------------------------------------------------------------------------------------- @@ -1720,49 +1720,49 @@ tm_port_header_type_out_237.BCM8887X=ETH lane_to_serdes_map_nif_lane240.BCM8887X=rx242:tx242 phy_rx_polarity_flip_phy240.BCM8887X=0 phy_tx_polarity_flip_phy240.BCM8887X=1 -serdes_tx_taps_240.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_240.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 30 lane241 lane_to_serdes_map_nif_lane241.BCM8887X=rx243:tx241 phy_rx_polarity_flip_phy241.BCM8887X=1 phy_tx_polarity_flip_phy241.BCM8887X=0 -serdes_tx_taps_241.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_241.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 30 lane242 lane_to_serdes_map_nif_lane242.BCM8887X=rx244:tx247 phy_rx_polarity_flip_phy242.BCM8887X=1 phy_tx_polarity_flip_phy242.BCM8887X=1 -serdes_tx_taps_242.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_242.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 30 lane243 lane_to_serdes_map_nif_lane243.BCM8887X=rx246:tx240 phy_rx_polarity_flip_phy243.BCM8887X=0 phy_tx_polarity_flip_phy243.BCM8887X=1 -serdes_tx_taps_243.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_243.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 30 lane244 lane_to_serdes_map_nif_lane244.BCM8887X=rx245:tx244 phy_rx_polarity_flip_phy244.BCM8887X=0 phy_tx_polarity_flip_phy244.BCM8887X=0 -serdes_tx_taps_244.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_244.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 30 lane245 lane_to_serdes_map_nif_lane245.BCM8887X=rx247:tx243 phy_rx_polarity_flip_phy245.BCM8887X=1 phy_tx_polarity_flip_phy245.BCM8887X=0 -serdes_tx_taps_245.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_245.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 30 lane246 lane_to_serdes_map_nif_lane246.BCM8887X=rx240:tx246 phy_rx_polarity_flip_phy246.BCM8887X=1 phy_tx_polarity_flip_phy246.BCM8887X=0 -serdes_tx_taps_246.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_246.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 30 lane247 lane_to_serdes_map_nif_lane247.BCM8887X=rx241:tx245 phy_rx_polarity_flip_phy247.BCM8887X=1 phy_tx_polarity_flip_phy247.BCM8887X=0 -serdes_tx_taps_247.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_247.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # ---------------------------------------------------------------------------------------------------- @@ -1777,49 +1777,49 @@ tm_port_header_type_out_229.BCM8887X=ETH lane_to_serdes_map_nif_lane248.BCM8887X=rx250:tx250 phy_rx_polarity_flip_phy248.BCM8887X=0 phy_tx_polarity_flip_phy248.BCM8887X=1 -serdes_tx_taps_248.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_248.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 31 lane249 lane_to_serdes_map_nif_lane249.BCM8887X=rx251:tx249 phy_rx_polarity_flip_phy249.BCM8887X=1 phy_tx_polarity_flip_phy249.BCM8887X=0 -serdes_tx_taps_249.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_249.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 31 lane250 lane_to_serdes_map_nif_lane250.BCM8887X=rx252:tx255 phy_rx_polarity_flip_phy250.BCM8887X=1 phy_tx_polarity_flip_phy250.BCM8887X=1 -serdes_tx_taps_250.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_250.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 31 lane251 lane_to_serdes_map_nif_lane251.BCM8887X=rx254:tx248 phy_rx_polarity_flip_phy251.BCM8887X=0 phy_tx_polarity_flip_phy251.BCM8887X=1 -serdes_tx_taps_251.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_251.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 31 lane252 lane_to_serdes_map_nif_lane252.BCM8887X=rx253:tx252 phy_rx_polarity_flip_phy252.BCM8887X=0 phy_tx_polarity_flip_phy252.BCM8887X=0 -serdes_tx_taps_252.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_252.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 31 lane253 lane_to_serdes_map_nif_lane253.BCM8887X=rx255:tx251 phy_rx_polarity_flip_phy253.BCM8887X=1 phy_tx_polarity_flip_phy253.BCM8887X=0 -serdes_tx_taps_253.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_253.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 31 lane254 lane_to_serdes_map_nif_lane254.BCM8887X=rx248:tx254 phy_rx_polarity_flip_phy254.BCM8887X=1 phy_tx_polarity_flip_phy254.BCM8887X=0 -serdes_tx_taps_254.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_254.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # core 31 lane255 lane_to_serdes_map_nif_lane255.BCM8887X=rx249:tx253 phy_rx_polarity_flip_phy255.BCM8887X=1 phy_tx_polarity_flip_phy255.BCM8887X=0 -serdes_tx_taps_255.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3:0 +serdes_tx_taps_255.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3:0 # ---------------------------------------------------------------------------------------------------- # core_32 diff --git a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/port_config.ini b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/port_config.ini index 9d1540e394f..eb123965df6 100644 --- a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/port_config.ini +++ b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/port_config.ini @@ -1,68 +1,68 @@ -# name lanes alias index role speed asic_port_name core_id core_port_id num_voq -Ethernet0 96,97,98,99 Port1 1 Ext 400000 Eth0 3 1 8 -Ethernet4 100,101,102,103 Port2 2 Ext 400000 Eth4 3 5 8 -Ethernet8 104,105,106,107 Port3 3 Ext 400000 Eth8 3 9 8 -Ethernet12 108,109,110,111 Port4 4 Ext 400000 Eth12 3 13 8 -Ethernet16 112,113,114,115 Port5 5 Ext 400000 Eth16 3 17 8 -Ethernet20 116,117,118,119 Port6 6 Ext 400000 Eth20 3 21 8 -Ethernet24 120,121,122,123 Port7 7 Ext 400000 Eth24 3 25 8 -Ethernet28 124,125,126,127 Port8 8 Ext 400000 Eth28 3 29 8 -Ethernet32 56,57,58,59 Port9 9 Ext 400000 Eth32 1 25 8 -Ethernet36 60,61,62,63 Port10 10 Ext 400000 Eth36 1 29 8 -Ethernet40 48,49,50,51 Port11 11 Ext 400000 Eth40 1 17 8 -Ethernet44 52,53,54,55 Port12 12 Ext 400000 Eth44 1 21 8 -Ethernet48 40,41,42,43 Port13 13 Ext 400000 Eth48 1 9 8 -Ethernet52 44,45,46,47 Port14 14 Ext 400000 Eth52 1 13 8 -Ethernet56 32,33,34,35 Port15 15 Ext 400000 Eth56 1 1 8 -Ethernet60 36,37,38,39 Port16 16 Ext 400000 Eth60 1 5 8 -Ethernet64 128,129,130,131 Port17 17 Ext 400000 Eth64 4 1 8 -Ethernet68 132,133,134,135 Port18 18 Ext 400000 Eth68 4 5 8 -Ethernet72 136,137,138,139 Port19 19 Ext 400000 Eth72 4 9 8 -Ethernet76 140,141,142,143 Port20 20 Ext 400000 Eth76 4 13 8 -Ethernet80 144,145,146,147 Port21 21 Ext 400000 Eth80 4 17 8 -Ethernet84 148,149,150,151 Port22 22 Ext 400000 Eth84 4 21 8 -Ethernet88 152,153,154,155 Port23 23 Ext 400000 Eth88 4 25 8 -Ethernet92 156,157,158,159 Port24 24 Ext 400000 Eth92 4 29 8 -Ethernet96 216,217,218,219 Port25 25 Ext 400000 Eth96 6 25 8 -Ethernet100 220,221,222,223 Port26 26 Ext 400000 Eth100 6 29 8 -Ethernet104 208,209,210,211 Port27 27 Ext 400000 Eth108 6 17 8 -Ethernet108 212,213,214,215 Port28 28 Ext 400000 Eth108 6 21 8 -Ethernet112 200,201,202,203 Port29 29 Ext 400000 Eth112 6 9 8 -Ethernet116 204,205,206,207 Port30 30 Ext 400000 Eth116 6 13 8 -Ethernet120 192,193,194,195 Port31 31 Ext 400000 Eth120 6 1 8 -Ethernet124 196,197,198,199 Port32 32 Ext 400000 Eth124 6 5 8 -Ethernet128 64,65,66,67 Port33 33 Ext 400000 Eth128 2 1 8 -Ethernet132 68,69,70,71 Port34 34 Ext 400000 Eth132 2 5 8 -Ethernet136 72,73,74,75 Port35 35 Ext 400000 Eth136 2 9 8 -Ethernet140 76,77,78,79 Port36 36 Ext 400000 Eth140 2 13 8 -Ethernet144 80,81,82,83 Port37 37 Ext 400000 Eth144 2 17 8 -Ethernet148 84,85,86,87 Port38 38 Ext 400000 Eth148 2 21 8 -Ethernet152 88,89,90,91 Port39 39 Ext 400000 Eth152 2 25 8 -Ethernet156 92,93,94,95 Port40 40 Ext 400000 Eth156 2 29 8 -Ethernet160 24,25,26,27 Port41 41 Ext 400000 Eth160 0 25 8 -Ethernet164 28,29,30,31 Port42 42 Ext 400000 Eth164 0 29 8 -Ethernet168 16,17,18,19 Port43 43 Ext 400000 Eth168 0 17 8 -Ethernet172 20,21,22,23 Port44 44 Ext 400000 Eth172 0 21 8 -Ethernet176 8,9,10,11 Port45 45 Ext 400000 Eth176 0 9 8 -Ethernet180 12,13,14,15 Port46 46 Ext 400000 Eth180 0 13 8 -Ethernet184 0,1,2,3 Port47 47 Ext 400000 Eth184 0 1 8 -Ethernet188 4,5,6,7 Port48 48 Ext 400000 Eth188 0 5 8 -Ethernet192 160,161,162,163 Port49 49 Ext 400000 Eth192 5 1 8 -Ethernet196 164,165,166,167 Port50 50 Ext 400000 Eth196 5 5 8 -Ethernet200 168,169,170,171 Port51 51 Ext 400000 Eth200 5 9 8 -Ethernet204 172,173,174,175 Port52 52 Ext 400000 Eth204 5 13 8 -Ethernet208 176,177,178,179 Port53 53 Ext 400000 Eth208 5 17 8 -Ethernet212 180,181,182,183 Port54 54 Ext 400000 Eth212 5 21 8 -Ethernet216 184,185,186,187 Port55 55 Ext 400000 Eth216 5 25 8 -Ethernet220 188,189,190,191 Port56 56 Ext 400000 Eth220 5 29 8 -Ethernet224 248,249,250,251 Port57 57 Ext 400000 Eth224 7 25 8 -Ethernet228 252,253,254,255 Port58 58 Ext 400000 Eth228 7 29 8 -Ethernet232 240,241,242,243 Port59 59 Ext 400000 Eth232 7 17 8 -Ethernet236 244,245,246,247 Port60 60 Ext 400000 Eth236 7 21 8 -Ethernet240 232,233,234,235 Port61 61 Ext 400000 Eth240 7 9 8 -Ethernet244 236,237,238,239 Port62 62 Ext 400000 Eth244 7 13 8 -Ethernet248 224,225,226,227 Port63 63 Ext 400000 Eth248 7 1 8 -Ethernet252 228,229,230,231 Port64 64 Ext 400000 Eth252 7 5 8 -Ethernet256 256,257,258,259 Port65 65 Ext 100000 Eth256 2 33 8 -Ethernet260 260,261,262,263 Port66 66 Ext 100000 Eth260 6 33 8 -Ethernet-Rec0 621 Port67 67 Rec 400000 Rcy0 0 221 8 +# name lanes alias index role speed asic_port_name core_id core_port_id num_voq +Ethernet0 96,97,98,99 Port1 1 Ext 400000 Eth0 3 1 8 +Ethernet4 100,101,102,103 Port2 2 Ext 400000 Eth4 3 5 8 +Ethernet8 104,105,106,107 Port3 3 Ext 400000 Eth8 3 9 8 +Ethernet12 108,109,110,111 Port4 4 Ext 400000 Eth12 3 13 8 +Ethernet16 112,113,114,115 Port5 5 Ext 400000 Eth16 3 17 8 +Ethernet20 116,117,118,119 Port6 6 Ext 400000 Eth20 3 21 8 +Ethernet24 120,121,122,123 Port7 7 Ext 400000 Eth24 3 25 8 +Ethernet28 124,125,126,127 Port8 8 Ext 400000 Eth28 3 29 8 +Ethernet32 56,57,58,59 Port9 9 Ext 400000 Eth32 1 25 8 +Ethernet36 60,61,62,63 Port10 10 Ext 400000 Eth36 1 29 8 +Ethernet40 48,49,50,51 Port11 11 Ext 400000 Eth40 1 17 8 +Ethernet44 52,53,54,55 Port12 12 Ext 400000 Eth44 1 21 8 +Ethernet48 40,41,42,43 Port13 13 Ext 400000 Eth48 1 9 8 +Ethernet52 44,45,46,47 Port14 14 Ext 400000 Eth52 1 13 8 +Ethernet56 32,33,34,35 Port15 15 Ext 400000 Eth56 1 1 8 +Ethernet60 36,37,38,39 Port16 16 Ext 400000 Eth60 1 5 8 +Ethernet64 128,129,130,131 Port17 17 Ext 400000 Eth64 4 1 8 +Ethernet68 132,133,134,135 Port18 18 Ext 400000 Eth68 4 5 8 +Ethernet72 136,137,138,139 Port19 19 Ext 400000 Eth72 4 9 8 +Ethernet76 140,141,142,143 Port20 20 Ext 400000 Eth76 4 13 8 +Ethernet80 144,145,146,147 Port21 21 Ext 400000 Eth80 4 17 8 +Ethernet84 148,149,150,151 Port22 22 Ext 400000 Eth84 4 21 8 +Ethernet88 152,153,154,155 Port23 23 Ext 400000 Eth88 4 25 8 +Ethernet92 156,157,158,159 Port24 24 Ext 400000 Eth92 4 29 8 +Ethernet96 216,217,218,219 Port25 25 Ext 400000 Eth96 6 25 8 +Ethernet100 220,221,222,223 Port26 26 Ext 400000 Eth100 6 29 8 +Ethernet104 208,209,210,211 Port27 27 Ext 400000 Eth108 6 17 8 +Ethernet108 212,213,214,215 Port28 28 Ext 400000 Eth108 6 21 8 +Ethernet112 200,201,202,203 Port29 29 Ext 400000 Eth112 6 9 8 +Ethernet116 204,205,206,207 Port30 30 Ext 400000 Eth116 6 13 8 +Ethernet120 192,193,194,195 Port31 31 Ext 400000 Eth120 6 1 8 +Ethernet124 196,197,198,199 Port32 32 Ext 400000 Eth124 6 5 8 +Ethernet128 64,65,66,67 Port33 33 Ext 400000 Eth128 2 1 8 +Ethernet132 68,69,70,71 Port34 34 Ext 400000 Eth132 2 5 8 +Ethernet136 72,73,74,75 Port35 35 Ext 400000 Eth136 2 9 8 +Ethernet140 76,77,78,79 Port36 36 Ext 400000 Eth140 2 13 8 +Ethernet144 80,81,82,83 Port37 37 Ext 400000 Eth144 2 17 8 +Ethernet148 84,85,86,87 Port38 38 Ext 400000 Eth148 2 21 8 +Ethernet152 88,89,90,91 Port39 39 Ext 400000 Eth152 2 25 8 +Ethernet156 92,93,94,95 Port40 40 Ext 400000 Eth156 2 29 8 +Ethernet160 24,25,26,27 Port41 41 Ext 400000 Eth160 0 25 8 +Ethernet164 28,29,30,31 Port42 42 Ext 400000 Eth164 0 29 8 +Ethernet168 16,17,18,19 Port43 43 Ext 400000 Eth168 0 17 8 +Ethernet172 20,21,22,23 Port44 44 Ext 400000 Eth172 0 21 8 +Ethernet176 8,9,10,11 Port45 45 Ext 400000 Eth176 0 9 8 +Ethernet180 12,13,14,15 Port46 46 Ext 400000 Eth180 0 13 8 +Ethernet184 0,1,2,3 Port47 47 Ext 400000 Eth184 0 1 8 +Ethernet188 4,5,6,7 Port48 48 Ext 400000 Eth188 0 5 8 +Ethernet192 160,161,162,163 Port49 49 Ext 400000 Eth192 5 1 8 +Ethernet196 164,165,166,167 Port50 50 Ext 400000 Eth196 5 5 8 +Ethernet200 168,169,170,171 Port51 51 Ext 400000 Eth200 5 9 8 +Ethernet204 172,173,174,175 Port52 52 Ext 400000 Eth204 5 13 8 +Ethernet208 176,177,178,179 Port53 53 Ext 400000 Eth208 5 17 8 +Ethernet212 180,181,182,183 Port54 54 Ext 400000 Eth212 5 21 8 +Ethernet216 184,185,186,187 Port55 55 Ext 400000 Eth216 5 25 8 +Ethernet220 188,189,190,191 Port56 56 Ext 400000 Eth220 5 29 8 +Ethernet224 248,249,250,251 Port57 57 Ext 400000 Eth224 7 25 8 +Ethernet228 252,253,254,255 Port58 58 Ext 400000 Eth228 7 29 8 +Ethernet232 240,241,242,243 Port59 59 Ext 400000 Eth232 7 17 8 +Ethernet236 244,245,246,247 Port60 60 Ext 400000 Eth236 7 21 8 +Ethernet240 232,233,234,235 Port61 61 Ext 400000 Eth240 7 9 8 +Ethernet244 236,237,238,239 Port62 62 Ext 400000 Eth244 7 13 8 +Ethernet248 224,225,226,227 Port63 63 Ext 400000 Eth248 7 1 8 +Ethernet252 228,229,230,231 Port64 64 Ext 400000 Eth252 7 5 8 +Ethernet256 256,257,258,259 Port65 65 Ext 100000 Eth256 2 33 8 +Ethernet260 260,261,262,263 Port66 66 Ext 100000 Eth260 6 33 8 +Ethernet-Rec0 621 Port67 67 Rec 400000 Rcy0 0 221 8 diff --git a/device/nexthop/x86_64-nexthop_5010-r0/installer.conf b/device/nexthop/x86_64-nexthop_5010-r0/installer.conf deleted file mode 120000 index 97b3314541b..00000000000 --- a/device/nexthop/x86_64-nexthop_5010-r0/installer.conf +++ /dev/null @@ -1 +0,0 @@ -../x86_64-nexthop_4010-r0/installer.conf \ No newline at end of file diff --git a/device/nexthop/x86_64-nexthop_5010-r0/installer.conf b/device/nexthop/x86_64-nexthop_5010-r0/installer.conf new file mode 100644 index 00000000000..e172a88fc88 --- /dev/null +++ b/device/nexthop/x86_64-nexthop_5010-r0/installer.conf @@ -0,0 +1 @@ +ONIE_PLATFORM_EXTRA_CMDLINE_LINUX="crashkernel=512M" diff --git a/device/nexthop/x86_64-nexthop_5010-r0/pddf/pd-plugin.json b/device/nexthop/x86_64-nexthop_5010-r0/pddf/pd-plugin.json index ab136e44827..d260b308595 100644 --- a/device/nexthop/x86_64-nexthop_5010-r0/pddf/pd-plugin.json +++ b/device/nexthop/x86_64-nexthop_5010-r0/pddf/pd-plugin.json @@ -1,4 +1,288 @@ { + "DPM": { + "cpu_card": { + "nvmem_path": "/sys/bus/nvmem/devices/7-00410/nvmem", + "dpm_signal_to_fault_cause": [ + { + "pdio_mask": "0xC002", + "gpio_mask": "0x0000", + "pdio_value": "0x4000", + "gpio_value": "0x0000", + "hw_cause": "THERMTRIP_L", + "hw_desc": "CPU exceeded Tdie temperature threshold", + "summary": "System shutdown due to CPU thermal trip", + "reboot_cause": "REBOOT_CAUSE_THERMAL_OVERLOAD_CPU" + }, + { + "pdio_mask": "0xC002", + "gpio_mask": "0x0000", + "pdio_value": "0x8000", + "gpio_value": "0x0000", + "hw_cause": "CPU_PWR_CYC_REQ", + "hw_desc": "CPU requested power cycle", + "summary": "System power cycled due to CPU request", + "reboot_cause": "REBOOT_CAUSE_POWER_LOSS" + }, + { + "pdio_mask": "0xC002", + "gpio_mask": "0x0000", + "pdio_value": "0xC000", + "gpio_value": "0x0000", + "hw_cause": "BMC_PWR_CYC_REQ", + "hw_desc": "BMC requested power cycle", + "summary": "System power cycled due to BMC request", + "reboot_cause": "REBOOT_CAUSE_POWER_LOSS" + }, + { + "pdio_mask": "0xC002", + "gpio_mask": "0x0000", + "pdio_value": "0x0002", + "gpio_value": "0x0000", + "hw_cause": "FPGA_PWR_CYC_REQ", + "hw_desc": "FPGA requested power cycle", + "summary": "System power cycled due to FPGA request", + "reboot_cause": "REBOOT_CAUSE_POWER_LOSS" + }, + { + "pdio_mask": "0xC002", + "gpio_mask": "0x0000", + "pdio_value": "0x4002", + "gpio_value": "0x0000", + "hw_cause": "SWITCH_CARD_CP_PWR_BAD", + "hw_desc": "Switch card control plane power failure", + "summary": "System rebooted due to switch card control plane power failure", + "reboot_cause": "REBOOT_CAUSE_HARDWARE_OTHER" + } + ], + "vhx_to_rail_desc": { + "1": "POS12V", + "2": "POS5V0", + "4": "POS5V0_S0" + }, + "vpx_to_rail_desc": { + "1": "POS1V0_A7", + "2": "POS1V8_V7", + "3": "POS3V3", + "4": "POS1V0", + "5": "POS1V2_A7", + "6": "POS0V75_S5", + "7": "POS1V8_S5", + "8": "POS3V3_S5", + "9": "POS1V1_S0", + "10": "POS0V78_S0", + "11": "POS0V75_S0", + "12": "POS1V8_S0", + "13": "POS3V3_S0" + } + }, + "switch_card_1": { + "nvmem_path": "/sys/bus/nvmem/devices/9-00410/nvmem", + "dpm_signal_to_fault_cause": [ + { + "pdio_mask": "0x0001", + "gpio_mask": "0x0000", + "pdio_value": "0x0001", + "gpio_value": "0x0000", + "hw_cause": "PSU_VIN_LOSS", + "hw_desc": "Both PSUs lost input power", + "summary": "System powered off due to loss of input power on both PSUs", + "reboot_cause": "REBOOT_CAUSE_POWER_LOSS" + }, + { + "pdio_mask": "0x0002", + "gpio_mask": "0x0000", + "pdio_value": "0x0002", + "gpio_value": "0x0000", + "hw_cause": "OVER_TEMP", + "hw_desc": "Switch card temp sensor OT", + "summary": "System rebooted due to switch card temperature exceeding threshold", + "reboot_cause": "REBOOT_CAUSE_THERMAL_OVERLOAD_OTHER" + }, + { + "pdio_mask": "0x0004", + "gpio_mask": "0x0000", + "pdio_value": "0x0004", + "gpio_value": "0x0000", + "hw_cause": "CPU_PWR_BAD", + "hw_desc": "CPU card power bad", + "summary": "System rebooted due to CPU card power failure", + "reboot_cause": "REBOOT_CAUSE_HARDWARE_OTHER" + }, + { + "pdio_mask": "0x0008", + "gpio_mask": "0x0000", + "pdio_value": "0x0008", + "gpio_value": "0x0000", + "hw_cause": "WATCHDOG", + "hw_desc": "FPGA watchdog expired", + "summary": "System rebooted due to FPGA watchdog expiration", + "reboot_cause": "REBOOT_CAUSE_WATCHDOG" + }, + { + "pdio_mask": "0x0010", + "gpio_mask": "0x0000", + "pdio_value": "0x0010", + "gpio_value": "0x0000", + "hw_cause": "ASIC_OT", + "hw_desc": "ASIC MAX_TEMP exceeded OT threshold", + "summary": "System rebooted due to ASIC temperature exceeding maximum threshold", + "reboot_cause": "REBOOT_CAUSE_THERMAL_OVERLOAD_ASIC" + }, + { + "pdio_mask": "0x0020", + "gpio_mask": "0x0000", + "pdio_value": "0x0020", + "gpio_value": "0x0000", + "hw_cause": "CPU_CMD_PCYC", + "hw_desc": "CPU card commanded power cycle", + "summary": "System power cycled due to CPU card request", + "reboot_cause": "REBOOT_CAUSE_POWER_LOSS" + }, + { + "pdio_mask": "0x0040", + "gpio_mask": "0x0000", + "pdio_value": "0x0040", + "gpio_value": "0x0000", + "hw_cause": "FPGA_CMD_PCYC", + "hw_desc": "FPGA commanded power cycle", + "summary": "System power cycled due to FPGA request", + "reboot_cause": "REBOOT_CAUSE_POWER_LOSS" + } + ], + "vhx_to_rail_desc": { + "1": "POS12V0", + "2": "POS5V0", + "3": "POS1V0", + "4": "POS1V8_CP" + }, + "vpx_to_rail_desc": { + "1": "POS1V2_CP", + "2": "POS3V3", + "3": "POS3V3_WEST", + "4": "POS3V3_EAST", + "5": "POS1V2_DP", + "6": "POS1V8_DP", + "7": "POS0V78_VDDC_D0", + "8": "POS0V78_VDDC_D1", + "9": "POS0V75_TRVDD_D0", + "10": "POS0V75_TRVDD_D1", + "11": "POS0V9_PVDD_WEST", + "12": "POS0V9_PVDD_EAST", + "13": "PSU0 Imon" + } + }, + "switch_card_2": { + "nvmem_path": "/sys/bus/nvmem/devices/9-00430/nvmem", + "dpm_signal_to_fault_cause": [ + { + "pdio_mask": "0x0001", + "gpio_mask": "0x0000", + "pdio_value": "0x0001", + "gpio_value": "0x0000", + "hw_cause": "NO_FAN_PRSNT", + "hw_desc": "All 4 system fans removed", + "summary": "System rebooted due to loss of all system fans", + "reboot_cause": "REBOOT_CAUSE_INSUFFICIENT_FAN_SPEED" + } + ], + "vhx_to_rail_desc": { + "1": "POS12V0", + "2": "POS5V0", + "3": "POS0V9_TRVDD_D0", + "4": "POS0V9_TRVDD_D1" + }, + "vpx_to_rail_desc": { + "1": "POS0V8_AVDD", + "2": "POS1V5_APVDD_D0", + "3": "POS1V5_APVDD_D1", + "4": "POS1V5_VDDH", + "5": "POS1V5_PBU_VDDA", + "6": "POS0V8_PB_VDD", + "7": "POS2V5_HBM_D0", + "8": "POS2V5_HBM_D1", + "9": "POS1V2_HBM_D0", + "10": "POS1V2_HBM_D1", + "11": "D0 VDDC Imon", + "12": "D1 VDDC Imon", + "13": "PSU1 Imon" + } + }, + "mezzanine_card": { + "nvmem_path": "/sys/bus/nvmem/devices/9-00450/nvmem", + "dpm_signal_to_fault_cause": [ + { + "pdio_mask": "0x0001", + "gpio_mask": "0x0000", + "pdio_value": "0x0001", + "gpio_value": "0x0000", + "hw_cause": "PSU_VIN_LOSS", + "hw_desc": "Both PSUs lost input power", + "summary": "System powered off due to loss of input power on both PSUs", + "reboot_cause": "REBOOT_CAUSE_POWER_LOSS" + }, + { + "pdio_mask": "0x0002", + "gpio_mask": "0x0000", + "pdio_value": "0x0002", + "gpio_value": "0x0000", + "hw_cause": "OVER_TEMP", + "hw_desc": "Switch card temp sensor OT", + "summary": "System rebooted due to switch card temperature exceeding threshold", + "reboot_cause": "REBOOT_CAUSE_THERMAL_OVERLOAD_OTHER" + }, + { + "pdio_mask": "0x0004", + "gpio_mask": "0x0000", + "pdio_value": "0x0004", + "gpio_value": "0x0000", + "hw_cause": "CPU_PWR_BAD", + "hw_desc": "CPU card power bad", + "summary": "System rebooted due to CPU card power failure", + "reboot_cause": "REBOOT_CAUSE_HARDWARE_OTHER" + }, + { + "pdio_mask": "0x0008", + "gpio_mask": "0x0000", + "pdio_value": "0x0008", + "gpio_value": "0x0000", + "hw_cause": "WATCHDOG", + "hw_desc": "FPGA watchdog expired", + "summary": "System rebooted due to FPGA watchdog expiration", + "reboot_cause": "REBOOT_CAUSE_WATCHDOG" + }, + { + "pdio_mask": "0x0010", + "gpio_mask": "0x0000", + "pdio_value": "0x0010", + "gpio_value": "0x0000", + "hw_cause": "ASIC_OT", + "hw_desc": "ASIC MAX_TEMP exceeded OT threshold", + "summary": "System rebooted due to ASIC temperature exceeding maximum threshold", + "reboot_cause": "REBOOT_CAUSE_THERMAL_OVERLOAD_ASIC" + } + ], + "vhx_to_rail_desc": { + "1": "12V", + "2": "5V0", + "3": "1V0_FPGA", + "4": "1V8_FPGA" + }, + "vpx_to_rail_desc": { + "1": "1V2_FPGA", + "2": "3V3_FPGA", + "3": "3V3_WEST_MC", + "4": "POS1V5_VDD3V3_EAST_MCH", + "5": "VDDIOL_1P5", + "6": "VDDIO_1P8", + "7": "VDDC_WEST", + "8": "VDDC_EAST", + "9": "AVVDL_0P75_WEST", + "10": "AVVDL_0P75_EAST", + "11": "AVDDH_0P9_WEST", + "12": "AVDDH_0P9_EAST" + } + } + }, "PSU": { "name": { "1": "PSU1", @@ -39,7 +323,8 @@ "psu_fan_dir": { "i2c": { "valmap": { - "D1U74T-W-3200-12-HB4C": "exhaust" + "D1U74T-W-3200-12-HB4C": "exhaust", + "D1U74T-W-3200-12-HB4T": "exhaust" } } }, diff --git a/device/nexthop/x86_64-nexthop_5010-r0/pddf/pddf-device.json.j2 b/device/nexthop/x86_64-nexthop_5010-r0/pddf/pddf-device.json.j2 index e9a772366fe..2a91e4d28df 100644 --- a/device/nexthop/x86_64-nexthop_5010-r0/pddf/pddf-device.json.j2 +++ b/device/nexthop/x86_64-nexthop_5010-r0/pddf/pddf-device.json.j2 @@ -30,7 +30,6 @@ "std_kos": [ "at24", "i2c-dev", - "adm1266", "optoe" ], "pddf_kos": [ @@ -56,6 +55,7 @@ "pddf_custom_mdio_algo", "nh_pmbus_core", "nh_tda38740", + "nh_adm1266", "nh_tmp464" ] }, @@ -573,11 +573,11 @@ }, { "attr_name": "temp1_high_threshold", - "drv_attr_name": "temp2_max" + "drv_attr_name": "temp2_crit" }, { "attr_name": "temp1_high_crit_threshold", - "drv_attr_name": "temp2_crit" + "drv_attr_name": "temp2_max" } ] } @@ -600,11 +600,11 @@ }, { "attr_name": "temp1_high_threshold", - "drv_attr_name": "temp3_max" + "drv_attr_name": "temp3_crit" }, { "attr_name": "temp1_high_crit_threshold", - "drv_attr_name": "temp3_crit" + "drv_attr_name": "temp3_max" } ] } @@ -627,11 +627,11 @@ }, { "attr_name": "temp1_high_threshold", - "drv_attr_name": "temp4_max" + "drv_attr_name": "temp4_crit" }, { "attr_name": "temp1_high_crit_threshold", - "drv_attr_name": "temp4_crit" + "drv_attr_name": "temp4_max" } ] } @@ -654,11 +654,11 @@ }, { "attr_name": "temp1_high_threshold", - "drv_attr_name": "temp5_max" + "drv_attr_name": "temp5_crit" }, { "attr_name": "temp1_high_crit_threshold", - "drv_attr_name": "temp5_crit" + "drv_attr_name": "temp5_max" } ] } @@ -681,11 +681,11 @@ }, { "attr_name": "temp1_high_threshold", - "drv_attr_name": "temp6_max" + "drv_attr_name": "temp6_crit" }, { "attr_name": "temp1_high_crit_threshold", - "drv_attr_name": "temp6_crit" + "drv_attr_name": "temp6_max" } ] } @@ -708,11 +708,11 @@ }, { "attr_name": "temp1_high_threshold", - "drv_attr_name": "temp7_max" + "drv_attr_name": "temp7_crit" }, { "attr_name": "temp1_high_crit_threshold", - "drv_attr_name": "temp7_crit" + "drv_attr_name": "temp7_max" } ] } @@ -735,11 +735,11 @@ }, { "attr_name": "temp1_high_threshold", - "drv_attr_name": "temp8_max" + "drv_attr_name": "temp8_crit" }, { "attr_name": "temp1_high_crit_threshold", - "drv_attr_name": "temp8_crit" + "drv_attr_name": "temp8_max" } ] } @@ -762,11 +762,11 @@ }, { "attr_name": "temp1_high_threshold", - "drv_attr_name": "temp9_max" + "drv_attr_name": "temp9_crit" }, { "attr_name": "temp1_high_crit_threshold", - "drv_attr_name": "temp9_crit" + "drv_attr_name": "temp9_max" } ] } @@ -789,11 +789,11 @@ }, { "attr_name": "temp1_high_threshold", - "drv_attr_name": "temp2_max" + "drv_attr_name": "temp2_crit" }, { "attr_name": "temp1_high_crit_threshold", - "drv_attr_name": "temp2_crit" + "drv_attr_name": "temp2_max" } ] } @@ -816,11 +816,11 @@ }, { "attr_name": "temp1_high_threshold", - "drv_attr_name": "temp3_max" + "drv_attr_name": "temp3_crit" }, { "attr_name": "temp1_high_crit_threshold", - "drv_attr_name": "temp3_crit" + "drv_attr_name": "temp3_max" } ] } @@ -843,11 +843,11 @@ }, { "attr_name": "temp1_high_threshold", - "drv_attr_name": "temp4_max" + "drv_attr_name": "temp4_crit" }, { "attr_name": "temp1_high_crit_threshold", - "drv_attr_name": "temp4_crit" + "drv_attr_name": "temp4_max" } ] } @@ -870,11 +870,11 @@ }, { "attr_name": "temp1_high_threshold", - "drv_attr_name": "temp5_max" + "drv_attr_name": "temp5_crit" }, { "attr_name": "temp1_high_crit_threshold", - "drv_attr_name": "temp5_crit" + "drv_attr_name": "temp5_max" } ] } @@ -897,11 +897,11 @@ }, { "attr_name": "temp1_high_threshold", - "drv_attr_name": "temp6_max" + "drv_attr_name": "temp6_crit" }, { "attr_name": "temp1_high_crit_threshold", - "drv_attr_name": "temp6_crit" + "drv_attr_name": "temp6_max" } ] } @@ -924,11 +924,11 @@ }, { "attr_name": "temp1_high_threshold", - "drv_attr_name": "temp7_max" + "drv_attr_name": "temp7_crit" }, { "attr_name": "temp1_high_crit_threshold", - "drv_attr_name": "temp7_crit" + "drv_attr_name": "temp7_max" } ] } @@ -951,11 +951,11 @@ }, { "attr_name": "temp1_high_threshold", - "drv_attr_name": "temp8_max" + "drv_attr_name": "temp8_crit" }, { "attr_name": "temp1_high_crit_threshold", - "drv_attr_name": "temp8_crit" + "drv_attr_name": "temp8_max" } ] } @@ -978,11 +978,11 @@ }, { "attr_name": "temp1_high_threshold", - "drv_attr_name": "temp9_max" + "drv_attr_name": "temp9_crit" }, { "attr_name": "temp1_high_crit_threshold", - "drv_attr_name": "temp9_crit" + "drv_attr_name": "temp9_max" } ] } @@ -12925,7 +12925,7 @@ "topo_info": { "parent_bus": "0x7", "dev_addr": "0x41", - "dev_type": "adm1266" + "dev_type": "nh_adm1266" } } }, @@ -12939,7 +12939,7 @@ "topo_info": { "parent_bus": "0x9", "dev_addr": "0x41", - "dev_type": "adm1266" + "dev_type": "nh_adm1266" } } }, @@ -12953,7 +12953,7 @@ "topo_info": { "parent_bus": "0x9", "dev_addr": "0x43", - "dev_type": "adm1266" + "dev_type": "nh_adm1266" } } }, @@ -12967,7 +12967,7 @@ "topo_info": { "parent_bus": "0x9", "dev_addr": "0x45", - "dev_type": "adm1266" + "dev_type": "nh_adm1266" } } }, @@ -15630,11 +15630,11 @@ }, { "attr_name": "temp1_high_threshold", - "drv_attr_name": "temp2_max" + "drv_attr_name": "temp2_crit" }, { "attr_name": "temp1_high_crit_threshold", - "drv_attr_name": "temp2_crit" + "drv_attr_name": "temp2_max" } ] } @@ -15657,11 +15657,11 @@ }, { "attr_name": "temp1_high_threshold", - "drv_attr_name": "temp3_max" + "drv_attr_name": "temp3_crit" }, { "attr_name": "temp1_high_crit_threshold", - "drv_attr_name": "temp3_crit" + "drv_attr_name": "temp3_max" } ] } @@ -15684,11 +15684,11 @@ }, { "attr_name": "temp1_high_threshold", - "drv_attr_name": "temp4_max" + "drv_attr_name": "temp4_crit" }, { "attr_name": "temp1_high_crit_threshold", - "drv_attr_name": "temp4_crit" + "drv_attr_name": "temp4_max" } ] } @@ -15711,11 +15711,11 @@ }, { "attr_name": "temp1_high_threshold", - "drv_attr_name": "temp5_max" + "drv_attr_name": "temp5_crit" }, { "attr_name": "temp1_high_crit_threshold", - "drv_attr_name": "temp5_crit" + "drv_attr_name": "temp5_max" } ] } diff --git a/device/nexthop/x86_64-nexthop_5010-r0/sensors.conf b/device/nexthop/x86_64-nexthop_5010-r0/sensors.conf index 3fd9790c080..b0435675d51 100644 --- a/device/nexthop/x86_64-nexthop_5010-r0/sensors.conf +++ b/device/nexthop/x86_64-nexthop_5010-r0/sensors.conf @@ -15,22 +15,25 @@ chip "nh_tmp468-i2c-10-48" label temp8 "ASIC Diode0 HBM_PHY1 tsen" label temp9 "ASIC Diode0 HBM_PHY2 tsen" - set temp2_max 55 - set temp2_crit 56 - set temp3_max 45 - set temp3_crit 65 - set temp4_max 100 - set temp4_crit 105 - set temp5_max 100 - set temp5_crit 105 - set temp6_max 110 - set temp6_crit 115 - set temp7_max 95 - set temp7_crit 100 - set temp8_max 115 - set temp8_crit 120 - set temp9_max 115 - set temp9_crit 120 + # In HW vs kernel driver, max/crit are swapped. + # max: trigger reboot + # crit: used for fan algo + set temp2_crit 55 + set temp2_max 56 + set temp3_crit 45 + set temp3_max 65 + set temp4_crit 100 + set temp4_max 105 + set temp5_crit 100 + set temp5_max 105 + set temp6_crit 110 + set temp6_max 115 + set temp7_crit 95 + set temp7_max 100 + set temp8_crit 115 + set temp8_max 120 + set temp9_crit 115 + set temp9_max 120 chip "nh_tmp468-i2c-10-49" ignore temp1 @@ -43,23 +46,26 @@ chip "nh_tmp468-i2c-10-49" label temp7 "ASIC Diode1 NIF1 tsen" label temp8 "ASIC Diode1 HBM_PHY1 tsen" label temp9 "ASIC Diode1 HBM_PHY2 tsen" - - set temp2_max 55 - set temp2_crit 56 - set temp3_max 45 - set temp3_crit 65 - set temp4_max 100 - set temp4_crit 105 - set temp5_max 100 - set temp5_crit 105 - set temp6_max 110 - set temp6_crit 115 - set temp7_max 95 - set temp7_crit 100 - set temp8_max 115 - set temp8_crit 120 - set temp9_max 115 - set temp9_crit 120 + + # In HW vs kernel driver, max/crit are swapped. + # max: trigger reboot + # crit: used for fan algo + set temp2_crit 55 + set temp2_max 56 + set temp3_crit 45 + set temp3_max 65 + set temp4_crit 100 + set temp4_max 105 + set temp5_crit 100 + set temp5_max 105 + set temp6_crit 110 + set temp6_max 115 + set temp7_crit 95 + set temp7_max 100 + set temp8_crit 115 + set temp8_max 120 + set temp9_crit 115 + set temp9_max 120 chip "nh_tmp464-i2c-10-4a" label temp2 "Mezz Card Left Rear" @@ -67,14 +73,17 @@ chip "nh_tmp464-i2c-10-4a" label temp4 "Mezz Card Right Rear" label temp5 "Right Upper Port Side Intake" - set temp2_max 55 - set temp2_crit 56 - set temp3_max 45 - set temp3_crit 65 - set temp4_max 55 - set temp4_crit 56 - set temp5_max 45 - set temp5_crit 65 + # In HW vs kernel driver, max/crit are swapped. + # max: trigger reboot + # crit: used for fan algo + set temp2_crit 55 + set temp2_max 56 + set temp3_crit 45 + set temp3_max 65 + set temp4_crit 55 + set temp4_max 56 + set temp5_crit 45 + set temp5_max 65 ignore temp6 ignore temp7 diff --git a/platform/broadcom/sonic-platform-modules-nexthop/common/service/asic-temp-sensor-enable.service b/platform/broadcom/sonic-platform-modules-nexthop/common/service/asic-temp-sensor-enable.service deleted file mode 100644 index 37d575ed46e..00000000000 --- a/platform/broadcom/sonic-platform-modules-nexthop/common/service/asic-temp-sensor-enable.service +++ /dev/null @@ -1,13 +0,0 @@ -[Unit] -Description=Asic temperature sensor enable service -Requires=swss.service pddf-platform-init.service -After=swss.service pddf-platform-init.service -DefaultDependencies=no - -[Service] -Type=oneshot -ExecStart=/usr/local/bin/asic-temp-sensor-enable.py -RemainAfterExit=yes - -[Install] -WantedBy=multi-user.target diff --git a/platform/broadcom/sonic-platform-modules-nexthop/common/sonic_platform/adm1266.py b/platform/broadcom/sonic-platform-modules-nexthop/common/sonic_platform/adm1266.py index 0605216ea46..ff1d00f177b 100644 --- a/platform/broadcom/sonic-platform-modules-nexthop/common/sonic_platform/adm1266.py +++ b/platform/broadcom/sonic-platform-modules-nexthop/common/sonic_platform/adm1266.py @@ -1,48 +1,90 @@ # Copyright 2025 Nexthop Systems Inc. All rights reserved. # SPDX-License-Identifier: Apache-2.0 +"""ADM1266 power management and blackbox data processing. +Provides functionality for reading and processing blackbox fault data from +ADM1266 power management devices, including fault record parsing, reboot +cause determination, and power loss analysis. +""" + +import datetime import json -from typing import List, Dict, Callable, Any +import os +from typing import Any, Callable, Dict, List +from sonic_platform_base.chassis_base import ChassisBase + +# Rendering and formatting helpers -# Rendering helpers (no hardware-width assumptions) +def binw(val: int, width: int) -> str: + """Format value as binary string with specified width. -def binw(val, width): + Args: + val: Integer value to format + width: Number of bits in output + + Returns: + Binary string like "0b00001010" + """ return f"0b{val:0{width}b}" + def hex_value(_key: str, val: int) -> str: + """Format value as hexadecimal string. + + Args: + _key: Field name (unused) + val: Integer value to format + + Returns: + Hexadecimal string like "0x1a" + """ return f"0x{val:x}" -def time_since(_key: str, data: bytes) -> str: + +def default_render(_key: str, val: Any) -> Any: + """Default renderer returning empty string for falsy values. + + Args: + _key: Field name (unused) + val: Value to render + + Returns: + Original value or empty string if falsy """ - Convert an 8-byte ADM1266 blackbox timestamp into a human-readable - elapsed time since power-on, preserving fractional seconds. + return val or "" + - :param data: 8-byte timestamp from ADM1266 - :return: Human-readable string like "0 Day(s) 0 Hour(s) 3 Minute(s) 2.518700 Second(s)" +def time_since(_key: str, data: bytes) -> str: + """Convert ADM1266 8-byte timestamp to human-readable elapsed time. + + Parses the ADM1266 blackbox timestamp format and converts to elapsed + time since power-on with fractional seconds preserved. + + Args: + _key: Field name (unused) + data: 8-byte timestamp from ADM1266 blackbox + + Returns: + Human-readable string like "3 minutes 2.518700 seconds after power-on" + or empty string if data is invalid """ if not isinstance(data, (bytes, bytearray)) or len(data) != 8: return '' - if data == b'\x00' * 8 or data == b'\xff' * 8: + if data in (b'\x00' * 8, b'\xff' * 8): return '' - # Extract integer seconds from bytes [2:6] (little-endian) secs = int.from_bytes(data[2:6], 'little') - - # Extract fractional seconds from bytes [0:2] (16-bit fraction) frac = int.from_bytes(data[0:2], 'little') / 65536.0 - total_seconds = secs + frac - # Compute years, days, hours, minutes, seconds minutes_total, seconds = divmod(total_seconds, 60) hours_total, minutes = divmod(minutes_total, 60) days_total, hours = divmod(hours_total, 24) years, days = divmod(days_total, 365) - # Helper to format singular/plural - def fmt(value, name): + def fmt(value: float, name: str) -> str: if value == 0: return '' return f"{int(value)} {name}" + ('s' if int(value) != 1 else '') @@ -57,12 +99,15 @@ def fmt(value, name): parts.append(f"{seconds:.6f} second" + ('' if abs(seconds - 1.0) < 1e-6 else 's')) return " ".join(parts) + " after power-on" -# Channel naming: derive names from bit positions; use per-key prefix (no fixed widths) +# Channel naming configuration CHANNEL_PREFIX: Dict[str, str] = { 'vhx': 'VH', - 'vp_ov': 'VP', 'vp_uv': 'VP', - 'gpio_in': 'GPIO', 'gpio_out': 'GPIO', - 'pdio_in': 'PDIO', 'pdio_out': 'PDIO', + 'vp_ov': 'VP', + 'vp_uv': 'VP', + 'gpio_in': 'GPIO', + 'gpio_out': 'GPIO', + 'pdio_in': 'PDIO', + 'pdio_out': 'PDIO', } CHANNEL_WIDTH: Dict[str, int] = { @@ -75,10 +120,22 @@ def fmt(value, name): 'pdio_out': 16, } + def channel_names(key: str, value: int) -> str: + """Convert channel bitmask to human-readable channel names. + + Args: + key: Channel type (e.g., 'vhx', 'vp_ov', 'pdio_in') + value: Bitmask representing active channels + + Returns: + Comma-separated channel names with binary representation, + e.g., "VH1,VH3 (0b00000101)" + """ prefix = CHANNEL_PREFIX.get(key) if prefix is None: return hex_value(key, value) + names = [] idx = 1 mask = value @@ -87,85 +144,208 @@ def channel_names(key: str, value: int) -> str: names.append(f"{prefix}{idx}") mask >>= 1 idx += 1 + width = CHANNEL_WIDTH.get(key) - if not len(names): + if not names: return binw(value, width) return ','.join(names) + " (" + binw(value, width) + ")" -# Renderer map: defaults to hex; override specific keys -RENDER: Dict[str, Callable[[str, int], str]] = {} -for k in ['uid','powerup','action','rule','current','last', - 'vhx','vp_ov','vp_uv','gpio_in','gpio_out','pdio_in','pdio_out']: - RENDER[k] = hex_value -RENDER['timestamp'] = time_since -# dpm_fault and power_fault_cause are string labels; render as-is when present +def raw_pretty(_key: str, data: bytes) -> str: + """Format 64-byte blackbox record as hex dump. + + Args: + _key: Field name (unused) + data: 64-byte blackbox data + + Returns: + Multi-line hex dump (8 rows of 8 bytes each) + """ + rows = [] + for i in range(0, 64, 8): + chunk = data[i:i+8] + rows.append(' '.join(f"{b:02x}" for b in chunk)) + return '\n'.join(rows) + +# Field renderer mapping +RENDER: Dict[str, Callable[[str, Any], str]] = {} + +# Numeric fields rendered as hex +for prop in ['uid', 'powerup', 'action', 'rule', 'current', 'last', + 'vhx', 'vp_ov', 'vp_uv', 'gpio_in', 'gpio_out', 'pdio_in', 'pdio_out']: + RENDER[prop] = hex_value + +# Special renderers +RENDER['timestamp'] = time_since RENDER['dpm_fault'] = lambda _k, v: v if isinstance(v, str) else hex_value(_k, v) RENDER['power_fault_cause'] = lambda _k, v: v if isinstance(v, str) else hex_value(_k, v) -RENDER['power_fault_cause'] = lambda _k, v: v if isinstance(v, str) else hex_value(_k, v) +RENDER['raw'] = raw_pretty -# Channel keys use channel_names (more human friendly); keep raw hex available via get_blackbox_records -for k in ['vhx','vp_ov','vp_uv','gpio_in','gpio_out','pdio_in','pdio_out']: +# Channel fields use human-friendly names +for k in ['vhx', 'vp_ov', 'vp_uv', 'gpio_in', 'gpio_out', 'pdio_in', 'pdio_out']: RENDER[k] = channel_names -# Fixed output key order for human-friendly view +# Output field order for display OUTPUT_ORDER = [ - 'fault_uid','powerup','action','rule','current','last', - 'vhx','vp_ov','vp_uv','gpio_in','gpio_out','pdio_in','pdio_out', - 'dpm_fault','power_fault_cause','timestamp' + 'dpm_name', 'fault_uid', 'powerup', 'action', 'rule', 'power_loss', 'current', 'last', + 'vhx', 'vp_ov', 'vp_uv', 'gpio_in', 'gpio_out', 'pdio_in', 'pdio_out', + 'dpm_fault', 'power_fault_cause', 'timestamp', 'raw' ] -def find_power_loss(input_bits: int, output_bits: int, - mapping: Dict[int, Dict[str, Any]]) -> str: - """ - Return a terse rail name (e.g., "POS5V0_S0") if any input bit AND its mapped - output bit are both 1. Otherwise return an empty string. - All bit indices are zero-based. + +def find_voltage_faults(vx_bits: int, mapping: Dict[int, str]) -> str: + """Find power rails that experienced (under/over) voltage faults. + + Args: + vx_bits: Voltage fault bitmask + mapping: Mapping from bit index to rail description + + Returns: + Comma-separated list of affected rail names, or empty string if none """ reason = "" - for in_idx, pdio_desc in mapping.items(): - out_idx = pdio_desc.get("pdio") - desc = pdio_desc.get("rail") - if ((input_bits >> in_idx) & 1) and ((output_bits >> out_idx) & 1): + for vx_idx, rail_desc in mapping.items(): + if (vx_bits >> (vx_idx - 1)) & 1: if reason: reason += ", " - reason += desc + reason += rail_desc return reason -def determine_power_loss(vp_to_pdio_desc: Dict[int, Dict[str, Any]], - vh_to_pdio_desc: Dict[int, Dict[str, Any]], - vh: int, vp_uv: int, pdio_out: int) -> str: - reason = find_power_loss(vh, pdio_out, vh_to_pdio_desc) - if reason: - return reason - return find_power_loss(vp_uv, pdio_out, vp_to_pdio_desc) - -def decode_dpm_fault(dpm_table: Dict[int, str], dpm_bits: Dict[int, int], - pdio_in: int) -> str: - code = 0 - for pdio_bit, fault_pos in dpm_bits.items(): - code |= ((pdio_in >> pdio_bit) & 1) << fault_pos - return dpm_table.get(code, f"code={code}") if code != 0 else "" # empty string for zero - -def decode_power_fault_cause(power_fault_cause: Dict[int, Dict[str, str]], pdio_in: int) -> str: - """Return the first asserted power fault cause description based on pdio_in.""" - # Iterate in the table's order (dict preserves insertion order in Python 3.7+) - for idx, cause_dict in power_fault_cause.items(): - if ((pdio_in >> idx) & 1): - return cause_dict.get("cause") + " (" + cause_dict.get("desc") + ")" - return "" + +def determine_voltage_faults(vpx_to_rail_desc: Dict[int, str], + vhx_to_rail_desc: Dict[int, str], + vhx: int, vp_ov: int, vp_uv: int) -> Dict[str, str]: + """Determine under/over voltage faults from VHx and VPx bits + + Analyzes VH (voltage high) and VP (voltage positive) fault bits to + identify which power rails caused the fault. + + Args: + vpx_to_rail_desc: VPx to rail mapping descriptions + vhx_to_rail_desc: VHx to rail mapping descriptions + vhx: VH fault bitmask + vp_ov: VP overvoltage fault bitmask + vp_uv: VP undervoltage fault bitmask + + Returns: + Dictionary containing a list of under/over voltage faults + """ + vhx_ov_faults = find_voltage_faults(vhx & 0x0F, vhx_to_rail_desc) + vhx_uv_faults = find_voltage_faults(vhx & 0xF0, vhx_to_rail_desc) + + vpx_ov_faults = find_voltage_faults(vp_ov, vpx_to_rail_desc) + vpx_uv_faults = find_voltage_faults(vp_uv, vpx_to_rail_desc) + + ov_faults = [] + if vhx_ov_faults: + ov_faults.append(vhx_ov_faults) + if vpx_ov_faults: + ov_faults.append(vpx_ov_faults) + + faults = {} + if ov_faults: + faults['over_voltage_rails'] = ','.join(ov_faults) + + uv_faults = [] + if vhx_uv_faults: + uv_faults.append(vhx_uv_faults) + if vpx_uv_faults: + uv_faults.append(vpx_uv_faults) + + if uv_faults: + faults['under_voltage_rails'] = ','.join(uv_faults) + return faults + +def is_fault(pdio_in, pdio_mask, pdio_val, gpio_in, gpio_mask, gpio_val): + return (gpio_in & gpio_mask) == gpio_val and (pdio_in & pdio_mask) == pdio_val + +def decode_power_fault_cause(dpm_signal_to_fault_cause: List[Dict[str, Any]], + pdio_in: int, gpio_in: int) -> (str, str, str, str): + """Decode power fault cause from PDIO and GPIO input bits. + + Args: + dpm_signal_to_fault_cause: List of signal pattern to fault cause mappings + pdio_in: PDIO input bitmask + gpio_in: GPIO input bitmask + + Returns: + Tuple of (hw_cause, hw_desc, summary, reboot_cause) as comma-separated strings + """ + hw_cause = [] + hw_desc = [] + summary = [] + reboot_cause = [] + for cause_dict in dpm_signal_to_fault_cause: + if is_fault(pdio_in, cause_dict["pdio_mask"], cause_dict["pdio_value"], + gpio_in, cause_dict["gpio_mask"], cause_dict["gpio_value"]): + hw_cause.append(cause_dict.get("hw_cause")) + hw_desc.append(cause_dict.get("hw_desc")) + summary.append(cause_dict.get("summary")) + reboot_cause.append(cause_dict.get("reboot_cause")) + return ",".join(hw_cause), ",".join(hw_desc), ",".join(summary), ",".join(reboot_cause) + +def reboot_cause_str_to_type(cause: str) -> str: + """Return the cause specific type defined in ChassisBase. + + Args: + cause: Reboot cause string, may be comma-separated for multiple causes + + Returns: + ChassisBase reboot cause constant (takes first if comma-separated) + """ + # Handle comma-separated causes by taking the first one + if ',' in cause: + cause = cause.split(',')[0].strip() + + try: + return getattr(ChassisBase, cause) + except: + return ChassisBase.REBOOT_CAUSE_HARDWARE_OTHER + +def get_reboot_cause_type(reboot_causes): + """ + Choose a suitable reboot cause amongst the available ones + + Args: + reboot_causes: List of reboot causes recorded in DPMs + + Returns: + Chosen reboot cause type + """ + if not reboot_causes: + return ChassisBase.REBOOT_CAUSE_HARDWARE_OTHER + # Pick the first switch_card DPM's cause to report the REBOOT_CAUSE_ value. + # We ensure that there is no loss of information since we display all the + # selected (by earliest record uid) causes of all DPMs in the summary section + # right below the REBOOT_CAUSE_ value and more importantly display all the + # faults recorded in the DPMS in a supplementary command line. So the choice + # of a single cause from amongst many is to satisfy the API return value + # expectation. + reboot_cause = reboot_causes[0] + return reboot_cause_str_to_type(reboot_cause) class Adm1266: - def __init__(self, dpm_info): - self.dpm_info = dpm_info - self.nvmem_path = self.dpm_info.get_nvmem_path() + """ + ADM1266 Power Management Device Interface. + + This class provides methods to read blackbox data, parse fault records, + and determine reboot causes from ADM1266 power management devices. + """ + def __init__(self, platform_spec): + self.platform_spec = platform_spec + self.nvmem_path = self.platform_spec.get_nvmem_path() + + def get_name(self): + """Get the DPM device name.""" + return self.platform_spec.get_name() def read_blackbox(self) -> bytes: """Read the entire blackbox data blob from the nvmem sysfs file""" - with open(self.nvmem_path, 'rb') as f: - return f.read() + with open(self.nvmem_path, 'rb') as file: + return file.read() - def get_fault_record(self, data: bytes) -> Dict: + @staticmethod + def _get_fault_record(data: bytes) -> Dict: """Parse a 64-byte record (ADM1266 Table 79).""" if len(data) != 64: return {} @@ -195,14 +375,14 @@ def u16(off: int) -> int: } return rec - def parse_blackbox(self, data: bytes) -> List[Dict]: + @staticmethod + def _parse_blackbox(data: bytes) -> List[Dict]: """Parse blackbox data and return structured list of valid (non-empty) faults. - - - Skips records that are all 0xFF (erased) or all 0x00 (empty area) - - Uses the 'empty' bit parsed from byte 2 to keep only valid records + - Skips records that are all 0xFF (erased) or all 0x00 (empty area) + - Uses the 'empty' bit parsed from byte 2 to keep only valid records """ faults: List[Dict] = [] - if not len(data): + if not data: return faults fault_size = 64 @@ -213,7 +393,7 @@ def parse_blackbox(self, data: bytes) -> List[Dict]: # Skip cleared and erased records if all(b == 0x00 for b in rec) or all(b == 0xFF for b in rec): continue - fault_record = self.get_fault_record(rec) + fault_record = Adm1266._get_fault_record(rec) if (fault_record['empty'] & 0x01) == 0: fault_record['record_index'] = i faults.append(fault_record) @@ -222,7 +402,7 @@ def parse_blackbox(self, data: bytes) -> List[Dict]: def get_blackbox_records(self) -> List[Dict]: """Get reboot causes from blackbox faults read via sysfs.""" blackbox_data = self.read_blackbox() - faults = self.parse_blackbox(blackbox_data) + faults = Adm1266._parse_blackbox(blackbox_data) records: List[Dict] = [] for fault in faults: @@ -248,109 +428,226 @@ def get_blackbox_records(self) -> List[Dict]: if isinstance(rec_idx, int) and rec_idx >= 0: start = rec_idx * 64 record['raw'] = blackbox_data[start:start+64] - # Decode DPM fault (from pdio_in) and add a terse label - dpm = decode_dpm_fault(self.dpm_info.get_dpm_table(), - self.dpm_info.get_dpm_signals(), - record['pdio_in']) - if dpm: - record['dpm_fault'] = dpm - # Decode Power Fault Cause bits (from pdio_in) and add the first matching description - pf = decode_power_fault_cause(self.dpm_info.get_power_fault_cause(), record['pdio_in']) - if pf: - record['power_fault_cause'] = pf - record['dpm_name'] = self.dpm_info.get_name() + + # Decode Power Fault Cause bits (from pdio_in and gpio_in) + hw_cause, hw_desc, summary, reboot_cause = \ + decode_power_fault_cause(self.platform_spec.get_dpm_signal_to_fault_cause(), + record['pdio_in'], + record['gpio_in']) + if hw_cause: + record['power_fault_cause'] = hw_cause + ' (' + hw_desc + ')' + record['summary'] = summary + record['hw_cause'] = hw_cause + record['reboot_cause'] = reboot_cause + record['dpm_name'] = self.platform_spec.get_name() records.append(record) return records - def get_reboot_causes(self) -> List[Dict]: + def get_all_faults(self) -> List[Dict]: + """ + Return all faults recorded in the DPM + + Returns: + List of dictionaries containing fault information + """ records = self.get_blackbox_records() + # Compute a terse power-loss reason (if any) and attach it + for rec in records: + faults = determine_voltage_faults(self.platform_spec.get_vpx_to_rail_desc(), + self.platform_spec.get_vhx_to_rail_desc(), + rec.get('vhx', 0), + rec.get('vp_ov', 0), + rec.get('vp_uv', 0)) + if faults: + rec.update(faults) + return records + + def clear_blackbox(self): + """Clear the blackbox data by writing to the nvmem path.""" + with open(self.nvmem_path, 'wb') as file: + file.write(b"1") +class Adm1266Display: + """ + Display formatter for ADM1266 fault records. + + This class provides methods to format and render fault records from ADM1266 + devices into human-readable messages for debugging and analysis. + """ + MSG_ORDER = [ + 'dpm_name', 'fault_uid', 'power_loss', 'dpm_fault', 'power_fault_cause', + 'powerup', 'timestamp', 'current', 'last', 'action', + 'rule', 'vhx', 'vp_ov', 'vp_uv', + 'gpio_in', 'gpio_out', 'pdio_in', 'pdio_out', + 'raw', + ] + def __init__(self, faults): + self.faults = faults + + @staticmethod + def _format_fault(fault, is_first_message): + """Format a single fault into a printable message.""" + rendered_items = [] + for key in Adm1266Display.MSG_ORDER: + val = fault.get(key) + if val is None: + continue + if isinstance(val, str) and val in ('', '0x0'): + continue + rendered_items.append((key, val)) + + if not rendered_items: + return "" + + max_key = max(len(k) for k, _ in rendered_items) + lines: List[str] = [] + for key, val in rendered_items: + prefix = f" {key.ljust(max_key)} = " + if isinstance(val, str) and ('\n' in val): + indented = val.replace('\n', '\n' + ' ' * len(prefix)) + lines.append(prefix + indented) + else: + lines.append(prefix + str(val)) + + if not is_first_message: + # Prepend a newline to the first attribute so each block starts on a new line + lines[0] = "\n" + lines[0] + return "\n".join(lines) + + @staticmethod + def _render_faults(faults) -> List[Dict]: + """ + Get formatted DPM fault records from blackbox data. + + Returns: + List of dictionaries containing formatted fault information. + + Example output: + [ + { + 'dpm_name': 'cpu_card', + 'fault_uid': '0x1a3f', + 'powerup': '0x1', + 'action': '0x0', + 'rule': '0x0', + 'power_loss': 'POS5V0_S0, POS3V3_S5', + 'current': '0x0', + 'last': '0x0', + 'vhx': 'VH1,VH3 (0b00000101)', + 'vp_ov': '0b0000000000000000', + 'vp_uv': 'VP1,VP5 (0b0000000000010001)', + 'gpio_in': '0b0000000000000000', + 'gpio_out': '0b0000000000000000', + 'pdio_in': 'PDIO1,PDIO8 (0b0000000010000001)', + 'pdio_out': '0b0000000000000000', + 'dpm_fault': 'VH fault', + 'power_fault_cause': 'PSU input power lost', + 'timestamp': '3 minutes 2.518700 seconds after power-on', + 'raw': '1a 3f 01 00 00 00 05 00\n...' + } + ] + """ rendered: List[Dict] = [] - for rec in records: + for fault in faults: out: Dict[str, str] = {} - out['dpm_name'] = rec.get('dpm_name', '') for key in OUTPUT_ORDER: - renderer = RENDER.get(key, hex_value) - out[key] = renderer(key, rec.get(key, 0)) - # Compute a terse power-loss reason (if any) and attach it - ploss = determine_power_loss(self.dpm_info.get_vp_to_pdio_desc(), - self.dpm_info.get_vh_to_pdio_desc(), - rec.get('vhx', 0), - rec.get('vp_uv', 0), - rec.get('pdio_out', 0)) - if ploss: - out['power_loss'] = ploss - # Add raw 64-byte record as 8 rows of 8 bytes each (hex) - raw = rec.get('raw') - if isinstance(raw, (bytes, bytearray)) and len(raw) == 64: - rows = [] - for i in range(0, 64, 8): - chunk = raw[i:i+8] - rows.append(' '.join(f"{b:02x}" for b in chunk)) - out['raw'] = '\n'.join(rows) + renderer = RENDER.get(key, default_render) + out[key] = renderer(key, fault.get(key, 0)) rendered.append(out) return rendered - def get_reboot_cause(self): - """Return a single string each reboot cause separated by a newline. - It preserves the order from the driver (newest -> oldest). - """ - causes = self.get_reboot_causes() - msg_order = [ - 'dpm_name', 'fault_uid', 'power_loss', 'dpm_fault', 'power_fault_cause', - 'powerup', 'timestamp', 'current', 'last', 'action', - 'rule', 'vhx', 'vp_ov', 'vp_uv', - 'gpio_in', 'gpio_out', 'pdio_in', 'pdio_out', - 'raw', - ] - + def render(self, is_first=False): + """ Render all faults recorded in a DPM into a printable message.""" messages: List[str] = [] - for c in causes: - rendered_items = [] - for k in msg_order: - v = c.get(k) - if v is None: - continue - if isinstance(v, str) and (v == '' or v == '0x0'): - continue - rendered_items.append((k, v)) - if not rendered_items: - messages.append("") - continue - max_key = max(len(k) for k, _ in rendered_items) - lines: List[str] = [] - for k, v in rendered_items: - prefix = f" {k.ljust(max_key)} = " - if isinstance(v, str) and ('\n' in v): - indented = v.replace('\n', '\n' + ' ' * len(prefix)) - lines.append(prefix + indented) - else: - lines.append(prefix + str(v)) - # Prepend a newline to the first attribute so each block starts on a new line - lines[0] = "\n" + lines[0] - messages.append("\n".join(lines)) - if not messages: - return "" - return "\n".join(messages) + rendered_faults = Adm1266Display._render_faults(self.faults) + for fault in rendered_faults: + message = Adm1266Display._format_fault(fault, is_first) + messages.append(message) + return messages - def clear_blackbox(self): - with open(self.nvmem_path, 'w') as f: - f.write("1") +def render_all_faults(all_faults): + """ + Render all faults from multiple DPMs into formatted messages. + + Args: + all_faults: Dictionary mapping DPM names to lists of fault records -def get_reboot_cause(): + Returns: + List of formatted message strings for all faults + """ messages = [] - from sonic_platform.dpm_info import DpmInfo - with open('/usr/share/sonic/platform/pddf/pd-plugin.json') as pd: - pddf_plugin_data = json.load(pd) + for faults in all_faults.values(): + dpm_display = Adm1266Display(faults) + dpm_messages = dpm_display.render(not messages) # Use implicit boolean check + messages += dpm_messages + return messages + +def get_all_faults(pddf_plugin_path=None) -> List[Dict]: + """ + Get all faults recorded in the DPMs. + + Args: + pddf_plugin_path: Optional path to PDDF plugin file. If None, uses default system path. + + Returns: + List of dictionaries containing faults of each DPM. + Among each DPM, the list of faults are sorted by UID (earlier fault comes first). + """ + from sonic_platform.adm1266_platform_spec import Adm1266PlatformSpec # pylint: disable=import-outside-toplevel + if pddf_plugin_path is None: + pddf_plugin_path = '/usr/share/sonic/platform/pddf/pd-plugin.json' + with open(pddf_plugin_path, encoding='utf-8') as pddf_file: + pddf_plugin_data = json.load(pddf_file) + + all_faults = [] adms = pddf_plugin_data.get("DPM", {}) for adm in adms: - dpm_info = DpmInfo(adm, pddf_plugin_data) - adm = Adm1266(dpm_info) - message = adm.get_reboot_cause() - if message: - adm.clear_blackbox() - messages.append(message) - if len(messages): - return "REBOOT_CAUSE_HARDWARE_OTHER", "\n".join(messages) - return "REBOOT_CAUSE_UNKNOWN", "" + platform_spec = Adm1266PlatformSpec(adm, pddf_plugin_data) + dev = Adm1266(platform_spec) + faults = dev.get_all_faults() + if faults: + dev.clear_blackbox() + faults = sorted(faults, key=lambda f: f['fault_uid']) + for fault in faults: + fault['dpm_name'] = dev.get_name() + all_faults.extend(faults) + return all_faults + +def get_reboot_cause(pddf_plugin_path=None) -> tuple[str, str] | None: + """ + Get system reboot cause by analyzing ADM1266 blackbox data. + + Args: + pddf_plugin_path: Optional path to PDDF plugin file. If None, uses default system path. + + Returns: + Tuple of (reboot_cause, debug_message) where reboot_cause is a + ChassisBase.REBOOT_CAUSE_* constant and debug_message contains detailed + fault information. + """ + from sonic_platform.dpm import SystemDPMLogHistory # pylint: disable=import-outside-toplevel + + all_faults = get_all_faults(pddf_plugin_path) + if all_faults: + # Save all_faults history via SystemDPMLogHistory + SystemDPMLogHistory().save('adm1266', all_faults) + # We intentionally do not include rendered fault messages here. + # Return the initial reboot cause and the collected summaries. The per-DPM + # records have been saved to history files which can be loaded and + # rendered separately if more details are needed. + + # Extract causes and summaries from all_faults (which is a list) + causes = [] + summaries = [] + for fault in all_faults: + if 'reboot_cause' in fault: + causes.append(fault['reboot_cause']) + if 'summary' in fault: + summaries.append(fault['summary']) + + reboot_cause = get_reboot_cause_type(causes) + # summaries is a list of strings; coalesce to single debug message + return reboot_cause, ", ".join(summaries) + + return None diff --git a/platform/broadcom/sonic-platform-modules-nexthop/common/sonic_platform/adm1266_platform_spec.py b/platform/broadcom/sonic-platform-modules-nexthop/common/sonic_platform/adm1266_platform_spec.py new file mode 100644 index 00000000000..d3ef490f21c --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-nexthop/common/sonic_platform/adm1266_platform_spec.py @@ -0,0 +1,99 @@ +# Copyright 2025 Nexthop Systems Inc. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +"""ADM1266 platform-specific configuration and mappings. + +Provides platform-specific data for ADM1266 devices including power rail +mappings, fault tables, signal definitions, and device paths. +""" + +from typing import Any, Dict, List + + +class Adm1266PlatformSpec: + """Platform-specific configuration for an ADM1266 device. + + Encapsulates platform-specific data including: + - Power rail to PDIO mappings for voltage monitoring + - DPM fault signals + - Power fault cause descriptions and reboot cause mappings + - NVMEM device path for blackbox data access + + Attributes: + name: Device name identifier + nvmem_path: Path to NVMEM device for blackbox data + vpx_to_rail_desc: VP (voltage positive) to rail mappings + vhx_to_rail_desc: VH (voltage high) to rail mappings + dpm_signal_to_fault_cause: DPM signal pattern to fault cause mappings + """ + + def __init__(self, name: str, pddf_plugin_data: Dict[str, Any]): + """Initialize platform specification from PDDF plugin data. + + Args: + name: Device name identifier + pddf_plugin_data: PDDF plugin data dictionary containing DPM configuration + """ + self.name = name + dpm_info = pddf_plugin_data["DPM"][name] + self.nvmem_path = dpm_info["nvmem_path"] + + self.vpx_to_rail_desc: Dict[int, str] = { + int(k): v for k, v in dpm_info["vpx_to_rail_desc"].items() + } + self.vhx_to_rail_desc: Dict[int, str] = { + int(k): v for k, v in dpm_info["vhx_to_rail_desc"].items() + } + self.dpm_signal_to_fault_cause: List[Dict[str, Any]] = [] + for entry in dpm_info.get("dpm_signal_to_fault_cause", []): + converted = { + "pdio_mask": int(entry["pdio_mask"], 16), + "gpio_mask": int(entry["gpio_mask"], 16), + "pdio_value": int(entry["pdio_value"], 16), + "gpio_value": int(entry["gpio_value"], 16), + "hw_cause": entry["hw_cause"], + "hw_desc": entry["hw_desc"], + "summary": entry["summary"], + "reboot_cause": entry["reboot_cause"] + } + self.dpm_signal_to_fault_cause.append(converted) + + def get_vpx_to_rail_desc(self) -> Dict[int, str]: + """Get VP (voltage positive) to rail descriptions. + + Returns: + Dictionary mapping VP indices to rail descriptions + """ + return self.vpx_to_rail_desc + + def get_vhx_to_rail_desc(self) -> Dict[int, str]: + """Get VH (voltage high) to rail descriptions. + + Returns: + Dictionary mapping VH indices to rail descriptions + """ + return self.vhx_to_rail_desc + + def get_dpm_signal_to_fault_cause(self) -> List[Dict[str, Any]]: + """Get DPM signal pattern to fault cause mappings. + + Returns: + List of signal pattern entries with integer mask/value fields and string fault cause info + """ + return self.dpm_signal_to_fault_cause + + def get_nvmem_path(self) -> str: + """Get NVMEM device path for blackbox data access. + + Returns: + Path to NVMEM device file + """ + return self.nvmem_path + + def get_name(self) -> str: + """Get device name identifier. + + Returns: + Device name string + """ + return self.name diff --git a/platform/broadcom/sonic-platform-modules-nexthop/common/sonic_platform/chassis.py b/platform/broadcom/sonic-platform-modules-nexthop/common/sonic_platform/chassis.py index 81b4edd2ca1..cf8949f60d9 100644 --- a/platform/broadcom/sonic-platform-modules-nexthop/common/sonic_platform/chassis.py +++ b/platform/broadcom/sonic-platform-modules-nexthop/common/sonic_platform/chassis.py @@ -14,9 +14,9 @@ import sys import time +from sonic_platform import adm1266 from sonic_platform.thermal import NexthopFpgaAsicThermal from sonic_platform.watchdog import Watchdog -from sonic_platform.adm1266 import get_reboot_cause try: from sonic_platform_pddf_base.pddf_chassis import PddfChassis @@ -154,34 +154,58 @@ def set_status_led(self, color): def get_status_led(self): return self.get_system_led("SYS_LED") + def _get_sw_reboot_cause(self) -> str | None: + # The presence of reboot-cause.txt with valid content indicates that reboot + # was triggered by software at some point before the current boot. We trust that + # determine-reboot-cause.service will clear the content in this file after + # calling this function. + reboot_cause_path = self.plugin_data.get("REBOOT_CAUSE", {}).get( + "reboot_cause_file", None + ) + if not reboot_cause_path or not os.path.exists(reboot_cause_path): + return None + + with open(reboot_cause_path, "r", errors="replace") as file: + sw_reboot_cause = file.read().strip() + + # We parse the SW cause here, so we can attach the HW events as a minor cause. + # Note: This logic is taken from `determine-reboot-cause`. + if match := re.search(r"User issued '(.*)' command", sw_reboot_cause): + # Normally, it is from one of the reboot scripts, e.g. 'reboot', 'warm-reboot'. + return match.group(1) + elif re.search(r"Kernel Panic", sw_reboot_cause): + return "Kernel Panic" + elif re.search(r"Heartbeat with the Supervisor card lost", sw_reboot_cause): + return "Heartbeat with the Supervisor card lost" + else: + return None + def get_reboot_cause(self): """ Retrieves the cause of the previous reboot Returns: - A tuple (string, string) where the first element is a string - containing the cause of the previous reboot. This string must be - one of the predefined strings in this class. If the first string - is "REBOOT_CAUSE_HARDWARE_OTHER", the second string can be used - to pass a description of the reboot cause. - """ - - # First check for hardware specific causes - hw_cause, hw_description = get_reboot_cause() - if hw_cause != "REBOOT_CAUSE_UNKNOWN": - return (hw_cause, hw_description) - - # Fall back to software reboot cause file - reboot_cause_path = self.plugin_data["REBOOT_CAUSE"]["reboot_cause_file"] - - try: - with open(reboot_cause_path, "r", errors="replace") as fd: - data = fd.read() - sw_reboot_cause = data.strip() - return ("REBOOT_CAUSE_NON_HARDWARE", sw_reboot_cause) - except IOError: - sw_reboot_cause = "Unknown" - return ("REBOOT_CAUSE_UNKNOWN", "Unknown") + (string, string): + (major reboot cause, minor reboot cause). + - major cause can be from either SW or HW. + - minor cause contains all of the HW fault + events from ADM1266 blackbox records since + the last successful boot. + - determine-reboot-cause.service will display + the cause as " ()" + """ + # Always show hardware events for diagnostics, regardless of SW or HW. + # TODO: currently, when SW reboot cause is present, we assume it is + # the major cause. However, we should check based on the timestamp + # whether SW cause or HW cause came first. + sw_cause = self._get_sw_reboot_cause() + hw_cause, all_hw_fault_events = adm1266.get_reboot_cause() or (None, "") + if sw_cause: + return (sw_cause, all_hw_fault_events) + elif hw_cause: + return (hw_cause, all_hw_fault_events) + else: + return ("Unknown", "Unknown") return ('REBOOT_CAUSE_NON_HARDWARE', sw_reboot_cause) diff --git a/platform/broadcom/sonic-platform-modules-nexthop/common/sonic_platform/dpm.py b/platform/broadcom/sonic-platform-modules-nexthop/common/sonic_platform/dpm.py new file mode 100644 index 00000000000..28415fbf68e --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-nexthop/common/sonic_platform/dpm.py @@ -0,0 +1,264 @@ +# Copyright 2025 Nexthop Systems Inc. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +"""Digital Power Manager (DPM) persistence and serialization. + +This module provides device-independent functionality for storing and retrieving +DPM fault records in JSON format on the filesystem. +""" + +import base64 +import datetime +import json +import os +from typing import Any, Dict, List, Optional, Tuple + + +class Serializer: + """Convert DPM fault records to and from JSON-safe format. + + Handles encoding of binary data (bytes) to base64 strings for JSON storage, + and decoding back to original types when loading from disk. + """ + + @staticmethod + def _encode_value(value: Any) -> Any: + """Encode a single value to JSON-safe format. + + Args: + value: Value to encode (bytes, int, float, str, None, or other) + + Returns: + JSON-safe representation (base64 string for bytes, original for primitives) + """ + if isinstance(value, (bytes, bytearray)): + return 'base64:' + base64.b64encode(bytes(value)).decode('ascii') + if isinstance(value, (int, float, str)) or value is None: + return value + return str(value) + + @staticmethod + def _decode_value(value: Any) -> Any: + """Decode a JSON-safe value back to original format. + + Args: + value: JSON-safe value (potentially base64-encoded string) + + Returns: + Original value (bytes for base64 strings, original for others) + """ + if isinstance(value, str) and value.startswith('base64:'): + return base64.b64decode(value[len('base64:'):]) + return value + + @staticmethod + def encode_records(records: List[Dict]) -> List[Dict]: + """Encode a list of fault records to JSON-safe format. + + Args: + records: List of fault record dictionaries + + Returns: + List of JSON-safe record dictionaries + """ + out = [] + for rec in (records or []): + obj = {} + for key, value in (rec or {}).items(): + obj[key] = Serializer._encode_value(value) + out.append(obj) + return out + + @staticmethod + def decode_records(json_records: List[Dict]) -> List[Dict]: + """Decode JSON-safe records back to original format. + + Args: + json_records: List of JSON-safe record dictionaries + + Returns: + List of decoded record dictionaries with original types + """ + out = [] + for rec in (json_records or []): + obj = {} + for key, value in (rec or {}).items(): + obj[key] = Serializer._decode_value(value) + out.append(obj) + return out + + +class SystemDPMLogHistory: + """Manage persistent storage of system-wide DPM fault records. + + Stores fault records in JSON format with automatic retention management. + Each file contains an envelope with metadata and encoded fault records. + + Envelope format: + { + "dpm_type": str, # DPM device type (e.g., "adm1266") + "gen_time": str, # Timestamp in YYYY_MM_DD_HH_MM_SS format + "schema_version": int, # Format version (currently 1) + "records_json": [...] # List of JSON-safe fault records + } + + Attributes: + HISTORY_DIR: Directory path for storing history files + PREVIOUS_FILE: Symlink name pointing to most recent file + RETENTION: Maximum number of history files to retain + """ + HISTORY_DIR = "/host/reboot-cause/nexthop" + PREVIOUS_FILE = "previous-reboot-cause.json" + RETENTION = 10 + + def __init__(self): + """Initialize history manager and load existing files. + + Creates history directory if needed, discovers existing history files, + enforces retention policy, and updates symlink to latest file. + """ + self.prev_link = os.path.join(self.HISTORY_DIR, self.PREVIOUS_FILE) + os.makedirs(self.HISTORY_DIR, exist_ok=True) + + self._history_files = [] + for filename in os.listdir(self.HISTORY_DIR): + if filename.startswith("reboot-cause-") and filename.endswith(".json"): + self._history_files.append(os.path.join(self.HISTORY_DIR, filename)) + self._history_files.sort() + + while len(self._history_files) > self.RETENTION: + self.remove_oldest_history() + + if self._history_files: + self.update_latest_symlink() + + def get_timestamp(self, path: str) -> str: + """Extract timestamp from a history file's envelope. + + Args: + path: Path to history file + + Returns: + Timestamp string from gen_time field, or empty string if not found + """ + envelope = self._load_json_file(path) + return envelope.get('gen_time', '') + + def add_history_file(self, path: str) -> None: + """Add a new history file and enforce retention policy. + + Args: + path: Path to history file to add + """ + self._history_files.append(path) + while len(self._history_files) > self.RETENTION: + self.remove_oldest_history() + + @staticmethod + def _delete_path(path: str) -> None: + """Delete a file, suppressing all errors. + + Args: + path: Path to file to delete + """ + try: + os.remove(path) + except Exception: # pylint: disable=broad-except + pass + + def remove_oldest_history(self) -> Optional[str]: + """Remove the oldest history file from cache and filesystem. + + Returns: + Path of removed file, or None if no files exist + """ + if not self._history_files: + return None + oldest = self._history_files.pop(0) + self._delete_path(oldest) + return oldest + + @staticmethod + def _load_json_file(path: str) -> Dict: + """Load and parse a JSON file. + + Args: + path: Path to JSON file + + Returns: + Parsed JSON dictionary, or empty dict on any error + """ + try: + with open(path, 'r', encoding='utf-8') as file_handle: + return json.load(file_handle) + except Exception: # pylint: disable=broad-except + return {} + + def save(self, dpm_type: str, all_faults: List[Dict]) -> None: + """Save fault records to a new history file. + + Creates a timestamped file with an envelope containing the DPM type + and encoded fault records. Updates the symlink and enforces retention. + + Args: + dpm: DPM device type identifier (e.g., "adm1266") + all_faults: List of fault record dictionaries to save + """ + timestamp = datetime.datetime.utcnow().strftime('%Y_%m_%d_%H_%M_%S') + filename = os.path.join(self.HISTORY_DIR, f"reboot-cause-{timestamp}.json") + + envelope = { + 'dpm_type': dpm_type, + 'gen_time': timestamp, + 'schema_version': 1, + 'records_json': Serializer.encode_records(all_faults), + } + + with open(filename, 'w', encoding='utf-8') as file_handle: + json.dump(envelope, file_handle, ensure_ascii=False) + + self.add_history_file(filename) + self.update_latest_symlink() + + def update_latest_symlink(self) -> None: + """Update symlink to point to the most recent history file.""" + if not self._history_files: + return + + if os.path.exists(self.prev_link) or os.path.islink(self.prev_link): + os.remove(self.prev_link) + + os.symlink(self._history_files[-1], self.prev_link) + + def load(self) -> Tuple[Optional[str], List[Dict]]: + """Load fault records from the most recent history file. + + Returns: + Tuple of (dpm_type, records) where: + - dpm_type: DPM device type string, or None if file invalid + - records: List of decoded fault record dictionaries + """ + return self.load_file(self.prev_link) + + def load_file(self, path: str) -> Tuple[Optional[str], List[Dict]]: + """Load fault records from a specific history file. + + Args: + path: Path to history file to load + + Returns: + Tuple of (dpm_type, records) where: + - dpm_type: DPM device type string, or None if file invalid + - records: List of decoded fault record dictionaries + """ + envelope = self._load_json_file(path) + if not isinstance(envelope, dict): + return (None, []) + + dpm_type = envelope.get('dpm_type') + records_json = envelope.get('records_json') + + if not isinstance(records_json, list): + return (dpm_type, []) + + return (dpm_type, Serializer.decode_records(records_json)) diff --git a/platform/broadcom/sonic-platform-modules-nexthop/common/sonic_platform/dpm_info.py b/platform/broadcom/sonic-platform-modules-nexthop/common/sonic_platform/dpm_info.py deleted file mode 100644 index 7eeefc594cf..00000000000 --- a/platform/broadcom/sonic-platform-modules-nexthop/common/sonic_platform/dpm_info.py +++ /dev/null @@ -1,47 +0,0 @@ -# Copyright 2025 Nexthop Systems Inc. All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -from typing import Dict, Any - -class DpmInfo: - def __init__(self, name, pddf_plugin_data): - self.name = name - dpm_info = pddf_plugin_data["DPM"][name] - self.nvmem_path = dpm_info["nvmem_path"] - - self.vp_to_pdio_desc: Dict[int, Dict[str, Any]] = { - int(k): v for k, v in dpm_info["vp_to_pdio_desc"].items() - } - self.vh_to_pdio_desc: Dict[int, Dict[int, Any]] = { - int(k): v for k, v in dpm_info["vh_to_pdio_desc"].items() - } - self.dpm_signals: Dict[int, int] = { - int(k): v for k, v in dpm_info["dpm_signals"].items() - } - self.dpm_table: Dict[int, str] = { - int(k): v for k, v in dpm_info["dpm_table"].items() - } - self.power_fault_cause: Dict[int, Dict[str, str]] = { - int(k): v for k, v in dpm_info["power_fault_cause"].items() - } - - def get_vp_to_pdio_desc(self): - return self.vp_to_pdio_desc - - def get_vh_to_pdio_desc(self): - return self.vh_to_pdio_desc - - def get_dpm_signals(self): - return self.dpm_signals - - def get_dpm_table(self): - return self.dpm_table - - def get_power_fault_cause(self): - return self.power_fault_cause - - def get_nvmem_path(self): - return self.nvmem_path - - def get_name(self): - return self.name diff --git a/platform/broadcom/sonic-platform-modules-nexthop/common/sonic_platform/thermal.py b/platform/broadcom/sonic-platform-modules-nexthop/common/sonic_platform/thermal.py index 57ab0a18d2a..6a14ceda20c 100644 --- a/platform/broadcom/sonic-platform-modules-nexthop/common/sonic_platform/thermal.py +++ b/platform/broadcom/sonic-platform-modules-nexthop/common/sonic_platform/thermal.py @@ -4,18 +4,17 @@ # SPDX-License-Identifier: Apache-2.0 import abc +import re +import threading import time from nexthop import fpga_lib -from sonic_platform.syslog import SYSLOG_IDENTIFIER_THERMAL +from sonic_platform_base.thermal_base import ThermalBase +from sonic_platform_pddf_base.pddf_thermal import PddfThermal from sonic_py_common import syslogger -try: - from sonic_platform_base.thermal_base import ThermalBase - from sonic_platform_pddf_base.pddf_thermal import PddfThermal - from sonic_platform_base.thermal_base import ThermalBase -except ImportError as e: - raise ImportError(str(e) + "- required module not found") +from swsscommon import swsscommon +from sonic_platform.syslog import SYSLOG_IDENTIFIER_THERMAL # Nexthop FPGA thermal sensor value to Celsius conversion TYPE_TO_CELSIUS_LAMBDA_DICT = { @@ -25,6 +24,76 @@ thermal_syslogger = syslogger.SysLogger(SYSLOG_IDENTIFIER_THERMAL) +def _intf_name_key(intf_name): + """Convert interface name to key for sorting""" + match = re.match(r"Ethernet(\d+)", intf_name) + if match: + return int(match.group(1)) + return None + + +class PortIndexMapper: + """Singleton class for mapping port index to interface name from CONFIG_DB PORT table""" + _instance = None + _lock = threading.Lock() + + def __new__(cls): + if cls._instance is None: + with cls._lock: + if cls._instance is None: + cls._instance = super(PortIndexMapper, cls).__new__(cls) + cls._instance._initialized = False + return cls._instance + + def __init__(self): + if self._initialized: + return + self._initialized = True + self._port_index_to_interface = {} + self._mapping_lock = threading.RLock() + + def _build_mapping(self): + """Build port index to interface mapping from CONFIG_DB""" + with self._mapping_lock: + cfg_db = swsscommon.SonicV2Connector(use_unix_socket_path=True) + cfg_db.connect(cfg_db.CONFIG_DB) + # Get the underlying DBConnector for swsscommon.Table + db_connector = cfg_db.get_redis_client(cfg_db.CONFIG_DB) + port_tbl = swsscommon.Table(db_connector, swsscommon.CFG_PORT_TABLE_NAME) + + self._port_index_to_interface.clear() + + for intf_name in port_tbl.getKeys(): + (status, port_data) = port_tbl.get(intf_name) + if not status: + continue + + port_dict = dict(port_data) + port_index = port_dict.get('index') + try: + port_index = int(port_index) + except (ValueError, TypeError): + continue + + dict_intf = self._port_index_to_interface.get(port_index) + dict_intf_key = float("inf") if dict_intf is None else _intf_name_key(dict_intf) + db_intf_key = _intf_name_key(intf_name) + if db_intf_key is None: + continue + + # Map to lowest interface name for this port index + if db_intf_key < dict_intf_key: + self._port_index_to_interface[port_index] = intf_name + + def get_interface_name(self, port_index): + """Get interface name by port index""" + with self._mapping_lock: + port_index = int(port_index) + if port_index not in self._port_index_to_interface: + self._build_mapping() + return self._port_index_to_interface.get(port_index) + + class PidThermalMixin(abc.ABC): DEFAULT_PID_SETPOINT_MARGIN = 10.0 @@ -242,18 +311,27 @@ class SfpThermal(ThermalBase, MinMaxTempMixin, PidThermalMixin): """SFP thermal interface class""" THRESHOLDS_CACHE_INTERVAL_SEC = 5 MIN_VALID_SETPOINT = 30.0 - DEFAULT_SETPOINT = 65.0 + DEFAULT_SETPOINT = 62.0 def __init__(self, sfp, pddf_data): - ThermalBase.__init__(self) - MinMaxTempMixin.__init__(self) - PidThermalMixin.__init__(self, pddf_data.data['PLATFORM']) self._sfp = sfp self._min_temperature = None self._max_temperature = None self._threshold_info = {} self._threshold_info_time = 0 self._invalid_setpoint_logged = False + self._state_db = None + ThermalBase.__init__(self) + MinMaxTempMixin.__init__(self) + PidThermalMixin.__init__(self, pddf_data.data["PLATFORM"]) + + def __del__(self): + """Cleanup database connection when object is destroyed""" + if self._state_db: + try: + self._state_db.close(self._state_db.STATE_DB) + except (AttributeError, ConnectionError, OSError): + pass # Ignore errors during cleanup def get_name(self): return f"Transceiver {self._sfp.get_name().capitalize()}" @@ -262,6 +340,8 @@ def get_presence(self): presence = self._sfp.get_presence() if not presence: self._threshold_info = {} + self._threshold_info_time = 0 + self._invalid_setpoint_logged = False return presence def get_model(self): @@ -289,6 +369,13 @@ def get_temperature(self): self._update_min_max_temp(temp) return temp + def _get_state_db(self): + """Connect to STATE_DB if not already connected""" + if not self._state_db: + self._state_db = swsscommon.SonicV2Connector(use_unix_socket_path=True) + self._state_db.connect(self._state_db.STATE_DB) + return self._state_db + def maybe_update_threshold_info(self): time_elapsed = time.monotonic() - self._threshold_info_time if time_elapsed < self.THRESHOLDS_CACHE_INTERVAL_SEC: @@ -296,10 +383,29 @@ def maybe_update_threshold_info(self): self._threshold_info_time = time.monotonic() if not self.get_presence(): return - self._threshold_info = self._sfp.get_transceiver_threshold_info() or {} - # SFP driver may return "N/A" for unsupported fields. Rest of the thermal code expects None in this case. - self._threshold_info = { k : (None if isinstance(v, str) else v) - for k, v in self._threshold_info.items() } + + self._state_db = self._get_state_db() + port_mapper = PortIndexMapper() + intf_name = port_mapper.get_interface_name(self._sfp.get_position_in_parent()) + if not intf_name: + thermal_syslogger.log_warning(f"Failed to get interface name for port {self._sfp.get_position_in_parent()}" + ". Threshold information will not be available.") + return + + threshold_key = f"TRANSCEIVER_DOM_THRESHOLD|{intf_name}" + threshold_data = self._state_db.get_all(self._state_db.STATE_DB, threshold_key) + + if threshold_data: + # Convert string values to float, handle "N/A" and invalid values + self._threshold_info = {} + for key, value in threshold_data.items(): + if isinstance(value, str) and value.lower() in ['n/a', 'none', '']: + self._threshold_info[key] = None + else: + try: + self._threshold_info[key] = float(value) + except (ValueError, TypeError): + self._threshold_info[key] = None def get_high_threshold(self): self.maybe_update_threshold_info() @@ -338,11 +444,16 @@ def get_maximum_recorded(self): # Make sure temp is recorded at least once. self.get_temperature() return MinMaxTempMixin.get_maximum_recorded(self) - + def get_pid_setpoint(self): setpoint = super().get_pid_setpoint() if setpoint is None: - return setpoint + if self.get_presence(): + # Threshold info may be a little bit delayed as it is read by xcvrd. Start with a default setpoint + # until thresholds are available. + return self.DEFAULT_SETPOINT + else: + return setpoint # Setpoint cannot be guaranteed on pluggables - some modules may have invalid values such as 0. # For these cases, use a default setpoint. if setpoint < self.MIN_VALID_SETPOINT: diff --git a/platform/broadcom/sonic-platform-modules-nexthop/common/utils/asic-temp-sensor-enable.py b/platform/broadcom/sonic-platform-modules-nexthop/common/utils/asic-temp-sensor-enable.py deleted file mode 100755 index 1b4016958a1..00000000000 --- a/platform/broadcom/sonic-platform-modules-nexthop/common/utils/asic-temp-sensor-enable.py +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/python3 - -from swsscommon.swsscommon import SonicV2Connector -from sonic_py_common import logger - -INTERVAL_SECONDS = '10' - -LOG_TAG = "asic_temp_sensor_enable" -log = logger.Logger(LOG_TAG) -log.set_min_log_priority_info() - -log.log_info("Enabling asic temperature sensor polling") - -db = SonicV2Connector() -db.connect(db.CONFIG_DB) - -if db.get(db.CONFIG_DB, "ASIC_SENSORS|ASIC_SENSORS_POLLER_STATUS", 'admin_status') != 'enable': - log.log_info("Enabling asic temperature sensor polling") - db.set(db.CONFIG_DB, "ASIC_SENSORS|ASIC_SENSORS_POLLER_STATUS", 'admin_status', 'enable') -else: - log.log_warning("Asic temperature sensor polling is already enabled") - -if db.get(db.CONFIG_DB, "ASIC_SENSORS|ASIC_SENSORS_POLLER_INTERVAL", 'interval') != INTERVAL_SECONDS: - log.log_info(f"Setting asic temperature sensor polling interval to {INTERVAL_SECONDS} seconds") - db.set(db.CONFIG_DB, "ASIC_SENSORS|ASIC_SENSORS_POLLER_INTERVAL", 'interval', INTERVAL_SECONDS) -else: - log.log_info(f"Asic temperature sensor polling interval is already set to {INTERVAL_SECONDS} seconds") diff --git a/platform/broadcom/sonic-platform-modules-nexthop/common/utils/nh_reboot_cause b/platform/broadcom/sonic-platform-modules-nexthop/common/utils/nh_reboot_cause new file mode 100755 index 00000000000..2edde929e45 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-nexthop/common/utils/nh_reboot_cause @@ -0,0 +1,97 @@ +#!/usr/bin/env python3 +"""Nexthop reboot-cause display utility. + +Displays reboot-cause information from saved DPM fault records. +Reads persisted JSON files only - no device access or recomputation. +""" + +import os +import click +from typing import List + +from sonic_platform.adm1266 import Adm1266Display +from sonic_platform.dpm import SystemDPMLogHistory + + +@click.command() +@click.option('--history', is_flag=True, + help='Show history of all saved reboot-cause records') +def reboot_cause(history: bool) -> None: + """Show reboot-cause information from DPM fault records. + + By default, displays the most recent reboot-cause. + Use --history to show all saved historical records. + """ + if history: + show_history() + else: + show_current() + + +def show_current() -> None: + """Display the most recent reboot-cause from saved data.""" + dpm_type, records = SystemDPMLogHistory().load() + + if not records: + click.echo("No reboot-cause records found") + return + + if dpm_type != "adm1266": + click.echo(f"Error: Unsupported DPM type '{dpm_type}' (expected 'adm1266')") + return + + messages = Adm1266Display(records).render(is_first=True) + for msg in messages: + if msg: + click.echo(msg) + + +def show_history() -> None: + """Display reboot-cause history with most recent entry first.""" + history = SystemDPMLogHistory() + files: List[str] = list(getattr(history, '_history_files', [])) + + if not files: + click.echo("No reboot-cause history found") + return + + # Determine the current (most recent) file + latest = None + if os.path.exists(history.prev_link) or os.path.islink(history.prev_link): + try: + latest = os.path.realpath(history.prev_link) + except Exception: + pass + + # Build display order: current first, then remaining files newest to oldest + ordered: List[str] = [] + if latest and latest in files: + ordered.append(latest) + + for path in reversed(files): + if path != latest: + ordered.append(path) + + # Display each history entry + is_first = True + for path in ordered: + timestamp = history.get_timestamp(path) + click.echo(f"Logs recorded at {timestamp}") + + dpm_type, records = history.load_file(path) + if not records: + continue + + if dpm_type != "adm1266": + click.echo(f" Warning: Unsupported DPM type '{dpm_type}' (skipping)") + continue + + messages = Adm1266Display(records).render(is_first=is_first) + for msg in messages: + if msg: + click.echo(msg) + is_first = False + + +if __name__ == '__main__': + reboot_cause() diff --git a/platform/broadcom/sonic-platform-modules-nexthop/debian/rules b/platform/broadcom/sonic-platform-modules-nexthop/debian/rules index 3f57ad2a32c..3fc45d3eb7f 100755 --- a/platform/broadcom/sonic-platform-modules-nexthop/debian/rules +++ b/platform/broadcom/sonic-platform-modules-nexthop/debian/rules @@ -40,6 +40,7 @@ override_dh_auto_build: set -e; \ if [ -d $(MOD_SRC_DIR)/$${mod}/modules ]; then \ make -C $(KERNEL_BUILD) M=$(MOD_SRC_DIR)/$${mod}/modules; \ + ./sign-modules.sh $(MOD_SRC_DIR)/$${mod}/modules; \ fi; \ done) python3 setup.py bdist_wheel -d $(MOD_SRC_DIR) diff --git a/platform/broadcom/sonic-platform-modules-nexthop/debian/sonic-platform-nexthop-4010-r0.install b/platform/broadcom/sonic-platform-modules-nexthop/debian/sonic-platform-nexthop-4010-r0.install deleted file mode 100644 index 065157729df..00000000000 --- a/platform/broadcom/sonic-platform-modules-nexthop/debian/sonic-platform-nexthop-4010-r0.install +++ /dev/null @@ -1,2 +0,0 @@ -sonic_platform-1.0-py3-none-any.whl usr/share/sonic/device/x86_64-nexthop_4010-r0/pddf -nh-4010/utils/system_powercycle usr/lib/systemd/system-shutdown diff --git a/platform/broadcom/sonic-platform-modules-nexthop/debian/sonic-platform-nexthop-4010-r1.install b/platform/broadcom/sonic-platform-modules-nexthop/debian/sonic-platform-nexthop-4010-r1.install deleted file mode 100644 index c041b35e02a..00000000000 --- a/platform/broadcom/sonic-platform-modules-nexthop/debian/sonic-platform-nexthop-4010-r1.install +++ /dev/null @@ -1,2 +0,0 @@ -sonic_platform-1.0-py3-none-any.whl usr/share/sonic/device/x86_64-nexthop_4010-r1/pddf -nh-4010/utils/system_powercycle usr/lib/systemd/system-shutdown diff --git a/platform/broadcom/sonic-platform-modules-nexthop/debian/sonic-platform-nexthop-4020-r0.install b/platform/broadcom/sonic-platform-modules-nexthop/debian/sonic-platform-nexthop-4020-r0.install deleted file mode 100644 index 462da9f2b02..00000000000 --- a/platform/broadcom/sonic-platform-modules-nexthop/debian/sonic-platform-nexthop-4020-r0.install +++ /dev/null @@ -1,2 +0,0 @@ -sonic_platform-1.0-py3-none-any.whl usr/share/sonic/device/x86_64-nexthop_4020-r0/pddf -nh-4010/utils/system_powercycle usr/lib/systemd/system-shutdown diff --git a/platform/broadcom/sonic-platform-modules-nexthop/nh-4010/utils/system_powercycle b/platform/broadcom/sonic-platform-modules-nexthop/nh-4010/utils/system_powercycle deleted file mode 100755 index ed2b7f0dc3b..00000000000 --- a/platform/broadcom/sonic-platform-modules-nexthop/nh-4010/utils/system_powercycle +++ /dev/null @@ -1,65 +0,0 @@ -#!/usr/bin/python3 - -import sys -import time - -from nexthop import fpga_lib, pcie_lib -from sonic_py_common import logger - -REBOOT_DELAY_MS = 1000 -REBOOT_ENABLE = 0xdeadbeef -SWITCHCARD_REBOOT_REG_OFFSET = 0x4 -CPU_REBOOT_REG_OFFSET = 0x8 - -sonic_logger = logger.Logger("platform_reboot") -sonic_logger.set_min_log_priority_info() - -def log_error(msg: str): - sonic_logger.log_error(msg) - -def main(): - switchcard_fpga_bdf = pcie_lib.get_switchcard_fpga_bdf() - try: - sonic_logger.log_info("Writing to power cycle control register to initiate reboot") - fpga_lib.write_32( - switchcard_fpga_bdf, - SWITCHCARD_REBOOT_REG_OFFSET, - REBOOT_ENABLE, - ) - except Exception as e: - log_error( - "Error writing to power cycle control register on switchcard FPGA" - f" {switchcard_fpga_bdf}: {str(e)}, trying CPU FPGA" - ) - time.sleep(REBOOT_DELAY_MS / 1000) - - cpu_card_fpga_bdf = pcie_lib.get_cpu_card_fpga_bdf() - try: - fpga_lib.write_32( - cpu_card_fpga_bdf, - CPU_REBOOT_REG_OFFSET, - REBOOT_ENABLE - ) - except Exception as e: - log_error( - "Error writing to power cycle control register on CPU FPGA" - f" {cpu_card_fpga_bdf}: {str(e)}" - ) - return 2 - time.sleep(REBOOT_DELAY_MS / 1000) - - # If we reach here, we silently failed to reboot the dataplane! - log_error( - "Failed to initiate reboot, the control plane will reboot and" - " leave the dataplane in an undefined state" - ) - return 1 - -if __name__ == "__main__": - # Systemd calls this script with one of 4 arguments. "poweroff" and "halt" we don't expect. - # A cold reboot will pass "reboot". In the first 3 cases, we continue with the powercycle. - # Warm reboots will use kexec and will pass "kexec" as the first argument, therefore we - # must skip the powercycle in that case. - if len(sys.argv) > 1 and sys.argv[1] == "kexec": - sys.exit(0) - sys.exit(main()) diff --git a/platform/broadcom/sonic-platform-modules-nexthop/nh-4010/utils/transceiver_init.sh b/platform/broadcom/sonic-platform-modules-nexthop/nh-4010/utils/transceiver_init.sh deleted file mode 100755 index c20c81b83d1..00000000000 --- a/platform/broadcom/sonic-platform-modules-nexthop/nh-4010/utils/transceiver_init.sh +++ /dev/null @@ -1,74 +0,0 @@ -#!/bin/bash - -# Transceiver initialization script for NH-4010 -# This script deasserts reset and disables low power mode for all OSFP transceivers - -SYSLOG_IDENTIFIER="transceiver-init" -MAX_WAIT_TIME=30 # Maximum time to wait for transceiver control in seconds -XCVR_OSFP_I2C_BUSES_START=23 # Starting I2C bus number for OSFP transceivers -XCVR_OSFP_COUNT=64 # Number of OSFP transceivers - -log_info() { - logger -p info -t "${SYSLOG_IDENTIFIER}" "$@" -} - -log_error() { - logger -p err -t "${SYSLOG_IDENTIFIER}" "$@" -} - -wait_for() { - local function="$1" - local max_wait_time="$2" - local description="$3" - local start_time=$(date +%s) - local elapsed_time=0 - - log_info "Waiting for ${description}." - for ((elapsed_time=0; elapsed_time "/sys/bus/i2c/devices/${bus}-0008/xcvr_reset"; then - log_error "Failed to disable xcvr reset for bus ${bus}." - status=1 - continue - fi - if ! echo 0 > "/sys/bus/i2c/devices/${bus}-0008/xcvr_lpmode"; then - log_error "Failed to disable xcvr low power mode for bus ${bus}." - status=1 - continue - fi - done - return $status -} - - -log_info "Starting transceiver initialization" -wait_for is_xcvr_control_available "$MAX_WAIT_TIME" "transceiver control" || exit 1 -init_xcvrs || exit 1 -log_info "Transceiver initialization completed successfully" -exit 0 diff --git a/platform/broadcom/sonic-platform-modules-nexthop/sign-modules.sh b/platform/broadcom/sonic-platform-modules-nexthop/sign-modules.sh new file mode 100755 index 00000000000..36abab32fc2 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-nexthop/sign-modules.sh @@ -0,0 +1,99 @@ +#!/bin/bash +# This script is intended to be called during platform module building in order +# to sign any kernel modules with the necessary secureboot keys. Platform +# modules are packed into .deb files so aren't caught by the normal signing +# procedure. This script simply calls into the pre-existing scripts used for +# signing. +# +# The exception is when "${SECURE_UPGRADE_MODE}" is not specified, it will look +# for dev-keys/non-production.crt and dev-keys/non-production.key and call the +# kernel's sign-file directly. Please note this logic is for Nexthop-internal +# development purposes only and these keys do not normally exist and this path +# is not expected to be used outside of Nexthop. +# +# When the environment variable SECURE_UPGRADE_MODE is "prod" or "dev", this +# depends on these environment variables: +# From rules/config: +# SECURE_UPGRADE_SIGNING_CERT +# dev-only: +# SECURE_UPGRADE_DEV_SIGNING_KEY +# prod-only: +# SECURE_UPGRADE_PROD_SIGNING_TOOL +# SECURE_UPGRADE_PROD_TOOL_ARGS +# Passed in from configuration/build: +# CONFIGURED_ARCH +# KVERSION +# From slave.mk +# PROJECT_ROOT - base path for source +# BUILD_WORKDIR - base build path (typically same as PROJECT_ROOT) +# +# This script takes a single command line argument, the path to recursively +# search for kernel modules. + +die() { + echo "$*" + exit 1 +} + +if [ "${SECURE_UPGRADE_MODE}" = "dev" ]; then + ${PROJECT_ROOT}/scripts/signing_kernel_modules.sh -l ${KVERSION} -c ${SECURE_UPGRADE_SIGNING_CERT} -p ${SECURE_UPGRADE_DEV_SIGNING_KEY} -k ${1} || die "Kernel module signing failed (dev)" +elif [ "${SECURE_UPGRADE_MODE}" = "prod" ]; then + ${PROJECT_ROOT}/${SECURE_UPGRADE_PROD_SIGNING_TOOL} ${SECURE_UPGRADE_PROD_TOOL_ARGS} -a ${CONFIGURED_ARCH} -l ${KVERSION} -r ${1} || die "Kernel module signing failed (prod)" +elif [ "${SECURE_UPGRADE_MODE}" = "no_sign" ]; then + # Do nothing + echo "No kernel module signing requested" +else + # Signing for Nexthop kernel module development. + # + # This is only used during development of the kernel modules themselves for + # quick iteration as the kernel may be built with Secureboot enabled to + # ensure Linux "lockdown" mode is properly honored. + # + # Sign using a local key and certificate trusted by the development + # environment. This method is never used for full SONiC image builds, + # regardless if this is for Development or Production. + # + # Requires: + # * dev-keys/non-production.key and dev-keys/non-production.crt + # * /usr/lib/linux-kbuild-${KVERSION}/scripts/sign-file + FILESYSTEM_ROOT=fsroot + + echo " ** ATTEMPTING DEVELOPMENT-ONLY KERNEL MODULE SIGNING **" + + script_path=`dirname $0` + if [ "${script_path}" != "" ] ; then + script_path="${script_path}/" + fi + + keypath="${script_path}./dev-keys/non-production.key" + certpath="${script_path}./dev-keys/non-production.crt" + if [ ! -f "${keypath}" -o ! -f "${certpath}" ] ; then + die "Could not find ${keypath} or ${certpath}" + fi + + KVER="$(echo ${KVERSION} | cut -d '.' -f 1)"."$(echo ${KVERSION} | cut -d '.' -f 2)" + sign_file="${BUILD_WORKDIR}/${FILESYSTEM_ROOT}/usr/lib/linux-kbuild-${KVER}/scripts/sign-file" + if [ ! -x "${sign_file}" ] ; then + # Fallback for building on-DUT + sign_file="/usr/lib/linux-kbuild-${KVER}/scripts/sign-file" + if [ ! -x "${sign_file}" ] ; then + die "Could not find ${sign_file}" + fi + fi + + # Sign the modules + modules_list=$(find ${1} -name "*.ko") + # Do sign for each found module + cnt=0 + for mod in $modules_list ; do + echo "signing module ${mod} ..." + ${sign_file} sha512 ${keypath} ${certpath} ${mod} || die "failed to sign ${mod}" + cnt=$((cnt+1)) + done + + if [ "$cnt" = "0" ] ; then + die "No kernel modules found" + fi + + echo "${cnt} modules signed" +fi diff --git a/platform/broadcom/sonic-platform-modules-nexthop/test/fixtures/fixtures_unit_test.py b/platform/broadcom/sonic-platform-modules-nexthop/test/fixtures/fixtures_unit_test.py index 4a33f27d18e..b8faaadc456 100644 --- a/platform/broadcom/sonic-platform-modules-nexthop/test/fixtures/fixtures_unit_test.py +++ b/platform/broadcom/sonic-platform-modules-nexthop/test/fixtures/fixtures_unit_test.py @@ -27,7 +27,7 @@ def __init__(self, pddf_data=None, pddf_plugin_data=None): self._watchdog = None self._eeprom = Mock() self._eeprom.modelstr = Mock(return_value="Test Model") - self.plugin_data = {'REBOOT_CAUSE': {'reboot_cause_file': '/tmp/test_reboot_cause'}} + self.plugin_data = pddf_plugin_data or {'REBOOT_CAUSE': {'reboot_cause_file': '/tmp/test_reboot_cause'}} def get_all_sfps(self): return self._sfp_list @@ -69,114 +69,207 @@ def parse_hexdump_lines(lines): return blackbox_data, expected_records, expected_causes -class DpmInfoMock: - def __init__(self): - # Carelessly made up stuff - Not accurate for any HW platform - - self.dpm_signals = { - 1 : 2, # PDIO bit 0 - Fault code bit 2 - 14 : 0, # PDIO bit 13 - Fault code bit 0 - 15 : 1 # PDIO bit 14 - Fault code bit 1 - } - self.dpm_table = { - 0 : "", - 1 : "THERMTRIP_L: CPU has exceeded Tdie,shutdown", - 2 : "CPU_PWR_CYC_REQ", - 3 : "BMC_PWR_CYC_REQ", - 4 : "FPGA_PWR_CYC_REQ", - 5 : "Switch Card CP power bad" - } - self.power_fault_cause = { - 0: ("PSU_VIN_LOSS", "Both PSUs lost input power"), # PDIO1 (0) - 1: ("OVER_TEMP", "Switch card temp sensor OT)"), # PDIO2 (1) - 2: ("CPU_PWR_BAD", "CPU card power bad"), # PDIO3 (2) - 3: ("WACHDOG", "FPGA watchdog expired"), # PDIO4 (3) - 4: ("ASIC_OT", "ASIC MAX_TEMP exceeded OT threshold"), # PDIO5 (4) - 5: ("NO_FAN_PRSNT", "All 4 fans have same ID=0xf"), # PDIO6 (5) - 6: ("CMD_PWR_CYC", "Software commanded power cycle"), # PDIO7 (6) - 7: ("DP_PWR_ON", "P2 only: from shift chain; not used on P1"), # PDIO8 (7) - 9: ("FPGA_CMD_PCYC", "FPGA commanded power cycle"), # PDIO10 (9) - 10:("CMD_ASIC_PWR_OFF", "FPGA command ASIC power off"), # PDIO11 (10) - } - - self.vp_to_pdio_desc = { - 5: { "pdio": 2, "rail": "POS0V75_S5" }, # VP6 -> PDIO3 - 6: { "pdio": 3, "rail": "POS1V8_S5" }, # VP7 -> PDIO4 - 7: { "pdio": 4, "rail": "POS3V3_S5" }, # VP8 -> PDIO5 - 8: { "pdio": 6, "rail": "POS1V1_S0" }, # VP9 -> PDIO7 - 9: { "pdio": 7, "rail": "POS0V78_S0" }, # VP10 -> PDIO8 - 10: { "pdio": 8, "rail": "POS0V75_S0" }, # VP11 -> PDIO9 - 11: { "pdio": 9, "rail": "POS1V8_S0" }, # VP12 -> PDIO10 - 12: { "pdio": 10, "rail": "POS3V3_S0" }, # VP13 -> PDIO11 - } - - self.vh_to_pdio_desc = { - 4: { "pdio": 5, "rail": "POS5V0_S0" }, # VH4_UV (bit 4) -> PDIO6 (bit 5) +class Adm1266PlatformSpecMock: + pddf_plugin_data = { + "DPM": { + "dpm-mock": { + "dpm_signal_to_fault_cause": [ + { + "pdio_mask": "0x0001", + "gpio_mask": "0x0000", + "pdio_value": "0x0001", + "gpio_value": "0x0000", + "hw_cause": "PSU_VIN_LOSS", + "hw_desc": "Both PSUs lost input power", + "summary": "PSU input power lost", + "reboot_cause": "REBOOT_CAUSE_POWER_LOSS" + }, + { + "pdio_mask": "0x0002", + "gpio_mask": "0x0000", + "pdio_value": "0x0002", + "gpio_value": "0x0000", + "hw_cause": "OVER_TEMP", + "hw_desc": "Switch card temp sensor OT", + "summary": "Temperature exceeded threshold", + "reboot_cause": "REBOOT_CAUSE_THERMAL_OVERLOAD_OTHER" + }, + { + "pdio_mask": "0x0004", + "gpio_mask": "0x0000", + "pdio_value": "0x0004", + "gpio_value": "0x0000", + "hw_cause": "CPU_PWR_BAD", + "hw_desc": "CPU card power bad", + "summary": "CPU power failure", + "reboot_cause": "REBOOT_CAUSE_HARDWARE_OTHER" + }, + { + "pdio_mask": "0x0008", + "gpio_mask": "0x0000", + "pdio_value": "0x0008", + "gpio_value": "0x0000", + "hw_cause": "WATCHDOG", + "hw_desc": "FPGA watchdog expired", + "summary": "Watchdog timeout", + "reboot_cause": "REBOOT_CAUSE_WATCHDOG" + }, + { + "pdio_mask": "0x0010", + "gpio_mask": "0x0000", + "pdio_value": "0x0010", + "gpio_value": "0x0000", + "hw_cause": "ASIC_OT", + "hw_desc": "ASIC MAX_TEMP exceeded OT threshold", + "summary": "ASIC overtemperature", + "reboot_cause": "REBOOT_CAUSE_THERMAL_OVERLOAD_ASIC" + }, + { + "pdio_mask": "0x0020", + "gpio_mask": "0x0000", + "pdio_value": "0x0020", + "gpio_value": "0x0000", + "hw_cause": "NO_FAN_PRSNT", + "hw_desc": "All 4 fans have same ID=0xf", + "summary": "No fans present", + "reboot_cause": "REBOOT_CAUSE_HARDWARE_OTHER" + }, + { + "pdio_mask": "0x0040", + "gpio_mask": "0x0000", + "pdio_value": "0x0040", + "gpio_value": "0x0000", + "hw_cause": "CMD_PWR_CYC", + "hw_desc": "Software commanded power cycle", + "summary": "Software power cycle", + "reboot_cause": "REBOOT_CAUSE_POWER_LOSS" + }, + { + "pdio_mask": "0x0080", + "gpio_mask": "0x0000", + "pdio_value": "0x0080", + "gpio_value": "0x0000", + "hw_cause": "DP_PWR_ON", + "hw_desc": "P2 only: from shift chain; not used on P1", + "summary": "DP power on", + "reboot_cause": "REBOOT_CAUSE_POWER_LOSS" + }, + { + "pdio_mask": "0x0100", + "gpio_mask": "0x0000", + "pdio_value": "0x0100", + "gpio_value": "0x0000", + "hw_cause": "FPGA_CMD_PCYC", + "hw_desc": "FPGA commanded power cycle", + "summary": "FPGA power cycle", + "reboot_cause": "REBOOT_CAUSE_POWER_LOSS" + }, + { + "pdio_mask": "0x0200", + "gpio_mask": "0x0000", + "pdio_value": "0x0200", + "gpio_value": "0x0000", + "hw_cause": "CMD_ASIC_PWR_OFF", + "hw_desc": "FPGA command ASIC power off", + "summary": "ASIC power off", + "reboot_cause": "REBOOT_CAUSE_POWER_LOSS" + } + ], + "vpx_to_rail_desc": { + "6": "POS0V75_S5", + "7": "POS1V8_S5", + "8": "POS3V3_S5", + "9": "POS1V1_S0", + "10": "POS0V78_S0", + "11": "POS0V75_S0", + "12": "POS1V8_S0", + "13": "POS3V3_S0", + }, + "vhx_to_rail_desc": { + "5": "POS5V0_S0" + } + } } - self._create_nvmem_path() - - def get_vp_to_pdio_desc(self): - return self.vp_to_pdio_desc - - def get_vh_to_pdio_desc(self): - return self.vh_to_pdio_desc - - def get_dpm_signals(self): - return self.dpm_signals - - def get_dpm_table(self): - return self.dpm_table - - def get_power_fault_cause(self): - return self.power_fault_cause - - def get_nvmem_path(self): - return self.nvmem_path - - def get_name(self): - return "dpm-mock" + } - def _create_nvmem_path(self): - """Create temporary file with binary data and return path""" + def __init__(self): + # Create temporary nvmem file nvmem_file = tempfile.NamedTemporaryFile(delete=False) nvmem_file.close() - self.nvmem_path = nvmem_file.name + nvmem_path = nvmem_file.name + Adm1266PlatformSpecMock.pddf_plugin_data["DPM"]["dpm-mock"]["nvmem_path"] = nvmem_path + self.nvmem_path = nvmem_path + + """ + Create a Adm1266PlatformSpec instance using mock data for testing. + """ + test_dir = os.path.dirname(os.path.realpath(__file__)) + adm1266_platform_spec_path = os.path.join(test_dir, "../../common/sonic_platform/adm1266_platform_spec.py") + spec = importlib.util.spec_from_file_location("adm1266_platform_spec", adm1266_platform_spec_path) + adm1266_platform_spec_module = importlib.util.module_from_spec(spec) + spec.loader.exec_module(adm1266_platform_spec_module) + adm1266_platform_spec = adm1266_platform_spec_module.Adm1266PlatformSpec("dpm-mock", Adm1266PlatformSpecMock.pddf_plugin_data) + + # Store cleanup info for later + self.adm1266_platform_spec = adm1266_platform_spec def __del__(self): """Clean up temporary file""" if os.path.exists(self.nvmem_path): os.unlink(self.nvmem_path) + class Adm1266Mock: """ Mock implementation of ADM1266 for unit testing. Reads test data from provided file paths. """ def __init__(self): - os.path.dirname(__file__), + test_dir = os.path.dirname(__file__) - json_file = os.path.join(os.path.dirname(__file__), "adm1266_test_spec.json") + json_file = os.path.join(test_dir, "adm1266_test_spec.json") data, records, causes = process_input(json_file) self.blackbox_input = data self.expected_records = records self.expected_causes = causes - self.dpm_info = DpmInfoMock() + self.adm1266_platform_spec_mock = Adm1266PlatformSpecMock() - # Load the adm1266 module directly from file path - test_dir = os.path.dirname(os.path.realpath(__file__)) - adm1266_path = os.path.join(test_dir, "../../common/sonic_platform/adm1266.py") + # SET UP MOCKS BEFORE LOADING adm1266.py + # Mock sonic_platform_base.chassis_base that adm1266.py imports + chassis_base_mock = Mock() + chassis_base_mock.ChassisBase = Mock() + sys.modules["sonic_platform_base.chassis_base"] = chassis_base_mock + + # Mock sonic_platform.adm1266_platform_spec so the import works + adm1266_platform_spec_mock = Mock() + adm1266_platform_spec_mock.Adm1266PlatformSpec = lambda name, pddf_data: self.adm1266_platform_spec_mock.adm1266_platform_spec + sys.modules["sonic_platform.adm1266_platform_spec"] = adm1266_platform_spec_mock + # Mock SystemDPMLogHistory to avoid file system operations + dpm_history = Mock() + dpm_history.save = Mock() + sys.modules["sonic_platform.dpm"] = dpm_history + + # NOW load the adm1266 module directly from file path + adm1266_path = os.path.join(test_dir, "../../common/sonic_platform/adm1266.py") spec = importlib.util.spec_from_file_location("adm1266", adm1266_path) adm1266_module = importlib.util.module_from_spec(spec) spec.loader.exec_module(adm1266_module) - self.adm = adm1266_module.Adm1266(self.dpm_info) + self.adm = adm1266_module.Adm1266(self.adm1266_platform_spec_mock.adm1266_platform_spec) + self.adm_get_reboot_cause = adm1266_module.get_reboot_cause + + # Set up path to test PDDF plugin file + # Use absolute path in the container + self.test_pddf_path = "/sonic/device/nexthop/x86_64-nexthop_4010-r0/pddf/pd-plugin.json" + + # Write the test blackbox data to the nvmem file self._setup_nvmem_file(data) def _setup_nvmem_file(self, binary_data): - """Populate nvmem file with binary data """ - with open(self.dpm_info.get_nvmem_path(), 'wb') as nvmem_file: + """Populate nvmem file with binary data""" + with open(self.adm1266_platform_spec_mock.nvmem_path, 'wb') as nvmem_file: nvmem_file.write(binary_data) def get_blackbox_input(self): @@ -194,14 +287,11 @@ def read_blackbox(self): def get_blackbox_records(self): return self.adm.get_blackbox_records() - def get_reboot_causes(self): - return self.adm.get_reboot_causes() - def parse_blackbox(self, data): - return self.adm.parse_blackbox(data) + return self.adm._parse_blackbox(data) def get_reboot_cause(self): - return self.adm.get_reboot_cause() + return self.adm_get_reboot_cause(self.test_pddf_path) def clear_blackbox(self): self.adm.clear_blackbox() @@ -334,31 +424,6 @@ def watchdog(mock_pddf_data): ) -@pytest.fixture -def watchdog(mock_pddf_data): - """ - Fixture providing a Watchdog instance for testing. - """ - # Set up the specific WatchdogBase mock with our test implementation - watchdog_base_mock = Mock() - watchdog_base_mock.WatchdogBase = WatchdogBaseMock - sys.modules["sonic_platform_base.watchdog_base"] = watchdog_base_mock - - # Load the module directly from file path - test_dir = os.path.dirname(os.path.realpath(__file__)) - watchdog_path = os.path.join(test_dir, "../../common/sonic_platform/watchdog.py") - - spec = importlib.util.spec_from_file_location("watchdog", watchdog_path) - watchdog_module = importlib.util.module_from_spec(spec) - spec.loader.exec_module(watchdog_module) - - return watchdog_module.Watchdog( - fpga_pci_addr="FAKE_FPGA_PCI_ADDR", - event_driven_power_cycle_control_reg_offset=0x28, - watchdog_counter_reg_offset=0x1E0, - ) - - @pytest.fixture def mock_sfps(chassis): """ diff --git a/platform/broadcom/sonic-platform-modules-nexthop/test/unit/nexthop/test_nh_reboot_cause.py b/platform/broadcom/sonic-platform-modules-nexthop/test/unit/nexthop/test_nh_reboot_cause.py new file mode 100644 index 00000000000..40dca34ad50 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-nexthop/test/unit/nexthop/test_nh_reboot_cause.py @@ -0,0 +1,218 @@ +#!/usr/bin/env python3 + +# Copyright 2025 Nexthop Systems Inc. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +""" +Test script for nh_reboot_cause utility. +This script sets up the necessary mocks and imports to test the CLI tool. +""" + +import base64 +import importlib.util +import json +import os +import sys +import tempfile +from unittest.mock import Mock + +# Prevent Python from writing .pyc files during test imports +# This avoids __pycache__ directories in common/utils/ that interfere with builds +sys.dont_write_bytecode = True + +def setup_test_environment(): + """Set up mocks and load modules using the fixture pattern.""" + + # Mock sonic_platform_base.chassis_base that adm1266.py imports + chassis_base_mock = Mock() + chassis_base_mock.ChassisBase = Mock() + chassis_base_mock.ChassisBase.REBOOT_CAUSE_HARDWARE_OTHER = "Unknown" + chassis_base_mock.ChassisBase.REBOOT_CAUSE_POWER_LOSS = "Power Loss" + chassis_base_mock.ChassisBase.REBOOT_CAUSE_THERMAL_OVERLOAD_CPU = "Thermal Overload" + chassis_base_mock.ChassisBase.REBOOT_CAUSE_WATCHDOG = "Watchdog" + sys.modules["sonic_platform_base"] = Mock() + sys.modules["sonic_platform_base.chassis_base"] = chassis_base_mock + + # Get the test directory (we're in test/unit/sonic_platform/) + test_dir = os.path.dirname(os.path.realpath(__file__)) + + # Load dpm module directly from file path + dpm_path = os.path.join(test_dir, "../../../common/sonic_platform/dpm.py") + spec = importlib.util.spec_from_file_location("sonic_platform.dpm", dpm_path) + dpm_module = importlib.util.module_from_spec(spec) + sys.modules["sonic_platform.dpm"] = dpm_module + spec.loader.exec_module(dpm_module) + + # Load adm1266 module directly from file path + adm1266_path = os.path.join(test_dir, "../../../common/sonic_platform/adm1266.py") + spec = importlib.util.spec_from_file_location("sonic_platform.adm1266", adm1266_path) + adm1266_module = importlib.util.module_from_spec(spec) + sys.modules["sonic_platform.adm1266"] = adm1266_module + spec.loader.exec_module(adm1266_module) + + # Now load the nh_reboot_cause utility (file has no .py extension) + nh_reboot_cause_path = os.path.join(test_dir, "../../../common/utils/nh_reboot_cause") + + # For files without .py extension, we need to use SourceFileLoader explicitly + from importlib.machinery import SourceFileLoader + loader = SourceFileLoader("nh_reboot_cause", nh_reboot_cause_path) + spec = importlib.util.spec_from_loader(loader.name, loader) + nh_reboot_cause_module = importlib.util.module_from_spec(spec) + sys.modules["nh_reboot_cause"] = nh_reboot_cause_module + spec.loader.exec_module(nh_reboot_cause_module) + + return nh_reboot_cause_module, dpm_module + + +def create_test_data(): + """Create test DPM fault records in the correct envelope format. + + The 'raw' field must be a base64-encoded string (as stored by Serializer) + representing 64 bytes of blackbox data. + """ + # Create a minimal 64-byte raw record (all zeros) and encode it + raw_bytes = bytes(64) + raw_encoded = 'base64:' + base64.b64encode(raw_bytes).decode('ascii') + + records = [ + { + "dpm_name": "test-dpm-1", + "fault_uid": "0x1234", + "power_loss": "Yes", + "timestamp": "2025-01-15 10:30:45", + "dpm_fault": "PSU input power lost", + "raw": raw_encoded, + }, + { + "dpm_name": "test-dpm-2", + "fault_uid": "0x5678", + "power_loss": "No", + "timestamp": "2025-01-15 10:30:46", + "dpm_fault": "Watchdog timeout", + "raw": raw_encoded, + } + ] + + return { + "dpm_type": "adm1266", + "gen_time": "2025_01_15_10_30_45", + "schema_version": 1, + "records_json": records + } + + +def test_show_current(capsys): + """Test showing current reboot-cause.""" + nh_reboot_cause_module, dpm_module = setup_test_environment() + + with tempfile.TemporaryDirectory() as tmpdir: + original_history_dir = dpm_module.SystemDPMLogHistory.HISTORY_DIR + dpm_module.SystemDPMLogHistory.HISTORY_DIR = tmpdir + + try: + # Create test data file + test_data = create_test_data() + timestamp = "2025_01_15_10_30_45" + test_file = os.path.join(tmpdir, f"reboot-cause-{timestamp}.json") + + with open(test_file, 'w') as f: + json.dump(test_data, f) + + # Create symlink to latest + prev_link = os.path.join(tmpdir, "previous-reboot-cause.json") + os.symlink(test_file, prev_link) + + # Test show_current and verify output + nh_reboot_cause_module.show_current() + captured = capsys.readouterr() + + assert "test-dpm-1" in captured.out, "Expected DPM name in output" + assert "test-dpm-2" in captured.out, "Expected second DPM name in output" + assert "0x1234" in captured.out, "Expected fault UID in output" + assert "Unsupported DPM type" not in captured.out, "Should not show DPM type error" + + finally: + dpm_module.SystemDPMLogHistory.HISTORY_DIR = original_history_dir + + +def test_show_history(capsys): + """Test showing reboot-cause history.""" + nh_reboot_cause_module, dpm_module = setup_test_environment() + + with tempfile.TemporaryDirectory() as tmpdir: + original_history_dir = dpm_module.SystemDPMLogHistory.HISTORY_DIR + dpm_module.SystemDPMLogHistory.HISTORY_DIR = tmpdir + + try: + # Create multiple test data files + test_data = create_test_data() + timestamps = ["2025_01_15_10_30_45", "2025_01_15_11_45_30", "2025_01_15_14_20_15"] + + for ts in timestamps: + test_file = os.path.join(tmpdir, f"reboot-cause-{ts}.json") + with open(test_file, 'w') as f: + json.dump(test_data, f) + + # Create symlink to latest + latest_file = os.path.join(tmpdir, f"reboot-cause-{timestamps[-1]}.json") + prev_link = os.path.join(tmpdir, "previous-reboot-cause.json") + os.symlink(latest_file, prev_link) + + # Test show_history and verify output + nh_reboot_cause_module.show_history() + captured = capsys.readouterr() + + assert captured.out.count("Logs recorded at") == len(timestamps), \ + f"Expected {len(timestamps)} history entries" + assert "test-dpm-1" in captured.out, "Expected DPM name in history output" + + finally: + dpm_module.SystemDPMLogHistory.HISTORY_DIR = original_history_dir + + +def test_cli_help(): + """Test that the CLI command is properly configured with click.""" + nh_reboot_cause_module, _ = setup_test_environment() + + cli = nh_reboot_cause_module.reboot_cause + + # Verify the command has help text + assert cli.help is not None, "CLI command should have help text" + assert "reboot-cause" in cli.help.lower(), "Help text should mention reboot-cause" + + # Verify --history option exists + has_history_option = any(param.name == 'history' for param in cli.params) + assert has_history_option, "CLI should have --history option" + + +def test_unsupported_dpm_type(capsys): + """Test that unsupported DPM types are rejected.""" + nh_reboot_cause_module, dpm_module = setup_test_environment() + + with tempfile.TemporaryDirectory() as tmpdir: + original_history_dir = dpm_module.SystemDPMLogHistory.HISTORY_DIR + dpm_module.SystemDPMLogHistory.HISTORY_DIR = tmpdir + + try: + # Create test data with wrong DPM type + test_data = create_test_data() + test_data["dpm_type"] = "unknown_dpm" + timestamp = "2025_01_15_10_30_45" + test_file = os.path.join(tmpdir, f"reboot-cause-{timestamp}.json") + + with open(test_file, 'w') as f: + json.dump(test_data, f) + + prev_link = os.path.join(tmpdir, "previous-reboot-cause.json") + os.symlink(test_file, prev_link) + + # Test show_current with wrong DPM type + nh_reboot_cause_module.show_current() + captured = capsys.readouterr() + + assert "Unsupported DPM type" in captured.out, "Should show DPM type error" + assert "unknown_dpm" in captured.out, "Should mention the unsupported DPM type" + + finally: + dpm_module.SystemDPMLogHistory.HISTORY_DIR = original_history_dir + diff --git a/platform/broadcom/sonic-platform-modules-nexthop/test/unit/sonic_platform/test_adm1266.py b/platform/broadcom/sonic-platform-modules-nexthop/test/unit/sonic_platform/test_adm1266.py index 4be21ef1243..0475306ba15 100644 --- a/platform/broadcom/sonic-platform-modules-nexthop/test/unit/sonic_platform/test_adm1266.py +++ b/platform/broadcom/sonic-platform-modules-nexthop/test/unit/sonic_platform/test_adm1266.py @@ -10,6 +10,16 @@ sys.path.insert(0, '../../fixtures') from fixtures_unit_test import Adm1266Mock +@pytest.fixture(scope="module") +def decode_power_fault_cause(): + from fixtures_unit_test import Adm1266Mock + adm = Adm1266Mock() + _decode_power_fault_cause = adm.adm_get_reboot_cause.__globals__['decode_power_fault_cause'] + return _decode_power_fault_cause + +PSU_VIN_LOSS_PDIO_MASK_AND_VALUE = 0x0001 +OVER_TEMP_PDIO_MASK_AND_VALUE=0x0002 + class TestAdm1266Basic: """Test ADM1266 basic properties and interface.""" def test_read_blackbox(self): @@ -70,29 +80,204 @@ def test_get_blackbox_records(self): print(" Passed") def test_get_reboot_causes(self): - """Test Adm1266.get_reboot_causes by rendering expected numerics with same RENDERers. + """Test Adm1266.get_blackbox_records by comparing with expected records. - We reuse expected_causes (numeric) and render them using RENDER to compare with - the human-friendly output, avoiding spec duplication. + We use expected_records to validate the blackbox record parsing functionality. """ - print("\n--- Testing get_reboot_causes ---") + print("\n--- Testing get_blackbox_records ---") adm = Adm1266Mock() blackbox_input = adm.get_blackbox_input() expected_records = adm.get_expected_records() expected_causes = adm.get_expected_causes() - causes = adm.get_reboot_causes() - exp = expected_causes - assert exp is not None, "expected_causes not provided" - assert len(causes) == len(exp), f"Count mismatch: {len(causes)} != {len(exp)}" - - print(f"expected_causes: {expected_causes}") - print(f"actual_causes: {causes}") + records = adm.get_blackbox_records() + exp = expected_records + assert exp is not None, "expected_records not provided" + assert len(records) == len(exp), f"Count mismatch: {len(records)} != {len(exp)}" for i, e in enumerate(exp): - a = causes[i] + a = records[i] for k, v in e.items(): - assert k in a, f"[{i}] missing '{k}' in reboot cause" + assert k in a, f"[{i}] missing '{k}' in blackbox record" assert a[k] == v, f"[{i}] {k}: {a[k]} != {v}" print(" Passed") + + def test_get_name(self): + """Test get_name method returns DPM name.""" + adm = Adm1266Mock() + name = adm.adm.get_name() + assert name == "dpm-mock" + + def test_clear_blackbox(self): + """Test clear_blackbox method clears data.""" + adm = Adm1266Mock() + # Verify we have data initially + initial_data = adm.read_blackbox() + assert len(initial_data) > 0 + + # Clear and verify empty + adm.clear_blackbox() + cleared_data = adm.read_blackbox() + assert len(cleared_data) == 1 + assert cleared_data == b"1" + + def test_get_all_faults(self): + """Test get_all_faults method returns fault list.""" + adm = Adm1266Mock() + faults = adm.adm.get_all_faults() + assert isinstance(faults, list) + assert len(faults) > 0 + # Each fault should have required fields + for fault in faults: + assert 'fault_uid' in fault + assert 'dpm_name' in fault + + def test_module_get_reboot_cause(self): + """Test module-level get_reboot_cause function.""" + adm = Adm1266Mock() + result = adm.get_reboot_cause() + assert result is not None + + reboot_cause, debug_msg = result + assert reboot_cause is not None + assert isinstance(debug_msg, str) + + def test_get_reboot_cause_type(self): + """Test get_reboot_cause_type function.""" + from fixtures_unit_test import Adm1266Mock + adm = Adm1266Mock() + # Import the function from the loaded module + get_reboot_cause_type = adm.adm_get_reboot_cause.__globals__['get_reboot_cause_type'] + + # Test with known reboot causes + causes = ["REBOOT_CAUSE_POWER_LOSS", "REBOOT_CAUSE_WATCHDOG"] + result = get_reboot_cause_type(causes) + assert result is not None + + def test_time_since(self): + """Test time_since function converts timestamp to readable format.""" + from fixtures_unit_test import Adm1266Mock + adm = Adm1266Mock() + time_since = adm.adm_get_reboot_cause.__globals__['time_since'] + + # Test with 8-byte timestamp + timestamp = b'\x79\x2e\xee\x02\x00\x00\x00\x00' + result = time_since('timestamp', timestamp) + assert isinstance(result, str) + assert 'seconds after power-on' in result + + def test_channel_names(self): + """Test channel_names function formats GPIO/PDIO bits.""" + from fixtures_unit_test import Adm1266Mock + adm = Adm1266Mock() + channel_names = adm.adm_get_reboot_cause.__globals__['channel_names'] + + # Test GPIO formatting + result = channel_names('gpio_in', 15391) # From test data + assert isinstance(result, str) + assert 'GPIO' in result or '0b' in result + + def test_decode_power_fault_cause_no_match(self, decode_power_fault_cause): + """Test decode_power_fault_cause decoding when there is no match """ + dpm_signal_to_fault_cause = [ + { + "pdio_mask": PSU_VIN_LOSS_PDIO_MASK_AND_VALUE, + "gpio_mask": 0x0000, + "pdio_value": PSU_VIN_LOSS_PDIO_MASK_AND_VALUE, + "gpio_value": 0x0000, + "hw_cause": "TEST_FAULT", + "hw_desc": "Test fault description", + "summary": "Test summary", + "reboot_cause": "REBOOT_CAUSE_HARDWARE_OTHER" + } + ] + hw_cause, hw_desc, summary, reboot_cause = decode_power_fault_cause( + dpm_signal_to_fault_cause, 0x0000, 0x0000) + assert hw_cause == "" + assert hw_desc == "" + assert summary == "" + assert reboot_cause == "" + + def test_decode_power_fault_cause_single_match(self, decode_power_fault_cause): + """Test decode_power_fault_cause decoding when there is only one match """ + # Test single fault match + dpm_signal_to_fault_cause = [ + { + "pdio_mask": PSU_VIN_LOSS_PDIO_MASK_AND_VALUE, + "gpio_mask": 0x0000, + "pdio_value": PSU_VIN_LOSS_PDIO_MASK_AND_VALUE, + "gpio_value": 0x0000, + "hw_cause": "TEST_FAULT", + "hw_desc": "Test fault description", + "summary": "Test summary", + "reboot_cause": "REBOOT_CAUSE_HARDWARE_OTHER" + } + ] + hw_cause, hw_desc, summary, reboot_cause = decode_power_fault_cause( + dpm_signal_to_fault_cause, PSU_VIN_LOSS_PDIO_MASK_AND_VALUE, 0x0000) + assert hw_cause == "TEST_FAULT" + assert hw_desc == "Test fault description" + assert summary == "Test summary" + assert reboot_cause == "REBOOT_CAUSE_HARDWARE_OTHER" + + def test_decode_power_fault_cause_multiple_match(self, decode_power_fault_cause): + """Test decode_power_fault_cause decoding when there are multiple matches """ + # Test multiple fault matches (comma-separated) + dpm_signal_to_fault_cause = [ + { + "pdio_mask": PSU_VIN_LOSS_PDIO_MASK_AND_VALUE, + "gpio_mask": 0x0000, + "pdio_value": PSU_VIN_LOSS_PDIO_MASK_AND_VALUE, + "gpio_value": 0x0000, + "hw_cause": "PSU_VIN_LOSS", + "hw_desc": "Both PSUs lost input power", + "summary": "PSU input power lost", + "reboot_cause": "REBOOT_CAUSE_POWER_LOSS" + }, + { + "pdio_mask": OVER_TEMP_PDIO_MASK_AND_VALUE, + "gpio_mask": 0x0000, + "pdio_value": OVER_TEMP_PDIO_MASK_AND_VALUE, + "gpio_value": 0x0000, + "hw_cause": "OVER_TEMP", + "hw_desc": "Temperature exceeded threshold", + "summary": "Overtemperature event", + "reboot_cause": "REBOOT_CAUSE_THERMAL_OVERLOAD_OTHER" + } + ] + # Both bits set - should get comma-separated results + hw_cause, hw_desc, summary, reboot_cause = decode_power_fault_cause( + dpm_signal_to_fault_cause, + PSU_VIN_LOSS_PDIO_MASK_AND_VALUE | OVER_TEMP_PDIO_MASK_AND_VALUE, + 0x0000) + assert hw_cause == "PSU_VIN_LOSS,OVER_TEMP" + assert hw_desc == "Both PSUs lost input power,Temperature exceeded threshold" + assert summary == "PSU input power lost,Overtemperature event" + assert reboot_cause == "REBOOT_CAUSE_POWER_LOSS,REBOOT_CAUSE_THERMAL_OVERLOAD_OTHER" + + @pytest.mark.parametrize("reboot_cause_str", [ + "REBOOT_CAUSE_POWER_LOSS", + "REBOOT_CAUSE_POWER_LOSS,REBOOT_CAUSE_WATCHDOG", + "REBOOT_CAUSE_THERMAL_OVERLOAD_ASIC, REBOOT_CAUSE_HARDWARE_OTHER", + "INVALID_CAUSE" + ]) + def test_reboot_cause_str_to_type(self, reboot_cause_str): + """Test reboot_cause_str_to_type handles single and comma-separated causes.""" + from fixtures_unit_test import Adm1266Mock + adm = Adm1266Mock() + reboot_cause_str_to_type = adm.adm_get_reboot_cause.__globals__['reboot_cause_str_to_type'] + ChassisBase = adm.adm_get_reboot_cause.__globals__['ChassisBase'] + + reboot_cause_to_type = { + "REBOOT_CAUSE_POWER_LOSS": + ChassisBase.REBOOT_CAUSE_POWER_LOSS, + "REBOOT_CAUSE_POWER_LOSS,REBOOT_CAUSE_WATCHDOG": + ChassisBase.REBOOT_CAUSE_POWER_LOSS, + "REBOOT_CAUSE_THERMAL_OVERLOAD_ASIC, REBOOT_CAUSE_HARDWARE_OTHER": + ChassisBase.REBOOT_CAUSE_THERMAL_OVERLOAD_ASIC, + "INVALID_CAUSE": ChassisBase.INVALID_CAUSE + } + + reboot_cause_type = reboot_cause_to_type.get(reboot_cause_str, "") + assert reboot_cause_str_to_type(reboot_cause_str) == reboot_cause_type diff --git a/platform/broadcom/sonic-platform-modules-nexthop/test/unit/sonic_platform/test_chassis.py b/platform/broadcom/sonic-platform-modules-nexthop/test/unit/sonic_platform/test_chassis.py index 033884f1fd9..4d86648c717 100755 --- a/platform/broadcom/sonic-platform-modules-nexthop/test/unit/sonic_platform/test_chassis.py +++ b/platform/broadcom/sonic-platform-modules-nexthop/test/unit/sonic_platform/test_chassis.py @@ -10,6 +10,9 @@ """ import copy +import os +import sys +import tempfile import time from unittest.mock import patch, Mock @@ -21,6 +24,20 @@ XCVR_INSERTED = "1" XCVR_REMOVED = "0" +def _create_temp_file(content: str) -> str: + """ + Creates a temporary file, under a temporary directory. + Args: + content: content to write to the temporary file. + Returns: + Path to the created file + """ + root = tempfile.mkdtemp() + filepath = os.path.join(root, 'reboot-cause.txt') + with open(filepath, 'w+') as file: + file.write(content) + return filepath + class SfpTestHelper: """ @@ -199,3 +216,90 @@ def test_chassis_get_watchdog_no_watchdog_presence_in_pddf_data(self, chassis): chassis.__init__(pddf_data=mock_pddf_data) assert chassis.get_watchdog() is None + + def test_chassis_get_reboot_cause_sw_reboot(self, chassis): + EXPECTED_SW_REBOOT_CAUSE = "reboot" + EXPECTED_MINOR_CAUSES = "System powered off due to software disabling data plane power, System powered off due to software disabling data plane power, System powered off due to software disabling data plane power" + + # Given + reboot_cause_filepath = _create_temp_file( + f"User issued '{EXPECTED_SW_REBOOT_CAUSE}' command [User: admin, Time: Thu Oct 2 11:22:56 PM UTC 2025]" + ) + chassis.__init__( + pddf_data={}, + pddf_plugin_data={ + "REBOOT_CAUSE": {"reboot_cause_file": reboot_cause_filepath} + }, + ) + + # When + mock_adm1266 = sys.modules["sonic_platform"].adm1266 + mock_adm1266.get_reboot_cause.return_value = ( + "Power Loss", + EXPECTED_MINOR_CAUSES, + ) + + # Then + assert chassis.get_reboot_cause() == ( + EXPECTED_SW_REBOOT_CAUSE, + EXPECTED_MINOR_CAUSES, + ) + + def test_chassis_get_reboot_cause_sw_kernel_panic(self, chassis): + # Given + reboot_cause_filepath = _create_temp_file( + f"Kernel Panic [Time: Thu Oct 2 11:22:56 PM UTC 2025]" + ) + chassis.__init__( + pddf_data={}, + pddf_plugin_data={"REBOOT_CAUSE": {"reboot_cause_file": reboot_cause_filepath}}, + ) + + # When + mock_adm1266 = sys.modules["sonic_platform"].adm1266 + mock_adm1266.get_reboot_cause.return_value = None + + # Then + assert chassis.get_reboot_cause() == ( + "Kernel Panic", + "", + ) + + def test_chassis_get_reboot_cause_hw(self, chassis): + EXPECTED_HW_CAUSE = "Power Loss" + EXPECTED_HW_MINOR_CAUSE = "System powered off due to loss of input power on both PSUs, System powered off due to software disabling data plane power" + + # Given + reboot_cause_filepath = _create_temp_file("") + chassis.__init__( + pddf_data={}, + pddf_plugin_data={"REBOOT_CAUSE": {"reboot_cause_file": reboot_cause_filepath}}, + ) + + # When + mock_adm1266 = sys.modules["sonic_platform"].adm1266 + mock_adm1266.get_reboot_cause.return_value = ( + EXPECTED_HW_CAUSE, + EXPECTED_HW_MINOR_CAUSE, + ) + + # Then + assert chassis.get_reboot_cause() == ( + EXPECTED_HW_CAUSE, + EXPECTED_HW_MINOR_CAUSE, + ) + + def test_chassis_get_reboot_cause_unknown(self, chassis): + # Given + reboot_cause_filepath = _create_temp_file("unknown") + chassis.__init__( + pddf_data={}, + pddf_plugin_data={"REBOOT_CAUSE": {"reboot_cause_file": reboot_cause_filepath}}, + ) + + # When + mock_adm1266 = sys.modules["sonic_platform"].adm1266 + mock_adm1266.get_reboot_cause.return_value = None + + # Then + assert chassis.get_reboot_cause() == ("Unknown", "Unknown") diff --git a/platform/broadcom/sonic-platform-modules-nexthop/test/unit/sonic_platform/test_thermal.py b/platform/broadcom/sonic-platform-modules-nexthop/test/unit/sonic_platform/test_thermal.py index bca995564c1..516ff09f3cc 100644 --- a/platform/broadcom/sonic-platform-modules-nexthop/test/unit/sonic_platform/test_thermal.py +++ b/platform/broadcom/sonic-platform-modules-nexthop/test/unit/sonic_platform/test_thermal.py @@ -10,11 +10,12 @@ """ import importlib.util -import pytest import os import sys +import types +from unittest.mock import Mock, call, patch -from unittest.mock import Mock, patch, call +import pytest @pytest.fixture(scope="session", autouse=True) @@ -35,12 +36,12 @@ def __init__(self): # Mock SysLogger class MockSysLogger: def __init__(self, *args, **kwargs): - pass - def log_info(self, msg): pass - def log_error(self, msg): pass - def log_warning(self, msg): pass - def log_debug(self, msg): pass - def log(self, priority, msg, also_print_to_console=False): pass + # Methods as mocks so tests can assert calls + self.log_info = Mock() + self.log_error = Mock() + self.log_warning = Mock() + self.log_debug = Mock() + self.log = Mock() # Create mock modules for external SONiC dependencies mock_thermal_action_base = Mock() @@ -60,15 +61,76 @@ def log(self, priority, msg, also_print_to_console=False): pass mock_syslog = Mock() mock_syslog.SYSLOG_IDENTIFIER_THERMAL = "nh_thermal" mock_syslog.NhLoggerMixin = MockSysLogger + # Build mock for swsscommon package and submodule + mock_swsscommon_pkg = types.ModuleType('swsscommon') + mock_swsscommon_sub = types.ModuleType('swsscommon.swsscommon') + + class MockSonicV2Connector: + CONFIG_DB = 4 + STATE_DB = 6 + RETURN_GET_ALL = {} + def __init__(self, *args, **kwargs): + pass + def connect(self, db): + pass + def get_redis_client(self, db): + return object() + def get_all(self, db, key): + return self.RETURN_GET_ALL + def close(self, db): + pass + + class MockTable: + MOCK_PORT_KEYS = [] + MOCK_PORT_DATA = {} + def __init__(self, db_connector, table_name): + self.table_name = table_name + def getKeys(self): + return list(self.MOCK_PORT_KEYS) + def get(self, intf_name): + data = self.MOCK_PORT_DATA.get(intf_name) + return (True, data) if data is not None else (False, []) + + setattr(mock_swsscommon_sub, 'SonicV2Connector', MockSonicV2Connector) + setattr(mock_swsscommon_sub, 'Table', MockTable) + setattr(mock_swsscommon_sub, 'CFG_PORT_TABLE_NAME', 'PORT') + setattr(mock_swsscommon_pkg, 'swsscommon', mock_swsscommon_sub) + + # Build other external dependency mocks + mock_fpga_lib = types.SimpleNamespace() + def _mock_read_32(addr, reg): + raise PermissionError("not root") + setattr(mock_fpga_lib, 'read_32', _mock_read_32) + + mock_thermal_base_module = types.ModuleType('sonic_platform_base.thermal_base') + class _ThermalBase: + def __init__(self): + pass + setattr(mock_thermal_base_module, 'ThermalBase', _ThermalBase) + + mock_pddf_thermal_module = types.ModuleType('sonic_platform_pddf_base.pddf_thermal') + class _PddfThermal: + def __init__(self, *args, **kwargs): + pass + def get_temperature(self): + return None + setattr(mock_pddf_thermal_module, 'PddfThermal', _PddfThermal) + # Mock all dependencies that aren't available in test environment with patch.dict('sys.modules', { - # External SONiC dependencies + # External SONiC dependencies for thermal_actions 'sonic_platform_base.sonic_thermal_control.thermal_action_base': mock_thermal_action_base, 'sonic_platform_base.sonic_thermal_control.thermal_json_object': mock_thermal_json_object_module, 'sonic_platform_base.sonic_thermal_control.thermal_info_base': Mock(), 'sonic_platform_base.fan_base': Mock(), 'sonic_py_common.syslogger': mock_syslogger, + # External SONiC dependencies for thermal.py + 'swsscommon': mock_swsscommon_pkg, + 'swsscommon.swsscommon': mock_swsscommon_sub, + 'nexthop.fpga_lib': mock_fpga_lib, + 'sonic_platform_base.thermal_base': mock_thermal_base_module, + 'sonic_platform_pddf_base.pddf_thermal': mock_pddf_thermal_module, # Local dependencies 'sonic_platform.thermal_infos': mock_thermal_infos, 'sonic_platform.syslog': mock_syslog, @@ -88,6 +150,19 @@ def thermal_actions_module(): return thermal_actions +@pytest.fixture(scope="session") +def thermal_module(): + """Import the actual thermal module (thermal.py) using normal Python imports.""" + test_dir = os.path.dirname(os.path.realpath(__file__)) + thermal_path = os.path.join(test_dir, "../../../common/sonic_platform/thermal.py") + + spec = importlib.util.spec_from_file_location("thermal", thermal_path) + thermal = importlib.util.module_from_spec(spec) + spec.loader.exec_module(thermal) + + return thermal + + class TestPIDController: """Test class for PIDController functionality.""" @@ -542,7 +617,7 @@ def mock_thermal_info_dict(self, thermal_actions_module, mock_fans): """Fixture providing mock thermal info dictionary.""" fan_drawer_info = Mock() fan_drawer_info.get_fans = Mock(return_value=mock_fans) - + return { thermal_actions_module.FanDrawerInfo.INFO_TYPE: fan_drawer_info } @@ -566,10 +641,10 @@ def test_fan_set_speed_action_execute(self, fan_set_speed_action, mock_thermal_i """Test FanSetSpeedAction execution.""" # Configure action fan_set_speed_action.load_from_json({'speed': 75}) - + # Execute action fan_set_speed_action.execute(mock_thermal_info_dict) - + # Verify all fans were set to correct speed for fan in mock_fans: fan.set_speed.assert_called_once_with(75) @@ -673,7 +748,7 @@ def test_thermal_control_action_initialization(self, thermal_control_action): def test_thermal_control_action_load_from_json_valid(self, thermal_control_action, valid_json_config): """Test loading valid JSON configuration.""" thermal_control_action.load_from_json(valid_json_config) - + assert thermal_control_action._pidDomains == valid_json_config['pid_domains'] assert thermal_control_action._constants == valid_json_config['constants'] assert thermal_control_action._fan_limits == valid_json_config['fan_limits'] @@ -1081,15 +1156,111 @@ def test_sfp_thermal_get_pid_setpoint_boundary_conditions(self, sfp_thermal): # Reset the logged flag for this test sfp_thermal._invalid_setpoint_logged = False sfp_thermal._thermal_syslogger.reset_mock() - sfp_thermal._parent_setpoint = just_below_boundary - setpoint = sfp_thermal.get_pid_setpoint() - # Should return default setpoint - assert setpoint == sfp_thermal.DEFAULT_SETPOINT +class TestPortIndexMapper: + def test_get_interface_name_picks_lowest_and_ignores_invalid(self, thermal_module): + """Verify PortIndexMapper builds mapping and picks lowest Ethernet name for same index.""" + sw = sys.modules['swsscommon.swsscommon'] + # Prepare mock PORT table data + sw.Table.MOCK_PORT_KEYS = ['Ethernet4', 'Ethernet0', 'NotAnEthernet'] + sw.Table.MOCK_PORT_DATA = { + 'Ethernet4': [('index', '1')], + 'Ethernet0': [('index', '1')], + 'NotAnEthernet': [('index', '1')], + } + # Reset singleton to rebuild mapping + thermal_module.PortIndexMapper._instance = None + mapper = thermal_module.PortIndexMapper() + + assert mapper.get_interface_name(1) == 'Ethernet0' + assert mapper.get_interface_name(2) is None + + +class TestSfpThermal: + @pytest.fixture + def pddf_platform(self): + # Provide minimal PLATFORM data to avoid None .lower() in PidThermalMixin + return types.SimpleNamespace(data={'PLATFORM': { + 'nexthop_thermal_xcvr_setpoint_override': None, + 'nexthop_thermal_xcvr_pid_domain': 'none' + }}) + + def test_default_setpoint_when_thresholds_unavailable(self, thermal_module, pddf_platform): + """When thresholds are not yet available but SFP is present, default setpoint is used.""" + sw = sys.modules['swsscommon.swsscommon'] + sw.SonicV2Connector.RETURN_GET_ALL = {} + + sfp = Mock() + sfp.get_name.return_value = 'sfp1' + sfp.get_presence.return_value = True + sfp.get_position_in_parent.return_value = 1 + + with patch.object(thermal_module.PortIndexMapper, 'get_interface_name', return_value='Ethernet0'): + sfp_th = thermal_module.SfpThermal(sfp, pddf_platform) + setpoint = sfp_th.get_pid_setpoint() + assert setpoint == thermal_module.SfpThermal.DEFAULT_SETPOINT + + def test_invalid_computed_setpoint_logs_once_and_uses_default(self, thermal_module, pddf_platform): + """If computed setpoint < MIN_VALID_SETPOINT, fallback to default and log once.""" + sw = sys.modules['swsscommon.swsscommon'] + # temphighwarning - margin (10) => 25 < 30 -> invalid + sw.SonicV2Connector.RETURN_GET_ALL = {'temphighwarning': '35'} + + sfp = Mock() + sfp.get_name.return_value = 'sfp2' + sfp.get_presence.return_value = True + sfp.get_position_in_parent.return_value = 2 + + with patch.object(thermal_module.PortIndexMapper, 'get_interface_name', return_value='Ethernet4'): + sfp_th = thermal_module.SfpThermal(sfp, pddf_platform) + logger = thermal_module.thermal_syslogger + before = getattr(logger, 'log_warning').call_count + + sp1 = sfp_th.get_pid_setpoint() + assert sp1 == thermal_module.SfpThermal.DEFAULT_SETPOINT + assert getattr(logger, 'log_warning').call_count == before + 1 + + # Second call should not log again + sp2 = sfp_th.get_pid_setpoint() + assert sp2 == thermal_module.SfpThermal.DEFAULT_SETPOINT + assert getattr(logger, 'log_warning').call_count == before + 1 + + def test_thresholds_parsing_and_cache(self, thermal_module, pddf_platform): + """State DB threshold values are parsed to float and cached for THRESHOLDS_CACHE_INTERVAL_SEC.""" + sw = sys.modules['swsscommon.swsscommon'] + sw.SonicV2Connector.RETURN_GET_ALL = { + 'temphighwarning': '75.0', + 'templowwarning': '10.5', + 'temphighalarm': '90', + 'templowalarm': '5', + 'irrelevant': 'N/A', + } + + sfp = Mock() + sfp.get_name.return_value = 'sfp3' + sfp.get_presence.return_value = True + sfp.get_position_in_parent.return_value = 3 + + with patch.object(thermal_module.PortIndexMapper, 'get_interface_name', return_value='Ethernet8'): + sfp_th = thermal_module.SfpThermal(sfp, pddf_platform) + + # First fetch reads from DB and caches + assert sfp_th.get_high_threshold() == 75.0 + assert sfp_th.get_low_threshold() == 10.5 + assert sfp_th.get_high_critical_threshold() == 90.0 + assert sfp_th.get_low_critical_threshold() == 5.0 + + # Change underlying DB data; cache should prevent update immediately + sw.SonicV2Connector.RETURN_GET_ALL = { + 'temphighwarning': '10', + 'templowwarning': '1', + 'temphighalarm': '20', + 'templowalarm': '0', + } + # Values should remain cached (unchanged) + assert sfp_th.get_high_threshold() == 75.0 + assert sfp_th.get_low_threshold() == 10.5 - # Should log warning - sfp_thermal._thermal_syslogger.log_warning.assert_called_once() - assert sfp_thermal._invalid_setpoint_logged From 4ab385b2be95e228198fc32af989e7c6a2698d47 Mon Sep 17 00:00:00 2001 From: Roy Wen Date: Tue, 21 Oct 2025 15:20:38 -0400 Subject: [PATCH 06/13] macsec property and tap changes --- .../NH-5010-F-O32-C32/nh5010-default.bcm | 5 +++++ .../NH-5010-F-O64/gearbox_config.json | 12 ++++++------ .../NH-5010-F-O64/nh5010-default.bcm | 5 +++++ 3 files changed, 16 insertions(+), 6 deletions(-) diff --git a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/nh5010-default.bcm b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/nh5010-default.bcm index 522d09de224..9509ef4112e 100644 --- a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/nh5010-default.bcm +++ b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/nh5010-default.bcm @@ -2258,3 +2258,8 @@ eventor_sbus_dma_channels.BCM8887X=0,24,0,25,1,24,1,25 #Default CPU Tx Tc Queue sai_default_cpu_tx_tc=7 + +#macsec properties +xflow_macsec_secure_chan_to_num_secure_assoc=4 +xflow_macsec_secure_chan_to_num_secure_assoc_encrypt=2 +xflow_macsec_secure_chan_to_num_secure_assoc_decrypt=4 diff --git a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/gearbox_config.json b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/gearbox_config.json index 72dcdbee5b9..6301bed550c 100644 --- a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/gearbox_config.json +++ b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/gearbox_config.json @@ -325,9 +325,9 @@ "system_tx_fir_post3": [0,0,0,0], "line_tx_fir_pre3": [0,0,0,0,0,0,0,0], "line_tx_fir_pre2": [0,0,0,0,0,0,0,0], - "line_tx_fir_pre1": [-20,-20,-20,-20,-20,-20,-20,-20], - "line_tx_fir_main": [100,100,100,100,100,100,100,100], - "line_tx_fir_post1": [-20,-20,-20,-20,-20,-20,-20,-20], + "line_tx_fir_pre1": [-18,-18,-18,-18,-18,-18,-18,-18], + "line_tx_fir_main": [112,112,112,112,112,112,112,112], + "line_tx_fir_post1": [0,0,0,0,0,0,0,0], "line_tx_fir_post2": [0,0,0,0,0,0,0,0], "line_tx_fir_post3": [0,0,0,0,0,0,0,0] }, @@ -388,9 +388,9 @@ "system_tx_fir_post3": [0,0,0,0], "line_tx_fir_pre3": [0,0,0,0,0,0,0,0], "line_tx_fir_pre2": [0,0,0,0,0,0,0,0], - "line_tx_fir_pre1": [-20,-20,-20,-20,-20,-20,-20,-20], - "line_tx_fir_main": [100,100,100,100,100,100,100,100], - "line_tx_fir_post1": [-20,-20,-20,-20,-20,-20,-20,-20], + "line_tx_fir_pre1": [-18,-18,-18,-18,-18,-18,-18,-18], + "line_tx_fir_main": [112,112,112,112,112,112,112,112], + "line_tx_fir_post1": [0,0,0,0,0,0,0,0], "line_tx_fir_post2": [0,0,0,0,0,0,0,0], "line_tx_fir_post3": [0,0,0,0,0,0,0,0] }, diff --git a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/nh5010-default.bcm b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/nh5010-default.bcm index a8a869a0a75..23415fa80f5 100644 --- a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/nh5010-default.bcm +++ b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/nh5010-default.bcm @@ -2258,3 +2258,8 @@ eventor_sbus_dma_channels.BCM8887X=0,24,0,25,1,24,1,25 #Default CPU Tx Tc Queue sai_default_cpu_tx_tc=7 + +#macsec properties +xflow_macsec_secure_chan_to_num_secure_assoc=4 +xflow_macsec_secure_chan_to_num_secure_assoc_encrypt=2 +xflow_macsec_secure_chan_to_num_secure_assoc_decrypt=4 From f10969cd2edc5e87df996d06125d6b49d833adc6 Mon Sep 17 00:00:00 2001 From: Louis Maliyam Date: Wed, 22 Oct 2025 21:20:57 +0000 Subject: [PATCH 07/13] Update adm1266 test to use pd-plugin.json from nh-5010 --- .../test/fixtures/fixtures_unit_test.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/platform/broadcom/sonic-platform-modules-nexthop/test/fixtures/fixtures_unit_test.py b/platform/broadcom/sonic-platform-modules-nexthop/test/fixtures/fixtures_unit_test.py index b8faaadc456..205eaa1eb6d 100644 --- a/platform/broadcom/sonic-platform-modules-nexthop/test/fixtures/fixtures_unit_test.py +++ b/platform/broadcom/sonic-platform-modules-nexthop/test/fixtures/fixtures_unit_test.py @@ -262,7 +262,7 @@ def __init__(self): # Set up path to test PDDF plugin file # Use absolute path in the container - self.test_pddf_path = "/sonic/device/nexthop/x86_64-nexthop_4010-r0/pddf/pd-plugin.json" + self.test_pddf_path = "/sonic/device/nexthop/x86_64-nexthop_5010-r0/pddf/pd-plugin.json" # Write the test blackbox data to the nvmem file self._setup_nvmem_file(data) From 6cbc4bb045830d3a645b2f87ec726e8ec2e4fd7f Mon Sep 17 00:00:00 2001 From: Roy Wen Date: Wed, 22 Oct 2025 19:12:15 -0400 Subject: [PATCH 08/13] use nh_powercycle for nh platforms --- .../x86_64-nexthop_4010-r0/pddf/pddf-device.json.j2 | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/device/nexthop/x86_64-nexthop_4010-r0/pddf/pddf-device.json.j2 b/device/nexthop/x86_64-nexthop_4010-r0/pddf/pddf-device.json.j2 index 38d1cc5dc18..9fcdb47bf4c 100644 --- a/device/nexthop/x86_64-nexthop_4010-r0/pddf/pddf-device.json.j2 +++ b/device/nexthop/x86_64-nexthop_4010-r0/pddf/pddf-device.json.j2 @@ -224,6 +224,10 @@ "device_bdf": "{{cpu_card_fpga_bdf}}", "dev_attr": {} }, + "dev_attr": { + "pwr_cycle_reg_offset": "0x8", + "pwr_cycle_enable_word": "0xdeadbeef" + }, "i2c": { "dev_attr": { "virt_bus": "0x4", @@ -1379,6 +1383,10 @@ "device_bdf": "{{switchcard_fpga_bdf}}", "dev_attr": {} }, + "dev_attr": { + "pwr_cycle_reg_offset": "0x4", + "pwr_cycle_enable_word": "0xdeadbeef" + }, "i2c": { "dev_attr": { "virt_bus": "0x13", From 51e611fe57f0d23885f4b37a83bf8e1fe5b58a5c Mon Sep 17 00:00:00 2001 From: Roy Wen Date: Wed, 22 Oct 2025 19:35:25 -0400 Subject: [PATCH 09/13] address review comments --- .../BALANCED/buffers_defaults_t2.j2 | 18 ++- .../NH-5010-F-O32-C32/BALANCED/qos.json.j2 | 8 ++ .../NH-5010-F-O32-C32/buffer_ports.j2 | 2 +- .../NH-5010-F-O32-C32/buffers_defaults_t2.j2 | 6 +- .../NH-5010-F-O32-C32/nh5010-default.bcm | 18 ++- .../NH-5010-F-O32-C32/port_config.ini | 132 +++++++++--------- .../NH-5010-F-O32-C32/qos.json.j2 | 7 + .../BALANCED/buffers_defaults_t2.j2 | 18 ++- .../NH-5010-F-O64/BALANCED/qos.json.j2 | 8 ++ .../NH-5010-F-O64/buffer_ports.j2 | 2 +- .../NH-5010-F-O64/buffers_defaults_t2.j2 | 6 +- .../NH-5010-F-O64/nh5010-default.bcm | 20 +-- .../NH-5010-F-O64/port_config.ini | 132 +++++++++--------- .../NH-5010-F-O64/qos.json.j2 | 7 + 14 files changed, 217 insertions(+), 167 deletions(-) diff --git a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/BALANCED/buffers_defaults_t2.j2 b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/BALANCED/buffers_defaults_t2.j2 index b13d888689d..82b04ee679e 100644 --- a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/BALANCED/buffers_defaults_t2.j2 +++ b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/BALANCED/buffers_defaults_t2.j2 @@ -1,18 +1,24 @@ {%- set default_cable = '300m' %} +{%- include 'buffer_ports.j2' %} + {%- set ports2cable = { 'torrouter_server' : '300m', 'leafrouter_torrouter' : '300m', - 'spinerouter_leafrouter' : '300m', - 'regionalhub_spinerouter': '300m', - 'aznghub_spinerouter' : '300m' + 'spinerouter_leafrouter' : '2000m', + 'upperspinerouter_spinerouter' : '50m', + 'upperspinerouter_lowerspinerouter' : '50m', + 'regionalhub_upperspinerouter': '120000m', + 'aznghub_upperspinerouter' : '120000m', + 'regionalhub_spinerouter': '120000m', + 'aznghub_spinerouter' : '120000m' } -%} -{%- macro generate_port_lists(PORT_ALL) %} +{%- macro generate_qos_bypass_port_list(PORT_QOS_BYPASS) %} {# Generate list of ports #} - {%- for port_idx in range(0,256,8) %} - {%- if PORT_ALL.append("Ethernet%d" % (port_idx)) %}{%- endif %} + {%- for port_idx in range(256, 261, 4) %} + {%- if PORT_QOS_BYPASS.append("Ethernet%d" % (port_idx)) %}{%- endif %} {%- endfor %} {%- endmacro %} diff --git a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/BALANCED/qos.json.j2 b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/BALANCED/qos.json.j2 index af1c4dfb256..b28c251ad53 100644 --- a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/BALANCED/qos.json.j2 +++ b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/BALANCED/qos.json.j2 @@ -1,4 +1,12 @@ {%- macro generate_global_dscp_to_tc_map() %} {# This is an empty macro since the global DSCP_TO_TC map is not required #} {%- endmacro %} + +{%- macro generate_qos_bypass_port_list(PORT_QOS_BYPASS) %} + {# Generate list of ports #} + {%- for port_idx in range(256, 261, 4) %} + {%- if PORT_QOS_BYPASS.append("Ethernet%d" % (port_idx)) %}{%- endif %} + {%- endfor %} +{%- endmacro %} + {%- include 'qos_config.j2' %} diff --git a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/buffer_ports.j2 b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/buffer_ports.j2 index b69a14551aa..50d3c8a1c86 100644 --- a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/buffer_ports.j2 +++ b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/buffer_ports.j2 @@ -1,6 +1,6 @@ {%- macro generate_port_lists(PORT_ALL) %} {# Generate list of ports #} - {%- for port_idx in range(128, 260, 4) %} + {%- for port_idx in range(128, 253, 4) %} {%- if PORT_ALL.append("Ethernet%d" % (port_idx)) %}{%- endif %} {%- endfor %} {%- endmacro %} diff --git a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/buffers_defaults_t2.j2 b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/buffers_defaults_t2.j2 index 2cf7dca105c..463d5b1bb58 100644 --- a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/buffers_defaults_t2.j2 +++ b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/buffers_defaults_t2.j2 @@ -2,10 +2,10 @@ {%- include 'buffer_ports.j2' %} -{%- macro generate_port_lists(PORT_ALL) %} +{%- macro generate_qos_bypass_port_list(PORT_QOS_BYPASS) %} {# Generate list of ports #} - {%- for port_idx in range(0,256,8) %} - {%- if PORT_ALL.append("Ethernet%d" % (port_idx)) %}{%- endif %} + {%- for port_idx in range(256, 261, 4) %} + {%- if PORT_QOS_BYPASS.append("Ethernet%d" % (port_idx)) %}{%- endif %} {%- endfor %} {%- endmacro %} diff --git a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/nh5010-default.bcm b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/nh5010-default.bcm index 9509ef4112e..43d286afad3 100644 --- a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/nh5010-default.bcm +++ b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/nh5010-default.bcm @@ -1823,6 +1823,11 @@ serdes_tx_taps_255.BCM8887X=mode:PAM4,pre:0,main:168,post:0,pre2:0,post2:0,pre3: # ---------------------------------------------------------------------------------------------------- # core_32 +# +# NOTE: +# The QoS configuration (refer qos.json.j2 and buffers_defaults_XXX.j2 file per SKU) +# does not include this management port. If you are modifying the management port, ensure that the +# QoS configuration is updated accordingly to reflect the change. # ---------------------------------------------------------------------------------------------------- ucode_port_257.BCM8887X=CGE64:core_2.33 tm_port_header_type_out_257.BCM8887X=ETH @@ -1850,6 +1855,11 @@ phy_tx_polarity_flip_phy259.BCM8887X=0 # ---------------------------------------------------------------------------------------------------- # core_33 +# +# NOTE: +# The QoS configuration (refer qos.json.j2 and buffers_defaults_XXX.j2 file per SKU) +# does not include this management port. If you are modifying the management port, ensure that the +# QoS configuration is updated accordingly to reflect the change. # ---------------------------------------------------------------------------------------------------- ucode_port_261.BCM8887X=CGE65:core_6.33 tm_port_header_type_out_261.BCM8887X=ETH @@ -2014,9 +2024,6 @@ ucode_port_385.BCM8887X=CPU.12:core_7.205 ucode_port_386.BCM8887X=CPU.20:core_4.206 ucode_port_387.BCM8887X=CPU.28:core_5.207 -#SDK 6.5.31 -custom_feature_statdma_enable.BCM8887X=1 - #special ports ucode_port_330.BCM8887X=EVENTOR:core_0.230 @@ -2110,7 +2117,7 @@ stable_size.BCM8887X=1700000000 stable_size.BCM8887X_ADAPTER=1700000000 #disable counter thread -bcm_stat_interval.BCM8887X_ADAPTER=0 +bcm_stat_interval.BCM8887X_ADAPTER=1000000 ######################### ######################### @@ -2243,9 +2250,6 @@ custom_feature_adapter_do_collect_enable.BCM8887X_ADAPTER=1 custom_feature_use_new_access.BCM8887X_ADAPTER=1 mem_cache_enable_all.BCM8887X_ADAPTER=1 -#Disable DMA stat -custom_feature_statdma_enable.BCM8887X_ADAPTER=0 - #dram dram_temperature_monitor_enable.BCM8887X_ADAPTER=0 diff --git a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/port_config.ini b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/port_config.ini index d016d6c14a6..e88f23e7631 100644 --- a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/port_config.ini +++ b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/port_config.ini @@ -1,68 +1,68 @@ # name lanes alias index role speed asic_port_name core_id core_port_id num_voq -Ethernet0 96,97,98,99 Port1 1 Ext 100000 Eth0 3 1 8 -Ethernet4 100,101,102,103 Port2 2 Ext 100000 Eth4 3 5 8 -Ethernet8 104,105,106,107 Port3 3 Ext 100000 Eth8 3 9 8 -Ethernet12 108,109,110,111 Port4 4 Ext 100000 Eth12 3 13 8 -Ethernet16 112,113,114,115 Port5 5 Ext 100000 Eth16 3 17 8 -Ethernet20 116,117,118,119 Port6 6 Ext 100000 Eth20 3 21 8 -Ethernet24 120,121,122,123 Port7 7 Ext 100000 Eth24 3 25 8 -Ethernet28 124,125,126,127 Port8 8 Ext 100000 Eth28 3 29 8 -Ethernet32 56,57,58,59 Port9 9 Ext 100000 Eth32 1 25 8 -Ethernet36 60,61,62,63 Port10 10 Ext 100000 Eth36 1 29 8 -Ethernet40 48,49,50,51 Port11 11 Ext 100000 Eth40 1 17 8 -Ethernet44 52,53,54,55 Port12 12 Ext 100000 Eth44 1 21 8 -Ethernet48 40,41,42,43 Port13 13 Ext 100000 Eth48 1 9 8 -Ethernet52 44,45,46,47 Port14 14 Ext 100000 Eth52 1 13 8 -Ethernet56 32,33,34,35 Port15 15 Ext 100000 Eth56 1 1 8 -Ethernet60 36,37,38,39 Port16 16 Ext 100000 Eth60 1 5 8 -Ethernet64 128,129,130,131 Port17 17 Ext 100000 Eth64 4 1 8 -Ethernet68 132,133,134,135 Port18 18 Ext 100000 Eth68 4 5 8 -Ethernet72 136,137,138,139 Port19 19 Ext 100000 Eth72 4 9 8 -Ethernet76 140,141,142,143 Port20 20 Ext 100000 Eth76 4 13 8 -Ethernet80 144,145,146,147 Port21 21 Ext 100000 Eth80 4 17 8 -Ethernet84 148,149,150,151 Port22 22 Ext 100000 Eth84 4 21 8 -Ethernet88 152,153,154,155 Port23 23 Ext 100000 Eth88 4 25 8 -Ethernet92 156,157,158,159 Port24 24 Ext 100000 Eth92 4 29 8 -Ethernet96 216,217,218,219 Port25 25 Ext 100000 Eth96 6 25 8 -Ethernet100 220,221,222,223 Port26 26 Ext 100000 Eth100 6 29 8 -Ethernet104 208,209,210,211 Port27 27 Ext 100000 Eth108 6 17 8 -Ethernet108 212,213,214,215 Port28 28 Ext 100000 Eth108 6 21 8 -Ethernet112 200,201,202,203 Port29 29 Ext 100000 Eth112 6 9 8 -Ethernet116 204,205,206,207 Port30 30 Ext 100000 Eth116 6 13 8 -Ethernet120 192,193,194,195 Port31 31 Ext 100000 Eth120 6 1 8 -Ethernet124 196,197,198,199 Port32 32 Ext 100000 Eth124 6 5 8 -Ethernet128 64,65,66,67 Port33 33 Ext 400000 Eth128 2 1 8 -Ethernet132 68,69,70,71 Port34 34 Ext 400000 Eth132 2 5 8 -Ethernet136 72,73,74,75 Port35 35 Ext 400000 Eth136 2 9 8 -Ethernet140 76,77,78,79 Port36 36 Ext 400000 Eth140 2 13 8 -Ethernet144 80,81,82,83 Port37 37 Ext 400000 Eth144 2 17 8 -Ethernet148 84,85,86,87 Port38 38 Ext 400000 Eth148 2 21 8 -Ethernet152 88,89,90,91 Port39 39 Ext 400000 Eth152 2 25 8 -Ethernet156 92,93,94,95 Port40 40 Ext 400000 Eth156 2 29 8 -Ethernet160 24,25,26,27 Port41 41 Ext 400000 Eth160 0 25 8 -Ethernet164 28,29,30,31 Port42 42 Ext 400000 Eth164 0 29 8 -Ethernet168 16,17,18,19 Port43 43 Ext 400000 Eth168 0 17 8 -Ethernet172 20,21,22,23 Port44 44 Ext 400000 Eth172 0 21 8 -Ethernet176 8,9,10,11 Port45 45 Ext 400000 Eth176 0 9 8 -Ethernet180 12,13,14,15 Port46 46 Ext 400000 Eth180 0 13 8 -Ethernet184 0,1,2,3 Port47 47 Ext 400000 Eth184 0 1 8 -Ethernet188 4,5,6,7 Port48 48 Ext 400000 Eth188 0 5 8 -Ethernet192 160,161,162,163 Port49 49 Ext 400000 Eth192 5 1 8 -Ethernet196 164,165,166,167 Port50 50 Ext 400000 Eth196 5 5 8 -Ethernet200 168,169,170,171 Port51 51 Ext 400000 Eth200 5 9 8 -Ethernet204 172,173,174,175 Port52 52 Ext 400000 Eth204 5 13 8 -Ethernet208 176,177,178,179 Port53 53 Ext 400000 Eth208 5 17 8 -Ethernet212 180,181,182,183 Port54 54 Ext 400000 Eth212 5 21 8 -Ethernet216 184,185,186,187 Port55 55 Ext 400000 Eth216 5 25 8 -Ethernet220 188,189,190,191 Port56 56 Ext 400000 Eth220 5 29 8 -Ethernet224 248,249,250,251 Port57 57 Ext 400000 Eth224 7 25 8 -Ethernet228 252,253,254,255 Port58 58 Ext 400000 Eth228 7 29 8 -Ethernet232 240,241,242,243 Port59 59 Ext 400000 Eth232 7 17 8 -Ethernet236 244,245,246,247 Port60 60 Ext 400000 Eth236 7 21 8 -Ethernet240 232,233,234,235 Port61 61 Ext 400000 Eth240 7 9 8 -Ethernet244 236,237,238,239 Port62 62 Ext 400000 Eth244 7 13 8 -Ethernet248 224,225,226,227 Port63 63 Ext 400000 Eth248 7 1 8 -Ethernet252 228,229,230,231 Port64 64 Ext 400000 Eth252 7 5 8 -Ethernet256 256,257,258,259 Port65 65 Ext 100000 Eth256 2 33 8 -Ethernet260 260,261,262,263 Port66 66 Ext 100000 Eth260 6 33 8 +Ethernet0 96,97,98,99 Port1 1 Ext 100000 etp1 3 1 8 +Ethernet4 100,101,102,103 Port2 2 Ext 100000 etp2 3 5 8 +Ethernet8 104,105,106,107 Port3 3 Ext 100000 etp3 3 9 8 +Ethernet12 108,109,110,111 Port4 4 Ext 100000 etp4 3 13 8 +Ethernet16 112,113,114,115 Port5 5 Ext 100000 etp5 3 17 8 +Ethernet20 116,117,118,119 Port6 6 Ext 100000 etp6 3 21 8 +Ethernet24 120,121,122,123 Port7 7 Ext 100000 etp7 3 25 8 +Ethernet28 124,125,126,127 Port8 8 Ext 100000 etp8 3 29 8 +Ethernet32 56,57,58,59 Port9 9 Ext 100000 etp9 1 25 8 +Ethernet36 60,61,62,63 Port10 10 Ext 100000 etp10 1 29 8 +Ethernet40 48,49,50,51 Port11 11 Ext 100000 etp11 1 17 8 +Ethernet44 52,53,54,55 Port12 12 Ext 100000 etp12 1 21 8 +Ethernet48 40,41,42,43 Port13 13 Ext 100000 etp13 1 9 8 +Ethernet52 44,45,46,47 Port14 14 Ext 100000 etp14 1 13 8 +Ethernet56 32,33,34,35 Port15 15 Ext 100000 etp15 1 1 8 +Ethernet60 36,37,38,39 Port16 16 Ext 100000 etp16 1 5 8 +Ethernet64 128,129,130,131 Port17 17 Ext 100000 etp17 4 1 8 +Ethernet68 132,133,134,135 Port18 18 Ext 100000 etp18 4 5 8 +Ethernet72 136,137,138,139 Port19 19 Ext 100000 etp19 4 9 8 +Ethernet76 140,141,142,143 Port20 20 Ext 100000 etp20 4 13 8 +Ethernet80 144,145,146,147 Port21 21 Ext 100000 etp21 4 17 8 +Ethernet84 148,149,150,151 Port22 22 Ext 100000 etp22 4 21 8 +Ethernet88 152,153,154,155 Port23 23 Ext 100000 etp23 4 25 8 +Ethernet92 156,157,158,159 Port24 24 Ext 100000 etp24 4 29 8 +Ethernet96 216,217,218,219 Port25 25 Ext 100000 etp25 6 25 8 +Ethernet100 220,221,222,223 Port26 26 Ext 100000 etp26 6 29 8 +Ethernet104 208,209,210,211 Port27 27 Ext 100000 etp27 6 17 8 +Ethernet108 212,213,214,215 Port28 28 Ext 100000 etp28 6 21 8 +Ethernet112 200,201,202,203 Port29 29 Ext 100000 etp29 6 9 8 +Ethernet116 204,205,206,207 Port30 30 Ext 100000 etp30 6 13 8 +Ethernet120 192,193,194,195 Port31 31 Ext 100000 etp31 6 1 8 +Ethernet124 196,197,198,199 Port32 32 Ext 100000 etp32 6 5 8 +Ethernet128 64,65,66,67 Port33 33 Ext 400000 etp33 2 1 8 +Ethernet132 68,69,70,71 Port34 34 Ext 400000 etp34 2 5 8 +Ethernet136 72,73,74,75 Port35 35 Ext 400000 etp35 2 9 8 +Ethernet140 76,77,78,79 Port36 36 Ext 400000 etp36 2 13 8 +Ethernet144 80,81,82,83 Port37 37 Ext 400000 etp37 2 17 8 +Ethernet148 84,85,86,87 Port38 38 Ext 400000 etp38 2 21 8 +Ethernet152 88,89,90,91 Port39 39 Ext 400000 etp39 2 25 8 +Ethernet156 92,93,94,95 Port40 40 Ext 400000 etp40 2 29 8 +Ethernet160 24,25,26,27 Port41 41 Ext 400000 etp41 0 25 8 +Ethernet164 28,29,30,31 Port42 42 Ext 400000 etp42 0 29 8 +Ethernet168 16,17,18,19 Port43 43 Ext 400000 etp43 0 17 8 +Ethernet172 20,21,22,23 Port44 44 Ext 400000 etp44 0 21 8 +Ethernet176 8,9,10,11 Port45 45 Ext 400000 etp45 0 9 8 +Ethernet180 12,13,14,15 Port46 46 Ext 400000 etp46 0 13 8 +Ethernet184 0,1,2,3 Port47 47 Ext 400000 etp47 0 1 8 +Ethernet188 4,5,6,7 Port48 48 Ext 400000 etp48 0 5 8 +Ethernet192 160,161,162,163 Port49 49 Ext 400000 etp49 5 1 8 +Ethernet196 164,165,166,167 Port50 50 Ext 400000 etp50 5 5 8 +Ethernet200 168,169,170,171 Port51 51 Ext 400000 etp51 5 9 8 +Ethernet204 172,173,174,175 Port52 52 Ext 400000 etp52 5 13 8 +Ethernet208 176,177,178,179 Port53 53 Ext 400000 etp53 5 17 8 +Ethernet212 180,181,182,183 Port54 54 Ext 400000 etp54 5 21 8 +Ethernet216 184,185,186,187 Port55 55 Ext 400000 etp55 5 25 8 +Ethernet220 188,189,190,191 Port56 56 Ext 400000 etp56 5 29 8 +Ethernet224 248,249,250,251 Port57 57 Ext 400000 etp57 7 25 8 +Ethernet228 252,253,254,255 Port58 58 Ext 400000 etp58 7 29 8 +Ethernet232 240,241,242,243 Port59 59 Ext 400000 etp59 7 17 8 +Ethernet236 244,245,246,247 Port60 60 Ext 400000 etp60 7 21 8 +Ethernet240 232,233,234,235 Port61 61 Ext 400000 etp61 7 9 8 +Ethernet244 236,237,238,239 Port62 62 Ext 400000 etp62 7 13 8 +Ethernet248 224,225,226,227 Port63 63 Ext 400000 etp63 7 1 8 +Ethernet252 228,229,230,231 Port64 64 Ext 400000 etp64 7 5 8 +Ethernet256 256,257,258,259 Port65 65 Ext 100000 etp65 2 33 8 +Ethernet260 260,261,262,263 Port66 66 Ext 100000 etp66 6 33 8 Ethernet-Rec0 621 Port67 67 Rec 400000 Rcy0 0 221 8 diff --git a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/qos.json.j2 b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/qos.json.j2 index 42255ff45d9..96566a63792 100644 --- a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/qos.json.j2 +++ b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O32-C32/qos.json.j2 @@ -169,4 +169,11 @@ {# wred is disabled #} {%- endmacro %} +{%- macro generate_qos_bypass_port_list(PORT_QOS_BYPASS) %} + {# Generate list of ports #} + {%- for port_idx in range(256, 261, 4) %} + {%- if PORT_QOS_BYPASS.append("Ethernet%d" % (port_idx)) %}{%- endif %} + {%- endfor %} +{%- endmacro %} + {%- include 'qos_config.j2' %} diff --git a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/BALANCED/buffers_defaults_t2.j2 b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/BALANCED/buffers_defaults_t2.j2 index b13d888689d..82b04ee679e 100644 --- a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/BALANCED/buffers_defaults_t2.j2 +++ b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/BALANCED/buffers_defaults_t2.j2 @@ -1,18 +1,24 @@ {%- set default_cable = '300m' %} +{%- include 'buffer_ports.j2' %} + {%- set ports2cable = { 'torrouter_server' : '300m', 'leafrouter_torrouter' : '300m', - 'spinerouter_leafrouter' : '300m', - 'regionalhub_spinerouter': '300m', - 'aznghub_spinerouter' : '300m' + 'spinerouter_leafrouter' : '2000m', + 'upperspinerouter_spinerouter' : '50m', + 'upperspinerouter_lowerspinerouter' : '50m', + 'regionalhub_upperspinerouter': '120000m', + 'aznghub_upperspinerouter' : '120000m', + 'regionalhub_spinerouter': '120000m', + 'aznghub_spinerouter' : '120000m' } -%} -{%- macro generate_port_lists(PORT_ALL) %} +{%- macro generate_qos_bypass_port_list(PORT_QOS_BYPASS) %} {# Generate list of ports #} - {%- for port_idx in range(0,256,8) %} - {%- if PORT_ALL.append("Ethernet%d" % (port_idx)) %}{%- endif %} + {%- for port_idx in range(256, 261, 4) %} + {%- if PORT_QOS_BYPASS.append("Ethernet%d" % (port_idx)) %}{%- endif %} {%- endfor %} {%- endmacro %} diff --git a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/BALANCED/qos.json.j2 b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/BALANCED/qos.json.j2 index af1c4dfb256..b28c251ad53 100644 --- a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/BALANCED/qos.json.j2 +++ b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/BALANCED/qos.json.j2 @@ -1,4 +1,12 @@ {%- macro generate_global_dscp_to_tc_map() %} {# This is an empty macro since the global DSCP_TO_TC map is not required #} {%- endmacro %} + +{%- macro generate_qos_bypass_port_list(PORT_QOS_BYPASS) %} + {# Generate list of ports #} + {%- for port_idx in range(256, 261, 4) %} + {%- if PORT_QOS_BYPASS.append("Ethernet%d" % (port_idx)) %}{%- endif %} + {%- endfor %} +{%- endmacro %} + {%- include 'qos_config.j2' %} diff --git a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/buffer_ports.j2 b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/buffer_ports.j2 index ec6460f1243..5775b7a37ad 100644 --- a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/buffer_ports.j2 +++ b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/buffer_ports.j2 @@ -1,6 +1,6 @@ {%- macro generate_port_lists(PORT_ALL) %} {# Generate list of ports #} - {%- for port_idx in range(0, 260, 4) %} + {%- for port_idx in range(0, 253, 4) %} {%- if PORT_ALL.append("Ethernet%d" % (port_idx)) %}{%- endif %} {%- endfor %} {%- endmacro %} diff --git a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/buffers_defaults_t2.j2 b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/buffers_defaults_t2.j2 index 2cf7dca105c..463d5b1bb58 100644 --- a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/buffers_defaults_t2.j2 +++ b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/buffers_defaults_t2.j2 @@ -2,10 +2,10 @@ {%- include 'buffer_ports.j2' %} -{%- macro generate_port_lists(PORT_ALL) %} +{%- macro generate_qos_bypass_port_list(PORT_QOS_BYPASS) %} {# Generate list of ports #} - {%- for port_idx in range(0,256,8) %} - {%- if PORT_ALL.append("Ethernet%d" % (port_idx)) %}{%- endif %} + {%- for port_idx in range(256, 261, 4) %} + {%- if PORT_QOS_BYPASS.append("Ethernet%d" % (port_idx)) %}{%- endif %} {%- endfor %} {%- endmacro %} diff --git a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/nh5010-default.bcm b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/nh5010-default.bcm index 23415fa80f5..c226863090e 100644 --- a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/nh5010-default.bcm +++ b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/nh5010-default.bcm @@ -1823,6 +1823,11 @@ serdes_tx_taps_255.BCM8887X=mode:PAM4,pre:0,main:128,post:0,pre2:0,post2:0,pre3: # ---------------------------------------------------------------------------------------------------- # core_32 +# +# NOTE: +# The QoS configuration (refer qos.json.j2 and buffers_defaults_XXX.j2 file per SKU) +# does not include this management port. If you are modifying the management port, ensure that the +# QoS configuration is updated accordingly to reflect the change. # ---------------------------------------------------------------------------------------------------- ucode_port_257.BCM8887X=CGE64:core_2.33 tm_port_header_type_out_257.BCM8887X=ETH @@ -1850,6 +1855,11 @@ phy_tx_polarity_flip_phy259.BCM8887X=0 # ---------------------------------------------------------------------------------------------------- # core_33 +# +# NOTE: +# The QoS configuration (refer qos.json.j2 and buffers_defaults_XXX.j2 file per SKU) +# does not include this management port. If you are modifying the management port, ensure that the +# QoS configuration is updated accordingly to reflect the change. # ---------------------------------------------------------------------------------------------------- ucode_port_261.BCM8887X=CGE65:core_6.33 tm_port_header_type_out_261.BCM8887X=ETH @@ -2014,9 +2024,6 @@ ucode_port_385.BCM8887X=CPU.12:core_7.205 ucode_port_386.BCM8887X=CPU.20:core_4.206 ucode_port_387.BCM8887X=CPU.28:core_5.207 -#SDK 6.5.31 -custom_feature_statdma_enable.BCM8887X=1 - #special ports ucode_port_330.BCM8887X=EVENTOR:core_0.230 @@ -2109,8 +2116,8 @@ stable_filename.2.BCM8887X=/dev/shm/warmboot_data_2 stable_size.BCM8887X=1700000000 stable_size.BCM8887X_ADAPTER=1700000000 -#disable counter thread -bcm_stat_interval.BCM8887X_ADAPTER=0 +#counter stat interval +bcm_stat_interval.BCM8887X_ADAPTER=1000000 ######################### ######################### @@ -2243,9 +2250,6 @@ custom_feature_adapter_do_collect_enable.BCM8887X_ADAPTER=1 custom_feature_use_new_access.BCM8887X_ADAPTER=1 mem_cache_enable_all.BCM8887X_ADAPTER=1 -#Disable DMA stat -custom_feature_statdma_enable.BCM8887X_ADAPTER=0 - #dram dram_temperature_monitor_enable.BCM8887X_ADAPTER=0 diff --git a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/port_config.ini b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/port_config.ini index eb123965df6..c74f9289d97 100644 --- a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/port_config.ini +++ b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/port_config.ini @@ -1,68 +1,68 @@ # name lanes alias index role speed asic_port_name core_id core_port_id num_voq -Ethernet0 96,97,98,99 Port1 1 Ext 400000 Eth0 3 1 8 -Ethernet4 100,101,102,103 Port2 2 Ext 400000 Eth4 3 5 8 -Ethernet8 104,105,106,107 Port3 3 Ext 400000 Eth8 3 9 8 -Ethernet12 108,109,110,111 Port4 4 Ext 400000 Eth12 3 13 8 -Ethernet16 112,113,114,115 Port5 5 Ext 400000 Eth16 3 17 8 -Ethernet20 116,117,118,119 Port6 6 Ext 400000 Eth20 3 21 8 -Ethernet24 120,121,122,123 Port7 7 Ext 400000 Eth24 3 25 8 -Ethernet28 124,125,126,127 Port8 8 Ext 400000 Eth28 3 29 8 -Ethernet32 56,57,58,59 Port9 9 Ext 400000 Eth32 1 25 8 -Ethernet36 60,61,62,63 Port10 10 Ext 400000 Eth36 1 29 8 -Ethernet40 48,49,50,51 Port11 11 Ext 400000 Eth40 1 17 8 -Ethernet44 52,53,54,55 Port12 12 Ext 400000 Eth44 1 21 8 -Ethernet48 40,41,42,43 Port13 13 Ext 400000 Eth48 1 9 8 -Ethernet52 44,45,46,47 Port14 14 Ext 400000 Eth52 1 13 8 -Ethernet56 32,33,34,35 Port15 15 Ext 400000 Eth56 1 1 8 -Ethernet60 36,37,38,39 Port16 16 Ext 400000 Eth60 1 5 8 -Ethernet64 128,129,130,131 Port17 17 Ext 400000 Eth64 4 1 8 -Ethernet68 132,133,134,135 Port18 18 Ext 400000 Eth68 4 5 8 -Ethernet72 136,137,138,139 Port19 19 Ext 400000 Eth72 4 9 8 -Ethernet76 140,141,142,143 Port20 20 Ext 400000 Eth76 4 13 8 -Ethernet80 144,145,146,147 Port21 21 Ext 400000 Eth80 4 17 8 -Ethernet84 148,149,150,151 Port22 22 Ext 400000 Eth84 4 21 8 -Ethernet88 152,153,154,155 Port23 23 Ext 400000 Eth88 4 25 8 -Ethernet92 156,157,158,159 Port24 24 Ext 400000 Eth92 4 29 8 -Ethernet96 216,217,218,219 Port25 25 Ext 400000 Eth96 6 25 8 -Ethernet100 220,221,222,223 Port26 26 Ext 400000 Eth100 6 29 8 -Ethernet104 208,209,210,211 Port27 27 Ext 400000 Eth108 6 17 8 -Ethernet108 212,213,214,215 Port28 28 Ext 400000 Eth108 6 21 8 -Ethernet112 200,201,202,203 Port29 29 Ext 400000 Eth112 6 9 8 -Ethernet116 204,205,206,207 Port30 30 Ext 400000 Eth116 6 13 8 -Ethernet120 192,193,194,195 Port31 31 Ext 400000 Eth120 6 1 8 -Ethernet124 196,197,198,199 Port32 32 Ext 400000 Eth124 6 5 8 -Ethernet128 64,65,66,67 Port33 33 Ext 400000 Eth128 2 1 8 -Ethernet132 68,69,70,71 Port34 34 Ext 400000 Eth132 2 5 8 -Ethernet136 72,73,74,75 Port35 35 Ext 400000 Eth136 2 9 8 -Ethernet140 76,77,78,79 Port36 36 Ext 400000 Eth140 2 13 8 -Ethernet144 80,81,82,83 Port37 37 Ext 400000 Eth144 2 17 8 -Ethernet148 84,85,86,87 Port38 38 Ext 400000 Eth148 2 21 8 -Ethernet152 88,89,90,91 Port39 39 Ext 400000 Eth152 2 25 8 -Ethernet156 92,93,94,95 Port40 40 Ext 400000 Eth156 2 29 8 -Ethernet160 24,25,26,27 Port41 41 Ext 400000 Eth160 0 25 8 -Ethernet164 28,29,30,31 Port42 42 Ext 400000 Eth164 0 29 8 -Ethernet168 16,17,18,19 Port43 43 Ext 400000 Eth168 0 17 8 -Ethernet172 20,21,22,23 Port44 44 Ext 400000 Eth172 0 21 8 -Ethernet176 8,9,10,11 Port45 45 Ext 400000 Eth176 0 9 8 -Ethernet180 12,13,14,15 Port46 46 Ext 400000 Eth180 0 13 8 -Ethernet184 0,1,2,3 Port47 47 Ext 400000 Eth184 0 1 8 -Ethernet188 4,5,6,7 Port48 48 Ext 400000 Eth188 0 5 8 -Ethernet192 160,161,162,163 Port49 49 Ext 400000 Eth192 5 1 8 -Ethernet196 164,165,166,167 Port50 50 Ext 400000 Eth196 5 5 8 -Ethernet200 168,169,170,171 Port51 51 Ext 400000 Eth200 5 9 8 -Ethernet204 172,173,174,175 Port52 52 Ext 400000 Eth204 5 13 8 -Ethernet208 176,177,178,179 Port53 53 Ext 400000 Eth208 5 17 8 -Ethernet212 180,181,182,183 Port54 54 Ext 400000 Eth212 5 21 8 -Ethernet216 184,185,186,187 Port55 55 Ext 400000 Eth216 5 25 8 -Ethernet220 188,189,190,191 Port56 56 Ext 400000 Eth220 5 29 8 -Ethernet224 248,249,250,251 Port57 57 Ext 400000 Eth224 7 25 8 -Ethernet228 252,253,254,255 Port58 58 Ext 400000 Eth228 7 29 8 -Ethernet232 240,241,242,243 Port59 59 Ext 400000 Eth232 7 17 8 -Ethernet236 244,245,246,247 Port60 60 Ext 400000 Eth236 7 21 8 -Ethernet240 232,233,234,235 Port61 61 Ext 400000 Eth240 7 9 8 -Ethernet244 236,237,238,239 Port62 62 Ext 400000 Eth244 7 13 8 -Ethernet248 224,225,226,227 Port63 63 Ext 400000 Eth248 7 1 8 -Ethernet252 228,229,230,231 Port64 64 Ext 400000 Eth252 7 5 8 -Ethernet256 256,257,258,259 Port65 65 Ext 100000 Eth256 2 33 8 -Ethernet260 260,261,262,263 Port66 66 Ext 100000 Eth260 6 33 8 +Ethernet0 96,97,98,99 Port1 1 Ext 400000 etp1 3 1 8 +Ethernet4 100,101,102,103 Port2 2 Ext 400000 etp2 3 5 8 +Ethernet8 104,105,106,107 Port3 3 Ext 400000 etp3 3 9 8 +Ethernet12 108,109,110,111 Port4 4 Ext 400000 etp4 3 13 8 +Ethernet16 112,113,114,115 Port5 5 Ext 400000 etp5 3 17 8 +Ethernet20 116,117,118,119 Port6 6 Ext 400000 etp6 3 21 8 +Ethernet24 120,121,122,123 Port7 7 Ext 400000 etp7 3 25 8 +Ethernet28 124,125,126,127 Port8 8 Ext 400000 etp8 3 29 8 +Ethernet32 56,57,58,59 Port9 9 Ext 400000 etp9 1 25 8 +Ethernet36 60,61,62,63 Port10 10 Ext 400000 etp10 1 29 8 +Ethernet40 48,49,50,51 Port11 11 Ext 400000 etp11 1 17 8 +Ethernet44 52,53,54,55 Port12 12 Ext 400000 etp12 1 21 8 +Ethernet48 40,41,42,43 Port13 13 Ext 400000 etp13 1 9 8 +Ethernet52 44,45,46,47 Port14 14 Ext 400000 etp14 1 13 8 +Ethernet56 32,33,34,35 Port15 15 Ext 400000 etp15 1 1 8 +Ethernet60 36,37,38,39 Port16 16 Ext 400000 etp16 1 5 8 +Ethernet64 128,129,130,131 Port17 17 Ext 400000 etp17 4 1 8 +Ethernet68 132,133,134,135 Port18 18 Ext 400000 etp18 4 5 8 +Ethernet72 136,137,138,139 Port19 19 Ext 400000 etp19 4 9 8 +Ethernet76 140,141,142,143 Port20 20 Ext 400000 etp20 4 13 8 +Ethernet80 144,145,146,147 Port21 21 Ext 400000 etp21 4 17 8 +Ethernet84 148,149,150,151 Port22 22 Ext 400000 etp22 4 21 8 +Ethernet88 152,153,154,155 Port23 23 Ext 400000 etp23 4 25 8 +Ethernet92 156,157,158,159 Port24 24 Ext 400000 etp24 4 29 8 +Ethernet96 216,217,218,219 Port25 25 Ext 400000 etp25 6 25 8 +Ethernet100 220,221,222,223 Port26 26 Ext 400000 etp26 6 29 8 +Ethernet104 208,209,210,211 Port27 27 Ext 400000 etp27 6 17 8 +Ethernet108 212,213,214,215 Port28 28 Ext 400000 etp28 6 21 8 +Ethernet112 200,201,202,203 Port29 29 Ext 400000 etp29 6 9 8 +Ethernet116 204,205,206,207 Port30 30 Ext 400000 etp30 6 13 8 +Ethernet120 192,193,194,195 Port31 31 Ext 400000 etp31 6 1 8 +Ethernet124 196,197,198,199 Port32 32 Ext 400000 etp32 6 5 8 +Ethernet128 64,65,66,67 Port33 33 Ext 400000 etp33 2 1 8 +Ethernet132 68,69,70,71 Port34 34 Ext 400000 etp34 2 5 8 +Ethernet136 72,73,74,75 Port35 35 Ext 400000 etp35 2 9 8 +Ethernet140 76,77,78,79 Port36 36 Ext 400000 etp36 2 13 8 +Ethernet144 80,81,82,83 Port37 37 Ext 400000 etp37 2 17 8 +Ethernet148 84,85,86,87 Port38 38 Ext 400000 etp38 2 21 8 +Ethernet152 88,89,90,91 Port39 39 Ext 400000 etp39 2 25 8 +Ethernet156 92,93,94,95 Port40 40 Ext 400000 etp40 2 29 8 +Ethernet160 24,25,26,27 Port41 41 Ext 400000 etp41 0 25 8 +Ethernet164 28,29,30,31 Port42 42 Ext 400000 etp42 0 29 8 +Ethernet168 16,17,18,19 Port43 43 Ext 400000 etp43 0 17 8 +Ethernet172 20,21,22,23 Port44 44 Ext 400000 etp44 0 21 8 +Ethernet176 8,9,10,11 Port45 45 Ext 400000 etp45 0 9 8 +Ethernet180 12,13,14,15 Port46 46 Ext 400000 etp46 0 13 8 +Ethernet184 0,1,2,3 Port47 47 Ext 400000 etp47 0 1 8 +Ethernet188 4,5,6,7 Port48 48 Ext 400000 etp48 0 5 8 +Ethernet192 160,161,162,163 Port49 49 Ext 400000 etp49 5 1 8 +Ethernet196 164,165,166,167 Port50 50 Ext 400000 etp50 5 5 8 +Ethernet200 168,169,170,171 Port51 51 Ext 400000 etp51 5 9 8 +Ethernet204 172,173,174,175 Port52 52 Ext 400000 etp52 5 13 8 +Ethernet208 176,177,178,179 Port53 53 Ext 400000 etp53 5 17 8 +Ethernet212 180,181,182,183 Port54 54 Ext 400000 etp54 5 21 8 +Ethernet216 184,185,186,187 Port55 55 Ext 400000 etp55 5 25 8 +Ethernet220 188,189,190,191 Port56 56 Ext 400000 etp56 5 29 8 +Ethernet224 248,249,250,251 Port57 57 Ext 400000 etp57 7 25 8 +Ethernet228 252,253,254,255 Port58 58 Ext 400000 etp58 7 29 8 +Ethernet232 240,241,242,243 Port59 59 Ext 400000 etp59 7 17 8 +Ethernet236 244,245,246,247 Port60 60 Ext 400000 etp60 7 21 8 +Ethernet240 232,233,234,235 Port61 61 Ext 400000 etp61 7 9 8 +Ethernet244 236,237,238,239 Port62 62 Ext 400000 etp62 7 13 8 +Ethernet248 224,225,226,227 Port63 63 Ext 400000 etp63 7 1 8 +Ethernet252 228,229,230,231 Port64 64 Ext 400000 etp64 7 5 8 +Ethernet256 256,257,258,259 Port65 65 Ext 100000 etp65 2 33 8 +Ethernet260 260,261,262,263 Port66 66 Ext 100000 etp66 6 33 8 Ethernet-Rec0 621 Port67 67 Rec 400000 Rcy0 0 221 8 diff --git a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/qos.json.j2 b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/qos.json.j2 index 42255ff45d9..96566a63792 100644 --- a/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/qos.json.j2 +++ b/device/nexthop/x86_64-nexthop_5010-r0/NH-5010-F-O64/qos.json.j2 @@ -169,4 +169,11 @@ {# wred is disabled #} {%- endmacro %} +{%- macro generate_qos_bypass_port_list(PORT_QOS_BYPASS) %} + {# Generate list of ports #} + {%- for port_idx in range(256, 261, 4) %} + {%- if PORT_QOS_BYPASS.append("Ethernet%d" % (port_idx)) %}{%- endif %} + {%- endfor %} +{%- endmacro %} + {%- include 'qos_config.j2' %} From d6910b34d9628162b2267850caf1d73178ed4224 Mon Sep 17 00:00:00 2001 From: Roy Wen Date: Thu, 23 Oct 2025 09:08:03 -0400 Subject: [PATCH 10/13] update top level build files --- platform/broadcom/one-image.mk | 2 ++ platform/broadcom/platform-modules-nexthop.mk | 9 +++++++++ 2 files changed, 11 insertions(+) diff --git a/platform/broadcom/one-image.mk b/platform/broadcom/one-image.mk index 955f9d23c27..2370d6ebc54 100755 --- a/platform/broadcom/one-image.mk +++ b/platform/broadcom/one-image.mk @@ -112,6 +112,8 @@ $(SONIC_ONE_IMAGE)_LAZY_INSTALLS += $(DELL_S6000_PLATFORM_MODULE) \ $(NEXTHOP_4010_R0_PLATFORM_MODULE) \ $(NEXTHOP_4010_R1_PLATFORM_MODULE) \ $(NEXTHOP_4020_R0_PLATFORM_MODULE) \ + $(NEXTHOP_5010_PLATFORM_MODULE) \ + $(NEXTHOP_5010_R0_PLATFORM_MODULE) \ $(MICAS_M2_W6510_48V8C_PLATFORM_MODULE) \ $(MICAS_M2_W6510_48GT4V_PLATFORM_MODULE) \ $(MICAS_M2_W6520_24DC8QC_PLATFORM_MODULE) \ diff --git a/platform/broadcom/platform-modules-nexthop.mk b/platform/broadcom/platform-modules-nexthop.mk index c0ea67a72a5..f247035aa09 100644 --- a/platform/broadcom/platform-modules-nexthop.mk +++ b/platform/broadcom/platform-modules-nexthop.mk @@ -30,3 +30,12 @@ $(eval $(call add_extra_package,$(NEXTHOP_COMMON_PLATFORM_MODULE),$(NEXTHOP_4010 NEXTHOP_4020_R0_PLATFORM_MODULE = sonic-platform-nexthop-4020-r0_1.0_amd64.deb $(NEXTHOP_4020_R0_PLATFORM_MODULE)_PLATFORM = x86_64-nexthop_4020-r0 $(eval $(call add_extra_package,$(NEXTHOP_COMMON_PLATFORM_MODULE),$(NEXTHOP_4020_R0_PLATFORM_MODULE))) + +# NH-5010 +NEXTHOP_5010_PLATFORM_MODULE = sonic-platform-nexthop-5010_1.0_amd64.deb +$(NEXTHOP_5010_PLATFORM_MODULE)_PLATFORM = nexthop-5010 +$(eval $(call add_extra_package,$(NEXTHOP_COMMON_PLATFORM_MODULE),$(NEXTHOP_5010_PLATFORM_MODULE))) + +NEXTHOP_5010_R0_PLATFORM_MODULE = sonic-platform-nexthop-5010-r0_1.0_amd64.deb +$(NEXTHOP_5010_R0_PLATFORM_MODULE)_PLATFORM = x86_64-nexthop_5010-r0 +$(eval $(call add_extra_package,$(NEXTHOP_COMMON_PLATFORM_MODULE),$(NEXTHOP_5010_R0_PLATFORM_MODULE))) From 863e6e8dec52749f1d54c2e75144515dca47a0c1 Mon Sep 17 00:00:00 2001 From: Roy Wen Date: Thu, 23 Oct 2025 21:37:45 -0400 Subject: [PATCH 11/13] remove spi module from pddf json --- device/nexthop/x86_64-nexthop_5010-r0/pddf/pddf-device.json.j2 | 1 - 1 file changed, 1 deletion(-) diff --git a/device/nexthop/x86_64-nexthop_5010-r0/pddf/pddf-device.json.j2 b/device/nexthop/x86_64-nexthop_5010-r0/pddf/pddf-device.json.j2 index 2a91e4d28df..952cbfed37a 100644 --- a/device/nexthop/x86_64-nexthop_5010-r0/pddf/pddf-device.json.j2 +++ b/device/nexthop/x86_64-nexthop_5010-r0/pddf/pddf-device.json.j2 @@ -36,7 +36,6 @@ "pddf_multifpgapci_i2c_module", "pddf_multifpgapci_gpio_module", "pddf_multifpgapci_mdio_module", - "pddf_multifpgapci_spi_module", "pddf_client_module", "pddf_multifpgapci_driver", "pddf_multifpgapci_module", From e2e4c98312d87d89572b7325254477be1eb3433c Mon Sep 17 00:00:00 2001 From: Roy Wen Date: Wed, 29 Oct 2025 13:27:05 -0400 Subject: [PATCH 12/13] follow-up cleanup after resolving merge conflict --- .../test/fixtures/fixtures_unit_test.py | 28 ------------------- 1 file changed, 28 deletions(-) diff --git a/platform/broadcom/sonic-platform-modules-nexthop/test/fixtures/fixtures_unit_test.py b/platform/broadcom/sonic-platform-modules-nexthop/test/fixtures/fixtures_unit_test.py index 205eaa1eb6d..5ff371747f3 100644 --- a/platform/broadcom/sonic-platform-modules-nexthop/test/fixtures/fixtures_unit_test.py +++ b/platform/broadcom/sonic-platform-modules-nexthop/test/fixtures/fixtures_unit_test.py @@ -326,34 +326,6 @@ def __init__( self.watchdog_counter_reg_offset: int = watchdog_counter_reg_offset -class WatchdogBaseMock: - """Mock of WatchdogBase for testing.""" - - def arm(self, seconds): - raise NotImplementedError - - def disarm(self): - raise NotImplementedError - - def is_armed(self): - raise NotImplementedError - - def get_remaining_time(self): - raise NotImplementedError - - -class WatchdogMock(WatchdogBaseMock): - def __init__( - self, - fpga_pci_addr: str, - event_driven_power_cycle_control_reg_offset: int, - watchdog_counter_reg_offset: int, - ): - self.fpga_pci_addr: str = fpga_pci_addr - self.event_driven_power_cycle_control_reg_offset: int = event_driven_power_cycle_control_reg_offset - self.watchdog_counter_reg_offset: int = watchdog_counter_reg_offset - - @pytest.fixture def mock_pddf_data(): """Fixture providing mock PDDF data for tests.""" From 6c7f0f3cbc1bb1757ef60b3140259c6c7cd3a476 Mon Sep 17 00:00:00 2001 From: Roy Wen Date: Thu, 30 Oct 2025 10:39:47 -0400 Subject: [PATCH 13/13] empty commit to retrigger checks