Merge branch 'master' into master-dash-merge

Author: theasianpianist

orchagent/portsorch.cpp

@@ -514,6 +514,18 @@ PortsOrch::PortsOrch(DBConnector *db, DBConnector *stateDb, vector<table_name_wi
 
     if (gMySwitchType != "dpu")
     {
+        sai_attr_capability_t attr_cap;
+        if (sai_query_attribute_capability(gSwitchId, SAI_OBJECT_TYPE_PORT,
+                                           SAI_PORT_ATTR_AUTO_NEG_FEC_MODE_OVERRIDE,
+                                           &attr_cap) != SAI_STATUS_SUCCESS)
+        {
+            SWSS_LOG_NOTICE("Unable to query autoneg fec mode override");
+        }
+        else if (attr_cap.set_implemented && attr_cap.create_implemented)
+        {
+            fec_override_sup = true;
+        }
+
         /* Get default 1Q bridge and default VLAN */
         sai_status_t status;
         sai_attribute_t attr;
@@ -1508,6 +1520,28 @@ bool PortsOrch::setPortTpid(Port &port, sai_uint16_t tpid)
     return true;
 }
 
+bool PortsOrch::setPortFecOverride(sai_object_id_t port_obj, bool fec_override)
+{
+    sai_attribute_t attr;
+    sai_status_t status;
+
+    attr.id = SAI_PORT_ATTR_AUTO_NEG_FEC_MODE_OVERRIDE;
+    attr.value.booldata = fec_override;
+
+    status = sai_port_api->set_port_attribute(port_obj, &attr);
+    if (status != SAI_STATUS_SUCCESS)
+    {
+        SWSS_LOG_ERROR("Failed to set fec override %d to port pid:%" PRIx64, attr.value.booldata, port_obj);
+        task_process_status handle_status = handleSaiSetStatus(SAI_API_PORT, status);
+        if (handle_status != task_success)
+        {
+            return parseHandleSaiStatusFailure(handle_status);
+        }
+    }
+    SWSS_LOG_INFO("Set fec override %d to port pid:%" PRIx64, attr.value.booldata, port_obj);
+    return true;
+}
+
 bool PortsOrch::setPortFec(Port &port, sai_port_fec_mode_t fec_mode)
 {
     SWSS_LOG_ENTER();
@@ -1527,6 +1561,10 @@ bool PortsOrch::setPortFec(Port &port, sai_port_fec_mode_t fec_mode)
         }
     }
 
+    if (fec_override_sup && !setPortFecOverride(port.m_port_id, true))
+    {
+        return false;
+    }
     setGearboxPortsAttr(port, SAI_PORT_ATTR_FEC_MODE, &fec_mode);
 
     SWSS_LOG_NOTICE("Set port %s FEC mode %d", port.m_alias.c_str(), fec_mode);
@@ -2530,6 +2568,10 @@ bool PortsOrch::setGearboxPortAttr(const Port &port, dest_port_type_t port_type,
                     m_gearboxTable->hset(key, speed_attr, to_string(speed));
                     SWSS_LOG_NOTICE("BOX: Updated APPL_DB key:%s %s %d", key.c_str(), speed_attr.c_str(), speed);
                 }
+                else if (id == SAI_PORT_ATTR_FEC_MODE && fec_override_sup && !setPortFecOverride(dest_port_id, true))
+                {
+                    return false;
+                }
             }
             else
             {

orchagent/portsorch.h

@@ -322,6 +322,7 @@ class PortsOrch : public Orch, public Subject
     map<string, uint32_t> m_bridge_port_ref_count;
 
     NotificationConsumer* m_portStatusNotificationConsumer;
+    bool fec_override_sup = false;
 
     swss::SelectableTimer *m_port_state_poller = nullptr;
 
@@ -379,6 +380,7 @@ class PortsOrch : public Orch, public Subject
     bool setPortPvid (Port &port, sai_uint32_t pvid);
     bool getPortPvid(Port &port, sai_uint32_t &pvid);
     bool setPortFec(Port &port, sai_port_fec_mode_t fec_mode);
+    bool setPortFecOverride(sai_object_id_t port_obj, bool fec_override);
     bool setPortPfcAsym(Port &port, sai_port_priority_flow_control_mode_t pfc_asym);
     bool getDestPortId(sai_object_id_t src_port_id, dest_port_type_t port_type, sai_object_id_t &des_port_id);
 

tests/test_port_fec_override.py

@@ -0,0 +1,30 @@
+import time
+import os
+import pytest
+
+from swsscommon import swsscommon
+
+DVS_ENV = ["HWSKU=Mellanox-SN2700"]
+
+class TestPort(object):
+    def test_PortFecOverride(self, dvs, testlog):
+        db = swsscommon.DBConnector(0, dvs.redis_sock, 0)
+        adb = dvs.get_asic_db()
+
+        ptbl = swsscommon.ProducerStateTable(db, "PORT_TABLE")
+
+        # set fec
+        fvs = swsscommon.FieldValuePairs([("fec","rs")])
+        ptbl.set("Ethernet4", fvs)
+
+        # validate if fec rs is pushed to asic db when set first time
+        port_oid = adb.port_name_map["Ethernet4"]
+        expected_fields = {"SAI_PORT_ATTR_FEC_MODE":"SAI_PORT_FEC_MODE_RS", "SAI_PORT_ATTR_AUTO_NEG_FEC_MODE_OVERRIDE":"true"}
+        adb.wait_for_field_match("ASIC_STATE:SAI_OBJECT_TYPE_PORT", port_oid, expected_fields)
+
+
+# Add Dummy always-pass test at end as workaroud
+# for issue when Flaky fail on final test it invokes module tear-down before retrying
+def test_nonflaky_dummy():
+    pass
+