From 89fbc86d733ace3a48390830022fdd02ffb1ba9c Mon Sep 17 00:00:00 2001 From: Badr Bacem KAABIA Date: Wed, 26 Nov 2025 21:08:11 +0100 Subject: [PATCH] target: Add support for NXP FRDM-KW38A4 board The support was implemented using assets from the NXP SDK_2_6_15_FRDM-KW38, which includes the **MKW38A4** MCU. - Added the **MKW38A4** SVD file for peripheral register access and debugging. - Generated and integrated a new FLASH ALGO using KW38x_P256_2KB_SEC.FLM - Implemented the specific KW38A4 target class definition. - Registered the new class in the target module's `__init__.py` to enable automatic detection. Signed-off-by: Badr Bacem KAABIA --- docs/builtin-targets.md | 5 + pyocd/board/board_ids.py | 2 +- pyocd/debug/svd/data/MKW38A4.svd | 192110 ++++++++++++++++ pyocd/target/builtin/__init__.py | 2 + pyocd/target/builtin/target_MKW38A512xxx4.py | 220 + 5 files changed, 192338 insertions(+), 1 deletion(-) create mode 100644 pyocd/debug/svd/data/MKW38A4.svd create mode 100644 pyocd/target/builtin/target_MKW38A512xxx4.py diff --git a/docs/builtin-targets.md b/docs/builtin-targets.md index 2c60d7697..79a7ef03f 100644 --- a/docs/builtin-targets.md +++ b/docs/builtin-targets.md @@ -516,6 +516,11 @@ title: Built-in targets KW36Z4 + kw38a4 + NXP + KW38A4 + + kw40z4 NXP KW40Z4 diff --git a/pyocd/board/board_ids.py b/pyocd/board/board_ids.py index a66a10fb8..80d4d6983 100644 --- a/pyocd/board/board_ids.py +++ b/pyocd/board/board_ids.py @@ -71,7 +71,7 @@ class BoardInfo(NamedTuple): "0246": BoardInfo( "MIMXRT1160-EVK", "mimxrt1166dvm6a", None, ), "0250": BoardInfo( "FRDM-KW24D512", "kw24d5", "l1_kw24d5.bin" ), "0251": BoardInfo( "FRDM-KW36", "kw36z4", "l1_kw36z.bin", ), - "0252": BoardInfo( "FRDM-KW38", "kw38z4", None, ), + "0252": BoardInfo( "FRDM-KW38", "kw38a4", None, ), "0253": BoardInfo( "USB-KW38", "kw38z4", None, ), "0254": BoardInfo( "KW38-ER-RD", "kw38z4", None, ), "0255": BoardInfo( "MIMXRT1040-EVK", "mimxrt1042xjm5b", None, ), diff --git a/pyocd/debug/svd/data/MKW38A4.svd b/pyocd/debug/svd/data/MKW38A4.svd new file mode 100644 index 000000000..f395e7dff --- /dev/null +++ b/pyocd/debug/svd/data/MKW38A4.svd @@ -0,0 +1,192110 @@ + + + NXP Semiconductors + NXP + MKW38A4 + Kinetis_W + 1.6 + MKW38A4 NXP Microcontroller + Copyright 2016-2019 NXP\n All rights reserved.\n SPDX-License-Identifier: BSD-3-Clause + + CM0PLUS + r0p0 + little + false + false + true + 2 + false + + 8 + 32 + + + FTFE_FlashConfig + Flash configuration field + NV_ + 0x400 + + 0 + 0x10 + registers + + + + BACKKEY3 + Backdoor Comparison Key 3. + 0 + 8 + read-only + 0xFF + 0xFF + + + KEY + Backdoor Comparison Key. + 0 + 8 + read-only + + + + + BACKKEY2 + Backdoor Comparison Key 2. + 0x1 + 8 + read-only + 0xFF + 0xFF + + + KEY + Backdoor Comparison Key. + 0 + 8 + read-only + + + + + BACKKEY1 + Backdoor Comparison Key 1. + 0x2 + 8 + read-only + 0xFF + 0xFF + + + KEY + Backdoor Comparison Key. + 0 + 8 + read-only + + + + + BACKKEY0 + Backdoor Comparison Key 0. + 0x3 + 8 + read-only + 0xFF + 0xFF + + + KEY + Backdoor Comparison Key. + 0 + 8 + read-only + + + + + BACKKEY7 + Backdoor Comparison Key 7. + 0x4 + 8 + read-only + 0xFF + 0xFF + + + KEY + Backdoor Comparison Key. + 0 + 8 + read-only + + + + + BACKKEY6 + Backdoor Comparison Key 6. + 0x5 + 8 + read-only + 0xFF + 0xFF + + + KEY + Backdoor Comparison Key. + 0 + 8 + read-only + + + + + BACKKEY5 + Backdoor Comparison Key 5. + 0x6 + 8 + read-only + 0xFF + 0xFF + + + KEY + Backdoor Comparison Key. + 0 + 8 + read-only + + + + + BACKKEY4 + Backdoor Comparison Key 4. + 0x7 + 8 + read-only + 0xFF + 0xFF + + + KEY + Backdoor Comparison Key. + 0 + 8 + read-only + + + + + FPROT3 + Non-volatile P-Flash Protection 1 - Low Register + 0x8 + 8 + read-only + 0xFF + 0xFF + + + PROT + P-Flash Region Protect + 0 + 8 + read-only + + + + + FPROT2 + Non-volatile P-Flash Protection 1 - High Register + 0x9 + 8 + read-only + 0xFF + 0xFF + + + PROT + P-Flash Region Protect + 0 + 8 + read-only + + + + + FPROT1 + Non-volatile P-Flash Protection 0 - Low Register + 0xA + 8 + read-only + 0xFF + 0xFF + + + PROT + P-Flash Region Protect + 0 + 8 + read-only + + + + + FPROT0 + Non-volatile P-Flash Protection 0 - High Register + 0xB + 8 + read-only + 0xFF + 0xFF + + + PROT + P-Flash Region Protect + 0 + 8 + read-only + + + + + FSEC + Non-volatile Flash Security Register + 0xC + 8 + read-only + 0xFF + 0xFF + + + SEC + Flash Security + 0 + 2 + read-only + + + 10 + MCU security status is unsecure + #10 + + + 11 + MCU security status is secure + #11 + + + + + FSLACC + Freescale Failure Analysis Access Code + 2 + 2 + read-only + + + 10 + Freescale factory access denied + #10 + + + 11 + Freescale factory access granted + #11 + + + + + MEEN + no description available + 4 + 2 + read-only + + + 10 + Mass erase is disabled + #10 + + + 11 + Mass erase is enabled + #11 + + + + + KEYEN + Backdoor Key Security Enable + 6 + 2 + read-only + + + 10 + Backdoor key access enabled + #10 + + + 11 + Backdoor key access disabled + #11 + + + + + + + FOPT + Non-volatile Flash Option Register + 0xD + 8 + read-only + 0xFF + 0xFF + + + LPBOOT0 + no description available + 0 + 1 + read-only + + + 0 + Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) when LPBOOT1=0 or 0x1 (divide by 2) when LPBOOT1=1. + #0 + + + 1 + Core and system clock divider (OUTDIV1) is 0x3 (divide by 4) when LPBOOT1=0 or 0x0 (divide by 1) when LPBOOT1=1. + #1 + + + + + NMI_DIS + no description available + 2 + 1 + read-only + + + 0 + NMI interrupts are always blocked + #0 + + + 1 + NMI_b pin/interrupts reset default to enabled + #1 + + + + + RESET_PIN_CFG + no description available + 3 + 1 + read-only + + + 0 + RESET pin is disabled following a POR and cannot be enabled as reset function + #0 + + + 1 + RESET_b pin is dedicated + #1 + + + + + LPBOOT1 + no description available + 4 + 1 + read-only + + + 0 + Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) when LPBOOT0=0 or 0x3 (divide by 4) when LPBOOT0=1. + #0 + + + 1 + Core and system clock divider (OUTDIV1) is 0x1 (divide by 2) when LPBOOT0=0 or 0x0 (divide by 1) when LPBOOT0=1. + #1 + + + + + + + FEPROT + Non-volatile EERAM Protection Register + 0xE + 8 + read-only + 0xFF + 0xFF + + + EPROT + no description available + 0 + 8 + read-only + + + + + FDPROT + Non-volatile D-Flash Protection Register + 0xF + 8 + read-only + 0xFF + 0xFF + + + DPROT + D-Flash Region Protect + 0 + 8 + read-only + + + + + + + DMA0 + DMA + 0x40008000 + + 0 + 0x1080 + registers + + + + CR + Control + 0 + 32 + read-write + 0 + 0x80FFFFFF + + + EDBG + Enable Debug + 1 + 1 + read-write + + + 0 + . When in debug mode, the DMA continues to operate. + #0 + + + 1 + Assertion of system debug control input is effective + #1 + + + + + ERCA + Enable Round Robin Channel Arbitration + 2 + 1 + read-write + + + 0 + Fixed priority arbitration + #0 + + + 1 + Round robin arbitration + #1 + + + + + HOE + Halt On Error + 4 + 1 + read-write + + + 0 + Normal operation + #0 + + + 1 + Error causes HALT field to be automatically set to 1 + #1 + + + + + HALT + Halt DMA Operations + 5 + 1 + read-write + + + 0 + Normal operation + #0 + + + 1 + DMA operations halted + #1 + + + + + CLM + Continuous Link Mode + 6 + 1 + read-write + + + 0 + Continuous link mode is off + #0 + + + 1 + Continuous link mode is on + #1 + + + + + EMLM + Enable Minor Loop Mapping + 7 + 1 + read-write + + + 0 + Disabled + #0 + + + 1 + Enabled + #1 + + + + + ECX + Error Cancel Transfer + 16 + 1 + read-write + + + 0 + Normal operation + #0 + + + 1 + Cancel the remaining data transfer + #1 + + + + + CX + Cancel Transfer + 17 + 1 + read-write + + + 0 + Normal operation + #0 + + + 1 + Cancel the remaining data transfer + #1 + + + + + ACTIVE + DMA Active Status + 31 + 1 + read-only + + + 0 + eDMA is idle + #0 + + + 1 + eDMA is executing a channel + #1 + + + + + + + ES + Error Status + 0x4 + 32 + read-only + 0 + 0xFFFFFFFF + + + DBE + Destination Bus Error + 0 + 1 + read-only + + + 0 + No destination bus error. + #0 + + + 1 + The most-recently recorded error was a bus error on a destination write. + #1 + + + + + SBE + Source Bus Error + 1 + 1 + read-only + + + 0 + No source bus error. + #0 + + + 1 + The most-recently recorded error was a bus error on a source read. + #1 + + + + + SGE + Scatter/Gather Configuration Error + 2 + 1 + read-only + + + 0 + No scatter/gather configuration error. + #0 + + + 1 + The most-recently recorded error was a configuration error detected in the TCDn_DLASTSGA field. + #1 + + + + + NCE + NBYTES/CITER Configuration Error + 3 + 1 + read-only + + + 0 + No NBYTES/CITER configuration error. + #0 + + + 1 + The most-recently recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields. TCDn_NBYTES is not a multiple of TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or TCDn_CITER[CITER] is equal to zero, or TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK]. + #1 + + + + + DOE + Destination Offset Error + 4 + 1 + read-only + + + 0 + No destination offset configuration error. + #0 + + + 1 + The most-recently recorded error was a configuration error detected in the TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE]. + #1 + + + + + DAE + Destination Address Error + 5 + 1 + read-only + + + 0 + No destination address configuration error. + #0 + + + 1 + The most-recently recorded error was a configuration error detected in the TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE]. + #1 + + + + + SOE + Source Offset Error + 6 + 1 + read-only + + + 0 + No source offset configuration error. + #0 + + + 1 + The most-recently recorded error was a configuration error detected in the TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE]. + #1 + + + + + SAE + Source Address Error + 7 + 1 + read-only + + + 0 + No source address configuration error. + #0 + + + 1 + The most-recently recorded error was a configuration error detected in the TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE]. + #1 + + + + + ERRCHN + Error Channel Number or Canceled Channel Number + 8 + 2 + read-only + + + CPE + Channel Priority Error + 14 + 1 + read-only + + + 0 + No channel priority error. + #0 + + + 1 + The most-recently recorded error was a configuration error in the channel priorities. Channel priorities are not unique. + #1 + + + + + ECX + Transfer Canceled + 16 + 1 + read-only + + + 0 + No canceled transfers + #0 + + + 1 + The most-recently recorded entry was a canceled transfer initiated by the error cancel transfer field + #1 + + + + + VLD + Logical OR of all ERR status fields + 31 + 1 + read-only + + + 0 + No ERR fields are 1 + #0 + + + 1 + At least one ERR field is 1, indicating a valid error exists that has not been cleared + #1 + + + + + + + ERQ + Enable Request + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + ERQ0 + Enable DMA Request 0 + 0 + 1 + read-write + + + 0 + The DMA request signal for channel 0 is disabled + #0 + + + 1 + The DMA request signal for channel 0 is enabled + #1 + + + + + ERQ1 + Enable DMA Request 1 + 1 + 1 + read-write + + + 0 + The DMA request signal for channel 1 is disabled + #0 + + + 1 + The DMA request signal for channel 1 is enabled + #1 + + + + + ERQ2 + Enable DMA Request 2 + 2 + 1 + read-write + + + 0 + The DMA request signal for channel 2 is disabled + #0 + + + 1 + The DMA request signal for channel 2 is enabled + #1 + + + + + ERQ3 + Enable DMA Request 3 + 3 + 1 + read-write + + + 0 + The DMA request signal for channel 3 is disabled + #0 + + + 1 + The DMA request signal for channel 3 is enabled + #1 + + + + + + + EEI + Enable Error Interrupt + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + EEI0 + Enable Error Interrupt 0 + 0 + 1 + read-write + + + 0 + The error signal for channel 0 does not generate an error interrupt + #0 + + + 1 + The assertion of the error signal for channel 0 generates an error interrupt request + #1 + + + + + EEI1 + Enable Error Interrupt 1 + 1 + 1 + read-write + + + 0 + The error signal for channel 1 does not generate an error interrupt + #0 + + + 1 + The assertion of the error signal for channel 1 generates an error interrupt request + #1 + + + + + EEI2 + Enable Error Interrupt 2 + 2 + 1 + read-write + + + 0 + The error signal for channel 2 does not generate an error interrupt + #0 + + + 1 + The assertion of the error signal for channel 2 generates an error interrupt request + #1 + + + + + EEI3 + Enable Error Interrupt 3 + 3 + 1 + read-write + + + 0 + The error signal for channel 3 does not generate an error interrupt + #0 + + + 1 + The assertion of the error signal for channel 3 generates an error interrupt request + #1 + + + + + + + CEEI + Clear Enable Error Interrupt + 0x18 + 8 + read-write + 0 + 0xFF + + + CEEI + Clear Enable Error Interrupt + 0 + 2 + read-write + + + CAEE + Clear All Enable Error Interrupts + 6 + 1 + read-write + + + 0 + Write 0 only to the EEI field specified in the CEEI field + #0 + + + 1 + Write 0 to all fields in EEI + #1 + + + + + NOP + No Op Enable + 7 + 1 + read-write + + + 0 + Normal operation + #0 + + + 1 + No operation, ignore the other fields in this register + #1 + + + + + + + SEEI + Set Enable Error Interrupt + 0x19 + 8 + read-write + 0 + 0xFF + + + SEEI + Set Enable Error Interrupt + 0 + 2 + read-write + + + SAEE + Set All Enable Error Interrupts + 6 + 1 + read-write + + + 0 + Write 1 only to the EEI field specified in the SEEI field + #0 + + + 1 + Writes 1 to all fields in EEI + #1 + + + + + NOP + No Op Enable + 7 + 1 + read-write + + + 0 + Normal operation + #0 + + + 1 + No operation, ignore the other fields in this register + #1 + + + + + + + CERQ + Clear Enable Request + 0x1A + 8 + read-write + 0 + 0xFF + + + CERQ + Clear Enable Request + 0 + 2 + read-write + + + CAER + Clear All Enable Requests + 6 + 1 + read-write + + + 0 + Write 0 to only the ERQ field specified in the CERQ field + #0 + + + 1 + Write 0 to all fields in ERQ + #1 + + + + + NOP + No Op Enable + 7 + 1 + read-write + + + 0 + Normal operation + #0 + + + 1 + No operation, ignore the other fields in this register + #1 + + + + + + + SERQ + Set Enable Request + 0x1B + 8 + read-write + 0 + 0xFF + + + SERQ + Set Enable Request + 0 + 2 + read-write + + + SAER + Set All Enable Requests + 6 + 1 + read-write + + + 0 + Write 1 to only the ERQ field specified in the SERQ field + #0 + + + 1 + Write 1 to all fields in ERQ + #1 + + + + + NOP + No Op Enable + 7 + 1 + read-write + + + 0 + Normal operation + #0 + + + 1 + No operation, ignore the other fields in this register + #1 + + + + + + + CDNE + Clear DONE Status Bit + 0x1C + 8 + read-write + 0 + 0xFF + + + CDNE + Clear DONE field + 0 + 2 + read-write + + + CADN + Clears All DONE fields + 6 + 1 + read-write + + + 0 + Writes 0 to only the TCDn_CSR[DONE] field specified in the CDNE field + #0 + + + 1 + Writes 0 to all bits in TCDn_CSR[DONE] + #1 + + + + + NOP + No Op Enable + 7 + 1 + read-write + + + 0 + Normal operation + #0 + + + 1 + No operation; all other fields in this register are ignored. + #1 + + + + + + + SSRT + Set START Bit + 0x1D + 8 + read-write + 0 + 0xFF + + + SSRT + Set START field + 0 + 2 + read-write + + + SAST + Set All START fields (activates all channels) + 6 + 1 + read-write + + + 0 + Write 1 to only the TCDn_CSR[START] field specified in the SSRT field + #0 + + + 1 + Write 1 to all bits in TCDn_CSR[START] + #1 + + + + + NOP + No Op Enable + 7 + 1 + read-write + + + 0 + Normal operation + #0 + + + 1 + No operation; all other fields in this register are ignored. + #1 + + + + + + + CERR + Clear Error + 0x1E + 8 + read-write + 0 + 0xFF + + + CERR + Clear Error Indicator + 0 + 2 + read-write + + + CAEI + Clear All Error Indicators + 6 + 1 + read-write + + + 0 + Write 0 to only the ERR field specified in the CERR field + #0 + + + 1 + Write 0 to all fields in ERR + #1 + + + + + NOP + No Op Enable + 7 + 1 + read-write + + + 0 + Normal operation + #0 + + + 1 + No operation; all other fields in this register are ignored. + #1 + + + + + + + CINT + Clear Interrupt Request + 0x1F + 8 + read-write + 0 + 0xFF + + + CINT + Clear Interrupt Request + 0 + 2 + read-write + + + CAIR + Clear All Interrupt Requests + 6 + 1 + read-write + + + 0 + Clear only the INT field specified in the CINT field + #0 + + + 1 + Clear all bits in INT + #1 + + + + + NOP + No Op Enable + 7 + 1 + read-write + + + 0 + Normal operation + #0 + + + 1 + No operation; all other fields in this register are ignored. + #1 + + + + + + + INT + Interrupt Request + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + INT0 + Interrupt Request 0 + 0 + 1 + read-write + + + 1 + The interrupt request for channel 0 is cleared + #1 + + + + + INT1 + Interrupt Request 1 + 1 + 1 + read-write + + + 1 + The interrupt request for channel 1 is cleared + #1 + + + + + INT2 + Interrupt Request 2 + 2 + 1 + read-write + + + 1 + The interrupt request for channel 2 is cleared + #1 + + + + + INT3 + Interrupt Request 3 + 3 + 1 + read-write + + + 1 + The interrupt request for channel 3 is cleared + #1 + + + + + + + ERR + Error + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + ERR0 + Error In Channel 0 + 0 + 1 + read-write + + + 0 + No error in this channel has occurred + #0 + + + 1 + An error in this channel has occurred + #1 + + + + + ERR1 + Error In Channel 1 + 1 + 1 + read-write + + + 0 + No error in this channel has occurred + #0 + + + 1 + An error in this channel has occurred + #1 + + + + + ERR2 + Error In Channel 2 + 2 + 1 + read-write + + + 0 + No error in this channel has occurred + #0 + + + 1 + An error in this channel has occurred + #1 + + + + + ERR3 + Error In Channel 3 + 3 + 1 + read-write + + + 0 + No error in this channel has occurred + #0 + + + 1 + An error in this channel has occurred + #1 + + + + + + + HRS + Hardware Request Status + 0x34 + 32 + read-only + 0 + 0xFFFFFFFF + + + HRS0 + Hardware Request Status Channel 0 + 0 + 1 + read-only + + + 0 + A hardware service request for channel 0 is not present + #0 + + + 1 + A hardware service request for channel 0 is present + #1 + + + + + HRS1 + Hardware Request Status Channel 1 + 1 + 1 + read-only + + + 0 + A hardware service request for channel 1 is not present + #0 + + + 1 + A hardware service request for channel 1 is present + #1 + + + + + HRS2 + Hardware Request Status Channel 2 + 2 + 1 + read-only + + + 0 + A hardware service request for channel 2 is not present + #0 + + + 1 + A hardware service request for channel 2 is present + #1 + + + + + HRS3 + Hardware Request Status Channel 3 + 3 + 1 + read-only + + + 0 + A hardware service request for channel 3 is not present + #0 + + + 1 + A hardware service request for channel 3 is present + #1 + + + + + + + EARS + Enable Asynchronous Request in Stop + 0x44 + 32 + read-write + 0 + 0xFFFFFFFF + + + EDREQ_0 + Enable asynchronous DMA request in stop mode for channel 0. + 0 + 1 + read-write + + + 0 + Disable asynchronous DMA request for channel 0 + #0 + + + 1 + Enable asynchronous DMA request for channel 0 + #1 + + + + + EDREQ_1 + Enable asynchronous DMA request in stop mode for channel 1. + 1 + 1 + read-write + + + 0 + Disable asynchronous DMA request for channel 1 + #0 + + + 1 + Enable asynchronous DMA request for channel 1 + #1 + + + + + EDREQ_2 + Enable asynchronous DMA request in stop mode for channel 2. + 2 + 1 + read-write + + + 0 + Disable asynchronous DMA request for channel 2 + #0 + + + 1 + Enable asynchronous DMA request for channel 2 + #1 + + + + + EDREQ_3 + Enable asynchronous DMA request in stop mode for channel 3. + 3 + 1 + read-write + + + 0 + Disable asynchronous DMA request for channel 3 + #0 + + + 1 + Enable asynchronous DMA request for channel 3 + #1 + + + + + + + DCHPRI3 + Channel Priority + 0x100 + 8 + read-write + 0x3 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 2 + read-write + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + 0 + Channel n can suspend a lower priority channel + #0 + + + 1 + Channel n cannot suspend any channel, regardless of channel priority + #1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + 0 + Channel n cannot be suspended by a higher priority channel's service request + #0 + + + 1 + Channel n can be temporarily suspended by the service request of a higher priority channel + #1 + + + + + + + DCHPRI2 + Channel Priority + 0x101 + 8 + read-write + 0x2 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 2 + read-write + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + 0 + Channel n can suspend a lower priority channel + #0 + + + 1 + Channel n cannot suspend any channel, regardless of channel priority + #1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + 0 + Channel n cannot be suspended by a higher priority channel's service request + #0 + + + 1 + Channel n can be temporarily suspended by the service request of a higher priority channel + #1 + + + + + + + DCHPRI1 + Channel Priority + 0x102 + 8 + read-write + 0x1 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 2 + read-write + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + 0 + Channel n can suspend a lower priority channel + #0 + + + 1 + Channel n cannot suspend any channel, regardless of channel priority + #1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + 0 + Channel n cannot be suspended by a higher priority channel's service request + #0 + + + 1 + Channel n can be temporarily suspended by the service request of a higher priority channel + #1 + + + + + + + DCHPRI0 + Channel Priority + 0x103 + 8 + read-write + 0 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 2 + read-write + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + 0 + Channel n can suspend a lower priority channel + #0 + + + 1 + Channel n cannot suspend any channel, regardless of channel priority + #1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + 0 + Channel n cannot be suspended by a higher priority channel's service request + #0 + + + 1 + Channel n can be temporarily suspended by the service request of a higher priority channel + #1 + + + + + + + TCD0_SADDR + TCD Source Address + 0x1000 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD0_SOFF + TCD Signed Source Address Offset + 0x1004 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD0_ATTR + TCD Transfer Attributes + 0x1006 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + 000 + 8-bit + #000 + + + 001 + 16-bit + #001 + + + 010 + 32-bit + #010 + + + 100 + 16-byte + #100 + + + 101 + 32-byte + #101 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + 0 + Source address modulo feature is disabled + #00000 + + + + + + + TCD0_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + DMA0 + 0x1008 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD0_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + DMA0 + 0x1008 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset Enable + 30 + 1 + read-write + + + 0 + The minor loop offset is not applied to the DADDR + #0 + + + 1 + The minor loop offset is applied to the DADDR + #1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + 0 + The minor loop offset is not applied to the SADDR + #0 + + + 1 + The minor loop offset is applied to the SADDR + #1 + + + + + + + TCD0_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + DMA0 + 0x1008 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset Enable + 30 + 1 + read-write + + + 0 + The minor loop offset is not applied to the DADDR + #0 + + + 1 + The minor loop offset is applied to the DADDR + #1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + 0 + The minor loop offset is not applied to the SADDR + #0 + + + 1 + The minor loop offset is applied to the SADDR + #1 + + + + + + + TCD0_SLAST + TCD Last Source Address Adjustment + 0x100C + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD0_DADDR + TCD Destination Address + 0x1010 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD0_DOFF + TCD Signed Destination Address Offset + 0x1014 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD0_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + DMA0 + 0x1016 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + 0 + Channel-to-channel linking is disabled + #0 + + + 1 + Channel-to-channel linking is enabled + #1 + + + + + + + TCD0_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + DMA0 + 0x1016 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 2 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + 0 + Channel-to-channel linking is disabled + #0 + + + 1 + Channel-to-channel linking is enabled + #1 + + + + + + + TCD0_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x1018 + 32 + read-write + 0 + 0 + + + DLASTSGA + Destination last address adjustment, or next memory address transfer control descriptor for channel (scatter/gather) + 0 + 32 + read-write + + + + + TCD0_CSR + TCD Control and Status + 0x101C + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + 0 + Channel is not explicitly started + #0 + + + 1 + Channel is explicitly started via a software initiated service request + #1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + 0 + End of major loop interrupt is disabled + #0 + + + 1 + End of major loop interrupt is enabled + #1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + 0 + Half-point interrupt is disabled + #0 + + + 1 + Half-point interrupt is enabled + #1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + 0 + The channel's ERQ field is not affected + #0 + + + 1 + The channel's ERQ field is cleared when the major loop is complete + #1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + 0 + The current channel's TCD is normal format + #0 + + + 1 + The current channel's TCD specifies a scatter gather format + #1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + 1 + Channel-to-channel linking is disabled + #1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 2 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + 00 + No eDMA engine stalls + #00 + + + 10 + eDMA engine stalls for 4 cycles after each R/W + #10 + + + 11 + eDMA engine stalls for 8 cycles after each R/W + #11 + + + + + + + TCD0_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + DMA0 + 0x101E + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + 0 + Channel-to-channel linking is disabled + #0 + + + 1 + Channel-to-channel linking is enabled + #1 + + + + + + + TCD0_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + DMA0 + 0x101E + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 2 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + 0 + Channel-to-channel linking is disabled + #0 + + + 1 + Channel-to-channel linking is enabled + #1 + + + + + + + TCD1_SADDR + TCD Source Address + 0x1020 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD1_SOFF + TCD Signed Source Address Offset + 0x1024 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD1_ATTR + TCD Transfer Attributes + 0x1026 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + 000 + 8-bit + #000 + + + 001 + 16-bit + #001 + + + 010 + 32-bit + #010 + + + 100 + 16-byte + #100 + + + 101 + 32-byte + #101 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + 0 + Source address modulo feature is disabled + #00000 + + + + + + + TCD1_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + DMA0 + 0x1028 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD1_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + DMA0 + 0x1028 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset Enable + 30 + 1 + read-write + + + 0 + The minor loop offset is not applied to the DADDR + #0 + + + 1 + The minor loop offset is applied to the DADDR + #1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + 0 + The minor loop offset is not applied to the SADDR + #0 + + + 1 + The minor loop offset is applied to the SADDR + #1 + + + + + + + TCD1_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + DMA0 + 0x1028 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset Enable + 30 + 1 + read-write + + + 0 + The minor loop offset is not applied to the DADDR + #0 + + + 1 + The minor loop offset is applied to the DADDR + #1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + 0 + The minor loop offset is not applied to the SADDR + #0 + + + 1 + The minor loop offset is applied to the SADDR + #1 + + + + + + + TCD1_SLAST + TCD Last Source Address Adjustment + 0x102C + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD1_DADDR + TCD Destination Address + 0x1030 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD1_DOFF + TCD Signed Destination Address Offset + 0x1034 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD1_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + DMA0 + 0x1036 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + 0 + Channel-to-channel linking is disabled + #0 + + + 1 + Channel-to-channel linking is enabled + #1 + + + + + + + TCD1_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + DMA0 + 0x1036 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 2 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + 0 + Channel-to-channel linking is disabled + #0 + + + 1 + Channel-to-channel linking is enabled + #1 + + + + + + + TCD1_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x1038 + 32 + read-write + 0 + 0 + + + DLASTSGA + Destination last address adjustment, or next memory address transfer control descriptor for channel (scatter/gather) + 0 + 32 + read-write + + + + + TCD1_CSR + TCD Control and Status + 0x103C + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + 0 + Channel is not explicitly started + #0 + + + 1 + Channel is explicitly started via a software initiated service request + #1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + 0 + End of major loop interrupt is disabled + #0 + + + 1 + End of major loop interrupt is enabled + #1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + 0 + Half-point interrupt is disabled + #0 + + + 1 + Half-point interrupt is enabled + #1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + 0 + The channel's ERQ field is not affected + #0 + + + 1 + The channel's ERQ field is cleared when the major loop is complete + #1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + 0 + The current channel's TCD is normal format + #0 + + + 1 + The current channel's TCD specifies a scatter gather format + #1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + 1 + Channel-to-channel linking is disabled + #1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 2 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + 00 + No eDMA engine stalls + #00 + + + 10 + eDMA engine stalls for 4 cycles after each R/W + #10 + + + 11 + eDMA engine stalls for 8 cycles after each R/W + #11 + + + + + + + TCD1_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + DMA0 + 0x103E + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + 0 + Channel-to-channel linking is disabled + #0 + + + 1 + Channel-to-channel linking is enabled + #1 + + + + + + + TCD1_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + DMA0 + 0x103E + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 2 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + 0 + Channel-to-channel linking is disabled + #0 + + + 1 + Channel-to-channel linking is enabled + #1 + + + + + + + TCD2_SADDR + TCD Source Address + 0x1040 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD2_SOFF + TCD Signed Source Address Offset + 0x1044 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD2_ATTR + TCD Transfer Attributes + 0x1046 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + 000 + 8-bit + #000 + + + 001 + 16-bit + #001 + + + 010 + 32-bit + #010 + + + 100 + 16-byte + #100 + + + 101 + 32-byte + #101 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + 0 + Source address modulo feature is disabled + #00000 + + + + + + + TCD2_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + DMA0 + 0x1048 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD2_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + DMA0 + 0x1048 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset Enable + 30 + 1 + read-write + + + 0 + The minor loop offset is not applied to the DADDR + #0 + + + 1 + The minor loop offset is applied to the DADDR + #1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + 0 + The minor loop offset is not applied to the SADDR + #0 + + + 1 + The minor loop offset is applied to the SADDR + #1 + + + + + + + TCD2_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + DMA0 + 0x1048 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset Enable + 30 + 1 + read-write + + + 0 + The minor loop offset is not applied to the DADDR + #0 + + + 1 + The minor loop offset is applied to the DADDR + #1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + 0 + The minor loop offset is not applied to the SADDR + #0 + + + 1 + The minor loop offset is applied to the SADDR + #1 + + + + + + + TCD2_SLAST + TCD Last Source Address Adjustment + 0x104C + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD2_DADDR + TCD Destination Address + 0x1050 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD2_DOFF + TCD Signed Destination Address Offset + 0x1054 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD2_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + DMA0 + 0x1056 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + 0 + Channel-to-channel linking is disabled + #0 + + + 1 + Channel-to-channel linking is enabled + #1 + + + + + + + TCD2_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + DMA0 + 0x1056 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 2 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + 0 + Channel-to-channel linking is disabled + #0 + + + 1 + Channel-to-channel linking is enabled + #1 + + + + + + + TCD2_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x1058 + 32 + read-write + 0 + 0 + + + DLASTSGA + Destination last address adjustment, or next memory address transfer control descriptor for channel (scatter/gather) + 0 + 32 + read-write + + + + + TCD2_CSR + TCD Control and Status + 0x105C + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + 0 + Channel is not explicitly started + #0 + + + 1 + Channel is explicitly started via a software initiated service request + #1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + 0 + End of major loop interrupt is disabled + #0 + + + 1 + End of major loop interrupt is enabled + #1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + 0 + Half-point interrupt is disabled + #0 + + + 1 + Half-point interrupt is enabled + #1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + 0 + The channel's ERQ field is not affected + #0 + + + 1 + The channel's ERQ field is cleared when the major loop is complete + #1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + 0 + The current channel's TCD is normal format + #0 + + + 1 + The current channel's TCD specifies a scatter gather format + #1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + 1 + Channel-to-channel linking is disabled + #1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 2 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + 00 + No eDMA engine stalls + #00 + + + 10 + eDMA engine stalls for 4 cycles after each R/W + #10 + + + 11 + eDMA engine stalls for 8 cycles after each R/W + #11 + + + + + + + TCD2_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + DMA0 + 0x105E + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + 0 + Channel-to-channel linking is disabled + #0 + + + 1 + Channel-to-channel linking is enabled + #1 + + + + + + + TCD2_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + DMA0 + 0x105E + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 2 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + 0 + Channel-to-channel linking is disabled + #0 + + + 1 + Channel-to-channel linking is enabled + #1 + + + + + + + TCD3_SADDR + TCD Source Address + 0x1060 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD3_SOFF + TCD Signed Source Address Offset + 0x1064 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD3_ATTR + TCD Transfer Attributes + 0x1066 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + 000 + 8-bit + #000 + + + 001 + 16-bit + #001 + + + 010 + 32-bit + #010 + + + 100 + 16-byte + #100 + + + 101 + 32-byte + #101 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + 0 + Source address modulo feature is disabled + #00000 + + + + + + + TCD3_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + DMA0 + 0x1068 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD3_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + DMA0 + 0x1068 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset Enable + 30 + 1 + read-write + + + 0 + The minor loop offset is not applied to the DADDR + #0 + + + 1 + The minor loop offset is applied to the DADDR + #1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + 0 + The minor loop offset is not applied to the SADDR + #0 + + + 1 + The minor loop offset is applied to the SADDR + #1 + + + + + + + TCD3_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + DMA0 + 0x1068 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset Enable + 30 + 1 + read-write + + + 0 + The minor loop offset is not applied to the DADDR + #0 + + + 1 + The minor loop offset is applied to the DADDR + #1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + 0 + The minor loop offset is not applied to the SADDR + #0 + + + 1 + The minor loop offset is applied to the SADDR + #1 + + + + + + + TCD3_SLAST + TCD Last Source Address Adjustment + 0x106C + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD3_DADDR + TCD Destination Address + 0x1070 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD3_DOFF + TCD Signed Destination Address Offset + 0x1074 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD3_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + DMA0 + 0x1076 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + 0 + Channel-to-channel linking is disabled + #0 + + + 1 + Channel-to-channel linking is enabled + #1 + + + + + + + TCD3_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + DMA0 + 0x1076 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 2 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + 0 + Channel-to-channel linking is disabled + #0 + + + 1 + Channel-to-channel linking is enabled + #1 + + + + + + + TCD3_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x1078 + 32 + read-write + 0 + 0 + + + DLASTSGA + Destination last address adjustment, or next memory address transfer control descriptor for channel (scatter/gather) + 0 + 32 + read-write + + + + + TCD3_CSR + TCD Control and Status + 0x107C + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + 0 + Channel is not explicitly started + #0 + + + 1 + Channel is explicitly started via a software initiated service request + #1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + 0 + End of major loop interrupt is disabled + #0 + + + 1 + End of major loop interrupt is enabled + #1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + 0 + Half-point interrupt is disabled + #0 + + + 1 + Half-point interrupt is enabled + #1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + 0 + The channel's ERQ field is not affected + #0 + + + 1 + The channel's ERQ field is cleared when the major loop is complete + #1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + 0 + The current channel's TCD is normal format + #0 + + + 1 + The current channel's TCD specifies a scatter gather format + #1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + 1 + Channel-to-channel linking is disabled + #1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 2 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + 00 + No eDMA engine stalls + #00 + + + 10 + eDMA engine stalls for 4 cycles after each R/W + #10 + + + 11 + eDMA engine stalls for 8 cycles after each R/W + #11 + + + + + + + TCD3_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + DMA0 + 0x107E + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + 0 + Channel-to-channel linking is disabled + #0 + + + 1 + Channel-to-channel linking is enabled + #1 + + + + + + + TCD3_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + DMA0 + 0x107E + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 2 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + 0 + Channel-to-channel linking is disabled + #0 + + + 1 + Channel-to-channel linking is enabled + #1 + + + + + + + + + PFLEXNVM + FAC + 0x4001F000 + + 0 + 0x380 + registers + + + + PFAPR + Flash Access Protection Register + 0 + 32 + read-write + 0xF8003F + 0xFFFFFFFF + + + M0AP + Master 0 Access Protection + 0 + 2 + read-write + + + 00 + No access may be performed by this master + #00 + + + 01 + Only read accesses may be performed by this master + #01 + + + 10 + Only write accesses may be performed by this master + #10 + + + 11 + Both read and write accesses may be performed by this master + #11 + + + + + M1AP + Master 1 Access Protection + 2 + 2 + read-write + + + 00 + No access may be performed by this master + #00 + + + 01 + Only read accesses may be performed by this master + #01 + + + 10 + Only write accesses may be performed by this master + #10 + + + 11 + Both read and write accesses may be performed by this master + #11 + + + + + M2AP + Master 2 Access Protection + 4 + 2 + read-write + + + 00 + No access may be performed by this master + #00 + + + 01 + Only read accesses may be performed by this master + #01 + + + 10 + Only write accesses may be performed by this master + #10 + + + 11 + Both read and write accesses may be performed by this master + #11 + + + + + M0PFD + Master 0 Prefetch Disable + 16 + 1 + read-write + + + 0 + Prefetching for this master is enabled. + #0 + + + 1 + Prefetching for this master is disabled. + #1 + + + + + M1PFD + Master 1 Prefetch Disable + 17 + 1 + read-write + + + 0 + Prefetching for this master is enabled. + #0 + + + 1 + Prefetching for this master is disabled. + #1 + + + + + M2PFD + Master 2 Prefetch Disable + 18 + 1 + read-write + + + 0 + Prefetching for this master is enabled. + #0 + + + 1 + Prefetching for this master is disabled. + #1 + + + + + + + PFB0CR + Flash Bank 0 Control Register + 0x4 + 32 + read-write + 0x3002001F + 0xFFFFFFFF + + + B0SEBE + Bank 0 Single Entry Buffer Enable + 0 + 1 + read-write + + + 0 + Single entry buffer is disabled. + #0 + + + 1 + Single entry buffer is enabled. + #1 + + + + + B0IPE + Bank 0 Instruction Prefetch Enable + 1 + 1 + read-write + + + 0 + Do not prefetch in response to instruction fetches. + #0 + + + 1 + Enable prefetches in response to instruction fetches. + #1 + + + + + B0DPE + Bank 0 Data Prefetch Enable + 2 + 1 + read-write + + + 0 + Do not prefetch in response to data references. + #0 + + + 1 + Enable prefetches in response to data references. + #1 + + + + + B0ICE + Bank 0 Instruction Cache Enable + 3 + 1 + read-write + + + 0 + Do not cache instruction fetches. + #0 + + + 1 + Cache instruction fetches. + #1 + + + + + B0DCE + Bank 0 Data Cache Enable + 4 + 1 + read-write + + + 0 + Do not cache data references. + #0 + + + 1 + Cache data references. + #1 + + + + + CRC + Cache Replacement Control + 5 + 3 + read-write + + + 00 + LRU replacement algorithm per set across all four ways + #000 + + + 10 + Independent LRU with ways [0-1] for ifetches, [2-3] for data + #010 + + + 11 + Independent LRU with ways [0-2] for ifetches, [3] for data + #011 + + + + + B0MW + Bank 0 Memory Width + 17 + 2 + read-only + + + 0 + 32 bits + #00 + + + 1 + 64 bits + #01 + + + + + S_B_INV + Invalidate Prefetch Speculation Buffer + 19 + 1 + read-write + + + 0 + Speculation buffer and single entry buffer are not affected. + #0 + + + 1 + Invalidate (clear) speculation buffer and single entry buffer. + #1 + + + + + CINV_WAY + Cache Invalidate Way x + 20 + 4 + read-write + + + 0 + No cache way invalidation for the corresponding cache + #0000 + + + 1 + Invalidate cache way for the corresponding cache: clear the tag, data, and vld bits of ways selected + #0001 + + + + + CLCK_WAY + Cache Lock Way x + 24 + 4 + read-write + + + 0 + Cache way is unlocked and may be displaced + #0000 + + + 1 + Cache way is locked and its contents are not displaced + #0001 + + + + + B0RWSC + Bank 0 Read Wait State Control + 28 + 4 + read-only + + + + + Reserved_PFB1CR + Reserved Flash Bank 1 Control Register + 0x8 + 32 + read-write + 0x3002001F + 0xFFFFFFFF + + + B1SEBE + Bank 1 Single Entry Buffer Enable + 0 + 1 + read-write + + + 0 + Single entry buffer is disabled. + #0 + + + 1 + Single entry buffer is enabled. + #1 + + + + + B1IPE + Bank 1 Instruction Prefetch Enable + 1 + 1 + read-write + + + 0 + Do not prefetch in response to instruction fetches. + #0 + + + 1 + Enable prefetches in response to instruction fetches. + #1 + + + + + B1DPE + Bank 1 Data Prefetch Enable + 2 + 1 + read-write + + + 0 + Do not prefetch in response to data references. + #0 + + + 1 + Enable prefetches in response to data references. + #1 + + + + + B1ICE + Bank 1 Instruction Cache Enable + 3 + 1 + read-write + + + 0 + Do not cache instruction fetches. + #0 + + + 1 + Cache instruction fetches. + #1 + + + + + B1DCE + Bank 1 Data Cache Enable + 4 + 1 + read-write + + + 0 + Do not cache data references. + #0 + + + 1 + Cache data references. + #1 + + + + + B1MW + Bank 1 Memory Width + 17 + 2 + read-only + + + 0 + 32 bits + #00 + + + 1 + 64 bits + #01 + + + + + B1RWSC + Bank 1 Read Wait State Control + 28 + 4 + read-only + + + + + TAGVDW0S0 + Cache Tag Storage + 0x180 + 32 + read-write + 0 + 0xFFFFFFFF + + + valid + 1-bit valid for cache entry + 0 + 1 + read-write + + + tag + 13-bit tag for cache entry + 6 + 13 + read-write + + + + + TAGVDW0S1 + Cache Tag Storage + 0x184 + 32 + read-write + 0 + 0xFFFFFFFF + + + valid + 1-bit valid for cache entry + 0 + 1 + read-write + + + tag + 13-bit tag for cache entry + 6 + 13 + read-write + + + + + TAGVDW0S2 + Cache Tag Storage + 0x188 + 32 + read-write + 0 + 0xFFFFFFFF + + + valid + 1-bit valid for cache entry + 0 + 1 + read-write + + + tag + 13-bit tag for cache entry + 6 + 13 + read-write + + + + + TAGVDW0S3 + Cache Tag Storage + 0x18C + 32 + read-write + 0 + 0xFFFFFFFF + + + valid + 1-bit valid for cache entry + 0 + 1 + read-write + + + tag + 13-bit tag for cache entry + 6 + 13 + read-write + + + + + TAGVDW1S0 + Cache Tag Storage + 0x190 + 32 + read-write + 0 + 0xFFFFFFFF + + + valid + 1-bit valid for cache entry + 0 + 1 + read-write + + + tag + 13-bit tag for cache entry + 6 + 13 + read-write + + + + + TAGVDW1S1 + Cache Tag Storage + 0x194 + 32 + read-write + 0 + 0xFFFFFFFF + + + valid + 1-bit valid for cache entry + 0 + 1 + read-write + + + tag + 13-bit tag for cache entry + 6 + 13 + read-write + + + + + TAGVDW1S2 + Cache Tag Storage + 0x198 + 32 + read-write + 0 + 0xFFFFFFFF + + + valid + 1-bit valid for cache entry + 0 + 1 + read-write + + + tag + 13-bit tag for cache entry + 6 + 13 + read-write + + + + + TAGVDW1S3 + Cache Tag Storage + 0x19C + 32 + read-write + 0 + 0xFFFFFFFF + + + valid + 1-bit valid for cache entry + 0 + 1 + read-write + + + tag + 13-bit tag for cache entry + 6 + 13 + read-write + + + + + TAGVDW2S0 + Cache Tag Storage + 0x1A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + valid + 1-bit valid for cache entry + 0 + 1 + read-write + + + tag + 13-bit tag for cache entry + 6 + 13 + read-write + + + + + TAGVDW2S1 + Cache Tag Storage + 0x1A4 + 32 + read-write + 0 + 0xFFFFFFFF + + + valid + 1-bit valid for cache entry + 0 + 1 + read-write + + + tag + 13-bit tag for cache entry + 6 + 13 + read-write + + + + + TAGVDW2S2 + Cache Tag Storage + 0x1A8 + 32 + read-write + 0 + 0xFFFFFFFF + + + valid + 1-bit valid for cache entry + 0 + 1 + read-write + + + tag + 13-bit tag for cache entry + 6 + 13 + read-write + + + + + TAGVDW2S3 + Cache Tag Storage + 0x1AC + 32 + read-write + 0 + 0xFFFFFFFF + + + valid + 1-bit valid for cache entry + 0 + 1 + read-write + + + tag + 13-bit tag for cache entry + 6 + 13 + read-write + + + + + TAGVDW3S0 + Cache Tag Storage + 0x1B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + valid + 1-bit valid for cache entry + 0 + 1 + read-write + + + tag + 13-bit tag for cache entry + 6 + 13 + read-write + + + + + TAGVDW3S1 + Cache Tag Storage + 0x1B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + valid + 1-bit valid for cache entry + 0 + 1 + read-write + + + tag + 13-bit tag for cache entry + 6 + 13 + read-write + + + + + TAGVDW3S2 + Cache Tag Storage + 0x1B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + valid + 1-bit valid for cache entry + 0 + 1 + read-write + + + tag + 13-bit tag for cache entry + 6 + 13 + read-write + + + + + TAGVDW3S3 + Cache Tag Storage + 0x1BC + 32 + read-write + 0 + 0xFFFFFFFF + + + valid + 1-bit valid for cache entry + 0 + 1 + read-write + + + tag + 13-bit tag for cache entry + 6 + 13 + read-write + + + + + DATAW0S0U + Cache Data Storage (upper word) + 0x300 + 32 + read-write + 0 + 0xFFFFFFFF + + + data + Bits [63:32] of data entry + 0 + 32 + read-write + + + + + DATAW0S0L + Cache Data Storage (lower word) + 0x304 + 32 + read-write + 0 + 0xFFFFFFFF + + + data + Bits [31:0] of data entry + 0 + 32 + read-write + + + + + DATAW0S1U + Cache Data Storage (upper word) + 0x308 + 32 + read-write + 0 + 0xFFFFFFFF + + + data + Bits [63:32] of data entry + 0 + 32 + read-write + + + + + DATAW0S1L + Cache Data Storage (lower word) + 0x30C + 32 + read-write + 0 + 0xFFFFFFFF + + + data + Bits [31:0] of data entry + 0 + 32 + read-write + + + + + DATAW0S2U + Cache Data Storage (upper word) + 0x310 + 32 + read-write + 0 + 0xFFFFFFFF + + + data + Bits [63:32] of data entry + 0 + 32 + read-write + + + + + DATAW0S2L + Cache Data Storage (lower word) + 0x314 + 32 + read-write + 0 + 0xFFFFFFFF + + + data + Bits [31:0] of data entry + 0 + 32 + read-write + + + + + DATAW0S3U + Cache Data Storage (upper word) + 0x318 + 32 + read-write + 0 + 0xFFFFFFFF + + + data + Bits [63:32] of data entry + 0 + 32 + read-write + + + + + DATAW0S3L + Cache Data Storage (lower word) + 0x31C + 32 + read-write + 0 + 0xFFFFFFFF + + + data + Bits [31:0] of data entry + 0 + 32 + read-write + + + + + DATAW1S0U + Cache Data Storage (upper word) + 0x320 + 32 + read-write + 0 + 0xFFFFFFFF + + + data + Bits [63:32] of data entry + 0 + 32 + read-write + + + + + DATAW1S0L + Cache Data Storage (lower word) + 0x324 + 32 + read-write + 0 + 0xFFFFFFFF + + + data + Bits [31:0] of data entry + 0 + 32 + read-write + + + + + DATAW1S1U + Cache Data Storage (upper word) + 0x328 + 32 + read-write + 0 + 0xFFFFFFFF + + + data + Bits [63:32] of data entry + 0 + 32 + read-write + + + + + DATAW1S1L + Cache Data Storage (lower word) + 0x32C + 32 + read-write + 0 + 0xFFFFFFFF + + + data + Bits [31:0] of data entry + 0 + 32 + read-write + + + + + DATAW1S2U + Cache Data Storage (upper word) + 0x330 + 32 + read-write + 0 + 0xFFFFFFFF + + + data + Bits [63:32] of data entry + 0 + 32 + read-write + + + + + DATAW1S2L + Cache Data Storage (lower word) + 0x334 + 32 + read-write + 0 + 0xFFFFFFFF + + + data + Bits [31:0] of data entry + 0 + 32 + read-write + + + + + DATAW1S3U + Cache Data Storage (upper word) + 0x338 + 32 + read-write + 0 + 0xFFFFFFFF + + + data + Bits [63:32] of data entry + 0 + 32 + read-write + + + + + DATAW1S3L + Cache Data Storage (lower word) + 0x33C + 32 + read-write + 0 + 0xFFFFFFFF + + + data + Bits [31:0] of data entry + 0 + 32 + read-write + + + + + DATAW2S0U + Cache Data Storage (upper word) + 0x340 + 32 + read-write + 0 + 0xFFFFFFFF + + + data + Bits [63:32] of data entry + 0 + 32 + read-write + + + + + DATAW2S0L + Cache Data Storage (lower word) + 0x344 + 32 + read-write + 0 + 0xFFFFFFFF + + + data + Bits [31:0] of data entry + 0 + 32 + read-write + + + + + DATAW2S1U + Cache Data Storage (upper word) + 0x348 + 32 + read-write + 0 + 0xFFFFFFFF + + + data + Bits [63:32] of data entry + 0 + 32 + read-write + + + + + DATAW2S1L + Cache Data Storage (lower word) + 0x34C + 32 + read-write + 0 + 0xFFFFFFFF + + + data + Bits [31:0] of data entry + 0 + 32 + read-write + + + + + DATAW2S2U + Cache Data Storage (upper word) + 0x350 + 32 + read-write + 0 + 0xFFFFFFFF + + + data + Bits [63:32] of data entry + 0 + 32 + read-write + + + + + DATAW2S2L + Cache Data Storage (lower word) + 0x354 + 32 + read-write + 0 + 0xFFFFFFFF + + + data + Bits [31:0] of data entry + 0 + 32 + read-write + + + + + DATAW2S3U + Cache Data Storage (upper word) + 0x358 + 32 + read-write + 0 + 0xFFFFFFFF + + + data + Bits [63:32] of data entry + 0 + 32 + read-write + + + + + DATAW2S3L + Cache Data Storage (lower word) + 0x35C + 32 + read-write + 0 + 0xFFFFFFFF + + + data + Bits [31:0] of data entry + 0 + 32 + read-write + + + + + DATAW3S0U + Cache Data Storage (upper word) + 0x360 + 32 + read-write + 0 + 0xFFFFFFFF + + + data + Bits [63:32] of data entry + 0 + 32 + read-write + + + + + DATAW3S0L + Cache Data Storage (lower word) + 0x364 + 32 + read-write + 0 + 0xFFFFFFFF + + + data + Bits [31:0] of data entry + 0 + 32 + read-write + + + + + DATAW3S1U + Cache Data Storage (upper word) + 0x368 + 32 + read-write + 0 + 0xFFFFFFFF + + + data + Bits [63:32] of data entry + 0 + 32 + read-write + + + + + DATAW3S1L + Cache Data Storage (lower word) + 0x36C + 32 + read-write + 0 + 0xFFFFFFFF + + + data + Bits [31:0] of data entry + 0 + 32 + read-write + + + + + DATAW3S2U + Cache Data Storage (upper word) + 0x370 + 32 + read-write + 0 + 0xFFFFFFFF + + + data + Bits [63:32] of data entry + 0 + 32 + read-write + + + + + DATAW3S2L + Cache Data Storage (lower word) + 0x374 + 32 + read-write + 0 + 0xFFFFFFFF + + + data + Bits [31:0] of data entry + 0 + 32 + read-write + + + + + DATAW3S3U + Cache Data Storage (upper word) + 0x378 + 32 + read-write + 0 + 0xFFFFFFFF + + + data + Bits [63:32] of data entry + 0 + 32 + read-write + + + + + DATAW3S3L + Cache Data Storage (lower word) + 0x37C + 32 + read-write + 0 + 0xFFFFFFFF + + + data + Bits [31:0] of data entry + 0 + 32 + read-write + + + + + + + FTFE + Flash Memory Interface + FTFE_ + 0x40020000 + + 0 + 0x30 + registers + + + FTFE + 5 + + + + FSTAT + Flash Status Register + 0 + 8 + read-write + 0 + 0xFF + + + MGSTAT0 + Memory Controller Command Completion Status Flag + 0 + 1 + read-only + + + FPVIOL + Flash Protection Violation Flag + 4 + 1 + read-write + + + 0 + No protection violation detected + #0 + + + 1 + Protection violation detected + #1 + + + + + ACCERR + Flash Access Error Flag + 5 + 1 + read-write + + + 0 + No access error detected + #0 + + + 1 + Access error detected + #1 + + + + + RDCOLERR + FTFE Read Collision Error Flag + 6 + 1 + read-write + + + 0 + No collision error detected + #0 + + + 1 + Collision error detected + #1 + + + + + CCIF + Command Complete Interrupt Flag + 7 + 1 + read-write + + + 0 + FTFE command or EEPROM file system operation in progress + #0 + + + 1 + FTFE command or EEPROM file system operation has completed + #1 + + + + + + + FCNFG + Flash Configuration Register + 0x1 + 8 + read-write + 0 + 0xFF + + + EEERDY + For devices with FlexNVM: This flag indicates if the EEPROM backup data has been copied to the FlexRAM and is therefore available for read access + 0 + 1 + read-only + + + 0 + For devices with FlexNVM: FlexRAM is not available for EEPROM operation For devices without FlexNVM: See RAMRDY for availability of programming acceleration RAM + #0 + + + 1 + For devices with FlexNVM: FlexRAM is available for EEPROM operations where: reads from the FlexRAM return data previously written to the FlexRAM in EEPROM mode and writes launch an EEPROM operation to store the written data in the FlexRAM and EEPROM backup For devices without FlexNVM: Reserved + #1 + + + + + RAMRDY + RAM Ready + 1 + 1 + read-only + + + 0 + For devices with FlexNVM: FlexRAM is not available for traditional RAM access For devices without FlexNVM: Programming acceleration RAM is not available + #0 + + + 1 + For devices with FlexNVM: FlexRAM is available as traditional RAM only; writes to the FlexRAM do not trigger EEPROM operations For devices without FlexNVM: Programming acceleration RAM is available + #1 + + + + + PFLSH + FTFE configuration + 2 + 1 + read-only + + + 0 + For devices with FlexNVM: FTFE configuration supports one program flash block and one FlexNVM block For devices with program flash only: Reserved + #0 + + + 1 + For devices with FlexNVM: Reserved For devices with program flash only: FTFE configuration supports two program flash blocks + #1 + + + + + SWAP + Swap + 3 + 1 + read-only + + + 0 + For devices with FlexNVM: Program flash 0 block is located at relative address 0x0000 For devices with program flash only: Program flash 0 block is located at relative address 0x0000 + #0 + + + 1 + For devices with program flash only: Program flash 1 block is located at relative address 0x0000 + #1 + + + + + ERSSUSP + Erase Suspend + 4 + 1 + read-write + + + 0 + No suspend requested + #0 + + + 1 + Suspend the current Erase Flash Sector command execution + #1 + + + + + ERSAREQ + Erase All Request + 5 + 1 + read-only + + + 0 + No request or request complete + #0 + + + 1 + Request to: run the Erase All Blocks command, verify the erased state, program the security byte in the Flash Configuration Field to the unsecure state, and release MCU security by setting the FSEC[SEC] field to the unsecure state + #1 + + + + + RDCOLLIE + Read Collision Error Interrupt Enable + 6 + 1 + read-write + + + 0 + Read collision error interrupt disabled + #0 + + + 1 + Read collision error interrupt enabled. An interrupt request is generated whenever an FTFE read collision error is detected (see the description of FSTAT[RDCOLERR]). + #1 + + + + + CCIE + Command Complete Interrupt Enable + 7 + 1 + read-write + + + 0 + Command complete interrupt disabled + #0 + + + 1 + Command complete interrupt enabled. An interrupt request is generated whenever the FSTAT[CCIF] flag is set. + #1 + + + + + + + FSEC + Flash Security Register + 0x2 + 8 + read-only + 0 + 0 + + + SEC + Flash Security + 0 + 2 + read-only + + + 00 + MCU security status is secure + #00 + + + 01 + MCU security status is secure + #01 + + + 10 + MCU security status is unsecure (The standard shipping condition of the FTFE is unsecure.) + #10 + + + 11 + MCU security status is secure + #11 + + + + + FSLACC + Factory Security Level Access Code + 2 + 2 + read-only + + + 00 + Factory access granted + #00 + + + 01 + Factory access denied + #01 + + + 10 + Factory access denied + #10 + + + 11 + Factory access granted + #11 + + + + + MEEN + Mass Erase Enable Bits + 4 + 2 + read-only + + + 00 + Mass erase is enabled + #00 + + + 01 + Mass erase is enabled + #01 + + + 10 + Mass erase is disabled + #10 + + + 11 + Mass erase is enabled + #11 + + + + + KEYEN + Backdoor Key Security Enable + 6 + 2 + read-only + + + 00 + Backdoor key access disabled + #00 + + + 01 + Backdoor key access disabled (preferred KEYEN state to disable backdoor key access) + #01 + + + 10 + Backdoor key access enabled + #10 + + + 11 + Backdoor key access disabled + #11 + + + + + + + FOPT + Flash Option Register + 0x3 + 8 + read-only + 0 + 0 + + + OPT + Nonvolatile Option + 0 + 8 + read-only + + + + + 12 + 0x1 + 3,2,1,0,7,6,5,4,B,A,9,8 + FCCOB%s + Flash Common Command Object Registers + 0x4 + 8 + read-write + 0 + 0xFF + + + CCOBn + The FCCOB register provides a command code and relevant parameters to the memory controller + 0 + 8 + read-write + + + + + 4 + 0x1 + 3,2,1,0 + FPROT%s + Program Flash Protection Registers + 0x10 + 8 + read-write + 0 + 0 + + + PROT + Program Flash Region Protect + 0 + 8 + read-write + + + 0 + Program flash region is protected. + #0 + + + 1 + Program flash region is not protected + #1 + + + + + + + FEPROT + EEPROM Protection Register + 0x16 + 8 + read-write + 0 + 0 + + + EPROT + EEPROM Region Protect + 0 + 8 + read-write + + + 0 + For devices with program flash only: Reserved For devices with FlexNVM: EEPROM region is protected + #0 + + + 1 + For devices with program flash only: Reserved For devices with FlexNVM: EEPROM region is not protected + #1 + + + + + + + FDPROT + Data Flash Protection Register + 0x17 + 8 + read-write + 0 + 0 + + + DPROT + Data Flash Region Protect + 0 + 8 + read-write + + + 0 + Data Flash region is protected + #0 + + + 1 + Data Flash region is not protected + #1 + + + + + + + FERSTAT + Flash Error Status Register + 0x2E + 8 + read-write + 0 + 0xFF + + + DFDIF + Double Bit Fault Detect Interrupt Flag + 1 + 1 + read-write + + + 0 + Double bit fault not detected during a valid flash read access from the platform flash controller + #0 + + + 1 + Double bit fault detected (or FERCNFG[FDFD] is set) during a valid flash read access from the platform flash controller + #1 + + + + + + + FERCNFG + Flash Error Configuration Register + 0x2F + 8 + read-write + 0 + 0xFF + + + DFDIE + Double Bit Fault Detect Interrupt Enable + 1 + 1 + read-write + + + 0 + Double bit fault detect interrupt disabled + #0 + + + 1 + Double bit fault detect interrupt enabled. An interrupt request is generated whenever the FERSTAT[DFDIF] flag is set. + #1 + + + + + FDFD + Force Double Bit Fault Detect + 5 + 1 + read-write + + + 0 + FERSTAT[DFDIF] sets only if a double bit fault is detected during read access from the platform flash controller + #0 + + + 1 + FERSTAT[DFDIF] sets during any valid flash read access from the platform flash controller. An interrupt request is generated if the DFDIE bit is set. + #1 + + + + + + + + + DMAMUX0 + DMAMUX + 0x40021000 + + 0 + 0x4 + registers + + + + CHCFG0 + Channel Configuration register + 0 + 8 + read-write + 0 + 0xFF + + + SOURCE + DMA Channel Source (Slot) + 0 + 6 + read-write + + + TRIG + DMA Channel Trigger Enable + 6 + 1 + read-write + + + 0 + Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) + #0 + + + 1 + Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode. + #1 + + + + + ENBL + DMA Channel Enable + 7 + 1 + read-write + + + 0 + DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel. + #0 + + + 1 + DMA channel is enabled + #1 + + + + + + + CHCFG1 + Channel Configuration register + 0x1 + 8 + read-write + 0 + 0xFF + + + SOURCE + DMA Channel Source (Slot) + 0 + 6 + read-write + + + TRIG + DMA Channel Trigger Enable + 6 + 1 + read-write + + + 0 + Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) + #0 + + + 1 + Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode. + #1 + + + + + ENBL + DMA Channel Enable + 7 + 1 + read-write + + + 0 + DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel. + #0 + + + 1 + DMA channel is enabled + #1 + + + + + + + CHCFG2 + Channel Configuration register + 0x2 + 8 + read-write + 0 + 0xFF + + + SOURCE + DMA Channel Source (Slot) + 0 + 6 + read-write + + + TRIG + DMA Channel Trigger Enable + 6 + 1 + read-write + + + 0 + Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) + #0 + + + 1 + Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode. + #1 + + + + + ENBL + DMA Channel Enable + 7 + 1 + read-write + + + 0 + DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel. + #0 + + + 1 + DMA channel is enabled + #1 + + + + + + + CHCFG3 + Channel Configuration register + 0x3 + 8 + read-write + 0 + 0xFF + + + SOURCE + DMA Channel Source (Slot) + 0 + 6 + read-write + + + TRIG + DMA Channel Trigger Enable + 6 + 1 + read-write + + + 0 + Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) + #0 + + + 1 + Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode. + #1 + + + + + ENBL + DMA Channel Enable + 7 + 1 + read-write + + + 0 + DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel. + #0 + + + 1 + DMA channel is enabled + #1 + + + + + + + + + CAN0 + CAN + 0x40024000 + + 0 + 0xC0C + registers + + + + MCR + Module Configuration register + 0 + 32 + read-write + 0xD890000F + 0xFFFFFFFF + + + MAXMB + Number Of The Last Message Buffer + 0 + 7 + read-write + + + IDAM + ID Acceptance Mode + 8 + 2 + read-write + + + 00 + Format A: One full ID (standard and extended) per ID filter table element. + #00 + + + 01 + Format B: Two full standard IDs or two partial 14-bit (standard and extended) IDs per ID filter table element. + #01 + + + 10 + Format C: Four partial 8-bit standard IDs per ID filter table element. + #10 + + + 11 + Format D: All frames rejected. + #11 + + + + + FDEN + CAN FD operation enable + 11 + 1 + read-write + + + 1 + CAN FD is enabled. FlexCAN is able to receive and transmit messages in both CAN FD and CAN 2.0 formats. + #1 + + + 0 + CAN FD is disabled. FlexCAN is able to receive and transmit messages in CAN 2.0 format. + #0 + + + + + AEN + Abort Enable + 12 + 1 + read-write + + + 0 + Abort disabled. + #0 + + + 1 + Abort enabled. + #1 + + + + + LPRIOEN + Local Priority Enable + 13 + 1 + read-write + + + 0 + Local Priority disabled. + #0 + + + 1 + Local Priority enabled. + #1 + + + + + DMA + DMA Enable + 15 + 1 + read-write + + + 0 + DMA feature for RX FIFO disabled. + #0 + + + 1 + DMA feature for RX FIFO enabled. + #1 + + + + + IRMQ + Individual Rx Masking And Queue Enable + 16 + 1 + read-write + + + 0 + Individual Rx masking and queue feature are disabled. For backward compatibility with legacy applications, the reading of C/S word locks the MB even if it is EMPTY. + #0 + + + 1 + Individual Rx masking and queue feature are enabled. + #1 + + + + + SRXDIS + Self Reception Disable + 17 + 1 + read-write + + + 0 + Self-reception enabled. + #0 + + + 1 + Self-reception disabled. + #1 + + + + + DOZE + Doze Mode Enable + 18 + 1 + read-write + + + 0 + FlexCAN is not enabled to enter low-power mode when Doze mode is requested. + #0 + + + 1 + FlexCAN is enabled to enter low-power mode when Doze mode is requested. + #1 + + + + + WAKSRC + Wake Up Source + 19 + 1 + read-write + + + 0 + FlexCAN uses the unfiltered Rx input to detect recessive to dominant edges on the CAN bus. + #0 + + + 1 + FlexCAN uses the filtered Rx input to detect recessive to dominant edges on the CAN bus. + #1 + + + + + LPMACK + Low-Power Mode Acknowledge + 20 + 1 + read-only + + + 0 + FlexCAN is not in a low-power mode. + #0 + + + 1 + FlexCAN is in a low-power mode. + #1 + + + + + WRNEN + Warning Interrupt Enable + 21 + 1 + read-write + + + 0 + TWRNINT and RWRNINT bits are zero, independent of the values in the error counters. + #0 + + + 1 + TWRNINT and RWRNINT bits are set when the respective error counter transitions from less than 96 to greater than or equal to 96. + #1 + + + + + SLFWAK + Self Wake Up + 22 + 1 + read-write + + + 0 + FlexCAN Self Wake Up feature is disabled. + #0 + + + 1 + FlexCAN Self Wake Up feature is enabled. + #1 + + + + + SUPV + Supervisor Mode + 23 + 1 + read-write + + + 0 + FlexCAN is in User mode. Affected registers allow both Supervisor and Unrestricted accesses. + #0 + + + 1 + FlexCAN is in Supervisor mode. Affected registers allow only Supervisor access. Unrestricted access behaves as though the access was done to an unimplemented register location. + #1 + + + + + FRZACK + Freeze Mode Acknowledge + 24 + 1 + read-only + + + 0 + FlexCAN not in Freeze mode, prescaler running. + #0 + + + 1 + FlexCAN in Freeze mode, prescaler stopped. + #1 + + + + + SOFTRST + Soft Reset + 25 + 1 + read-write + + + 0 + No reset request. + #0 + + + 1 + Resets the registers affected by soft reset. + #1 + + + + + WAKMSK + Wake Up Interrupt Mask + 26 + 1 + read-write + + + 0 + Wake Up interrupt is disabled. + #0 + + + 1 + Wake Up interrupt is enabled. + #1 + + + + + NOTRDY + FlexCAN Not Ready + 27 + 1 + read-only + + + 0 + FlexCAN module is either in Normal mode, Listen-Only mode, or Loop-Back mode. + #0 + + + 1 + FlexCAN module is either in Disable mode, Doze mode, Stop mode, or Freeze mode. + #1 + + + + + HALT + Halt FlexCAN + 28 + 1 + read-write + + + 0 + No Freeze mode request. + #0 + + + 1 + Enters Freeze mode if the FRZ bit is asserted. + #1 + + + + + RFEN + Rx FIFO Enable + 29 + 1 + read-write + + + 0 + Rx FIFO not enabled. + #0 + + + 1 + Rx FIFO enabled. + #1 + + + + + FRZ + Freeze Enable + 30 + 1 + read-write + + + 0 + Not enabled to enter Freeze mode. + #0 + + + 1 + Enabled to enter Freeze mode. + #1 + + + + + MDIS + Module Disable + 31 + 1 + read-write + + + 0 + Enable the FlexCAN module. + #0 + + + 1 + Disable the FlexCAN module. + #1 + + + + + + + CTRL1 + Control 1 register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + PROPSEG + Propagation Segment + 0 + 3 + read-write + + + LOM + Listen-Only Mode + 3 + 1 + read-write + + + 0 + Listen-Only mode is deactivated. + #0 + + + 1 + FlexCAN module operates in Listen-Only mode. + #1 + + + + + LBUF + Lowest Buffer Transmitted First + 4 + 1 + read-write + + + 0 + Buffer with highest priority is transmitted first. + #0 + + + 1 + Lowest number buffer is transmitted first. + #1 + + + + + TSYN + Timer Sync + 5 + 1 + read-write + + + 0 + Timer sync feature disabled + #0 + + + 1 + Timer sync feature enabled + #1 + + + + + BOFFREC + Bus Off Recovery + 6 + 1 + read-write + + + 0 + Automatic recovering from Bus Off state enabled. + #0 + + + 1 + Automatic recovering from Bus Off state disabled. + #1 + + + + + SMP + CAN Bit Sampling + 7 + 1 + read-write + + + 0 + Just one sample is used to determine the bit value. + #0 + + + 1 + Three samples are used to determine the value of the received bit: the regular one (sample point) and two preceding samples; a majority rule is used. + #1 + + + + + RWRNMSK + Rx Warning Interrupt Mask + 10 + 1 + read-write + + + 0 + Rx Warning interrupt disabled. + #0 + + + 1 + Rx Warning interrupt enabled. + #1 + + + + + TWRNMSK + Tx Warning Interrupt Mask + 11 + 1 + read-write + + + 0 + Tx Warning interrupt disabled. + #0 + + + 1 + Tx Warning interrupt enabled. + #1 + + + + + LPB + Loop Back Mode + 12 + 1 + read-write + + + 0 + Loop Back disabled. + #0 + + + 1 + Loop Back enabled. + #1 + + + + + CLKSRC + CAN Engine Clock Source + 13 + 1 + read-write + + + 0 + The CAN engine clock source is the oscillator clock. Under this condition, the oscillator clock frequency must be lower than the bus clock. + #0 + + + 1 + The CAN engine clock source is the peripheral clock. + #1 + + + + + ERRMSK + Error Interrupt Mask + 14 + 1 + read-write + + + 0 + Error interrupt disabled. + #0 + + + 1 + Error interrupt enabled. + #1 + + + + + BOFFMSK + Bus Off Interrupt Mask + 15 + 1 + read-write + + + 0 + Bus Off interrupt disabled. + #0 + + + 1 + Bus Off interrupt enabled. + #1 + + + + + PSEG2 + Phase Segment 2 + 16 + 3 + read-write + + + PSEG1 + Phase Segment 1 + 19 + 3 + read-write + + + RJW + Resync Jump Width + 22 + 2 + read-write + + + PRESDIV + Prescaler Division Factor + 24 + 8 + read-write + + + + + TIMER + Free Running Timer + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIMER + Timer Value + 0 + 16 + read-write + + + + + RXMGMASK + Rx Mailboxes Global Mask register + 0x10 + 32 + read-write + 0 + 0 + + + MG + Rx Mailboxes Global Mask Bits + 0 + 32 + read-write + + + + + RX14MASK + Rx 14 Mask register + 0x14 + 32 + read-write + 0 + 0 + + + RX14M + Rx Buffer 14 Mask Bits + 0 + 32 + read-write + + + + + RX15MASK + Rx 15 Mask register + 0x18 + 32 + read-write + 0 + 0 + + + RX15M + Rx Buffer 15 Mask Bits + 0 + 32 + read-write + + + + + ECR + Error Counter + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + TXERRCNT + Transmit Error Counter + 0 + 8 + read-write + + + RXERRCNT + Receive Error Counter + 8 + 8 + read-write + + + TXERRCNT_FAST + Transmit Error Counter for fast bits + 16 + 8 + read-write + + + RXERRCNT_FAST + Receive Error Counter for fast bits + 24 + 8 + read-write + + + + + ESR1 + Error and Status 1 register + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + WAKINT + Wake-Up Interrupt + 0 + 1 + read-write + + + 0 + No such occurrence. + #0 + + + 1 + Indicates a recessive to dominant transition was received on the CAN bus. + #1 + + + + + ERRINT + Error Interrupt + 1 + 1 + read-write + + + 0 + No such occurrence. + #0 + + + 1 + Indicates setting of any error bit in the Error and Status register. + #1 + + + + + BOFFINT + Bus Off Interrupt + 2 + 1 + read-write + + + 0 + No such occurrence. + #0 + + + 1 + FlexCAN module entered Bus Off state. + #1 + + + + + RX + FlexCAN In Reception + 3 + 1 + read-only + + + 0 + FlexCAN is not receiving a message. + #0 + + + 1 + FlexCAN is receiving a message. + #1 + + + + + FLTCONF + Fault Confinement State + 4 + 2 + read-only + + + 0 + Error Active + #00 + + + 1 + Error Passive + #01 + + + + + TX + FlexCAN In Transmission + 6 + 1 + read-only + + + 0 + FlexCAN is not transmitting a message. + #0 + + + 1 + FlexCAN is transmitting a message. + #1 + + + + + IDLE + IDLE + 7 + 1 + read-only + + + 0 + No such occurrence. + #0 + + + 1 + CAN bus is now IDLE. + #1 + + + + + RXWRN + Rx Error Warning + 8 + 1 + read-only + + + 0 + No such occurrence. + #0 + + + 1 + RXERRCNT is greater than or equal to 96. + #1 + + + + + TXWRN + TX Error Warning + 9 + 1 + read-only + + + 0 + No such occurrence. + #0 + + + 1 + TXERRCNT is greater than or equal to 96. + #1 + + + + + STFERR + Stuffing Error + 10 + 1 + read-only + + + 0 + No such occurrence. + #0 + + + 1 + A stuffing error occurred since last read of this register. + #1 + + + + + FRMERR + Form Error + 11 + 1 + read-only + + + 0 + No such occurrence. + #0 + + + 1 + A Form Error occurred since last read of this register. + #1 + + + + + CRCERR + Cyclic Redundancy Check Error + 12 + 1 + read-only + + + 0 + No such occurrence. + #0 + + + 1 + A CRC error occurred since last read of this register. + #1 + + + + + ACKERR + Acknowledge Error + 13 + 1 + read-only + + + 0 + No such occurrence. + #0 + + + 1 + An ACK error occurred since last read of this register. + #1 + + + + + BIT0ERR + Bit0 Error + 14 + 1 + read-only + + + 0 + No such occurrence. + #0 + + + 1 + At least one bit sent as dominant is received as recessive. + #1 + + + + + BIT1ERR + Bit1 Error + 15 + 1 + read-only + + + 0 + No such occurrence. + #0 + + + 1 + At least one bit sent as recessive is received as dominant. + #1 + + + + + RWRNINT + Rx Warning Interrupt Flag + 16 + 1 + read-write + + + 0 + No such occurrence. + #0 + + + 1 + The Rx error counter transitioned from less than 96 to greater than or equal to 96. + #1 + + + + + TWRNINT + Tx Warning Interrupt Flag + 17 + 1 + read-write + + + 0 + No such occurrence. + #0 + + + 1 + The Tx error counter transitioned from less than 96 to greater than or equal to 96. + #1 + + + + + SYNCH + CAN Synchronization Status + 18 + 1 + read-only + + + 0 + FlexCAN is not synchronized to the CAN bus. + #0 + + + 1 + FlexCAN is synchronized to the CAN bus. + #1 + + + + + BOFFDONEINT + Bus Off Done Interrupt + 19 + 1 + read-write + + + 0 + No such occurrence. + #0 + + + 1 + FlexCAN module has completed Bus Off process. + #1 + + + + + ERRINT_FAST + Error interrupt for errors detected in Data Phase of CAN FD frames with BRS bit set + 20 + 1 + read-write + + + 0 + No such occurrence. + #0 + + + 1 + Indicates setting of any error bit detected in the data phase of CAN FD frames with the BRS bit set. + #1 + + + + + ERROVR + Error Overrun + 21 + 1 + read-write + + + 0 + Overrun has not occurred. + #0 + + + 1 + Overrun has occurred. + #1 + + + + + STFERR_FAST + Stuffing Error in the Data Phase of CAN FD frames with the BRS bit set + 26 + 1 + read-only + + + 0 + No such occurrence. + #0 + + + 1 + A stuffing error occurred since last read of this register. + #1 + + + + + FRMERR_FAST + Form Error in the Data Phase of CAN FD frames with the BRS bit set + 27 + 1 + read-only + + + 0 + No such occurrence. + #0 + + + 1 + A form error occurred since last read of this register. + #1 + + + + + CRCERR_FAST + Cyclic Redundancy Check Error in the CRC field of CAN FD frames with the BRS bit set + 28 + 1 + read-only + + + 0 + No such occurrence. + #0 + + + 1 + A CRC error occurred since last read of this register. + #1 + + + + + BIT0ERR_FAST + Bit0 Error in the Data Phase of CAN FD frames with the BRS bit set + 30 + 1 + read-only + + + 0 + No such occurrence. + #0 + + + 1 + At least one bit sent as dominant is received as recessive. + #1 + + + + + BIT1ERR_FAST + Bit1 Error in the Data Phase of CAN FD frames with the BRS bit set + 31 + 1 + read-only + + + 0 + No such occurrence. + #0 + + + 1 + At least one bit sent as recessive is received as dominant. + #1 + + + + + + + IMASK1 + Interrupt Masks 1 register + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + BUF31TO0M + Buffer MB i Mask + 0 + 32 + read-write + + + + + IFLAG1 + Interrupt Flags 1 register + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + BUF0I + Buffer MB0 Interrupt Or Clear FIFO bit + 0 + 1 + read-write + + + 0 + The corresponding buffer has no occurrence of successfully completed transmission or reception when MCR[RFEN]=0. + #0 + + + 1 + The corresponding buffer has successfully completed transmission or reception when MCR[RFEN]=0. + #1 + + + + + BUF4TO1I + Buffer MB i Interrupt Or Reserved + 1 + 4 + read-write + + + BUF5I + Buffer MB5 Interrupt Or Frames available in Rx FIFO + 5 + 1 + read-write + + + 0 + No occurrence of MB5 completing transmission/reception when MCR[RFEN]=0, or of frame(s) available in the FIFO, when MCR[RFEN]=1 + #0 + + + 1 + MB5 completed transmission/reception when MCR[RFEN]=0, or frame(s) available in the Rx FIFO when MCR[RFEN]=1. It generates a DMA request in case of MCR[RFEN] and MCR[DMA] are enabled. + #1 + + + + + BUF6I + Buffer MB6 Interrupt Or Rx FIFO Warning + 6 + 1 + read-write + + + 0 + No occurrence of MB6 completing transmission/reception when MCR[RFEN]=0, or of Rx FIFO almost full when MCR[RFEN]=1 + #0 + + + 1 + MB6 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO almost full when MCR[RFEN]=1 + #1 + + + + + BUF7I + Buffer MB7 Interrupt Or Rx FIFO Overflow + 7 + 1 + read-write + + + 0 + No occurrence of MB7 completing transmission/reception when MCR[RFEN]=0, or of Rx FIFO overflow when MCR[RFEN]=1 + #0 + + + 1 + MB7 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO overflow when MCR[RFEN]=1 + #1 + + + + + BUF31TO8I + Buffer MBi Interrupt + 8 + 24 + read-write + + + + + CTRL2 + Control 2 register + 0x34 + 32 + read-write + 0xA00000 + 0xFFFFFFFF + + + EDFLTDIS + Edge Filter Disable + 11 + 1 + read-write + + + 0 + Edge filter is enabled + #0 + + + 1 + Edge filter is disabled + #1 + + + + + ISOCANFDEN + ISO CAN FD Enable + 12 + 1 + read-write + + + 0 + FlexCAN operates using the non-ISO CAN FD protocol. + #0 + + + 1 + FlexCAN operates using the ISO CAN FD protocol (ISO 11898-1). + #1 + + + + + PREXCEN + Protocol Exception Enable + 14 + 1 + read-write + + + 0 + Protocol exception is disabled. + #0 + + + 1 + Protocol exception is enabled. + #1 + + + + + TIMER_SRC + Timer Source + 15 + 1 + read-write + + + 0 + The free running timer is clocked by the CAN bit clock, which defines the baud rate on the CAN bus. + #0 + + + 1 + The free running timer is clocked by an external time tick. The period can be either adjusted to be equal to the baud rate on the CAN bus, or a different value as required. See the device-specific section for details about the external time tick. + #1 + + + + + EACEN + Entire Frame Arbitration Field Comparison Enable For Rx Mailboxes + 16 + 1 + read-write + + + 0 + Rx mailbox filter's IDE bit is always compared and RTR is never compared despite mask bits. + #0 + + + 1 + Enables the comparison of both Rx mailbox filter's IDE and RTR bit with their corresponding bits within the incoming frame. Mask bits do apply. + #1 + + + + + RRS + Remote Request Storing + 17 + 1 + read-write + + + 0 + Remote response frame is generated. + #0 + + + 1 + Remote request frame is stored. + #1 + + + + + MRP + Mailboxes Reception Priority + 18 + 1 + read-write + + + 0 + Matching starts from Rx FIFO or Enhanced Rx FIFO and continues on mailboxes. + #0 + + + 1 + Matching starts from mailboxes and continues on Rx FIFO. + #1 + + + + + TASD + Tx Arbitration Start Delay + 19 + 5 + read-write + + + RFFN + Number Of Rx FIFO Filters + 24 + 4 + read-write + + + BOFFDONEMSK + Bus Off Done Interrupt Mask + 30 + 1 + read-write + + + 0 + Bus off done interrupt disabled. + #0 + + + 1 + Bus off done interrupt enabled. + #1 + + + + + ERRMSK_FAST + Error Interrupt Mask for errors detected in the data phase of fast CAN FD frames + 31 + 1 + read-write + + + 0 + ERRINT_FAST error interrupt disabled. + #0 + + + 1 + ERRINT_FAST error interrupt enabled. + #1 + + + + + + + ESR2 + Error and Status 2 register + 0x38 + 32 + read-only + 0 + 0xFFFFFFFF + + + IMB + Inactive Mailbox + 13 + 1 + read-only + + + 0 + If ESR2[VPS] is asserted, the ESR2[LPTM] is not an inactive mailbox. + #0 + + + 1 + If ESR2[VPS] is asserted, there is at least one inactive mailbox. LPTM content is the number of the first one. + #1 + + + + + VPS + Valid Priority Status + 14 + 1 + read-only + + + 0 + Contents of IMB and LPTM are invalid. + #0 + + + 1 + Contents of IMB and LPTM are valid. + #1 + + + + + LPTM + Lowest Priority Tx Mailbox + 16 + 7 + read-only + + + + + CRCR + CRC register + 0x44 + 32 + read-only + 0 + 0xFFFFFFFF + + + TXCRC + Transmitted CRC value + 0 + 15 + read-only + + + MBCRC + CRC Mailbox + 16 + 7 + read-only + + + + + RXFGMASK + Rx FIFO Global Mask register + 0x48 + 32 + read-write + 0 + 0 + + + FGM + Rx FIFO Global Mask Bits + 0 + 32 + read-write + + + + + RXFIR + Rx FIFO Information register + 0x4C + 32 + read-only + 0 + 0 + + + IDHIT + Identifier Acceptance Filter Hit Indicator + 0 + 9 + read-only + + + + + CBT + CAN Bit Timing register + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + EPSEG2 + Extended Phase Segment 2 + 0 + 5 + read-write + + + EPSEG1 + Extended Phase Segment 1 + 5 + 5 + read-write + + + EPROPSEG + Extended Propagation Segment + 10 + 6 + read-write + + + ERJW + Extended Resync Jump Width + 16 + 5 + read-write + + + EPRESDIV + Extended Prescaler Division Factor + 21 + 10 + read-write + + + BTF + Bit Timing Format Enable + 31 + 1 + read-write + + + 0 + Extended bit time definitions disabled. + #0 + + + 1 + Extended bit time definitions enabled. + #1 + + + + + + + CS0 + Message Buffer 0 CS Register + CAN0 + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB0_16B_CS + Message Buffer 0 CS Register + CAN0 + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB0_32B_CS + Message Buffer 0 CS Register + CAN0 + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB0_64B_CS + Message Buffer 0 CS Register + CAN0 + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB0_8B_CS + Message Buffer 0 CS Register + CAN0 + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + ID0 + Message Buffer 0 ID Register + CAN0 + 0x84 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB0_16B_ID + Message Buffer 0 ID Register + CAN0 + 0x84 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB0_32B_ID + Message Buffer 0 ID Register + CAN0 + 0x84 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB0_64B_ID + Message Buffer 0 ID Register + CAN0 + 0x84 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB0_8B_ID + Message Buffer 0 ID Register + CAN0 + 0x84 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB0_16B_WORD0 + Message Buffer 0 WORD_16B Register + CAN0 + 0x88 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB0_32B_WORD0 + Message Buffer 0 WORD_32B Register + CAN0 + 0x88 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB0_64B_WORD0 + Message Buffer 0 WORD_64B Register + CAN0 + 0x88 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB0_8B_WORD0 + Message Buffer 0 WORD_8B Register + CAN0 + 0x88 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD00 + Message Buffer 0 WORD0 Register + CAN0 + 0x88 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB0_16B_WORD1 + Message Buffer 0 WORD_16B Register + CAN0 + 0x8C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB0_32B_WORD1 + Message Buffer 0 WORD_32B Register + CAN0 + 0x8C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB0_64B_WORD1 + Message Buffer 0 WORD_64B Register + CAN0 + 0x8C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB0_8B_WORD1 + Message Buffer 0 WORD_8B Register + CAN0 + 0x8C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD10 + Message Buffer 0 WORD1 Register + CAN0 + 0x8C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS1 + Message Buffer 1 CS Register + CAN0 + 0x90 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB0_16B_WORD2 + Message Buffer 0 WORD_16B Register + CAN0 + 0x90 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB0_32B_WORD2 + Message Buffer 0 WORD_32B Register + CAN0 + 0x90 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB0_64B_WORD2 + Message Buffer 0 WORD_64B Register + CAN0 + 0x90 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB1_8B_CS + Message Buffer 1 CS Register + CAN0 + 0x90 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + ID1 + Message Buffer 1 ID Register + CAN0 + 0x94 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB0_16B_WORD3 + Message Buffer 0 WORD_16B Register + CAN0 + 0x94 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB0_32B_WORD3 + Message Buffer 0 WORD_32B Register + CAN0 + 0x94 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB0_64B_WORD3 + Message Buffer 0 WORD_64B Register + CAN0 + 0x94 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB1_8B_ID + Message Buffer 1 ID Register + CAN0 + 0x94 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB0_32B_WORD4 + Message Buffer 0 WORD_32B Register + CAN0 + 0x98 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_19 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_18 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_17 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_16 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB0_64B_WORD4 + Message Buffer 0 WORD_64B Register + CAN0 + 0x98 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_19 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_18 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_17 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_16 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB1_16B_CS + Message Buffer 1 CS Register + CAN0 + 0x98 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB1_8B_WORD0 + Message Buffer 1 WORD_8B Register + CAN0 + 0x98 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD01 + Message Buffer 1 WORD0 Register + CAN0 + 0x98 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB0_32B_WORD5 + Message Buffer 0 WORD_32B Register + CAN0 + 0x9C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_23 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_22 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_21 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_20 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB0_64B_WORD5 + Message Buffer 0 WORD_64B Register + CAN0 + 0x9C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_23 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_22 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_21 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_20 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB1_16B_ID + Message Buffer 1 ID Register + CAN0 + 0x9C + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB1_8B_WORD1 + Message Buffer 1 WORD_8B Register + CAN0 + 0x9C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD11 + Message Buffer 1 WORD1 Register + CAN0 + 0x9C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS2 + Message Buffer 2 CS Register + CAN0 + 0xA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB0_32B_WORD6 + Message Buffer 0 WORD_32B Register + CAN0 + 0xA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_27 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_26 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_25 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_24 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB0_64B_WORD6 + Message Buffer 0 WORD_64B Register + CAN0 + 0xA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_27 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_26 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_25 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_24 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB1_16B_WORD0 + Message Buffer 1 WORD_16B Register + CAN0 + 0xA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB2_8B_CS + Message Buffer 2 CS Register + CAN0 + 0xA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + ID2 + Message Buffer 2 ID Register + CAN0 + 0xA4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB0_32B_WORD7 + Message Buffer 0 WORD_32B Register + CAN0 + 0xA4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_31 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_30 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_29 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_28 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB0_64B_WORD7 + Message Buffer 0 WORD_64B Register + CAN0 + 0xA4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_31 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_30 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_29 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_28 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB1_16B_WORD1 + Message Buffer 1 WORD_16B Register + CAN0 + 0xA4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB2_8B_ID + Message Buffer 2 ID Register + CAN0 + 0xA4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB0_64B_WORD8 + Message Buffer 0 WORD_64B Register + CAN0 + 0xA8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_35 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_34 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_33 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_32 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB1_16B_WORD2 + Message Buffer 1 WORD_16B Register + CAN0 + 0xA8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB1_32B_CS + Message Buffer 1 CS Register + CAN0 + 0xA8 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB2_8B_WORD0 + Message Buffer 2 WORD_8B Register + CAN0 + 0xA8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD02 + Message Buffer 2 WORD0 Register + CAN0 + 0xA8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB0_64B_WORD9 + Message Buffer 0 WORD_64B Register + CAN0 + 0xAC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_39 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_38 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_37 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_36 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB1_16B_WORD3 + Message Buffer 1 WORD_16B Register + CAN0 + 0xAC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB1_32B_ID + Message Buffer 1 ID Register + CAN0 + 0xAC + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB2_8B_WORD1 + Message Buffer 2 WORD_8B Register + CAN0 + 0xAC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD12 + Message Buffer 2 WORD1 Register + CAN0 + 0xAC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS3 + Message Buffer 3 CS Register + CAN0 + 0xB0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB0_64B_WORD10 + Message Buffer 0 WORD_64B Register + CAN0 + 0xB0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_43 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_42 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_41 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_40 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB1_32B_WORD0 + Message Buffer 1 WORD_32B Register + CAN0 + 0xB0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB2_16B_CS + Message Buffer 2 CS Register + CAN0 + 0xB0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB3_8B_CS + Message Buffer 3 CS Register + CAN0 + 0xB0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + ID3 + Message Buffer 3 ID Register + CAN0 + 0xB4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB0_64B_WORD11 + Message Buffer 0 WORD_64B Register + CAN0 + 0xB4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_47 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_46 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_45 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_44 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB1_32B_WORD1 + Message Buffer 1 WORD_32B Register + CAN0 + 0xB4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB2_16B_ID + Message Buffer 2 ID Register + CAN0 + 0xB4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB3_8B_ID + Message Buffer 3 ID Register + CAN0 + 0xB4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB0_64B_WORD12 + Message Buffer 0 WORD_64B Register + CAN0 + 0xB8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_51 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_50 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_49 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_48 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB1_32B_WORD2 + Message Buffer 1 WORD_32B Register + CAN0 + 0xB8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB2_16B_WORD0 + Message Buffer 2 WORD_16B Register + CAN0 + 0xB8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB3_8B_WORD0 + Message Buffer 3 WORD_8B Register + CAN0 + 0xB8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD03 + Message Buffer 3 WORD0 Register + CAN0 + 0xB8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB0_64B_WORD13 + Message Buffer 0 WORD_64B Register + CAN0 + 0xBC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_55 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_54 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_53 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_52 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB1_32B_WORD3 + Message Buffer 1 WORD_32B Register + CAN0 + 0xBC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB2_16B_WORD1 + Message Buffer 2 WORD_16B Register + CAN0 + 0xBC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB3_8B_WORD1 + Message Buffer 3 WORD_8B Register + CAN0 + 0xBC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD13 + Message Buffer 3 WORD1 Register + CAN0 + 0xBC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS4 + Message Buffer 4 CS Register + CAN0 + 0xC0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB0_64B_WORD14 + Message Buffer 0 WORD_64B Register + CAN0 + 0xC0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_59 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_58 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_57 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_56 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB1_32B_WORD4 + Message Buffer 1 WORD_32B Register + CAN0 + 0xC0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_19 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_18 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_17 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_16 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB2_16B_WORD2 + Message Buffer 2 WORD_16B Register + CAN0 + 0xC0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB4_8B_CS + Message Buffer 4 CS Register + CAN0 + 0xC0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + ID4 + Message Buffer 4 ID Register + CAN0 + 0xC4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB0_64B_WORD15 + Message Buffer 0 WORD_64B Register + CAN0 + 0xC4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_63 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_62 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_61 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_60 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB1_32B_WORD5 + Message Buffer 1 WORD_32B Register + CAN0 + 0xC4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_23 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_22 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_21 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_20 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB2_16B_WORD3 + Message Buffer 2 WORD_16B Register + CAN0 + 0xC4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB4_8B_ID + Message Buffer 4 ID Register + CAN0 + 0xC4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB1_32B_WORD6 + Message Buffer 1 WORD_32B Register + CAN0 + 0xC8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_27 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_26 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_25 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_24 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB1_64B_CS + Message Buffer 1 CS Register + CAN0 + 0xC8 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB3_16B_CS + Message Buffer 3 CS Register + CAN0 + 0xC8 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB4_8B_WORD0 + Message Buffer 4 WORD_8B Register + CAN0 + 0xC8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD04 + Message Buffer 4 WORD0 Register + CAN0 + 0xC8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB1_32B_WORD7 + Message Buffer 1 WORD_32B Register + CAN0 + 0xCC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_31 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_30 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_29 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_28 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB1_64B_ID + Message Buffer 1 ID Register + CAN0 + 0xCC + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB3_16B_ID + Message Buffer 3 ID Register + CAN0 + 0xCC + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB4_8B_WORD1 + Message Buffer 4 WORD_8B Register + CAN0 + 0xCC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD14 + Message Buffer 4 WORD1 Register + CAN0 + 0xCC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS5 + Message Buffer 5 CS Register + CAN0 + 0xD0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB1_64B_WORD0 + Message Buffer 1 WORD_64B Register + CAN0 + 0xD0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB2_32B_CS + Message Buffer 2 CS Register + CAN0 + 0xD0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB3_16B_WORD0 + Message Buffer 3 WORD_16B Register + CAN0 + 0xD0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB5_8B_CS + Message Buffer 5 CS Register + CAN0 + 0xD0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + ID5 + Message Buffer 5 ID Register + CAN0 + 0xD4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB1_64B_WORD1 + Message Buffer 1 WORD_64B Register + CAN0 + 0xD4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB2_32B_ID + Message Buffer 2 ID Register + CAN0 + 0xD4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB3_16B_WORD1 + Message Buffer 3 WORD_16B Register + CAN0 + 0xD4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB5_8B_ID + Message Buffer 5 ID Register + CAN0 + 0xD4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB1_64B_WORD2 + Message Buffer 1 WORD_64B Register + CAN0 + 0xD8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB2_32B_WORD0 + Message Buffer 2 WORD_32B Register + CAN0 + 0xD8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB3_16B_WORD2 + Message Buffer 3 WORD_16B Register + CAN0 + 0xD8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB5_8B_WORD0 + Message Buffer 5 WORD_8B Register + CAN0 + 0xD8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD05 + Message Buffer 5 WORD0 Register + CAN0 + 0xD8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB1_64B_WORD3 + Message Buffer 1 WORD_64B Register + CAN0 + 0xDC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB2_32B_WORD1 + Message Buffer 2 WORD_32B Register + CAN0 + 0xDC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB3_16B_WORD3 + Message Buffer 3 WORD_16B Register + CAN0 + 0xDC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB5_8B_WORD1 + Message Buffer 5 WORD_8B Register + CAN0 + 0xDC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD15 + Message Buffer 5 WORD1 Register + CAN0 + 0xDC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS6 + Message Buffer 6 CS Register + CAN0 + 0xE0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB1_64B_WORD4 + Message Buffer 1 WORD_64B Register + CAN0 + 0xE0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_19 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_18 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_17 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_16 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB2_32B_WORD2 + Message Buffer 2 WORD_32B Register + CAN0 + 0xE0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB4_16B_CS + Message Buffer 4 CS Register + CAN0 + 0xE0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB6_8B_CS + Message Buffer 6 CS Register + CAN0 + 0xE0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + ID6 + Message Buffer 6 ID Register + CAN0 + 0xE4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB1_64B_WORD5 + Message Buffer 1 WORD_64B Register + CAN0 + 0xE4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_23 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_22 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_21 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_20 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB2_32B_WORD3 + Message Buffer 2 WORD_32B Register + CAN0 + 0xE4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB4_16B_ID + Message Buffer 4 ID Register + CAN0 + 0xE4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB6_8B_ID + Message Buffer 6 ID Register + CAN0 + 0xE4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB1_64B_WORD6 + Message Buffer 1 WORD_64B Register + CAN0 + 0xE8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_27 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_26 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_25 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_24 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB2_32B_WORD4 + Message Buffer 2 WORD_32B Register + CAN0 + 0xE8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_19 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_18 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_17 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_16 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB4_16B_WORD0 + Message Buffer 4 WORD_16B Register + CAN0 + 0xE8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB6_8B_WORD0 + Message Buffer 6 WORD_8B Register + CAN0 + 0xE8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD06 + Message Buffer 6 WORD0 Register + CAN0 + 0xE8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB1_64B_WORD7 + Message Buffer 1 WORD_64B Register + CAN0 + 0xEC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_31 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_30 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_29 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_28 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB2_32B_WORD5 + Message Buffer 2 WORD_32B Register + CAN0 + 0xEC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_23 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_22 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_21 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_20 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB4_16B_WORD1 + Message Buffer 4 WORD_16B Register + CAN0 + 0xEC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB6_8B_WORD1 + Message Buffer 6 WORD_8B Register + CAN0 + 0xEC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD16 + Message Buffer 6 WORD1 Register + CAN0 + 0xEC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS7 + Message Buffer 7 CS Register + CAN0 + 0xF0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB1_64B_WORD8 + Message Buffer 1 WORD_64B Register + CAN0 + 0xF0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_35 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_34 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_33 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_32 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB2_32B_WORD6 + Message Buffer 2 WORD_32B Register + CAN0 + 0xF0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_27 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_26 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_25 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_24 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB4_16B_WORD2 + Message Buffer 4 WORD_16B Register + CAN0 + 0xF0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB7_8B_CS + Message Buffer 7 CS Register + CAN0 + 0xF0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + ID7 + Message Buffer 7 ID Register + CAN0 + 0xF4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB1_64B_WORD9 + Message Buffer 1 WORD_64B Register + CAN0 + 0xF4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_39 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_38 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_37 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_36 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB2_32B_WORD7 + Message Buffer 2 WORD_32B Register + CAN0 + 0xF4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_31 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_30 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_29 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_28 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB4_16B_WORD3 + Message Buffer 4 WORD_16B Register + CAN0 + 0xF4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB7_8B_ID + Message Buffer 7 ID Register + CAN0 + 0xF4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB1_64B_WORD10 + Message Buffer 1 WORD_64B Register + CAN0 + 0xF8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_43 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_42 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_41 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_40 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB3_32B_CS + Message Buffer 3 CS Register + CAN0 + 0xF8 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB5_16B_CS + Message Buffer 5 CS Register + CAN0 + 0xF8 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB7_8B_WORD0 + Message Buffer 7 WORD_8B Register + CAN0 + 0xF8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD07 + Message Buffer 7 WORD0 Register + CAN0 + 0xF8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB1_64B_WORD11 + Message Buffer 1 WORD_64B Register + CAN0 + 0xFC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_47 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_46 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_45 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_44 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB3_32B_ID + Message Buffer 3 ID Register + CAN0 + 0xFC + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB5_16B_ID + Message Buffer 5 ID Register + CAN0 + 0xFC + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB7_8B_WORD1 + Message Buffer 7 WORD_8B Register + CAN0 + 0xFC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD17 + Message Buffer 7 WORD1 Register + CAN0 + 0xFC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS8 + Message Buffer 8 CS Register + CAN0 + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB1_64B_WORD12 + Message Buffer 1 WORD_64B Register + CAN0 + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_51 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_50 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_49 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_48 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB3_32B_WORD0 + Message Buffer 3 WORD_32B Register + CAN0 + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB5_16B_WORD0 + Message Buffer 5 WORD_16B Register + CAN0 + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB8_8B_CS + Message Buffer 8 CS Register + CAN0 + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + ID8 + Message Buffer 8 ID Register + CAN0 + 0x104 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB1_64B_WORD13 + Message Buffer 1 WORD_64B Register + CAN0 + 0x104 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_55 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_54 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_53 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_52 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB3_32B_WORD1 + Message Buffer 3 WORD_32B Register + CAN0 + 0x104 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB5_16B_WORD1 + Message Buffer 5 WORD_16B Register + CAN0 + 0x104 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB8_8B_ID + Message Buffer 8 ID Register + CAN0 + 0x104 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB1_64B_WORD14 + Message Buffer 1 WORD_64B Register + CAN0 + 0x108 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_59 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_58 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_57 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_56 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB3_32B_WORD2 + Message Buffer 3 WORD_32B Register + CAN0 + 0x108 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB5_16B_WORD2 + Message Buffer 5 WORD_16B Register + CAN0 + 0x108 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB8_8B_WORD0 + Message Buffer 8 WORD_8B Register + CAN0 + 0x108 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD08 + Message Buffer 8 WORD0 Register + CAN0 + 0x108 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB1_64B_WORD15 + Message Buffer 1 WORD_64B Register + CAN0 + 0x10C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_63 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_62 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_61 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_60 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB3_32B_WORD3 + Message Buffer 3 WORD_32B Register + CAN0 + 0x10C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB5_16B_WORD3 + Message Buffer 5 WORD_16B Register + CAN0 + 0x10C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB8_8B_WORD1 + Message Buffer 8 WORD_8B Register + CAN0 + 0x10C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD18 + Message Buffer 8 WORD1 Register + CAN0 + 0x10C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS9 + Message Buffer 9 CS Register + CAN0 + 0x110 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB2_64B_CS + Message Buffer 2 CS Register + CAN0 + 0x110 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB3_32B_WORD4 + Message Buffer 3 WORD_32B Register + CAN0 + 0x110 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_19 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_18 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_17 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_16 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB6_16B_CS + Message Buffer 6 CS Register + CAN0 + 0x110 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB9_8B_CS + Message Buffer 9 CS Register + CAN0 + 0x110 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + ID9 + Message Buffer 9 ID Register + CAN0 + 0x114 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB2_64B_ID + Message Buffer 2 ID Register + CAN0 + 0x114 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB3_32B_WORD5 + Message Buffer 3 WORD_32B Register + CAN0 + 0x114 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_23 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_22 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_21 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_20 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB6_16B_ID + Message Buffer 6 ID Register + CAN0 + 0x114 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB9_8B_ID + Message Buffer 9 ID Register + CAN0 + 0x114 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB2_64B_WORD0 + Message Buffer 2 WORD_64B Register + CAN0 + 0x118 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB3_32B_WORD6 + Message Buffer 3 WORD_32B Register + CAN0 + 0x118 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_27 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_26 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_25 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_24 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB6_16B_WORD0 + Message Buffer 6 WORD_16B Register + CAN0 + 0x118 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB9_8B_WORD0 + Message Buffer 9 WORD_8B Register + CAN0 + 0x118 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD09 + Message Buffer 9 WORD0 Register + CAN0 + 0x118 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB2_64B_WORD1 + Message Buffer 2 WORD_64B Register + CAN0 + 0x11C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB3_32B_WORD7 + Message Buffer 3 WORD_32B Register + CAN0 + 0x11C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_31 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_30 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_29 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_28 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB6_16B_WORD1 + Message Buffer 6 WORD_16B Register + CAN0 + 0x11C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB9_8B_WORD1 + Message Buffer 9 WORD_8B Register + CAN0 + 0x11C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD19 + Message Buffer 9 WORD1 Register + CAN0 + 0x11C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS10 + Message Buffer 10 CS Register + CAN0 + 0x120 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB10_8B_CS + Message Buffer 10 CS Register + CAN0 + 0x120 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB2_64B_WORD2 + Message Buffer 2 WORD_64B Register + CAN0 + 0x120 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB4_32B_CS + Message Buffer 4 CS Register + CAN0 + 0x120 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB6_16B_WORD2 + Message Buffer 6 WORD_16B Register + CAN0 + 0x120 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + ID10 + Message Buffer 10 ID Register + CAN0 + 0x124 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB10_8B_ID + Message Buffer 10 ID Register + CAN0 + 0x124 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB2_64B_WORD3 + Message Buffer 2 WORD_64B Register + CAN0 + 0x124 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB4_32B_ID + Message Buffer 4 ID Register + CAN0 + 0x124 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB6_16B_WORD3 + Message Buffer 6 WORD_16B Register + CAN0 + 0x124 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB10_8B_WORD0 + Message Buffer 10 WORD_8B Register + CAN0 + 0x128 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB2_64B_WORD4 + Message Buffer 2 WORD_64B Register + CAN0 + 0x128 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_19 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_18 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_17 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_16 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB4_32B_WORD0 + Message Buffer 4 WORD_32B Register + CAN0 + 0x128 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB7_16B_CS + Message Buffer 7 CS Register + CAN0 + 0x128 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + WORD010 + Message Buffer 10 WORD0 Register + CAN0 + 0x128 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB10_8B_WORD1 + Message Buffer 10 WORD_8B Register + CAN0 + 0x12C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB2_64B_WORD5 + Message Buffer 2 WORD_64B Register + CAN0 + 0x12C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_23 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_22 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_21 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_20 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB4_32B_WORD1 + Message Buffer 4 WORD_32B Register + CAN0 + 0x12C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB7_16B_ID + Message Buffer 7 ID Register + CAN0 + 0x12C + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD110 + Message Buffer 10 WORD1 Register + CAN0 + 0x12C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS11 + Message Buffer 11 CS Register + CAN0 + 0x130 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB11_8B_CS + Message Buffer 11 CS Register + CAN0 + 0x130 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB2_64B_WORD6 + Message Buffer 2 WORD_64B Register + CAN0 + 0x130 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_27 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_26 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_25 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_24 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB4_32B_WORD2 + Message Buffer 4 WORD_32B Register + CAN0 + 0x130 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB7_16B_WORD0 + Message Buffer 7 WORD_16B Register + CAN0 + 0x130 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + ID11 + Message Buffer 11 ID Register + CAN0 + 0x134 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB11_8B_ID + Message Buffer 11 ID Register + CAN0 + 0x134 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB2_64B_WORD7 + Message Buffer 2 WORD_64B Register + CAN0 + 0x134 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_31 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_30 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_29 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_28 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB4_32B_WORD3 + Message Buffer 4 WORD_32B Register + CAN0 + 0x134 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB7_16B_WORD1 + Message Buffer 7 WORD_16B Register + CAN0 + 0x134 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB11_8B_WORD0 + Message Buffer 11 WORD_8B Register + CAN0 + 0x138 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB2_64B_WORD8 + Message Buffer 2 WORD_64B Register + CAN0 + 0x138 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_35 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_34 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_33 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_32 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB4_32B_WORD4 + Message Buffer 4 WORD_32B Register + CAN0 + 0x138 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_19 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_18 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_17 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_16 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB7_16B_WORD2 + Message Buffer 7 WORD_16B Register + CAN0 + 0x138 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD011 + Message Buffer 11 WORD0 Register + CAN0 + 0x138 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB11_8B_WORD1 + Message Buffer 11 WORD_8B Register + CAN0 + 0x13C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB2_64B_WORD9 + Message Buffer 2 WORD_64B Register + CAN0 + 0x13C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_39 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_38 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_37 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_36 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB4_32B_WORD5 + Message Buffer 4 WORD_32B Register + CAN0 + 0x13C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_23 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_22 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_21 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_20 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB7_16B_WORD3 + Message Buffer 7 WORD_16B Register + CAN0 + 0x13C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD111 + Message Buffer 11 WORD1 Register + CAN0 + 0x13C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS12 + Message Buffer 12 CS Register + CAN0 + 0x140 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB12_8B_CS + Message Buffer 12 CS Register + CAN0 + 0x140 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB2_64B_WORD10 + Message Buffer 2 WORD_64B Register + CAN0 + 0x140 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_43 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_42 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_41 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_40 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB4_32B_WORD6 + Message Buffer 4 WORD_32B Register + CAN0 + 0x140 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_27 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_26 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_25 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_24 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB8_16B_CS + Message Buffer 8 CS Register + CAN0 + 0x140 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + ID12 + Message Buffer 12 ID Register + CAN0 + 0x144 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB12_8B_ID + Message Buffer 12 ID Register + CAN0 + 0x144 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB2_64B_WORD11 + Message Buffer 2 WORD_64B Register + CAN0 + 0x144 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_47 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_46 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_45 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_44 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB4_32B_WORD7 + Message Buffer 4 WORD_32B Register + CAN0 + 0x144 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_31 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_30 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_29 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_28 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB8_16B_ID + Message Buffer 8 ID Register + CAN0 + 0x144 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB12_8B_WORD0 + Message Buffer 12 WORD_8B Register + CAN0 + 0x148 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB2_64B_WORD12 + Message Buffer 2 WORD_64B Register + CAN0 + 0x148 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_51 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_50 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_49 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_48 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB5_32B_CS + Message Buffer 5 CS Register + CAN0 + 0x148 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB8_16B_WORD0 + Message Buffer 8 WORD_16B Register + CAN0 + 0x148 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD012 + Message Buffer 12 WORD0 Register + CAN0 + 0x148 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB12_8B_WORD1 + Message Buffer 12 WORD_8B Register + CAN0 + 0x14C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB2_64B_WORD13 + Message Buffer 2 WORD_64B Register + CAN0 + 0x14C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_55 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_54 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_53 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_52 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB5_32B_ID + Message Buffer 5 ID Register + CAN0 + 0x14C + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB8_16B_WORD1 + Message Buffer 8 WORD_16B Register + CAN0 + 0x14C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD112 + Message Buffer 12 WORD1 Register + CAN0 + 0x14C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS13 + Message Buffer 13 CS Register + CAN0 + 0x150 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB13_8B_CS + Message Buffer 13 CS Register + CAN0 + 0x150 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB2_64B_WORD14 + Message Buffer 2 WORD_64B Register + CAN0 + 0x150 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_59 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_58 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_57 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_56 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB5_32B_WORD0 + Message Buffer 5 WORD_32B Register + CAN0 + 0x150 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB8_16B_WORD2 + Message Buffer 8 WORD_16B Register + CAN0 + 0x150 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + ID13 + Message Buffer 13 ID Register + CAN0 + 0x154 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB13_8B_ID + Message Buffer 13 ID Register + CAN0 + 0x154 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB2_64B_WORD15 + Message Buffer 2 WORD_64B Register + CAN0 + 0x154 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_63 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_62 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_61 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_60 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB5_32B_WORD1 + Message Buffer 5 WORD_32B Register + CAN0 + 0x154 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB8_16B_WORD3 + Message Buffer 8 WORD_16B Register + CAN0 + 0x154 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB13_8B_WORD0 + Message Buffer 13 WORD_8B Register + CAN0 + 0x158 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB3_64B_CS + Message Buffer 3 CS Register + CAN0 + 0x158 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB5_32B_WORD2 + Message Buffer 5 WORD_32B Register + CAN0 + 0x158 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB9_16B_CS + Message Buffer 9 CS Register + CAN0 + 0x158 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + WORD013 + Message Buffer 13 WORD0 Register + CAN0 + 0x158 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB13_8B_WORD1 + Message Buffer 13 WORD_8B Register + CAN0 + 0x15C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB3_64B_ID + Message Buffer 3 ID Register + CAN0 + 0x15C + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB5_32B_WORD3 + Message Buffer 5 WORD_32B Register + CAN0 + 0x15C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB9_16B_ID + Message Buffer 9 ID Register + CAN0 + 0x15C + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD113 + Message Buffer 13 WORD1 Register + CAN0 + 0x15C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS14 + Message Buffer 14 CS Register + CAN0 + 0x160 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB14_8B_CS + Message Buffer 14 CS Register + CAN0 + 0x160 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB3_64B_WORD0 + Message Buffer 3 WORD_64B Register + CAN0 + 0x160 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB5_32B_WORD4 + Message Buffer 5 WORD_32B Register + CAN0 + 0x160 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_19 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_18 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_17 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_16 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB9_16B_WORD0 + Message Buffer 9 WORD_16B Register + CAN0 + 0x160 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + ID14 + Message Buffer 14 ID Register + CAN0 + 0x164 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB14_8B_ID + Message Buffer 14 ID Register + CAN0 + 0x164 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB3_64B_WORD1 + Message Buffer 3 WORD_64B Register + CAN0 + 0x164 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB5_32B_WORD5 + Message Buffer 5 WORD_32B Register + CAN0 + 0x164 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_23 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_22 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_21 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_20 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB9_16B_WORD1 + Message Buffer 9 WORD_16B Register + CAN0 + 0x164 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB14_8B_WORD0 + Message Buffer 14 WORD_8B Register + CAN0 + 0x168 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB3_64B_WORD2 + Message Buffer 3 WORD_64B Register + CAN0 + 0x168 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB5_32B_WORD6 + Message Buffer 5 WORD_32B Register + CAN0 + 0x168 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_27 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_26 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_25 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_24 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB9_16B_WORD2 + Message Buffer 9 WORD_16B Register + CAN0 + 0x168 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD014 + Message Buffer 14 WORD0 Register + CAN0 + 0x168 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB14_8B_WORD1 + Message Buffer 14 WORD_8B Register + CAN0 + 0x16C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB3_64B_WORD3 + Message Buffer 3 WORD_64B Register + CAN0 + 0x16C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB5_32B_WORD7 + Message Buffer 5 WORD_32B Register + CAN0 + 0x16C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_31 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_30 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_29 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_28 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB9_16B_WORD3 + Message Buffer 9 WORD_16B Register + CAN0 + 0x16C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD114 + Message Buffer 14 WORD1 Register + CAN0 + 0x16C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS15 + Message Buffer 15 CS Register + CAN0 + 0x170 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB10_16B_CS + Message Buffer 10 CS Register + CAN0 + 0x170 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB15_8B_CS + Message Buffer 15 CS Register + CAN0 + 0x170 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB3_64B_WORD4 + Message Buffer 3 WORD_64B Register + CAN0 + 0x170 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_19 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_18 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_17 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_16 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB6_32B_CS + Message Buffer 6 CS Register + CAN0 + 0x170 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + ID15 + Message Buffer 15 ID Register + CAN0 + 0x174 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB10_16B_ID + Message Buffer 10 ID Register + CAN0 + 0x174 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB15_8B_ID + Message Buffer 15 ID Register + CAN0 + 0x174 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB3_64B_WORD5 + Message Buffer 3 WORD_64B Register + CAN0 + 0x174 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_23 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_22 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_21 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_20 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB6_32B_ID + Message Buffer 6 ID Register + CAN0 + 0x174 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB10_16B_WORD0 + Message Buffer 10 WORD_16B Register + CAN0 + 0x178 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB15_8B_WORD0 + Message Buffer 15 WORD_8B Register + CAN0 + 0x178 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB3_64B_WORD6 + Message Buffer 3 WORD_64B Register + CAN0 + 0x178 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_27 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_26 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_25 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_24 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB6_32B_WORD0 + Message Buffer 6 WORD_32B Register + CAN0 + 0x178 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD015 + Message Buffer 15 WORD0 Register + CAN0 + 0x178 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB10_16B_WORD1 + Message Buffer 10 WORD_16B Register + CAN0 + 0x17C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB15_8B_WORD1 + Message Buffer 15 WORD_8B Register + CAN0 + 0x17C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB3_64B_WORD7 + Message Buffer 3 WORD_64B Register + CAN0 + 0x17C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_31 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_30 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_29 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_28 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB6_32B_WORD1 + Message Buffer 6 WORD_32B Register + CAN0 + 0x17C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD115 + Message Buffer 15 WORD1 Register + CAN0 + 0x17C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS16 + Message Buffer 16 CS Register + CAN0 + 0x180 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB10_16B_WORD2 + Message Buffer 10 WORD_16B Register + CAN0 + 0x180 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB16_8B_CS + Message Buffer 16 CS Register + CAN0 + 0x180 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB3_64B_WORD8 + Message Buffer 3 WORD_64B Register + CAN0 + 0x180 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_35 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_34 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_33 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_32 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB6_32B_WORD2 + Message Buffer 6 WORD_32B Register + CAN0 + 0x180 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + ID16 + Message Buffer 16 ID Register + CAN0 + 0x184 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB10_16B_WORD3 + Message Buffer 10 WORD_16B Register + CAN0 + 0x184 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB16_8B_ID + Message Buffer 16 ID Register + CAN0 + 0x184 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB3_64B_WORD9 + Message Buffer 3 WORD_64B Register + CAN0 + 0x184 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_39 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_38 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_37 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_36 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB6_32B_WORD3 + Message Buffer 6 WORD_32B Register + CAN0 + 0x184 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB11_16B_CS + Message Buffer 11 CS Register + CAN0 + 0x188 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB16_8B_WORD0 + Message Buffer 16 WORD_8B Register + CAN0 + 0x188 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB3_64B_WORD10 + Message Buffer 3 WORD_64B Register + CAN0 + 0x188 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_43 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_42 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_41 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_40 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB6_32B_WORD4 + Message Buffer 6 WORD_32B Register + CAN0 + 0x188 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_19 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_18 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_17 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_16 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD016 + Message Buffer 16 WORD0 Register + CAN0 + 0x188 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB11_16B_ID + Message Buffer 11 ID Register + CAN0 + 0x18C + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB16_8B_WORD1 + Message Buffer 16 WORD_8B Register + CAN0 + 0x18C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB3_64B_WORD11 + Message Buffer 3 WORD_64B Register + CAN0 + 0x18C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_47 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_46 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_45 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_44 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB6_32B_WORD5 + Message Buffer 6 WORD_32B Register + CAN0 + 0x18C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_23 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_22 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_21 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_20 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD116 + Message Buffer 16 WORD1 Register + CAN0 + 0x18C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS17 + Message Buffer 17 CS Register + CAN0 + 0x190 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB11_16B_WORD0 + Message Buffer 11 WORD_16B Register + CAN0 + 0x190 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB17_8B_CS + Message Buffer 17 CS Register + CAN0 + 0x190 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB3_64B_WORD12 + Message Buffer 3 WORD_64B Register + CAN0 + 0x190 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_51 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_50 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_49 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_48 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB6_32B_WORD6 + Message Buffer 6 WORD_32B Register + CAN0 + 0x190 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_27 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_26 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_25 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_24 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + ID17 + Message Buffer 17 ID Register + CAN0 + 0x194 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB11_16B_WORD1 + Message Buffer 11 WORD_16B Register + CAN0 + 0x194 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB17_8B_ID + Message Buffer 17 ID Register + CAN0 + 0x194 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB3_64B_WORD13 + Message Buffer 3 WORD_64B Register + CAN0 + 0x194 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_55 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_54 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_53 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_52 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB6_32B_WORD7 + Message Buffer 6 WORD_32B Register + CAN0 + 0x194 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_31 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_30 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_29 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_28 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB11_16B_WORD2 + Message Buffer 11 WORD_16B Register + CAN0 + 0x198 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB17_8B_WORD0 + Message Buffer 17 WORD_8B Register + CAN0 + 0x198 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB3_64B_WORD14 + Message Buffer 3 WORD_64B Register + CAN0 + 0x198 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_59 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_58 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_57 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_56 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB7_32B_CS + Message Buffer 7 CS Register + CAN0 + 0x198 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + WORD017 + Message Buffer 17 WORD0 Register + CAN0 + 0x198 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB11_16B_WORD3 + Message Buffer 11 WORD_16B Register + CAN0 + 0x19C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB17_8B_WORD1 + Message Buffer 17 WORD_8B Register + CAN0 + 0x19C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB3_64B_WORD15 + Message Buffer 3 WORD_64B Register + CAN0 + 0x19C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_63 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_62 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_61 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_60 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB7_32B_ID + Message Buffer 7 ID Register + CAN0 + 0x19C + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD117 + Message Buffer 17 WORD1 Register + CAN0 + 0x19C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS18 + Message Buffer 18 CS Register + CAN0 + 0x1A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB12_16B_CS + Message Buffer 12 CS Register + CAN0 + 0x1A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB18_8B_CS + Message Buffer 18 CS Register + CAN0 + 0x1A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB4_64B_CS + Message Buffer 4 CS Register + CAN0 + 0x1A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB7_32B_WORD0 + Message Buffer 7 WORD_32B Register + CAN0 + 0x1A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + ID18 + Message Buffer 18 ID Register + CAN0 + 0x1A4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB12_16B_ID + Message Buffer 12 ID Register + CAN0 + 0x1A4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB18_8B_ID + Message Buffer 18 ID Register + CAN0 + 0x1A4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB4_64B_ID + Message Buffer 4 ID Register + CAN0 + 0x1A4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB7_32B_WORD1 + Message Buffer 7 WORD_32B Register + CAN0 + 0x1A4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB12_16B_WORD0 + Message Buffer 12 WORD_16B Register + CAN0 + 0x1A8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB18_8B_WORD0 + Message Buffer 18 WORD_8B Register + CAN0 + 0x1A8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB4_64B_WORD0 + Message Buffer 4 WORD_64B Register + CAN0 + 0x1A8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB7_32B_WORD2 + Message Buffer 7 WORD_32B Register + CAN0 + 0x1A8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD018 + Message Buffer 18 WORD0 Register + CAN0 + 0x1A8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB12_16B_WORD1 + Message Buffer 12 WORD_16B Register + CAN0 + 0x1AC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB18_8B_WORD1 + Message Buffer 18 WORD_8B Register + CAN0 + 0x1AC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB4_64B_WORD1 + Message Buffer 4 WORD_64B Register + CAN0 + 0x1AC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB7_32B_WORD3 + Message Buffer 7 WORD_32B Register + CAN0 + 0x1AC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD118 + Message Buffer 18 WORD1 Register + CAN0 + 0x1AC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS19 + Message Buffer 19 CS Register + CAN0 + 0x1B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB12_16B_WORD2 + Message Buffer 12 WORD_16B Register + CAN0 + 0x1B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB19_8B_CS + Message Buffer 19 CS Register + CAN0 + 0x1B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB4_64B_WORD2 + Message Buffer 4 WORD_64B Register + CAN0 + 0x1B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB7_32B_WORD4 + Message Buffer 7 WORD_32B Register + CAN0 + 0x1B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_19 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_18 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_17 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_16 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + ID19 + Message Buffer 19 ID Register + CAN0 + 0x1B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB12_16B_WORD3 + Message Buffer 12 WORD_16B Register + CAN0 + 0x1B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB19_8B_ID + Message Buffer 19 ID Register + CAN0 + 0x1B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB4_64B_WORD3 + Message Buffer 4 WORD_64B Register + CAN0 + 0x1B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB7_32B_WORD5 + Message Buffer 7 WORD_32B Register + CAN0 + 0x1B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_23 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_22 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_21 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_20 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB13_16B_CS + Message Buffer 13 CS Register + CAN0 + 0x1B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB19_8B_WORD0 + Message Buffer 19 WORD_8B Register + CAN0 + 0x1B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB4_64B_WORD4 + Message Buffer 4 WORD_64B Register + CAN0 + 0x1B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_19 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_18 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_17 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_16 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB7_32B_WORD6 + Message Buffer 7 WORD_32B Register + CAN0 + 0x1B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_27 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_26 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_25 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_24 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD019 + Message Buffer 19 WORD0 Register + CAN0 + 0x1B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB13_16B_ID + Message Buffer 13 ID Register + CAN0 + 0x1BC + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB19_8B_WORD1 + Message Buffer 19 WORD_8B Register + CAN0 + 0x1BC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB4_64B_WORD5 + Message Buffer 4 WORD_64B Register + CAN0 + 0x1BC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_23 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_22 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_21 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_20 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB7_32B_WORD7 + Message Buffer 7 WORD_32B Register + CAN0 + 0x1BC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_31 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_30 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_29 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_28 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD119 + Message Buffer 19 WORD1 Register + CAN0 + 0x1BC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS20 + Message Buffer 20 CS Register + CAN0 + 0x1C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB13_16B_WORD0 + Message Buffer 13 WORD_16B Register + CAN0 + 0x1C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB20_8B_CS + Message Buffer 20 CS Register + CAN0 + 0x1C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB4_64B_WORD6 + Message Buffer 4 WORD_64B Register + CAN0 + 0x1C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_27 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_26 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_25 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_24 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB8_32B_CS + Message Buffer 8 CS Register + CAN0 + 0x1C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + ID20 + Message Buffer 20 ID Register + CAN0 + 0x1C4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB13_16B_WORD1 + Message Buffer 13 WORD_16B Register + CAN0 + 0x1C4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB20_8B_ID + Message Buffer 20 ID Register + CAN0 + 0x1C4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB4_64B_WORD7 + Message Buffer 4 WORD_64B Register + CAN0 + 0x1C4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_31 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_30 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_29 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_28 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB8_32B_ID + Message Buffer 8 ID Register + CAN0 + 0x1C4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB13_16B_WORD2 + Message Buffer 13 WORD_16B Register + CAN0 + 0x1C8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB20_8B_WORD0 + Message Buffer 20 WORD_8B Register + CAN0 + 0x1C8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB4_64B_WORD8 + Message Buffer 4 WORD_64B Register + CAN0 + 0x1C8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_35 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_34 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_33 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_32 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB8_32B_WORD0 + Message Buffer 8 WORD_32B Register + CAN0 + 0x1C8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD020 + Message Buffer 20 WORD0 Register + CAN0 + 0x1C8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB13_16B_WORD3 + Message Buffer 13 WORD_16B Register + CAN0 + 0x1CC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB20_8B_WORD1 + Message Buffer 20 WORD_8B Register + CAN0 + 0x1CC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB4_64B_WORD9 + Message Buffer 4 WORD_64B Register + CAN0 + 0x1CC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_39 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_38 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_37 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_36 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB8_32B_WORD1 + Message Buffer 8 WORD_32B Register + CAN0 + 0x1CC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD120 + Message Buffer 20 WORD1 Register + CAN0 + 0x1CC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS21 + Message Buffer 21 CS Register + CAN0 + 0x1D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB14_16B_CS + Message Buffer 14 CS Register + CAN0 + 0x1D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB21_8B_CS + Message Buffer 21 CS Register + CAN0 + 0x1D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB4_64B_WORD10 + Message Buffer 4 WORD_64B Register + CAN0 + 0x1D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_43 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_42 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_41 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_40 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB8_32B_WORD2 + Message Buffer 8 WORD_32B Register + CAN0 + 0x1D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + ID21 + Message Buffer 21 ID Register + CAN0 + 0x1D4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB14_16B_ID + Message Buffer 14 ID Register + CAN0 + 0x1D4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB21_8B_ID + Message Buffer 21 ID Register + CAN0 + 0x1D4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB4_64B_WORD11 + Message Buffer 4 WORD_64B Register + CAN0 + 0x1D4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_47 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_46 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_45 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_44 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB8_32B_WORD3 + Message Buffer 8 WORD_32B Register + CAN0 + 0x1D4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB14_16B_WORD0 + Message Buffer 14 WORD_16B Register + CAN0 + 0x1D8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB21_8B_WORD0 + Message Buffer 21 WORD_8B Register + CAN0 + 0x1D8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB4_64B_WORD12 + Message Buffer 4 WORD_64B Register + CAN0 + 0x1D8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_51 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_50 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_49 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_48 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB8_32B_WORD4 + Message Buffer 8 WORD_32B Register + CAN0 + 0x1D8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_19 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_18 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_17 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_16 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD021 + Message Buffer 21 WORD0 Register + CAN0 + 0x1D8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB14_16B_WORD1 + Message Buffer 14 WORD_16B Register + CAN0 + 0x1DC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB21_8B_WORD1 + Message Buffer 21 WORD_8B Register + CAN0 + 0x1DC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB4_64B_WORD13 + Message Buffer 4 WORD_64B Register + CAN0 + 0x1DC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_55 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_54 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_53 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_52 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB8_32B_WORD5 + Message Buffer 8 WORD_32B Register + CAN0 + 0x1DC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_23 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_22 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_21 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_20 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD121 + Message Buffer 21 WORD1 Register + CAN0 + 0x1DC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS22 + Message Buffer 22 CS Register + CAN0 + 0x1E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB14_16B_WORD2 + Message Buffer 14 WORD_16B Register + CAN0 + 0x1E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB22_8B_CS + Message Buffer 22 CS Register + CAN0 + 0x1E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB4_64B_WORD14 + Message Buffer 4 WORD_64B Register + CAN0 + 0x1E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_59 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_58 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_57 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_56 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB8_32B_WORD6 + Message Buffer 8 WORD_32B Register + CAN0 + 0x1E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_27 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_26 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_25 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_24 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + ID22 + Message Buffer 22 ID Register + CAN0 + 0x1E4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB14_16B_WORD3 + Message Buffer 14 WORD_16B Register + CAN0 + 0x1E4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB22_8B_ID + Message Buffer 22 ID Register + CAN0 + 0x1E4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB4_64B_WORD15 + Message Buffer 4 WORD_64B Register + CAN0 + 0x1E4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_63 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_62 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_61 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_60 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB8_32B_WORD7 + Message Buffer 8 WORD_32B Register + CAN0 + 0x1E4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_31 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_30 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_29 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_28 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB15_16B_CS + Message Buffer 15 CS Register + CAN0 + 0x1E8 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB22_8B_WORD0 + Message Buffer 22 WORD_8B Register + CAN0 + 0x1E8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB5_64B_CS + Message Buffer 5 CS Register + CAN0 + 0x1E8 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB9_32B_CS + Message Buffer 9 CS Register + CAN0 + 0x1E8 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + WORD022 + Message Buffer 22 WORD0 Register + CAN0 + 0x1E8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB15_16B_ID + Message Buffer 15 ID Register + CAN0 + 0x1EC + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB22_8B_WORD1 + Message Buffer 22 WORD_8B Register + CAN0 + 0x1EC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB5_64B_ID + Message Buffer 5 ID Register + CAN0 + 0x1EC + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB9_32B_ID + Message Buffer 9 ID Register + CAN0 + 0x1EC + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD122 + Message Buffer 22 WORD1 Register + CAN0 + 0x1EC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS23 + Message Buffer 23 CS Register + CAN0 + 0x1F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB15_16B_WORD0 + Message Buffer 15 WORD_16B Register + CAN0 + 0x1F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB23_8B_CS + Message Buffer 23 CS Register + CAN0 + 0x1F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB5_64B_WORD0 + Message Buffer 5 WORD_64B Register + CAN0 + 0x1F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB9_32B_WORD0 + Message Buffer 9 WORD_32B Register + CAN0 + 0x1F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + ID23 + Message Buffer 23 ID Register + CAN0 + 0x1F4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB15_16B_WORD1 + Message Buffer 15 WORD_16B Register + CAN0 + 0x1F4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB23_8B_ID + Message Buffer 23 ID Register + CAN0 + 0x1F4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB5_64B_WORD1 + Message Buffer 5 WORD_64B Register + CAN0 + 0x1F4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB9_32B_WORD1 + Message Buffer 9 WORD_32B Register + CAN0 + 0x1F4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB15_16B_WORD2 + Message Buffer 15 WORD_16B Register + CAN0 + 0x1F8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB23_8B_WORD0 + Message Buffer 23 WORD_8B Register + CAN0 + 0x1F8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB5_64B_WORD2 + Message Buffer 5 WORD_64B Register + CAN0 + 0x1F8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB9_32B_WORD2 + Message Buffer 9 WORD_32B Register + CAN0 + 0x1F8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD023 + Message Buffer 23 WORD0 Register + CAN0 + 0x1F8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB15_16B_WORD3 + Message Buffer 15 WORD_16B Register + CAN0 + 0x1FC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB23_8B_WORD1 + Message Buffer 23 WORD_8B Register + CAN0 + 0x1FC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB5_64B_WORD3 + Message Buffer 5 WORD_64B Register + CAN0 + 0x1FC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB9_32B_WORD3 + Message Buffer 9 WORD_32B Register + CAN0 + 0x1FC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD123 + Message Buffer 23 WORD1 Register + CAN0 + 0x1FC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS24 + Message Buffer 24 CS Register + CAN0 + 0x200 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB16_16B_CS + Message Buffer 16 CS Register + CAN0 + 0x200 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB24_8B_CS + Message Buffer 24 CS Register + CAN0 + 0x200 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB5_64B_WORD4 + Message Buffer 5 WORD_64B Register + CAN0 + 0x200 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_19 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_18 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_17 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_16 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB9_32B_WORD4 + Message Buffer 9 WORD_32B Register + CAN0 + 0x200 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_19 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_18 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_17 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_16 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + ID24 + Message Buffer 24 ID Register + CAN0 + 0x204 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB16_16B_ID + Message Buffer 16 ID Register + CAN0 + 0x204 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB24_8B_ID + Message Buffer 24 ID Register + CAN0 + 0x204 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB5_64B_WORD5 + Message Buffer 5 WORD_64B Register + CAN0 + 0x204 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_23 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_22 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_21 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_20 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB9_32B_WORD5 + Message Buffer 9 WORD_32B Register + CAN0 + 0x204 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_23 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_22 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_21 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_20 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB16_16B_WORD0 + Message Buffer 16 WORD_16B Register + CAN0 + 0x208 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB24_8B_WORD0 + Message Buffer 24 WORD_8B Register + CAN0 + 0x208 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB5_64B_WORD6 + Message Buffer 5 WORD_64B Register + CAN0 + 0x208 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_27 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_26 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_25 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_24 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB9_32B_WORD6 + Message Buffer 9 WORD_32B Register + CAN0 + 0x208 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_27 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_26 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_25 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_24 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD024 + Message Buffer 24 WORD0 Register + CAN0 + 0x208 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB16_16B_WORD1 + Message Buffer 16 WORD_16B Register + CAN0 + 0x20C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB24_8B_WORD1 + Message Buffer 24 WORD_8B Register + CAN0 + 0x20C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB5_64B_WORD7 + Message Buffer 5 WORD_64B Register + CAN0 + 0x20C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_31 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_30 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_29 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_28 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB9_32B_WORD7 + Message Buffer 9 WORD_32B Register + CAN0 + 0x20C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_31 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_30 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_29 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_28 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD124 + Message Buffer 24 WORD1 Register + CAN0 + 0x20C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS25 + Message Buffer 25 CS Register + CAN0 + 0x210 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB10_32B_CS + Message Buffer 10 CS Register + CAN0 + 0x210 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB16_16B_WORD2 + Message Buffer 16 WORD_16B Register + CAN0 + 0x210 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB25_8B_CS + Message Buffer 25 CS Register + CAN0 + 0x210 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB5_64B_WORD8 + Message Buffer 5 WORD_64B Register + CAN0 + 0x210 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_35 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_34 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_33 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_32 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + ID25 + Message Buffer 25 ID Register + CAN0 + 0x214 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB10_32B_ID + Message Buffer 10 ID Register + CAN0 + 0x214 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB16_16B_WORD3 + Message Buffer 16 WORD_16B Register + CAN0 + 0x214 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB25_8B_ID + Message Buffer 25 ID Register + CAN0 + 0x214 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB5_64B_WORD9 + Message Buffer 5 WORD_64B Register + CAN0 + 0x214 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_39 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_38 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_37 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_36 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB10_32B_WORD0 + Message Buffer 10 WORD_32B Register + CAN0 + 0x218 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB17_16B_CS + Message Buffer 17 CS Register + CAN0 + 0x218 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB25_8B_WORD0 + Message Buffer 25 WORD_8B Register + CAN0 + 0x218 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB5_64B_WORD10 + Message Buffer 5 WORD_64B Register + CAN0 + 0x218 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_43 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_42 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_41 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_40 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD025 + Message Buffer 25 WORD0 Register + CAN0 + 0x218 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB10_32B_WORD1 + Message Buffer 10 WORD_32B Register + CAN0 + 0x21C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB17_16B_ID + Message Buffer 17 ID Register + CAN0 + 0x21C + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB25_8B_WORD1 + Message Buffer 25 WORD_8B Register + CAN0 + 0x21C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB5_64B_WORD11 + Message Buffer 5 WORD_64B Register + CAN0 + 0x21C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_47 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_46 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_45 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_44 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD125 + Message Buffer 25 WORD1 Register + CAN0 + 0x21C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS26 + Message Buffer 26 CS Register + CAN0 + 0x220 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB10_32B_WORD2 + Message Buffer 10 WORD_32B Register + CAN0 + 0x220 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB17_16B_WORD0 + Message Buffer 17 WORD_16B Register + CAN0 + 0x220 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB26_8B_CS + Message Buffer 26 CS Register + CAN0 + 0x220 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB5_64B_WORD12 + Message Buffer 5 WORD_64B Register + CAN0 + 0x220 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_51 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_50 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_49 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_48 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + ID26 + Message Buffer 26 ID Register + CAN0 + 0x224 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB10_32B_WORD3 + Message Buffer 10 WORD_32B Register + CAN0 + 0x224 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB17_16B_WORD1 + Message Buffer 17 WORD_16B Register + CAN0 + 0x224 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB26_8B_ID + Message Buffer 26 ID Register + CAN0 + 0x224 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB5_64B_WORD13 + Message Buffer 5 WORD_64B Register + CAN0 + 0x224 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_55 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_54 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_53 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_52 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB10_32B_WORD4 + Message Buffer 10 WORD_32B Register + CAN0 + 0x228 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_19 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_18 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_17 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_16 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB17_16B_WORD2 + Message Buffer 17 WORD_16B Register + CAN0 + 0x228 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB26_8B_WORD0 + Message Buffer 26 WORD_8B Register + CAN0 + 0x228 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB5_64B_WORD14 + Message Buffer 5 WORD_64B Register + CAN0 + 0x228 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_59 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_58 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_57 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_56 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD026 + Message Buffer 26 WORD0 Register + CAN0 + 0x228 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB10_32B_WORD5 + Message Buffer 10 WORD_32B Register + CAN0 + 0x22C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_23 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_22 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_21 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_20 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB17_16B_WORD3 + Message Buffer 17 WORD_16B Register + CAN0 + 0x22C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB26_8B_WORD1 + Message Buffer 26 WORD_8B Register + CAN0 + 0x22C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB5_64B_WORD15 + Message Buffer 5 WORD_64B Register + CAN0 + 0x22C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_63 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_62 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_61 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_60 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD126 + Message Buffer 26 WORD1 Register + CAN0 + 0x22C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS27 + Message Buffer 27 CS Register + CAN0 + 0x230 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB10_32B_WORD6 + Message Buffer 10 WORD_32B Register + CAN0 + 0x230 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_27 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_26 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_25 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_24 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB18_16B_CS + Message Buffer 18 CS Register + CAN0 + 0x230 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB27_8B_CS + Message Buffer 27 CS Register + CAN0 + 0x230 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB6_64B_CS + Message Buffer 6 CS Register + CAN0 + 0x230 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + ID27 + Message Buffer 27 ID Register + CAN0 + 0x234 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB10_32B_WORD7 + Message Buffer 10 WORD_32B Register + CAN0 + 0x234 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_31 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_30 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_29 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_28 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB18_16B_ID + Message Buffer 18 ID Register + CAN0 + 0x234 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB27_8B_ID + Message Buffer 27 ID Register + CAN0 + 0x234 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB6_64B_ID + Message Buffer 6 ID Register + CAN0 + 0x234 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB11_32B_CS + Message Buffer 11 CS Register + CAN0 + 0x238 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB18_16B_WORD0 + Message Buffer 18 WORD_16B Register + CAN0 + 0x238 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB27_8B_WORD0 + Message Buffer 27 WORD_8B Register + CAN0 + 0x238 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB6_64B_WORD0 + Message Buffer 6 WORD_64B Register + CAN0 + 0x238 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD027 + Message Buffer 27 WORD0 Register + CAN0 + 0x238 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB11_32B_ID + Message Buffer 11 ID Register + CAN0 + 0x23C + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB18_16B_WORD1 + Message Buffer 18 WORD_16B Register + CAN0 + 0x23C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB27_8B_WORD1 + Message Buffer 27 WORD_8B Register + CAN0 + 0x23C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB6_64B_WORD1 + Message Buffer 6 WORD_64B Register + CAN0 + 0x23C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD127 + Message Buffer 27 WORD1 Register + CAN0 + 0x23C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS28 + Message Buffer 28 CS Register + CAN0 + 0x240 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB11_32B_WORD0 + Message Buffer 11 WORD_32B Register + CAN0 + 0x240 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB18_16B_WORD2 + Message Buffer 18 WORD_16B Register + CAN0 + 0x240 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB28_8B_CS + Message Buffer 28 CS Register + CAN0 + 0x240 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB6_64B_WORD2 + Message Buffer 6 WORD_64B Register + CAN0 + 0x240 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + ID28 + Message Buffer 28 ID Register + CAN0 + 0x244 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB11_32B_WORD1 + Message Buffer 11 WORD_32B Register + CAN0 + 0x244 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB18_16B_WORD3 + Message Buffer 18 WORD_16B Register + CAN0 + 0x244 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB28_8B_ID + Message Buffer 28 ID Register + CAN0 + 0x244 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB6_64B_WORD3 + Message Buffer 6 WORD_64B Register + CAN0 + 0x244 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB11_32B_WORD2 + Message Buffer 11 WORD_32B Register + CAN0 + 0x248 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB19_16B_CS + Message Buffer 19 CS Register + CAN0 + 0x248 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB28_8B_WORD0 + Message Buffer 28 WORD_8B Register + CAN0 + 0x248 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB6_64B_WORD4 + Message Buffer 6 WORD_64B Register + CAN0 + 0x248 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_19 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_18 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_17 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_16 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD028 + Message Buffer 28 WORD0 Register + CAN0 + 0x248 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB11_32B_WORD3 + Message Buffer 11 WORD_32B Register + CAN0 + 0x24C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB19_16B_ID + Message Buffer 19 ID Register + CAN0 + 0x24C + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB28_8B_WORD1 + Message Buffer 28 WORD_8B Register + CAN0 + 0x24C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB6_64B_WORD5 + Message Buffer 6 WORD_64B Register + CAN0 + 0x24C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_23 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_22 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_21 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_20 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD128 + Message Buffer 28 WORD1 Register + CAN0 + 0x24C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS29 + Message Buffer 29 CS Register + CAN0 + 0x250 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB11_32B_WORD4 + Message Buffer 11 WORD_32B Register + CAN0 + 0x250 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_19 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_18 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_17 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_16 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB19_16B_WORD0 + Message Buffer 19 WORD_16B Register + CAN0 + 0x250 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB29_8B_CS + Message Buffer 29 CS Register + CAN0 + 0x250 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB6_64B_WORD6 + Message Buffer 6 WORD_64B Register + CAN0 + 0x250 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_27 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_26 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_25 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_24 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + ID29 + Message Buffer 29 ID Register + CAN0 + 0x254 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB11_32B_WORD5 + Message Buffer 11 WORD_32B Register + CAN0 + 0x254 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_23 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_22 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_21 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_20 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB19_16B_WORD1 + Message Buffer 19 WORD_16B Register + CAN0 + 0x254 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB29_8B_ID + Message Buffer 29 ID Register + CAN0 + 0x254 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB6_64B_WORD7 + Message Buffer 6 WORD_64B Register + CAN0 + 0x254 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_31 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_30 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_29 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_28 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB11_32B_WORD6 + Message Buffer 11 WORD_32B Register + CAN0 + 0x258 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_27 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_26 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_25 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_24 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB19_16B_WORD2 + Message Buffer 19 WORD_16B Register + CAN0 + 0x258 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB29_8B_WORD0 + Message Buffer 29 WORD_8B Register + CAN0 + 0x258 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB6_64B_WORD8 + Message Buffer 6 WORD_64B Register + CAN0 + 0x258 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_35 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_34 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_33 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_32 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD029 + Message Buffer 29 WORD0 Register + CAN0 + 0x258 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB11_32B_WORD7 + Message Buffer 11 WORD_32B Register + CAN0 + 0x25C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_31 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_30 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_29 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_28 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB19_16B_WORD3 + Message Buffer 19 WORD_16B Register + CAN0 + 0x25C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB29_8B_WORD1 + Message Buffer 29 WORD_8B Register + CAN0 + 0x25C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB6_64B_WORD9 + Message Buffer 6 WORD_64B Register + CAN0 + 0x25C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_39 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_38 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_37 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_36 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD129 + Message Buffer 29 WORD1 Register + CAN0 + 0x25C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS30 + Message Buffer 30 CS Register + CAN0 + 0x260 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB20_16B_CS + Message Buffer 20 CS Register + CAN0 + 0x260 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB30_8B_CS + Message Buffer 30 CS Register + CAN0 + 0x260 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB6_64B_WORD10 + Message Buffer 6 WORD_64B Register + CAN0 + 0x260 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_43 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_42 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_41 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_40 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + ID30 + Message Buffer 30 ID Register + CAN0 + 0x264 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB20_16B_ID + Message Buffer 20 ID Register + CAN0 + 0x264 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB30_8B_ID + Message Buffer 30 ID Register + CAN0 + 0x264 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB6_64B_WORD11 + Message Buffer 6 WORD_64B Register + CAN0 + 0x264 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_47 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_46 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_45 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_44 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB20_16B_WORD0 + Message Buffer 20 WORD_16B Register + CAN0 + 0x268 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB30_8B_WORD0 + Message Buffer 30 WORD_8B Register + CAN0 + 0x268 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB6_64B_WORD12 + Message Buffer 6 WORD_64B Register + CAN0 + 0x268 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_51 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_50 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_49 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_48 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD030 + Message Buffer 30 WORD0 Register + CAN0 + 0x268 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB20_16B_WORD1 + Message Buffer 20 WORD_16B Register + CAN0 + 0x26C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB30_8B_WORD1 + Message Buffer 30 WORD_8B Register + CAN0 + 0x26C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB6_64B_WORD13 + Message Buffer 6 WORD_64B Register + CAN0 + 0x26C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_55 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_54 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_53 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_52 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD130 + Message Buffer 30 WORD1 Register + CAN0 + 0x26C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS31 + Message Buffer 31 CS Register + CAN0 + 0x270 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB20_16B_WORD2 + Message Buffer 20 WORD_16B Register + CAN0 + 0x270 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB31_8B_CS + Message Buffer 31 CS Register + CAN0 + 0x270 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB6_64B_WORD14 + Message Buffer 6 WORD_64B Register + CAN0 + 0x270 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_59 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_58 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_57 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_56 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + ID31 + Message Buffer 31 ID Register + CAN0 + 0x274 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB20_16B_WORD3 + Message Buffer 20 WORD_16B Register + CAN0 + 0x274 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB31_8B_ID + Message Buffer 31 ID Register + CAN0 + 0x274 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB6_64B_WORD15 + Message Buffer 6 WORD_64B Register + CAN0 + 0x274 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_63 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_62 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_61 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_60 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB31_8B_WORD0 + Message Buffer 31 WORD_8B Register + CAN0 + 0x278 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD031 + Message Buffer 31 WORD0 Register + CAN0 + 0x278 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB31_8B_WORD1 + Message Buffer 31 WORD_8B Register + CAN0 + 0x27C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD131 + Message Buffer 31 WORD1 Register + CAN0 + 0x27C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + RXIMR0 + Rx Individual Mask registers + 0x880 + 32 + read-write + 0 + 0 + + + MI + Individual Mask Bits + 0 + 32 + read-write + + + + + RXIMR1 + Rx Individual Mask registers + 0x884 + 32 + read-write + 0 + 0 + + + MI + Individual Mask Bits + 0 + 32 + read-write + + + + + RXIMR2 + Rx Individual Mask registers + 0x888 + 32 + read-write + 0 + 0 + + + MI + Individual Mask Bits + 0 + 32 + read-write + + + + + RXIMR3 + Rx Individual Mask registers + 0x88C + 32 + read-write + 0 + 0 + + + MI + Individual Mask Bits + 0 + 32 + read-write + + + + + RXIMR4 + Rx Individual Mask registers + 0x890 + 32 + read-write + 0 + 0 + + + MI + Individual Mask Bits + 0 + 32 + read-write + + + + + RXIMR5 + Rx Individual Mask registers + 0x894 + 32 + read-write + 0 + 0 + + + MI + Individual Mask Bits + 0 + 32 + read-write + + + + + RXIMR6 + Rx Individual Mask registers + 0x898 + 32 + read-write + 0 + 0 + + + MI + Individual Mask Bits + 0 + 32 + read-write + + + + + RXIMR7 + Rx Individual Mask registers + 0x89C + 32 + read-write + 0 + 0 + + + MI + Individual Mask Bits + 0 + 32 + read-write + + + + + RXIMR8 + Rx Individual Mask registers + 0x8A0 + 32 + read-write + 0 + 0 + + + MI + Individual Mask Bits + 0 + 32 + read-write + + + + + RXIMR9 + Rx Individual Mask registers + 0x8A4 + 32 + read-write + 0 + 0 + + + MI + Individual Mask Bits + 0 + 32 + read-write + + + + + RXIMR10 + Rx Individual Mask registers + 0x8A8 + 32 + read-write + 0 + 0 + + + MI + Individual Mask Bits + 0 + 32 + read-write + + + + + RXIMR11 + Rx Individual Mask registers + 0x8AC + 32 + read-write + 0 + 0 + + + MI + Individual Mask Bits + 0 + 32 + read-write + + + + + RXIMR12 + Rx Individual Mask registers + 0x8B0 + 32 + read-write + 0 + 0 + + + MI + Individual Mask Bits + 0 + 32 + read-write + + + + + RXIMR13 + Rx Individual Mask registers + 0x8B4 + 32 + read-write + 0 + 0 + + + MI + Individual Mask Bits + 0 + 32 + read-write + + + + + RXIMR14 + Rx Individual Mask registers + 0x8B8 + 32 + read-write + 0 + 0 + + + MI + Individual Mask Bits + 0 + 32 + read-write + + + + + RXIMR15 + Rx Individual Mask registers + 0x8BC + 32 + read-write + 0 + 0 + + + MI + Individual Mask Bits + 0 + 32 + read-write + + + + + RXIMR16 + Rx Individual Mask registers + 0x8C0 + 32 + read-write + 0 + 0 + + + MI + Individual Mask Bits + 0 + 32 + read-write + + + + + RXIMR17 + Rx Individual Mask registers + 0x8C4 + 32 + read-write + 0 + 0 + + + MI + Individual Mask Bits + 0 + 32 + read-write + + + + + RXIMR18 + Rx Individual Mask registers + 0x8C8 + 32 + read-write + 0 + 0 + + + MI + Individual Mask Bits + 0 + 32 + read-write + + + + + RXIMR19 + Rx Individual Mask registers + 0x8CC + 32 + read-write + 0 + 0 + + + MI + Individual Mask Bits + 0 + 32 + read-write + + + + + RXIMR20 + Rx Individual Mask registers + 0x8D0 + 32 + read-write + 0 + 0 + + + MI + Individual Mask Bits + 0 + 32 + read-write + + + + + RXIMR21 + Rx Individual Mask registers + 0x8D4 + 32 + read-write + 0 + 0 + + + MI + Individual Mask Bits + 0 + 32 + read-write + + + + + RXIMR22 + Rx Individual Mask registers + 0x8D8 + 32 + read-write + 0 + 0 + + + MI + Individual Mask Bits + 0 + 32 + read-write + + + + + RXIMR23 + Rx Individual Mask registers + 0x8DC + 32 + read-write + 0 + 0 + + + MI + Individual Mask Bits + 0 + 32 + read-write + + + + + RXIMR24 + Rx Individual Mask registers + 0x8E0 + 32 + read-write + 0 + 0 + + + MI + Individual Mask Bits + 0 + 32 + read-write + + + + + RXIMR25 + Rx Individual Mask registers + 0x8E4 + 32 + read-write + 0 + 0 + + + MI + Individual Mask Bits + 0 + 32 + read-write + + + + + RXIMR26 + Rx Individual Mask registers + 0x8E8 + 32 + read-write + 0 + 0 + + + MI + Individual Mask Bits + 0 + 32 + read-write + + + + + RXIMR27 + Rx Individual Mask registers + 0x8EC + 32 + read-write + 0 + 0 + + + MI + Individual Mask Bits + 0 + 32 + read-write + + + + + RXIMR28 + Rx Individual Mask registers + 0x8F0 + 32 + read-write + 0 + 0 + + + MI + Individual Mask Bits + 0 + 32 + read-write + + + + + RXIMR29 + Rx Individual Mask registers + 0x8F4 + 32 + read-write + 0 + 0 + + + MI + Individual Mask Bits + 0 + 32 + read-write + + + + + RXIMR30 + Rx Individual Mask registers + 0x8F8 + 32 + read-write + 0 + 0 + + + MI + Individual Mask Bits + 0 + 32 + read-write + + + + + RXIMR31 + Rx Individual Mask registers + 0x8FC + 32 + read-write + 0 + 0 + + + MI + Individual Mask Bits + 0 + 32 + read-write + + + + + FDCTRL + CAN FD Control register + 0xC00 + 32 + read-write + 0x80000100 + 0xFFFFFFFF + + + TDCVAL + Transceiver Delay Compensation Value + 0 + 6 + read-only + + + TDCOFF + Transceiver Delay Compensation Offset + 8 + 5 + read-write + + + TDCFAIL + Transceiver Delay Compensation Fail + 14 + 1 + read-write + + + 0 + Measured loop delay is in range. + #0 + + + 1 + Measured loop delay is out of range. + #1 + + + + + TDCEN + Transceiver Delay Compensation Enable + 15 + 1 + read-write + + + 0 + TDC is disabled + #0 + + + 1 + TDC is enabled + #1 + + + + + MBDSR0 + Message Buffer Data Size for Region 0 + 16 + 2 + read-write + + + 00 + Selects 8 bytes per message buffer. + #00 + + + 01 + Selects 16 bytes per message buffer. + #01 + + + 10 + Selects 32 bytes per message buffer. + #10 + + + 11 + Selects 64 bytes per message buffer. + #11 + + + + + FDRATE + Bit Rate Switch Enable + 31 + 1 + read-write + + + 0 + Transmit a frame in nominal rate. The BRS bit in the Tx MB has no effect. + #0 + + + 1 + Transmit a frame with bit rate switching if the BRS bit in the Tx MB is recessive. + #1 + + + + + + + FDCBT + CAN FD Bit Timing register + 0xC04 + 32 + read-write + 0 + 0xFFFFFFFF + + + FPSEG2 + Fast Phase Segment 2 + 0 + 3 + read-write + + + FPSEG1 + Fast Phase Segment 1 + 5 + 3 + read-write + + + FPROPSEG + Fast Propagation Segment + 10 + 5 + read-write + + + FRJW + Fast Resync Jump Width + 16 + 3 + read-write + + + FPRESDIV + Fast Prescaler Division Factor + 20 + 10 + read-write + + + + + FDCRC + CAN FD CRC register + 0xC08 + 32 + read-only + 0 + 0xFFFFFFFF + + + FD_TXCRC + Extended Transmitted CRC value + 0 + 21 + read-only + + + FD_MBCRC + CRC Mailbox Number for FD_TXCRC + 24 + 7 + read-only + + + + + + + TRNG0 + TRNG0 + 0x40029000 + + 0 + 0xF8 + registers + + + TRNG0 + 13 + + + + MCTL + Miscellaneous Control Register + 0 + 32 + read-write + 0x12001 + 0xFFFFFFFF + + + SAMP_MODE + Sample Mode + 0 + 2 + read-write + + + 00 + use Von Neumann data into both Entropy shifter and Statistical Checker + #00 + + + 01 + use raw data into both Entropy shifter and Statistical Checker + #01 + + + 10 + use Von Neumann data into Entropy shifter. Use raw data into Statistical Checker + #10 + + + 11 + undefined/reserved. + #11 + + + + + OSC_DIV + Oscillator Divide + 2 + 2 + read-write + + + 00 + use ring oscillator with no divide + #00 + + + 01 + use ring oscillator divided-by-2 + #01 + + + 10 + use ring oscillator divided-by-4 + #10 + + + 11 + use ring oscillator divided-by-8 + #11 + + + + + UNUSED4 + This bit is unused. Always reads zero. + 4 + 1 + read-only + + + TRNG_ACC + TRNG Access Mode + 5 + 1 + read-write + + + RST_DEF + Reset Defaults + 6 + 1 + write-only + + + FOR_SCLK + Force System Clock + 7 + 1 + read-write + + + FCT_FAIL + Read only: Frequency Count Fail + 8 + 1 + read-only + + + FCT_VAL + Read only: Frequency Count Valid. Indicates that a valid frequency count may be read from FRQCNT. + 9 + 1 + read-only + + + ENT_VAL + Read only: Entropy Valid + 10 + 1 + read-only + + + TST_OUT + Read only: Test point inside ring oscillator. + 11 + 1 + read-only + + + ERR + Read: Error status + 12 + 1 + read-write + + + TSTOP_OK + TRNG_OK_TO_STOP + 13 + 1 + read-only + + + PRGM + Programming Mode Select + 16 + 1 + read-write + + + + + SCMISC + Statistical Check Miscellaneous Register + 0x4 + 32 + read-write + 0x1001F + 0xFFFFFFFF + + + LRUN_MAX + LONG RUN MAX LIMIT + 0 + 8 + read-write + + + RTY_CT + RETRY COUNT + 16 + 4 + read-write + + + + + PKRRNG + Poker Range Register + 0x8 + 32 + read-write + 0x9A3 + 0xFFFFFFFF + + + PKR_RNG + Poker Range + 0 + 16 + read-write + + + + + PKRMAX + Poker Maximum Limit Register + TRNG0 + 0xC + 32 + read-write + 0x6920 + 0xFFFFFFFF + + + PKR_MAX + Poker Maximum Limit. + 0 + 24 + read-write + + + + + PKRSQ + Poker Square Calculation Result Register + TRNG0 + 0xC + 32 + read-only + 0 + 0xFFFFFFFF + + + PKR_SQ + Poker Square Calculation Result. + 0 + 24 + read-only + + + + + SDCTL + Seed Control Register + 0x10 + 32 + read-write + 0xC8009C4 + 0xFFFFFFFF + + + SAMP_SIZE + Sample Size + 0 + 16 + read-write + + + ENT_DLY + Entropy Delay + 16 + 16 + read-write + + + + + SBLIM + Sparse Bit Limit Register + TRNG0 + 0x14 + 32 + read-write + 0x3F + 0xFFFFFFFF + + + SB_LIM + Sparse Bit Limit + 0 + 10 + read-write + + + + + TOTSAM + Total Samples Register + TRNG0 + 0x14 + 32 + read-only + 0 + 0xFFFFFFFF + + + TOT_SAM + Total Samples + 0 + 20 + read-only + + + + + FRQMIN + Frequency Count Minimum Limit Register + 0x18 + 32 + read-write + 0x640 + 0xFFFFFFFF + + + FRQ_MIN + Frequency Count Minimum Limit + 0 + 22 + read-write + + + + + FRQCNT + Frequency Count Register + TRNG0 + 0x1C + 32 + read-only + 0 + 0xFFFFFFFF + + + FRQ_CT + Frequency Count + 0 + 22 + read-only + + + + + FRQMAX + Frequency Count Maximum Limit Register + TRNG0 + 0x1C + 32 + read-write + 0x6400 + 0xFFFFFFFF + + + FRQ_MAX + Frequency Counter Maximum Limit + 0 + 22 + read-write + + + + + SCMC + Statistical Check Monobit Count Register + TRNG0 + 0x20 + 32 + read-only + 0 + 0xFFFFFFFF + + + MONO_CT + Monobit Count + 0 + 16 + read-only + + + + + SCML + Statistical Check Monobit Limit Register + TRNG0 + 0x20 + 32 + read-write + 0x10C0568 + 0xFFFFFFFF + + + MONO_MAX + Monobit Maximum Limit + 0 + 16 + read-write + + + MONO_RNG + Monobit Range + 16 + 16 + read-write + + + + + SCR1C + Statistical Check Run Length 1 Count Register + TRNG0 + 0x24 + 32 + read-only + 0 + 0xFFFFFFFF + + + R1_0_CT + Runs of Zero, Length 1 Count + 0 + 15 + read-only + + + R1_1_CT + Runs of One, Length 1 Count + 16 + 15 + read-only + + + + + SCR1L + Statistical Check Run Length 1 Limit Register + TRNG0 + 0x24 + 32 + read-write + 0xB20195 + 0xFFFFFFFF + + + RUN1_MAX + Run Length 1 Maximum Limit + 0 + 15 + read-write + + + RUN1_RNG + Run Length 1 Range + 16 + 15 + read-write + + + + + SCR2C + Statistical Check Run Length 2 Count Register + TRNG0 + 0x28 + 32 + read-only + 0 + 0xFFFFFFFF + + + R2_0_CT + Runs of Zero, Length 2 Count + 0 + 14 + read-only + + + R2_1_CT + Runs of One, Length 2 Count + 16 + 14 + read-only + + + + + SCR2L + Statistical Check Run Length 2 Limit Register + TRNG0 + 0x28 + 32 + read-write + 0x7A00DC + 0xFFFFFFFF + + + RUN2_MAX + Run Length 2 Maximum Limit + 0 + 14 + read-write + + + RUN2_RNG + Run Length 2 Range + 16 + 14 + read-write + + + + + SCR3C + Statistical Check Run Length 3 Count Register + TRNG0 + 0x2C + 32 + read-only + 0 + 0xFFFFFFFF + + + R3_0_CT + Runs of Zeroes, Length 3 Count + 0 + 13 + read-only + + + R3_1_CT + Runs of Ones, Length 3 Count + 16 + 13 + read-only + + + + + SCR3L + Statistical Check Run Length 3 Limit Register + TRNG0 + 0x2C + 32 + read-write + 0x58007D + 0xFFFFFFFF + + + RUN3_MAX + Run Length 3 Maximum Limit + 0 + 13 + read-write + + + RUN3_RNG + Run Length 3 Range + 16 + 13 + read-write + + + + + SCR4C + Statistical Check Run Length 4 Count Register + TRNG0 + 0x30 + 32 + read-only + 0 + 0xFFFFFFFF + + + R4_0_CT + Runs of Zero, Length 4 Count + 0 + 12 + read-only + + + R4_1_CT + Runs of One, Length 4 Count + 16 + 12 + read-only + + + + + SCR4L + Statistical Check Run Length 4 Limit Register + TRNG0 + 0x30 + 32 + read-write + 0x40004B + 0xFFFFFFFF + + + RUN4_MAX + Run Length 4 Maximum Limit + 0 + 12 + read-write + + + RUN4_RNG + Run Length 4 Range + 16 + 12 + read-write + + + + + SCR5C + Statistical Check Run Length 5 Count Register + TRNG0 + 0x34 + 32 + read-only + 0 + 0xFFFFFFFF + + + R5_0_CT + Runs of Zero, Length 5 Count + 0 + 11 + read-only + + + R5_1_CT + Runs of One, Length 5 Count + 16 + 11 + read-only + + + + + SCR5L + Statistical Check Run Length 5 Limit Register + TRNG0 + 0x34 + 32 + read-write + 0x2E002F + 0xFFFFFFFF + + + RUN5_MAX + Run Length 5 Maximum Limit + 0 + 11 + read-write + + + RUN5_RNG + Run Length 5 Range + 16 + 11 + read-write + + + + + SCR6PC + Statistical Check Run Length 6+ Count Register + TRNG0 + 0x38 + 32 + read-only + 0 + 0xFFFFFFFF + + + R6P_0_CT + Runs of Zero, Length 6+ Count + 0 + 11 + read-only + + + R6P_1_CT + Runs of One, Length 6+ Count + 16 + 11 + read-only + + + + + SCR6PL + Statistical Check Run Length 6+ Limit Register + TRNG0 + 0x38 + 32 + read-write + 0x2E002F + 0xFFFFFFFF + + + RUN6P_MAX + Run Length 6+ Maximum Limit + 0 + 11 + read-write + + + RUN6P_RNG + Run Length 6+ Range + 16 + 11 + read-write + + + + + STATUS + Status Register + 0x3C + 32 + read-only + 0 + 0xFFFFFFFF + + + TF1BR0 + Test Fail, 1-Bit Run, Sampling 0s. If TF1BR0=1, the 1-Bit Run, Sampling 0s Test has failed. + 0 + 1 + read-only + + + TF1BR1 + Test Fail, 1-Bit Run, Sampling 1s. If TF1BR1=1, the 1-Bit Run, Sampling 1s Test has failed. + 1 + 1 + read-only + + + TF2BR0 + Test Fail, 2-Bit Run, Sampling 0s. If TF2BR0=1, the 2-Bit Run, Sampling 0s Test has failed. + 2 + 1 + read-only + + + TF2BR1 + Test Fail, 2-Bit Run, Sampling 1s. If TF2BR1=1, the 2-Bit Run, Sampling 1s Test has failed. + 3 + 1 + read-only + + + TF3BR0 + Test Fail, 3-Bit Run, Sampling 0s. If TF3BR0=1, the 3-Bit Run, Sampling 0s Test has failed. + 4 + 1 + read-only + + + TF3BR1 + Test Fail, 3-Bit Run, Sampling 1s. If TF3BR1=1, the 3-Bit Run, Sampling 1s Test has failed. + 5 + 1 + read-only + + + TF4BR0 + Test Fail, 4-Bit Run, Sampling 0s. If TF4BR0=1, the 4-Bit Run, Sampling 0s Test has failed. + 6 + 1 + read-only + + + TF4BR1 + Test Fail, 4-Bit Run, Sampling 1s. If TF4BR1=1, the 4-Bit Run, Sampling 1s Test has failed. + 7 + 1 + read-only + + + TF5BR0 + Test Fail, 5-Bit Run, Sampling 0s. If TF5BR0=1, the 5-Bit Run, Sampling 0s Test has failed. + 8 + 1 + read-only + + + TF5BR1 + Test Fail, 5-Bit Run, Sampling 1s. If TF5BR1=1, the 5-Bit Run, Sampling 1s Test has failed. + 9 + 1 + read-only + + + TF6PBR0 + Test Fail, 6 Plus Bit Run, Sampling 0s + 10 + 1 + read-only + + + TF6PBR1 + Test Fail, 6 Plus Bit Run, Sampling 1s + 11 + 1 + read-only + + + TFSB + Test Fail, Sparse Bit. If TFSB=1, the Sparse Bit Test has failed. + 12 + 1 + read-only + + + TFLR + Test Fail, Long Run. If TFLR=1, the Long Run Test has failed. + 13 + 1 + read-only + + + TFP + Test Fail, Poker. If TFP=1, the Poker Test has failed. + 14 + 1 + read-only + + + TFMB + Test Fail, Mono Bit. If TFMB=1, the Mono Bit Test has failed. + 15 + 1 + read-only + + + RETRY_CT + RETRY COUNT + 16 + 4 + read-only + + + + + ENT0 + Entropy Read Register + 0x40 + 32 + read-only + 0 + 0xFFFFFFFF + + + ENT + Entropy Value + 0 + 32 + read-only + + + + + ENT1 + Entropy Read Register + 0x44 + 32 + read-only + 0 + 0xFFFFFFFF + + + ENT + Entropy Value + 0 + 32 + read-only + + + + + ENT2 + Entropy Read Register + 0x48 + 32 + read-only + 0 + 0xFFFFFFFF + + + ENT + Entropy Value + 0 + 32 + read-only + + + + + ENT3 + Entropy Read Register + 0x4C + 32 + read-only + 0 + 0xFFFFFFFF + + + ENT + Entropy Value + 0 + 32 + read-only + + + + + ENT4 + Entropy Read Register + 0x50 + 32 + read-only + 0 + 0xFFFFFFFF + + + ENT + Entropy Value + 0 + 32 + read-only + + + + + ENT5 + Entropy Read Register + 0x54 + 32 + read-only + 0 + 0xFFFFFFFF + + + ENT + Entropy Value + 0 + 32 + read-only + + + + + ENT6 + Entropy Read Register + 0x58 + 32 + read-only + 0 + 0xFFFFFFFF + + + ENT + Entropy Value + 0 + 32 + read-only + + + + + ENT7 + Entropy Read Register + 0x5C + 32 + read-only + 0 + 0xFFFFFFFF + + + ENT + Entropy Value + 0 + 32 + read-only + + + + + ENT8 + Entropy Read Register + 0x60 + 32 + read-only + 0 + 0xFFFFFFFF + + + ENT + Entropy Value + 0 + 32 + read-only + + + + + ENT9 + Entropy Read Register + 0x64 + 32 + read-only + 0 + 0xFFFFFFFF + + + ENT + Entropy Value + 0 + 32 + read-only + + + + + ENT10 + Entropy Read Register + 0x68 + 32 + read-only + 0 + 0xFFFFFFFF + + + ENT + Entropy Value + 0 + 32 + read-only + + + + + ENT11 + Entropy Read Register + 0x6C + 32 + read-only + 0 + 0xFFFFFFFF + + + ENT + Entropy Value + 0 + 32 + read-only + + + + + ENT12 + Entropy Read Register + 0x70 + 32 + read-only + 0 + 0xFFFFFFFF + + + ENT + Entropy Value + 0 + 32 + read-only + + + + + ENT13 + Entropy Read Register + 0x74 + 32 + read-only + 0 + 0xFFFFFFFF + + + ENT + Entropy Value + 0 + 32 + read-only + + + + + ENT14 + Entropy Read Register + 0x78 + 32 + read-only + 0 + 0xFFFFFFFF + + + ENT + Entropy Value + 0 + 32 + read-only + + + + + ENT15 + Entropy Read Register + 0x7C + 32 + read-only + 0 + 0xFFFFFFFF + + + ENT + Entropy Value + 0 + 32 + read-only + + + + + PKRCNT10 + Statistical Check Poker Count 1 and 0 Register + 0x80 + 32 + read-only + 0 + 0xFFFFFFFF + + + PKR_0_CT + Poker 0h Count + 0 + 16 + read-only + + + PKR_1_CT + Poker 1h Count + 16 + 16 + read-only + + + + + PKRCNT32 + Statistical Check Poker Count 3 and 2 Register + 0x84 + 32 + read-only + 0 + 0xFFFFFFFF + + + PKR_2_CT + Poker 2h Count + 0 + 16 + read-only + + + PKR_3_CT + Poker 3h Count + 16 + 16 + read-only + + + + + PKRCNT54 + Statistical Check Poker Count 5 and 4 Register + 0x88 + 32 + read-only + 0 + 0xFFFFFFFF + + + PKR_4_CT + Poker 4h Count + 0 + 16 + read-only + + + PKR_5_CT + Poker 5h Count + 16 + 16 + read-only + + + + + PKRCNT76 + Statistical Check Poker Count 7 and 6 Register + 0x8C + 32 + read-only + 0 + 0xFFFFFFFF + + + PKR_6_CT + Poker 6h Count + 0 + 16 + read-only + + + PKR_7_CT + Poker 7h Count + 16 + 16 + read-only + + + + + PKRCNT98 + Statistical Check Poker Count 9 and 8 Register + 0x90 + 32 + read-only + 0 + 0xFFFFFFFF + + + PKR_8_CT + Poker 8h Count + 0 + 16 + read-only + + + PKR_9_CT + Poker 9h Count + 16 + 16 + read-only + + + + + PKRCNTBA + Statistical Check Poker Count B and A Register + 0x94 + 32 + read-only + 0 + 0xFFFFFFFF + + + PKR_A_CT + Poker Ah Count + 0 + 16 + read-only + + + PKR_B_CT + Poker Bh Count + 16 + 16 + read-only + + + + + PKRCNTDC + Statistical Check Poker Count D and C Register + 0x98 + 32 + read-only + 0 + 0xFFFFFFFF + + + PKR_C_CT + Poker Ch Count + 0 + 16 + read-only + + + PKR_D_CT + Poker Dh Count + 16 + 16 + read-only + + + + + PKRCNTFE + Statistical Check Poker Count F and E Register + 0x9C + 32 + read-only + 0 + 0xFFFFFFFF + + + PKR_E_CT + Poker Eh Count + 0 + 16 + read-only + + + PKR_F_CT + Poker Fh Count + 16 + 16 + read-only + + + + + SEC_CFG + Security Configuration Register + 0xB0 + 32 + read-write + 0 + 0xFFFFFFFF + + + SH0 + Reserved. DRNG specific, not applicable to this version. + 0 + 1 + read-write + + + 0 + See DRNG version. + #0 + + + 1 + See DRNG version. + #1 + + + + + NO_PRGM + If set, the TRNG registers cannot be programmed + 1 + 1 + read-write + + + 0 + Programability of registers controlled only by the Miscellaneous Control Register's access mode bit. + #0 + + + 1 + Overides Miscellaneous Control Register access mode and prevents TRNG register programming. + #1 + + + + + SK_VAL + Reserved. DRNG-specific, not applicable to this version. + 2 + 1 + read-write + + + 0 + See DRNG version. + #0 + + + 1 + See DRNG version. + #1 + + + + + + + INT_CTRL + Interrupt Control Register + 0xB4 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + HW_ERR + Bit position that can be cleared if corresponding bit of INT_STATUS has been asserted. + 0 + 1 + read-write + + + 0 + Corresponding bit of INT_STATUS cleared. + #0 + + + 1 + Corresponding bit of INT_STATUS active. + #1 + + + + + ENT_VAL + Same behavior as bit 0 above. + 1 + 1 + read-write + + + 0 + Same behavior as bit 0 above. + #0 + + + 1 + Same behavior as bit 0 above. + #1 + + + + + FRQ_CT_FAIL + Same behavior as bit 0 above. + 2 + 1 + read-write + + + 0 + Same behavior as bit 0 above. + #0 + + + 1 + Same behavior as bit 0 above. + #1 + + + + + UNUSED + Reserved but writeable. + 3 + 29 + read-write + + + + + INT_MASK + Mask Register + 0xB8 + 32 + read-write + 0 + 0xFFFFFFFF + + + HW_ERR + Bit position that can be cleared if corresponding bit of INT_STATUS has been asserted. + 0 + 1 + read-write + + + 0 + Corresponding interrupt of INT_STATUS is masked. + #0 + + + 1 + Corresponding bit of INT_STATUS is active. + #1 + + + + + ENT_VAL + Same behavior as bit 0 above. + 1 + 1 + read-write + + + 0 + Same behavior as bit 0 above. + #0 + + + 1 + Same behavior as bit 0 above. + #1 + + + + + FRQ_CT_FAIL + Same behavior as bit 0 above. + 2 + 1 + read-write + + + 0 + Same behavior as bit 0 above. + #0 + + + 1 + Same behavior as bit 0 above. + #1 + + + + + + + INT_STATUS + Interrupt Status Register + 0xBC + 32 + read-only + 0 + 0xFFFFFFFF + + + HW_ERR + Read: Error status + 0 + 1 + read-only + + + 0 + no error + #0 + + + 1 + error detected. + #1 + + + + + ENT_VAL + Read only: Entropy Valid + 1 + 1 + read-only + + + 0 + Busy generation entropy. Any value read is invalid. + #0 + + + 1 + TRNG can be stopped and entropy is valid if read. + #1 + + + + + FRQ_CT_FAIL + Read only: Frequency Count Fail + 2 + 1 + read-only + + + 0 + No hardware nor self test frequency errors. + #0 + + + 1 + The frequency counter has detected a failure. + #1 + + + + + + + VID1 + Version ID Register (MS) + 0xF0 + 32 + read-only + 0x300100 + 0xFFFFFFFF + + + MIN_REV + Shows the IP's Minor revision of the TRNG. + 0 + 8 + read-only + + + 0 + Minor revision number for TRNG. + #0 + + + + + MAJ_REV + Shows the IP's Major revision of the TRNG. + 8 + 8 + read-only + + + 1 + Major revision number for TRNG. + #1 + + + + + IP_ID + Shows the IP ID. + 16 + 16 + read-only + + + 110000 + ID for TRNG. + #110000 + + + + + + + VID2 + Version ID Register (LS) + 0xF4 + 32 + read-only + 0 + 0xFFFFFFFF + + + CONFIG_OPT + Shows the IP's Configuaration options for the TRNG. + 0 + 8 + read-only + + + 0 + TRNG_CONFIG_OPT for TRNG. + #0 + + + + + ECO_REV + Shows the IP's ECO revision of the TRNG. + 8 + 8 + read-only + + + 0 + TRNG_ECO_REV for TRNG. + #0 + + + + + INTG_OPT + Shows the integration options for the TRNG. + 16 + 8 + read-only + + + 0 + INTG_OPT for TRNG. + #0 + + + + + ERA + Shows the compile options for the TRNG. + 24 + 8 + read-only + + + 0 + COMPILE_OPT for TRNG. + #0 + + + + + + + + + SPI0 + Serial Peripheral Interface + SPI + SPI0_ + 0x4002C000 + + 0 + 0x8C + registers + + + SPI0 + 10 + + + + MCR + Module Configuration Register + 0 + 32 + read-write + 0x4001 + 0xFFFFFFFF + + + HALT + Halt + 0 + 1 + read-write + + + 0 + Start transfers. + #0 + + + 1 + Stop transfers. + #1 + + + + + SMPL_PT + Sample Point + 8 + 2 + read-write + + + 00 + 0 protocol clock cycles between SCK edge and SIN sample + #00 + + + 01 + 1 protocol clock cycle between SCK edge and SIN sample + #01 + + + 10 + 2 protocol clock cycles between SCK edge and SIN sample + #10 + + + + + CLR_RXF + Clear RX FIFO + 10 + 1 + read-write + + + 0 + Do not clear the RX FIFO counter. + #0 + + + 1 + Clear the RX FIFO counter. + #1 + + + + + CLR_TXF + Clear TX FIFO + 11 + 1 + read-write + + + 0 + Do not clear the TX FIFO counter. + #0 + + + 1 + Clear the TX FIFO counter. + #1 + + + + + DIS_RXF + Disable Receive FIFO + 12 + 1 + read-write + + + 0 + RX FIFO is enabled. + #0 + + + 1 + RX FIFO is disabled. + #1 + + + + + DIS_TXF + Disable Transmit FIFO + 13 + 1 + read-write + + + 0 + TX FIFO is enabled. + #0 + + + 1 + TX FIFO is disabled. + #1 + + + + + MDIS + Module Disable + 14 + 1 + read-write + + + 0 + Enables the module clocks. + #0 + + + 1 + Allows external logic to disable the module clocks. + #1 + + + + + DOZE + Doze Enable + 15 + 1 + read-write + + + 0 + Doze mode has no effect on the module. + #0 + + + 1 + Doze mode disables the module. + #1 + + + + + PCSIS0 + Peripheral Chip Select x Inactive State + 16 + 1 + read-write + + + 0 + The inactive state of PCSx is low. + #0000 + + + 1 + The inactive state of PCSx is high. + #0001 + + + + + PCSIS1 + Peripheral Chip Select x Inactive State + 17 + 1 + read-write + + + 0 + The inactive state of PCSx is low. + #0000 + + + 1 + The inactive state of PCSx is high. + #0001 + + + + + PCSIS2 + Peripheral Chip Select x Inactive State + 18 + 1 + read-write + + + 0 + The inactive state of PCSx is low. + #0000 + + + 1 + The inactive state of PCSx is high. + #0001 + + + + + PCSIS3 + Peripheral Chip Select x Inactive State + 19 + 1 + read-write + + + 0 + The inactive state of PCSx is low. + #0000 + + + 1 + The inactive state of PCSx is high. + #0001 + + + + + ROOE + Receive FIFO Overflow Overwrite Enable + 24 + 1 + read-write + + + 0 + Incoming data is ignored. + #0 + + + 1 + Incoming data is shifted into the shift register. + #1 + + + + + MTFE + Modified Transfer Format Enable + 26 + 1 + read-write + + + 0 + Modified SPI transfer format disabled. + #0 + + + 1 + Modified SPI transfer format enabled. + #1 + + + + + FRZ + Freeze + 27 + 1 + read-write + + + 0 + Do not halt serial transfers in Debug mode. + #0 + + + 1 + Halt serial transfers in Debug mode. + #1 + + + + + DCONF + SPI Configuration. + 28 + 2 + read-only + + + 0 + SPI + #00 + + + + + CONT_SCKE + Continuous SCK Enable + 30 + 1 + read-write + + + 0 + Continuous SCK disabled. + #0 + + + 1 + Continuous SCK enabled. + #1 + + + + + MSTR + Master/Slave Mode Select + 31 + 1 + read-write + + + 0 + Enables Slave mode + #0 + + + 1 + Enables Master mode + #1 + + + + + + + TCR + Transfer Count Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + SPI_TCNT + SPI Transfer Counter + 16 + 16 + read-write + + + + + 2 + 0x4 + 0,1 + CTAR%s + Clock and Transfer Attributes Register (In Master Mode) + SPI0 + 0xC + 32 + read-write + 0x78000000 + 0xFFFFFFFF + + + BR + Baud Rate Scaler + 0 + 4 + read-write + + + DT + Delay After Transfer Scaler + 4 + 4 + read-write + + + ASC + After SCK Delay Scaler + 8 + 4 + read-write + + + CSSCK + PCS to SCK Delay Scaler + 12 + 4 + read-write + + + PBR + Baud Rate Prescaler + 16 + 2 + read-write + + + 00 + Baud Rate Prescaler value is 2. + #00 + + + 01 + Baud Rate Prescaler value is 3. + #01 + + + 10 + Baud Rate Prescaler value is 5. + #10 + + + 11 + Baud Rate Prescaler value is 7. + #11 + + + + + PDT + Delay after Transfer Prescaler + 18 + 2 + read-write + + + 00 + Delay after Transfer Prescaler value is 1. + #00 + + + 01 + Delay after Transfer Prescaler value is 3. + #01 + + + 10 + Delay after Transfer Prescaler value is 5. + #10 + + + 11 + Delay after Transfer Prescaler value is 7. + #11 + + + + + PASC + After SCK Delay Prescaler + 20 + 2 + read-write + + + 00 + Delay after Transfer Prescaler value is 1. + #00 + + + 01 + Delay after Transfer Prescaler value is 3. + #01 + + + 10 + Delay after Transfer Prescaler value is 5. + #10 + + + 11 + Delay after Transfer Prescaler value is 7. + #11 + + + + + PCSSCK + PCS to SCK Delay Prescaler + 22 + 2 + read-write + + + 00 + PCS to SCK Prescaler value is 1. + #00 + + + 01 + PCS to SCK Prescaler value is 3. + #01 + + + 10 + PCS to SCK Prescaler value is 5. + #10 + + + 11 + PCS to SCK Prescaler value is 7. + #11 + + + + + LSBFE + LSB First + 24 + 1 + read-write + + + 0 + Data is transferred MSB first. + #0 + + + 1 + Data is transferred LSB first. + #1 + + + + + CPHA + Clock Phase + 25 + 1 + read-write + + + 0 + Data is captured on the leading edge of SCK and changed on the following edge. + #0 + + + 1 + Data is changed on the leading edge of SCK and captured on the following edge. + #1 + + + + + CPOL + Clock Polarity + 26 + 1 + read-write + + + 0 + The inactive state value of SCK is low. + #0 + + + 1 + The inactive state value of SCK is high. + #1 + + + + + FMSZ + Frame Size + 27 + 4 + read-write + + + DBR + Double Baud Rate + 31 + 1 + read-write + + + 0 + The baud rate is computed normally with a 50/50 duty cycle. + #0 + + + 1 + The baud rate is doubled with the duty cycle depending on the Baud Rate Prescaler. + #1 + + + + + + + CTAR_SLAVE + Clock and Transfer Attributes Register (In Slave Mode) + SPI0 + 0xC + 32 + read-write + 0x78000000 + 0xFFFFFFFF + + + CPHA + Clock Phase + 25 + 1 + read-write + + + 0 + Data is captured on the leading edge of SCK and changed on the following edge. + #0 + + + 1 + Data is changed on the leading edge of SCK and captured on the following edge. + #1 + + + + + CPOL + Clock Polarity + 26 + 1 + read-write + + + 0 + The inactive state value of SCK is low. + #0 + + + 1 + The inactive state value of SCK is high. + #1 + + + + + FMSZ + Frame Size + 27 + 4 + read-write + + + + + SR + Status Register + 0x2C + 32 + read-write + 0x2000000 + 0xFFFFFFFF + + + POPNXTPTR + Pop Next Pointer + 0 + 4 + read-only + + + RXCTR + RX FIFO Counter + 4 + 4 + read-only + + + TXNXTPTR + Transmit Next Pointer + 8 + 4 + read-only + + + TXCTR + TX FIFO Counter + 12 + 4 + read-only + + + RFDF + Receive FIFO Drain Flag + 17 + 1 + read-write + + + 0 + RX FIFO is empty. + #0 + + + 1 + RX FIFO is not empty. + #1 + + + + + RFOF + Receive FIFO Overflow Flag + 19 + 1 + read-write + + + 0 + No Rx FIFO overflow. + #0 + + + 1 + Rx FIFO overflow has occurred. + #1 + + + + + TFFF + Transmit FIFO Fill Flag + 25 + 1 + read-write + + + 0 + TX FIFO is full. + #0 + + + 1 + TX FIFO is not full. + #1 + + + + + TFUF + Transmit FIFO Underflow Flag + 27 + 1 + read-write + + + 0 + No TX FIFO underflow. + #0 + + + 1 + TX FIFO underflow has occurred. + #1 + + + + + EOQF + End of Queue Flag + 28 + 1 + read-write + + + 0 + EOQ is not set in the executing command. + #0 + + + 1 + EOQ is set in the executing SPI command. + #1 + + + + + TXRXS + TX and RX Status + 30 + 1 + read-only + + + 0 + Transmit and receive operations are disabled (The module is in Stopped state). + #0 + + + 1 + Transmit and receive operations are enabled (The module is in Running state). + #1 + + + + + TCF + Transfer Complete Flag + 31 + 1 + read-write + + + 0 + Transfer not complete. + #0 + + + 1 + Transfer complete. + #1 + + + + + + + RSER + DMA/Interrupt Request Select and Enable Register + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + RFDF_DIRS + Receive FIFO Drain DMA or Interrupt Request Select + 16 + 1 + read-write + + + 0 + Interrupt request. + #0 + + + 1 + DMA request. + #1 + + + + + RFDF_RE + Receive FIFO Drain Request Enable + 17 + 1 + read-write + + + 0 + RFDF interrupt or DMA requests are disabled. + #0 + + + 1 + RFDF interrupt or DMA requests are enabled. + #1 + + + + + RFOF_RE + Receive FIFO Overflow Request Enable + 19 + 1 + read-write + + + 0 + RFOF interrupt requests are disabled. + #0 + + + 1 + RFOF interrupt requests are enabled. + #1 + + + + + TFFF_DIRS + Transmit FIFO Fill DMA or Interrupt Request Select + 24 + 1 + read-write + + + 0 + TFFF flag generates interrupt requests. + #0 + + + 1 + TFFF flag generates DMA requests. + #1 + + + + + TFFF_RE + Transmit FIFO Fill Request Enable + 25 + 1 + read-write + + + 0 + TFFF interrupts or DMA requests are disabled. + #0 + + + 1 + TFFF interrupts or DMA requests are enabled. + #1 + + + + + TFUF_RE + Transmit FIFO Underflow Request Enable + 27 + 1 + read-write + + + 0 + TFUF interrupt requests are disabled. + #0 + + + 1 + TFUF interrupt requests are enabled. + #1 + + + + + EOQF_RE + Finished Request Enable + 28 + 1 + read-write + + + 0 + EOQF interrupt requests are disabled. + #0 + + + 1 + EOQF interrupt requests are enabled. + #1 + + + + + TCF_RE + Transmission Complete Request Enable + 31 + 1 + read-write + + + 0 + TCF interrupt requests are disabled. + #0 + + + 1 + TCF interrupt requests are enabled. + #1 + + + + + + + PUSHR + PUSH TX FIFO Register In Master Mode + SPI0 + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + TXDATA + Transmit Data + 0 + 16 + read-write + + + PCS0 + Select which PCS signals are to be asserted for the transfer + 16 + 1 + read-write + + + 0 + Negate the PCS[x] signal. + #0000 + + + 1 + Assert the PCS[x] signal. + #0001 + + + + + PCS1 + Select which PCS signals are to be asserted for the transfer + 17 + 1 + read-write + + + 0 + Negate the PCS[x] signal. + #0000 + + + 1 + Assert the PCS[x] signal. + #0001 + + + + + PCS2 + Select which PCS signals are to be asserted for the transfer + 18 + 1 + read-write + + + 0 + Negate the PCS[x] signal. + #0000 + + + 1 + Assert the PCS[x] signal. + #0001 + + + + + PCS3 + Select which PCS signals are to be asserted for the transfer + 19 + 1 + read-write + + + 0 + Negate the PCS[x] signal. + #0000 + + + 1 + Assert the PCS[x] signal. + #0001 + + + + + CTCNT + Clear Transfer Counter + 26 + 1 + read-write + + + 0 + Do not clear the TCR[TCNT] field. + #0 + + + 1 + Clear the TCR[TCNT] field. + #1 + + + + + EOQ + End Of Queue + 27 + 1 + read-write + + + 0 + The SPI data is not the last data to transfer. + #0 + + + 1 + The SPI data is the last data to transfer. + #1 + + + + + CTAS + Clock and Transfer Attributes Select + 28 + 3 + read-write + + + 0 + CTAR0 + #000 + + + 1 + CTAR1 + #001 + + + + + CONT + Continuous Peripheral Chip Select Enable + 31 + 1 + read-write + + + 0 + Return PCSn signals to their inactive state between transfers. + #0 + + + 1 + Keep PCSn signals asserted between transfers. + #1 + + + + + + + PUSHR_SLAVE + PUSH TX FIFO Register In Slave Mode + SPI0 + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + TXDATA + Transmit Data + 0 + 16 + read-write + + + + + POPR + POP RX FIFO Register + 0x38 + 32 + read-only + 0 + 0xFFFFFFFF + + + RXDATA + Received Data + 0 + 32 + read-only + + + + + 4 + 0x4 + 0,1,2,3 + TXFR%s + Transmit FIFO Registers + 0x3C + 32 + read-only + 0 + 0xFFFFFFFF + + + TXDATA + Transmit Data + 0 + 16 + read-only + + + TXCMD_TXDATA + Transmit Command or Transmit Data + 16 + 16 + read-only + + + + + 4 + 0x4 + 0,1,2,3 + RXFR%s + Receive FIFO Registers + 0x7C + 32 + read-only + 0 + 0xFFFFFFFF + + + RXDATA + Receive Data + 0 + 32 + read-only + + + + + + + SPI1 + Serial Peripheral Interface + SPI + SPI1_ + 0x4002D000 + + 0 + 0x8C + registers + + + SPI1 + 29 + + + + MCR + Module Configuration Register + 0 + 32 + read-write + 0x4001 + 0xFFFFFFFF + + + HALT + Halt + 0 + 1 + read-write + + + 0 + Start transfers. + #0 + + + 1 + Stop transfers. + #1 + + + + + SMPL_PT + Sample Point + 8 + 2 + read-write + + + 00 + 0 protocol clock cycles between SCK edge and SIN sample + #00 + + + 01 + 1 protocol clock cycle between SCK edge and SIN sample + #01 + + + 10 + 2 protocol clock cycles between SCK edge and SIN sample + #10 + + + + + CLR_RXF + Clear RX FIFO + 10 + 1 + read-write + + + 0 + Do not clear the RX FIFO counter. + #0 + + + 1 + Clear the RX FIFO counter. + #1 + + + + + CLR_TXF + Clear TX FIFO + 11 + 1 + read-write + + + 0 + Do not clear the TX FIFO counter. + #0 + + + 1 + Clear the TX FIFO counter. + #1 + + + + + DIS_RXF + Disable Receive FIFO + 12 + 1 + read-write + + + 0 + RX FIFO is enabled. + #0 + + + 1 + RX FIFO is disabled. + #1 + + + + + DIS_TXF + Disable Transmit FIFO + 13 + 1 + read-write + + + 0 + TX FIFO is enabled. + #0 + + + 1 + TX FIFO is disabled. + #1 + + + + + MDIS + Module Disable + 14 + 1 + read-write + + + 0 + Enables the module clocks. + #0 + + + 1 + Allows external logic to disable the module clocks. + #1 + + + + + DOZE + Doze Enable + 15 + 1 + read-write + + + 0 + Doze mode has no effect on the module. + #0 + + + 1 + Doze mode disables the module. + #1 + + + + + PCSIS0 + Peripheral Chip Select x Inactive State + 16 + 1 + read-write + + + 0 + The inactive state of PCSx is low. + #0000 + + + 1 + The inactive state of PCSx is high. + #0001 + + + + + PCSIS1 + Peripheral Chip Select x Inactive State + 17 + 1 + read-write + + + 0 + The inactive state of PCSx is low. + #0000 + + + 1 + The inactive state of PCSx is high. + #0001 + + + + + PCSIS2 + Peripheral Chip Select x Inactive State + 18 + 1 + read-write + + + 0 + The inactive state of PCSx is low. + #0000 + + + 1 + The inactive state of PCSx is high. + #0001 + + + + + PCSIS3 + Peripheral Chip Select x Inactive State + 19 + 1 + read-write + + + 0 + The inactive state of PCSx is low. + #0000 + + + 1 + The inactive state of PCSx is high. + #0001 + + + + + ROOE + Receive FIFO Overflow Overwrite Enable + 24 + 1 + read-write + + + 0 + Incoming data is ignored. + #0 + + + 1 + Incoming data is shifted into the shift register. + #1 + + + + + MTFE + Modified Transfer Format Enable + 26 + 1 + read-write + + + 0 + Modified SPI transfer format disabled. + #0 + + + 1 + Modified SPI transfer format enabled. + #1 + + + + + FRZ + Freeze + 27 + 1 + read-write + + + 0 + Do not halt serial transfers in Debug mode. + #0 + + + 1 + Halt serial transfers in Debug mode. + #1 + + + + + DCONF + SPI Configuration. + 28 + 2 + read-only + + + 0 + SPI + #00 + + + + + CONT_SCKE + Continuous SCK Enable + 30 + 1 + read-write + + + 0 + Continuous SCK disabled. + #0 + + + 1 + Continuous SCK enabled. + #1 + + + + + MSTR + Master/Slave Mode Select + 31 + 1 + read-write + + + 0 + Enables Slave mode + #0 + + + 1 + Enables Master mode + #1 + + + + + + + TCR + Transfer Count Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + SPI_TCNT + SPI Transfer Counter + 16 + 16 + read-write + + + + + 2 + 0x4 + 0,1 + CTAR%s + Clock and Transfer Attributes Register (In Master Mode) + SPI1 + 0xC + 32 + read-write + 0x78000000 + 0xFFFFFFFF + + + BR + Baud Rate Scaler + 0 + 4 + read-write + + + DT + Delay After Transfer Scaler + 4 + 4 + read-write + + + ASC + After SCK Delay Scaler + 8 + 4 + read-write + + + CSSCK + PCS to SCK Delay Scaler + 12 + 4 + read-write + + + PBR + Baud Rate Prescaler + 16 + 2 + read-write + + + 00 + Baud Rate Prescaler value is 2. + #00 + + + 01 + Baud Rate Prescaler value is 3. + #01 + + + 10 + Baud Rate Prescaler value is 5. + #10 + + + 11 + Baud Rate Prescaler value is 7. + #11 + + + + + PDT + Delay after Transfer Prescaler + 18 + 2 + read-write + + + 00 + Delay after Transfer Prescaler value is 1. + #00 + + + 01 + Delay after Transfer Prescaler value is 3. + #01 + + + 10 + Delay after Transfer Prescaler value is 5. + #10 + + + 11 + Delay after Transfer Prescaler value is 7. + #11 + + + + + PASC + After SCK Delay Prescaler + 20 + 2 + read-write + + + 00 + Delay after Transfer Prescaler value is 1. + #00 + + + 01 + Delay after Transfer Prescaler value is 3. + #01 + + + 10 + Delay after Transfer Prescaler value is 5. + #10 + + + 11 + Delay after Transfer Prescaler value is 7. + #11 + + + + + PCSSCK + PCS to SCK Delay Prescaler + 22 + 2 + read-write + + + 00 + PCS to SCK Prescaler value is 1. + #00 + + + 01 + PCS to SCK Prescaler value is 3. + #01 + + + 10 + PCS to SCK Prescaler value is 5. + #10 + + + 11 + PCS to SCK Prescaler value is 7. + #11 + + + + + LSBFE + LSB First + 24 + 1 + read-write + + + 0 + Data is transferred MSB first. + #0 + + + 1 + Data is transferred LSB first. + #1 + + + + + CPHA + Clock Phase + 25 + 1 + read-write + + + 0 + Data is captured on the leading edge of SCK and changed on the following edge. + #0 + + + 1 + Data is changed on the leading edge of SCK and captured on the following edge. + #1 + + + + + CPOL + Clock Polarity + 26 + 1 + read-write + + + 0 + The inactive state value of SCK is low. + #0 + + + 1 + The inactive state value of SCK is high. + #1 + + + + + FMSZ + Frame Size + 27 + 4 + read-write + + + DBR + Double Baud Rate + 31 + 1 + read-write + + + 0 + The baud rate is computed normally with a 50/50 duty cycle. + #0 + + + 1 + The baud rate is doubled with the duty cycle depending on the Baud Rate Prescaler. + #1 + + + + + + + CTAR_SLAVE + Clock and Transfer Attributes Register (In Slave Mode) + SPI1 + 0xC + 32 + read-write + 0x78000000 + 0xFFFFFFFF + + + CPHA + Clock Phase + 25 + 1 + read-write + + + 0 + Data is captured on the leading edge of SCK and changed on the following edge. + #0 + + + 1 + Data is changed on the leading edge of SCK and captured on the following edge. + #1 + + + + + CPOL + Clock Polarity + 26 + 1 + read-write + + + 0 + The inactive state value of SCK is low. + #0 + + + 1 + The inactive state value of SCK is high. + #1 + + + + + FMSZ + Frame Size + 27 + 4 + read-write + + + + + SR + Status Register + 0x2C + 32 + read-write + 0x2000000 + 0xFFFFFFFF + + + POPNXTPTR + Pop Next Pointer + 0 + 4 + read-only + + + RXCTR + RX FIFO Counter + 4 + 4 + read-only + + + TXNXTPTR + Transmit Next Pointer + 8 + 4 + read-only + + + TXCTR + TX FIFO Counter + 12 + 4 + read-only + + + RFDF + Receive FIFO Drain Flag + 17 + 1 + read-write + + + 0 + RX FIFO is empty. + #0 + + + 1 + RX FIFO is not empty. + #1 + + + + + RFOF + Receive FIFO Overflow Flag + 19 + 1 + read-write + + + 0 + No Rx FIFO overflow. + #0 + + + 1 + Rx FIFO overflow has occurred. + #1 + + + + + TFFF + Transmit FIFO Fill Flag + 25 + 1 + read-write + + + 0 + TX FIFO is full. + #0 + + + 1 + TX FIFO is not full. + #1 + + + + + TFUF + Transmit FIFO Underflow Flag + 27 + 1 + read-write + + + 0 + No TX FIFO underflow. + #0 + + + 1 + TX FIFO underflow has occurred. + #1 + + + + + EOQF + End of Queue Flag + 28 + 1 + read-write + + + 0 + EOQ is not set in the executing command. + #0 + + + 1 + EOQ is set in the executing SPI command. + #1 + + + + + TXRXS + TX and RX Status + 30 + 1 + read-only + + + 0 + Transmit and receive operations are disabled (The module is in Stopped state). + #0 + + + 1 + Transmit and receive operations are enabled (The module is in Running state). + #1 + + + + + TCF + Transfer Complete Flag + 31 + 1 + read-write + + + 0 + Transfer not complete. + #0 + + + 1 + Transfer complete. + #1 + + + + + + + RSER + DMA/Interrupt Request Select and Enable Register + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + RFDF_DIRS + Receive FIFO Drain DMA or Interrupt Request Select + 16 + 1 + read-write + + + 0 + Interrupt request. + #0 + + + 1 + DMA request. + #1 + + + + + RFDF_RE + Receive FIFO Drain Request Enable + 17 + 1 + read-write + + + 0 + RFDF interrupt or DMA requests are disabled. + #0 + + + 1 + RFDF interrupt or DMA requests are enabled. + #1 + + + + + RFOF_RE + Receive FIFO Overflow Request Enable + 19 + 1 + read-write + + + 0 + RFOF interrupt requests are disabled. + #0 + + + 1 + RFOF interrupt requests are enabled. + #1 + + + + + TFFF_DIRS + Transmit FIFO Fill DMA or Interrupt Request Select + 24 + 1 + read-write + + + 0 + TFFF flag generates interrupt requests. + #0 + + + 1 + TFFF flag generates DMA requests. + #1 + + + + + TFFF_RE + Transmit FIFO Fill Request Enable + 25 + 1 + read-write + + + 0 + TFFF interrupts or DMA requests are disabled. + #0 + + + 1 + TFFF interrupts or DMA requests are enabled. + #1 + + + + + TFUF_RE + Transmit FIFO Underflow Request Enable + 27 + 1 + read-write + + + 0 + TFUF interrupt requests are disabled. + #0 + + + 1 + TFUF interrupt requests are enabled. + #1 + + + + + EOQF_RE + Finished Request Enable + 28 + 1 + read-write + + + 0 + EOQF interrupt requests are disabled. + #0 + + + 1 + EOQF interrupt requests are enabled. + #1 + + + + + TCF_RE + Transmission Complete Request Enable + 31 + 1 + read-write + + + 0 + TCF interrupt requests are disabled. + #0 + + + 1 + TCF interrupt requests are enabled. + #1 + + + + + + + PUSHR + PUSH TX FIFO Register In Master Mode + SPI1 + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + TXDATA + Transmit Data + 0 + 16 + read-write + + + PCS0 + Select which PCS signals are to be asserted for the transfer + 16 + 1 + read-write + + + 0 + Negate the PCS[x] signal. + #0000 + + + 1 + Assert the PCS[x] signal. + #0001 + + + + + PCS1 + Select which PCS signals are to be asserted for the transfer + 17 + 1 + read-write + + + 0 + Negate the PCS[x] signal. + #0000 + + + 1 + Assert the PCS[x] signal. + #0001 + + + + + PCS2 + Select which PCS signals are to be asserted for the transfer + 18 + 1 + read-write + + + 0 + Negate the PCS[x] signal. + #0000 + + + 1 + Assert the PCS[x] signal. + #0001 + + + + + PCS3 + Select which PCS signals are to be asserted for the transfer + 19 + 1 + read-write + + + 0 + Negate the PCS[x] signal. + #0000 + + + 1 + Assert the PCS[x] signal. + #0001 + + + + + CTCNT + Clear Transfer Counter + 26 + 1 + read-write + + + 0 + Do not clear the TCR[TCNT] field. + #0 + + + 1 + Clear the TCR[TCNT] field. + #1 + + + + + EOQ + End Of Queue + 27 + 1 + read-write + + + 0 + The SPI data is not the last data to transfer. + #0 + + + 1 + The SPI data is the last data to transfer. + #1 + + + + + CTAS + Clock and Transfer Attributes Select + 28 + 3 + read-write + + + 0 + CTAR0 + #000 + + + 1 + CTAR1 + #001 + + + + + CONT + Continuous Peripheral Chip Select Enable + 31 + 1 + read-write + + + 0 + Return PCSn signals to their inactive state between transfers. + #0 + + + 1 + Keep PCSn signals asserted between transfers. + #1 + + + + + + + PUSHR_SLAVE + PUSH TX FIFO Register In Slave Mode + SPI1 + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + TXDATA + Transmit Data + 0 + 16 + read-write + + + + + POPR + POP RX FIFO Register + 0x38 + 32 + read-only + 0 + 0xFFFFFFFF + + + RXDATA + Received Data + 0 + 32 + read-only + + + + + 4 + 0x4 + 0,1,2,3 + TXFR%s + Transmit FIFO Registers + 0x3C + 32 + read-only + 0 + 0xFFFFFFFF + + + TXDATA + Transmit Data + 0 + 16 + read-only + + + TXCMD_TXDATA + Transmit Command or Transmit Data + 16 + 16 + read-only + + + + + 4 + 0x4 + 0,1,2,3 + RXFR%s + Receive FIFO Registers + 0x7C + 32 + read-only + 0 + 0xFFFFFFFF + + + RXDATA + Receive Data + 0 + 32 + read-only + + + + + + + PIT + PIT + 0x40037000 + + 0 + 0x120 + registers + + + + MCR + PIT Module Control Register + 0 + 32 + read-write + 0x2 + 0xFFFFFFFF + + + FRZ + Freeze + 0 + 1 + read-write + + + 0 + Timers continue to run in Debug mode. + #0 + + + 1 + Timers are stopped in Debug mode. + #1 + + + + + MDIS + Module Disable for PIT + 1 + 1 + read-write + + + 0 + Clock for standard PIT timers is enabled. + #0 + + + 1 + Clock for standard PIT timers is disabled. + #1 + + + + + + + LTMR64H + PIT Upper Lifetime Timer Register + 0xE0 + 32 + read-only + 0 + 0xFFFFFFFF + + + LTH + Life Timer value + 0 + 32 + read-only + + + + + LTMR64L + PIT Lower Lifetime Timer Register + 0xE4 + 32 + read-only + 0 + 0xFFFFFFFF + + + LTL + Life Timer value + 0 + 32 + read-only + + + + + LDVAL0 + Timer Load Value Register + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + TSV + Timer Start Value + 0 + 32 + read-write + + + + + CVAL0 + Current Timer Value Register + 0x104 + 32 + read-only + 0 + 0xFFFFFFFF + + + TVL + Current Timer Value + 0 + 32 + read-only + + + + + TCTRL0 + Timer Control Register + 0x108 + 32 + read-write + 0 + 0xFFFFFFFF + + + TEN + Timer Enable + 0 + 1 + read-write + + + 0 + Timer n is disabled. + #0 + + + 1 + Timer n is enabled. + #1 + + + + + TIE + Timer Interrupt Enable + 1 + 1 + read-write + + + 0 + Interrupt requests from Timer n are disabled. + #0 + + + 1 + Interrupt is requested whenever TIF is set. + #1 + + + + + CHN + Chain Mode + 2 + 1 + read-write + + + 0 + Timer is not chained. + #0 + + + 1 + Timer is chained to a previous timer. For example, for channel 2, if this field is set, Timer 2 is chained to Timer 1. + #1 + + + + + + + TFLG0 + Timer Flag Register + 0x10C + 32 + read-write + 0 + 0xFFFFFFFF + + + TIF + Timer Interrupt Flag + 0 + 1 + read-write + + + 0 + Timeout has not yet occurred. + #0 + + + 1 + Timeout has occurred. + #1 + + + + + + + LDVAL1 + Timer Load Value Register + 0x110 + 32 + read-write + 0 + 0xFFFFFFFF + + + TSV + Timer Start Value + 0 + 32 + read-write + + + + + CVAL1 + Current Timer Value Register + 0x114 + 32 + read-only + 0 + 0xFFFFFFFF + + + TVL + Current Timer Value + 0 + 32 + read-only + + + + + TCTRL1 + Timer Control Register + 0x118 + 32 + read-write + 0 + 0xFFFFFFFF + + + TEN + Timer Enable + 0 + 1 + read-write + + + 0 + Timer n is disabled. + #0 + + + 1 + Timer n is enabled. + #1 + + + + + TIE + Timer Interrupt Enable + 1 + 1 + read-write + + + 0 + Interrupt requests from Timer n are disabled. + #0 + + + 1 + Interrupt is requested whenever TIF is set. + #1 + + + + + CHN + Chain Mode + 2 + 1 + read-write + + + 0 + Timer is not chained. + #0 + + + 1 + Timer is chained to a previous timer. For example, for channel 2, if this field is set, Timer 2 is chained to Timer 1. + #1 + + + + + + + TFLG1 + Timer Flag Register + 0x11C + 32 + read-write + 0 + 0xFFFFFFFF + + + TIF + Timer Interrupt Flag + 0 + 1 + read-write + + + 0 + Timeout has not yet occurred. + #0 + + + 1 + Timeout has occurred. + #1 + + + + + + + + + TPM0 + Timer/PWM Module + TPM + TPM0_ + 0x40038000 + + 0 + 0x88 + registers + + + TPM0 + 17 + + + + SC + Status and Control + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + PS + Prescale Factor Selection + 0 + 3 + read-write + + + 000 + Divide by 1 + #000 + + + 001 + Divide by 2 + #001 + + + 010 + Divide by 4 + #010 + + + 011 + Divide by 8 + #011 + + + 100 + Divide by 16 + #100 + + + 101 + Divide by 32 + #101 + + + 110 + Divide by 64 + #110 + + + 111 + Divide by 128 + #111 + + + + + CMOD + Clock Mode Selection + 3 + 2 + read-write + + + 00 + TPM counter is disabled + #00 + + + 01 + TPM counter increments on every TPM counter clock + #01 + + + 10 + TPM counter increments on rising edge of TPM_EXTCLK synchronized to the TPM counter clock + #10 + + + + + CPWMS + Center-Aligned PWM Select + 5 + 1 + read-write + + + 0 + TPM counter operates in up counting mode. + #0 + + + 1 + TPM counter operates in up-down counting mode. + #1 + + + + + TOIE + Timer Overflow Interrupt Enable + 6 + 1 + read-write + + + 0 + Disable TOF interrupts. Use software polling or DMA request. + #0 + + + 1 + Enable TOF interrupts. An interrupt is generated when TOF equals one. + #1 + + + + + TOF + Timer Overflow Flag + 7 + 1 + read-write + + + 0 + TPM counter has not overflowed. + #0 + + + 1 + TPM counter has overflowed. + #1 + + + + + DMA + DMA Enable + 8 + 1 + read-write + + + 0 + Disables DMA transfers. + #0 + + + 1 + Enables DMA transfers. + #1 + + + + + + + CNT + Counter + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + COUNT + Counter value + 0 + 16 + read-write + + + + + MOD + Modulo + 0x8 + 32 + read-write + 0xFFFF + 0xFFFFFFFF + + + MOD + Modulo value + 0 + 16 + read-write + + + + + 4 + 0x8 + 0,1,2,3 + C%sSC + Channel (n) Status and Control + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + DMA + DMA Enable + 0 + 1 + read-write + + + 0 + Disable DMA transfers. + #0 + + + 1 + Enable DMA transfers. + #1 + + + + + ELSA + Edge or Level Select + 2 + 1 + read-write + + + ELSB + Edge or Level Select + 3 + 1 + read-write + + + MSA + Channel Mode Select + 4 + 1 + read-write + + + MSB + Channel Mode Select + 5 + 1 + read-write + + + CHIE + Channel Interrupt Enable + 6 + 1 + read-write + + + 0 + Disable channel interrupts. + #0 + + + 1 + Enable channel interrupts. + #1 + + + + + CHF + Channel Flag + 7 + 1 + read-write + + + 0 + No channel event has occurred. + #0 + + + 1 + A channel event has occurred. + #1 + + + + + + + 4 + 0x8 + 0,1,2,3 + C%sV + Channel (n) Value + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + VAL + Channel Value + 0 + 16 + read-write + + + + + STATUS + Capture and Compare Status + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + CH0F + Channel 0 Flag + 0 + 1 + read-write + + + 0 + No channel event has occurred. + #0 + + + 1 + A channel event has occurred. + #1 + + + + + CH1F + Channel 1 Flag + 1 + 1 + read-write + + + 0 + No channel event has occurred. + #0 + + + 1 + A channel event has occurred. + #1 + + + + + CH2F + Channel 2 Flag + 2 + 1 + read-write + + + 0 + No channel event has occurred. + #0 + + + 1 + A channel event has occurred. + #1 + + + + + CH3F + Channel 3 Flag + 3 + 1 + read-write + + + 0 + No channel event has occurred. + #0 + + + 1 + A channel event has occurred. + #1 + + + + + TOF + Timer Overflow Flag + 8 + 1 + read-write + + + 0 + TPM counter has not overflowed. + #0 + + + 1 + TPM counter has overflowed. + #1 + + + + + + + COMBINE + Combine Channel Register + 0x64 + 32 + read-write + 0 + 0xFFFFFFFF + + + COMBINE0 + Combine Channels 0 and 1 + 0 + 1 + read-write + + + 0 + Channels 0 and 1 are independent. + #0 + + + 1 + Channels 0 and 1 are combined. + #1 + + + + + COMSWAP0 + Combine Channel 0 and 1 Swap + 1 + 1 + read-write + + + 0 + Even channel is used for input capture and 1st compare. + #0 + + + 1 + Odd channel is used for input capture and 1st compare. + #1 + + + + + COMBINE1 + Combine Channels 2 and 3 + 8 + 1 + read-write + + + 0 + Channels 2 and 3 are independent. + #0 + + + 1 + Channels 2 and 3 are combined. + #1 + + + + + COMSWAP1 + Combine Channels 2 and 3 Swap + 9 + 1 + read-write + + + 0 + Even channel is used for input capture and 1st compare. + #0 + + + 1 + Odd channel is used for input capture and 1st compare. + #1 + + + + + + + POL + Channel Polarity + 0x70 + 32 + read-write + 0 + 0xFFFFFFFF + + + POL0 + Channel 0 Polarity + 0 + 1 + read-write + + + 0 + The channel polarity is active high. + #0 + + + 1 + The channel polarity is active low. + #1 + + + + + POL1 + Channel 1 Polarity + 1 + 1 + read-write + + + 0 + The channel polarity is active high. + #0 + + + 1 + The channel polarity is active low. + #1 + + + + + POL2 + Channel 2 Polarity + 2 + 1 + read-write + + + 0 + The channel polarity is active high. + #0 + + + 1 + The channel polarity is active low. + #1 + + + + + POL3 + Channel 3 Polarity + 3 + 1 + read-write + + + 0 + The channel polarity is active high. + #0 + + + 1 + The channel polarity is active low. + #1 + + + + + + + FILTER + Filter Control + 0x78 + 32 + read-write + 0 + 0xFFFFFFFF + + + CH0FVAL + Channel 0 Filter Value + 0 + 4 + read-write + + + CH1FVAL + Channel 1 Filter Value + 4 + 4 + read-write + + + CH2FVAL + Channel 2 Filter Value + 8 + 4 + read-write + + + CH3FVAL + Channel 3 Filter Value + 12 + 4 + read-write + + + + + QDCTRL + Quadrature Decoder Control and Status + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + QUADEN + Enables the quadrature decoder mode + 0 + 1 + read-write + + + 0 + Quadrature decoder mode is disabled. + #0 + + + 1 + Quadrature decoder mode is enabled. + #1 + + + + + TOFDIR + Indicates if the TOF bit was set on the top or the bottom of counting. + 1 + 1 + read-only + + + 0 + TOF bit was set on the bottom of counting. There was an FTM counter decrement and FTM counter changes from its minimum value (zero) to its maximum value (MOD register). + #0 + + + 1 + TOF bit was set on the top of counting. There was an FTM counter increment and FTM counter changes from its maximum value (MOD register) to its minimum value (zero). + #1 + + + + + QUADIR + Counter Direction in Quadrature Decode Mode + 2 + 1 + read-only + + + 0 + Counter direction is decreasing (counter decrement). + #0 + + + 1 + Counter direction is increasing (counter increment). + #1 + + + + + QUADMODE + Quadrature Decoder Mode + 3 + 1 + read-write + + + 0 + Phase encoding mode. + #0 + + + 1 + Count and direction encoding mode. + #1 + + + + + + + CONF + Configuration + 0x84 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOZEEN + Doze Enable + 5 + 1 + read-write + + + 0 + Internal TPM counter continues in Doze mode. + #0 + + + 1 + Internal TPM counter is paused and does not increment during Doze mode. Trigger inputs and input capture events are also ignored. + #1 + + + + + DBGMODE + Debug Mode + 6 + 2 + read-write + + + 00 + TPM counter is paused and does not increment during debug mode. Trigger inputs and input capture events are also ignored. + #00 + + + 11 + TPM counter continues in debug mode. + #11 + + + + + GTBSYNC + Global Time Base Synchronization + 8 + 1 + read-write + + + 0 + Global timebase synchronization disabled. + #0 + + + 1 + Global timebase synchronization enabled. + #1 + + + + + GTBEEN + Global time base enable + 9 + 1 + read-write + + + 0 + All channels use the internally generated TPM counter as their timebase + #0 + + + 1 + All channels use an externally generated global timebase as their timebase + #1 + + + + + CSOT + Counter Start on Trigger + 16 + 1 + read-write + + + 0 + TPM counter starts to increment immediately, once it is enabled. + #0 + + + 1 + TPM counter only starts to increment when it a rising edge on the selected input trigger is detected, after it has been enabled or after it has stopped due to overflow. + #1 + + + + + CSOO + Counter Stop On Overflow + 17 + 1 + read-write + + + 0 + TPM counter continues incrementing or decrementing after overflow + #0 + + + 1 + TPM counter stops incrementing or decrementing after overflow. + #1 + + + + + CROT + Counter Reload On Trigger + 18 + 1 + read-write + + + 0 + Counter is not reloaded due to a rising edge on the selected input trigger + #0 + + + 1 + Counter is reloaded when a rising edge is detected on the selected input trigger + #1 + + + + + CPOT + Counter Pause On Trigger + 19 + 1 + read-write + + + TRGPOL + Trigger Polarity + 22 + 1 + read-write + + + 0 + Trigger is active high. + #0 + + + 1 + Trigger is active low. + #1 + + + + + TRGSRC + Trigger Source + 23 + 1 + read-write + + + 0 + Trigger source selected by TRGSEL is external. + #0 + + + 1 + Trigger source selected by TRGSEL is internal (channel pin input capture). + #1 + + + + + TRGSEL + Trigger Select + 24 + 4 + read-write + + + 0001 + Channel 0 pin input capture + #0001 + + + 0010 + Channel 1 pin input capture + #0010 + + + 0011 + Channel 0 or Channel 1 pin input capture + #0011 + + + 0100 + Channel 2 pin input capture + #0100 + + + 0101 + Channel 0 or Channel 2 pin input capture + #0101 + + + 0110 + Channel 1 or Channel 2 pin input capture + #0110 + + + 0111 + Channel 0 or Channel 1 or Channel 2 pin input capture + #0111 + + + 1000 + Channel 3 pin input capture + #1000 + + + 1001 + Channel 0 or Channel 3 pin input capture + #1001 + + + 1010 + Channel 1 or Channel 3 pin input capture + #1010 + + + 1011 + Channel 0 or Channel 1 or Channel 3 pin input capture + #1011 + + + 1100 + Channel 2 or Channel 3 pin input capture + #1100 + + + 1101 + Channel 0 or Channel 2 or Channel 3 pin input capture + #1101 + + + 1110 + Channel 1 or Channel 2 or Channel 3 pin input capture + #1110 + + + 1111 + Channel 0 or Channel 1 or Channel 2 or Channel 3 pin input capture + #1111 + + + + + + + + + TPM1 + Timer/PWM Module + TPM + TPM1_ + 0x40039000 + + 0 + 0x88 + registers + + + TPM1 + 18 + + + + SC + Status and Control + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + PS + Prescale Factor Selection + 0 + 3 + read-write + + + 000 + Divide by 1 + #000 + + + 001 + Divide by 2 + #001 + + + 010 + Divide by 4 + #010 + + + 011 + Divide by 8 + #011 + + + 100 + Divide by 16 + #100 + + + 101 + Divide by 32 + #101 + + + 110 + Divide by 64 + #110 + + + 111 + Divide by 128 + #111 + + + + + CMOD + Clock Mode Selection + 3 + 2 + read-write + + + 00 + TPM counter is disabled + #00 + + + 01 + TPM counter increments on every TPM counter clock + #01 + + + 10 + TPM counter increments on rising edge of TPM_EXTCLK synchronized to the TPM counter clock + #10 + + + + + CPWMS + Center-Aligned PWM Select + 5 + 1 + read-write + + + 0 + TPM counter operates in up counting mode. + #0 + + + 1 + TPM counter operates in up-down counting mode. + #1 + + + + + TOIE + Timer Overflow Interrupt Enable + 6 + 1 + read-write + + + 0 + Disable TOF interrupts. Use software polling or DMA request. + #0 + + + 1 + Enable TOF interrupts. An interrupt is generated when TOF equals one. + #1 + + + + + TOF + Timer Overflow Flag + 7 + 1 + read-write + + + 0 + TPM counter has not overflowed. + #0 + + + 1 + TPM counter has overflowed. + #1 + + + + + DMA + DMA Enable + 8 + 1 + read-write + + + 0 + Disables DMA transfers. + #0 + + + 1 + Enables DMA transfers. + #1 + + + + + + + CNT + Counter + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + COUNT + Counter value + 0 + 16 + read-write + + + + + MOD + Modulo + 0x8 + 32 + read-write + 0xFFFF + 0xFFFFFFFF + + + MOD + Modulo value + 0 + 16 + read-write + + + + + 2 + 0x8 + 0,1 + C%sSC + Channel (n) Status and Control + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + DMA + DMA Enable + 0 + 1 + read-write + + + 0 + Disable DMA transfers. + #0 + + + 1 + Enable DMA transfers. + #1 + + + + + ELSA + Edge or Level Select + 2 + 1 + read-write + + + ELSB + Edge or Level Select + 3 + 1 + read-write + + + MSA + Channel Mode Select + 4 + 1 + read-write + + + MSB + Channel Mode Select + 5 + 1 + read-write + + + CHIE + Channel Interrupt Enable + 6 + 1 + read-write + + + 0 + Disable channel interrupts. + #0 + + + 1 + Enable channel interrupts. + #1 + + + + + CHF + Channel Flag + 7 + 1 + read-write + + + 0 + No channel event has occurred. + #0 + + + 1 + A channel event has occurred. + #1 + + + + + + + 2 + 0x8 + 0,1 + C%sV + Channel (n) Value + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + VAL + Channel Value + 0 + 16 + read-write + + + + + STATUS + Capture and Compare Status + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + CH0F + Channel 0 Flag + 0 + 1 + read-write + + + 0 + No channel event has occurred. + #0 + + + 1 + A channel event has occurred. + #1 + + + + + CH1F + Channel 1 Flag + 1 + 1 + read-write + + + 0 + No channel event has occurred. + #0 + + + 1 + A channel event has occurred. + #1 + + + + + CH2F + Channel 2 Flag + 2 + 1 + read-write + + + 0 + No channel event has occurred. + #0 + + + 1 + A channel event has occurred. + #1 + + + + + CH3F + Channel 3 Flag + 3 + 1 + read-write + + + 0 + No channel event has occurred. + #0 + + + 1 + A channel event has occurred. + #1 + + + + + TOF + Timer Overflow Flag + 8 + 1 + read-write + + + 0 + TPM counter has not overflowed. + #0 + + + 1 + TPM counter has overflowed. + #1 + + + + + + + COMBINE + Combine Channel Register + 0x64 + 32 + read-write + 0 + 0xFFFFFFFF + + + COMBINE0 + Combine Channels 0 and 1 + 0 + 1 + read-write + + + 0 + Channels 0 and 1 are independent. + #0 + + + 1 + Channels 0 and 1 are combined. + #1 + + + + + COMSWAP0 + Combine Channel 0 and 1 Swap + 1 + 1 + read-write + + + 0 + Even channel is used for input capture and 1st compare. + #0 + + + 1 + Odd channel is used for input capture and 1st compare. + #1 + + + + + COMBINE1 + Combine Channels 2 and 3 + 8 + 1 + read-write + + + 0 + Channels 2 and 3 are independent. + #0 + + + 1 + Channels 2 and 3 are combined. + #1 + + + + + COMSWAP1 + Combine Channels 2 and 3 Swap + 9 + 1 + read-write + + + 0 + Even channel is used for input capture and 1st compare. + #0 + + + 1 + Odd channel is used for input capture and 1st compare. + #1 + + + + + + + POL + Channel Polarity + 0x70 + 32 + read-write + 0 + 0xFFFFFFFF + + + POL0 + Channel 0 Polarity + 0 + 1 + read-write + + + 0 + The channel polarity is active high. + #0 + + + 1 + The channel polarity is active low. + #1 + + + + + POL1 + Channel 1 Polarity + 1 + 1 + read-write + + + 0 + The channel polarity is active high. + #0 + + + 1 + The channel polarity is active low. + #1 + + + + + POL2 + Channel 2 Polarity + 2 + 1 + read-write + + + 0 + The channel polarity is active high. + #0 + + + 1 + The channel polarity is active low. + #1 + + + + + POL3 + Channel 3 Polarity + 3 + 1 + read-write + + + 0 + The channel polarity is active high. + #0 + + + 1 + The channel polarity is active low. + #1 + + + + + + + FILTER + Filter Control + 0x78 + 32 + read-write + 0 + 0xFFFFFFFF + + + CH0FVAL + Channel 0 Filter Value + 0 + 4 + read-write + + + CH1FVAL + Channel 1 Filter Value + 4 + 4 + read-write + + + CH2FVAL + Channel 2 Filter Value + 8 + 4 + read-write + + + CH3FVAL + Channel 3 Filter Value + 12 + 4 + read-write + + + + + QDCTRL + Quadrature Decoder Control and Status + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + QUADEN + Enables the quadrature decoder mode + 0 + 1 + read-write + + + 0 + Quadrature decoder mode is disabled. + #0 + + + 1 + Quadrature decoder mode is enabled. + #1 + + + + + TOFDIR + Indicates if the TOF bit was set on the top or the bottom of counting. + 1 + 1 + read-only + + + 0 + TOF bit was set on the bottom of counting. There was an FTM counter decrement and FTM counter changes from its minimum value (zero) to its maximum value (MOD register). + #0 + + + 1 + TOF bit was set on the top of counting. There was an FTM counter increment and FTM counter changes from its maximum value (MOD register) to its minimum value (zero). + #1 + + + + + QUADIR + Counter Direction in Quadrature Decode Mode + 2 + 1 + read-only + + + 0 + Counter direction is decreasing (counter decrement). + #0 + + + 1 + Counter direction is increasing (counter increment). + #1 + + + + + QUADMODE + Quadrature Decoder Mode + 3 + 1 + read-write + + + 0 + Phase encoding mode. + #0 + + + 1 + Count and direction encoding mode. + #1 + + + + + + + CONF + Configuration + 0x84 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOZEEN + Doze Enable + 5 + 1 + read-write + + + 0 + Internal TPM counter continues in Doze mode. + #0 + + + 1 + Internal TPM counter is paused and does not increment during Doze mode. Trigger inputs and input capture events are also ignored. + #1 + + + + + DBGMODE + Debug Mode + 6 + 2 + read-write + + + 00 + TPM counter is paused and does not increment during debug mode. Trigger inputs and input capture events are also ignored. + #00 + + + 11 + TPM counter continues in debug mode. + #11 + + + + + GTBSYNC + Global Time Base Synchronization + 8 + 1 + read-write + + + 0 + Global timebase synchronization disabled. + #0 + + + 1 + Global timebase synchronization enabled. + #1 + + + + + GTBEEN + Global time base enable + 9 + 1 + read-write + + + 0 + All channels use the internally generated TPM counter as their timebase + #0 + + + 1 + All channels use an externally generated global timebase as their timebase + #1 + + + + + CSOT + Counter Start on Trigger + 16 + 1 + read-write + + + 0 + TPM counter starts to increment immediately, once it is enabled. + #0 + + + 1 + TPM counter only starts to increment when it a rising edge on the selected input trigger is detected, after it has been enabled or after it has stopped due to overflow. + #1 + + + + + CSOO + Counter Stop On Overflow + 17 + 1 + read-write + + + 0 + TPM counter continues incrementing or decrementing after overflow + #0 + + + 1 + TPM counter stops incrementing or decrementing after overflow. + #1 + + + + + CROT + Counter Reload On Trigger + 18 + 1 + read-write + + + 0 + Counter is not reloaded due to a rising edge on the selected input trigger + #0 + + + 1 + Counter is reloaded when a rising edge is detected on the selected input trigger + #1 + + + + + CPOT + Counter Pause On Trigger + 19 + 1 + read-write + + + TRGPOL + Trigger Polarity + 22 + 1 + read-write + + + 0 + Trigger is active high. + #0 + + + 1 + Trigger is active low. + #1 + + + + + TRGSRC + Trigger Source + 23 + 1 + read-write + + + 0 + Trigger source selected by TRGSEL is external. + #0 + + + 1 + Trigger source selected by TRGSEL is internal (channel pin input capture). + #1 + + + + + TRGSEL + Trigger Select + 24 + 4 + read-write + + + 0001 + Channel 0 pin input capture + #0001 + + + 0010 + Channel 1 pin input capture + #0010 + + + 0011 + Channel 0 or Channel 1 pin input capture + #0011 + + + 0100 + Channel 2 pin input capture + #0100 + + + 0101 + Channel 0 or Channel 2 pin input capture + #0101 + + + 0110 + Channel 1 or Channel 2 pin input capture + #0110 + + + 0111 + Channel 0 or Channel 1 or Channel 2 pin input capture + #0111 + + + 1000 + Channel 3 pin input capture + #1000 + + + 1001 + Channel 0 or Channel 3 pin input capture + #1001 + + + 1010 + Channel 1 or Channel 3 pin input capture + #1010 + + + 1011 + Channel 0 or Channel 1 or Channel 3 pin input capture + #1011 + + + 1100 + Channel 2 or Channel 3 pin input capture + #1100 + + + 1101 + Channel 0 or Channel 2 or Channel 3 pin input capture + #1101 + + + 1110 + Channel 1 or Channel 2 or Channel 3 pin input capture + #1110 + + + 1111 + Channel 0 or Channel 1 or Channel 2 or Channel 3 pin input capture + #1111 + + + + + + + + + TPM2 + Timer/PWM Module + TPM + TPM2_ + 0x4003A000 + + 0 + 0x88 + registers + + + TPM2 + 19 + + + + SC + Status and Control + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + PS + Prescale Factor Selection + 0 + 3 + read-write + + + 000 + Divide by 1 + #000 + + + 001 + Divide by 2 + #001 + + + 010 + Divide by 4 + #010 + + + 011 + Divide by 8 + #011 + + + 100 + Divide by 16 + #100 + + + 101 + Divide by 32 + #101 + + + 110 + Divide by 64 + #110 + + + 111 + Divide by 128 + #111 + + + + + CMOD + Clock Mode Selection + 3 + 2 + read-write + + + 00 + TPM counter is disabled + #00 + + + 01 + TPM counter increments on every TPM counter clock + #01 + + + 10 + TPM counter increments on rising edge of TPM_EXTCLK synchronized to the TPM counter clock + #10 + + + + + CPWMS + Center-Aligned PWM Select + 5 + 1 + read-write + + + 0 + TPM counter operates in up counting mode. + #0 + + + 1 + TPM counter operates in up-down counting mode. + #1 + + + + + TOIE + Timer Overflow Interrupt Enable + 6 + 1 + read-write + + + 0 + Disable TOF interrupts. Use software polling or DMA request. + #0 + + + 1 + Enable TOF interrupts. An interrupt is generated when TOF equals one. + #1 + + + + + TOF + Timer Overflow Flag + 7 + 1 + read-write + + + 0 + TPM counter has not overflowed. + #0 + + + 1 + TPM counter has overflowed. + #1 + + + + + DMA + DMA Enable + 8 + 1 + read-write + + + 0 + Disables DMA transfers. + #0 + + + 1 + Enables DMA transfers. + #1 + + + + + + + CNT + Counter + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + COUNT + Counter value + 0 + 16 + read-write + + + + + MOD + Modulo + 0x8 + 32 + read-write + 0xFFFF + 0xFFFFFFFF + + + MOD + Modulo value + 0 + 16 + read-write + + + + + 2 + 0x8 + 0,1 + C%sSC + Channel (n) Status and Control + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + DMA + DMA Enable + 0 + 1 + read-write + + + 0 + Disable DMA transfers. + #0 + + + 1 + Enable DMA transfers. + #1 + + + + + ELSA + Edge or Level Select + 2 + 1 + read-write + + + ELSB + Edge or Level Select + 3 + 1 + read-write + + + MSA + Channel Mode Select + 4 + 1 + read-write + + + MSB + Channel Mode Select + 5 + 1 + read-write + + + CHIE + Channel Interrupt Enable + 6 + 1 + read-write + + + 0 + Disable channel interrupts. + #0 + + + 1 + Enable channel interrupts. + #1 + + + + + CHF + Channel Flag + 7 + 1 + read-write + + + 0 + No channel event has occurred. + #0 + + + 1 + A channel event has occurred. + #1 + + + + + + + 2 + 0x8 + 0,1 + C%sV + Channel (n) Value + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + VAL + Channel Value + 0 + 16 + read-write + + + + + STATUS + Capture and Compare Status + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + CH0F + Channel 0 Flag + 0 + 1 + read-write + + + 0 + No channel event has occurred. + #0 + + + 1 + A channel event has occurred. + #1 + + + + + CH1F + Channel 1 Flag + 1 + 1 + read-write + + + 0 + No channel event has occurred. + #0 + + + 1 + A channel event has occurred. + #1 + + + + + CH2F + Channel 2 Flag + 2 + 1 + read-write + + + 0 + No channel event has occurred. + #0 + + + 1 + A channel event has occurred. + #1 + + + + + CH3F + Channel 3 Flag + 3 + 1 + read-write + + + 0 + No channel event has occurred. + #0 + + + 1 + A channel event has occurred. + #1 + + + + + TOF + Timer Overflow Flag + 8 + 1 + read-write + + + 0 + TPM counter has not overflowed. + #0 + + + 1 + TPM counter has overflowed. + #1 + + + + + + + COMBINE + Combine Channel Register + 0x64 + 32 + read-write + 0 + 0xFFFFFFFF + + + COMBINE0 + Combine Channels 0 and 1 + 0 + 1 + read-write + + + 0 + Channels 0 and 1 are independent. + #0 + + + 1 + Channels 0 and 1 are combined. + #1 + + + + + COMSWAP0 + Combine Channel 0 and 1 Swap + 1 + 1 + read-write + + + 0 + Even channel is used for input capture and 1st compare. + #0 + + + 1 + Odd channel is used for input capture and 1st compare. + #1 + + + + + COMBINE1 + Combine Channels 2 and 3 + 8 + 1 + read-write + + + 0 + Channels 2 and 3 are independent. + #0 + + + 1 + Channels 2 and 3 are combined. + #1 + + + + + COMSWAP1 + Combine Channels 2 and 3 Swap + 9 + 1 + read-write + + + 0 + Even channel is used for input capture and 1st compare. + #0 + + + 1 + Odd channel is used for input capture and 1st compare. + #1 + + + + + + + POL + Channel Polarity + 0x70 + 32 + read-write + 0 + 0xFFFFFFFF + + + POL0 + Channel 0 Polarity + 0 + 1 + read-write + + + 0 + The channel polarity is active high. + #0 + + + 1 + The channel polarity is active low. + #1 + + + + + POL1 + Channel 1 Polarity + 1 + 1 + read-write + + + 0 + The channel polarity is active high. + #0 + + + 1 + The channel polarity is active low. + #1 + + + + + POL2 + Channel 2 Polarity + 2 + 1 + read-write + + + 0 + The channel polarity is active high. + #0 + + + 1 + The channel polarity is active low. + #1 + + + + + POL3 + Channel 3 Polarity + 3 + 1 + read-write + + + 0 + The channel polarity is active high. + #0 + + + 1 + The channel polarity is active low. + #1 + + + + + + + FILTER + Filter Control + 0x78 + 32 + read-write + 0 + 0xFFFFFFFF + + + CH0FVAL + Channel 0 Filter Value + 0 + 4 + read-write + + + CH1FVAL + Channel 1 Filter Value + 4 + 4 + read-write + + + CH2FVAL + Channel 2 Filter Value + 8 + 4 + read-write + + + CH3FVAL + Channel 3 Filter Value + 12 + 4 + read-write + + + + + QDCTRL + Quadrature Decoder Control and Status + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + QUADEN + Enables the quadrature decoder mode + 0 + 1 + read-write + + + 0 + Quadrature decoder mode is disabled. + #0 + + + 1 + Quadrature decoder mode is enabled. + #1 + + + + + TOFDIR + Indicates if the TOF bit was set on the top or the bottom of counting. + 1 + 1 + read-only + + + 0 + TOF bit was set on the bottom of counting. There was an FTM counter decrement and FTM counter changes from its minimum value (zero) to its maximum value (MOD register). + #0 + + + 1 + TOF bit was set on the top of counting. There was an FTM counter increment and FTM counter changes from its maximum value (MOD register) to its minimum value (zero). + #1 + + + + + QUADIR + Counter Direction in Quadrature Decode Mode + 2 + 1 + read-only + + + 0 + Counter direction is decreasing (counter decrement). + #0 + + + 1 + Counter direction is increasing (counter increment). + #1 + + + + + QUADMODE + Quadrature Decoder Mode + 3 + 1 + read-write + + + 0 + Phase encoding mode. + #0 + + + 1 + Count and direction encoding mode. + #1 + + + + + + + CONF + Configuration + 0x84 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOZEEN + Doze Enable + 5 + 1 + read-write + + + 0 + Internal TPM counter continues in Doze mode. + #0 + + + 1 + Internal TPM counter is paused and does not increment during Doze mode. Trigger inputs and input capture events are also ignored. + #1 + + + + + DBGMODE + Debug Mode + 6 + 2 + read-write + + + 00 + TPM counter is paused and does not increment during debug mode. Trigger inputs and input capture events are also ignored. + #00 + + + 11 + TPM counter continues in debug mode. + #11 + + + + + GTBSYNC + Global Time Base Synchronization + 8 + 1 + read-write + + + 0 + Global timebase synchronization disabled. + #0 + + + 1 + Global timebase synchronization enabled. + #1 + + + + + GTBEEN + Global time base enable + 9 + 1 + read-write + + + 0 + All channels use the internally generated TPM counter as their timebase + #0 + + + 1 + All channels use an externally generated global timebase as their timebase + #1 + + + + + CSOT + Counter Start on Trigger + 16 + 1 + read-write + + + 0 + TPM counter starts to increment immediately, once it is enabled. + #0 + + + 1 + TPM counter only starts to increment when it a rising edge on the selected input trigger is detected, after it has been enabled or after it has stopped due to overflow. + #1 + + + + + CSOO + Counter Stop On Overflow + 17 + 1 + read-write + + + 0 + TPM counter continues incrementing or decrementing after overflow + #0 + + + 1 + TPM counter stops incrementing or decrementing after overflow. + #1 + + + + + CROT + Counter Reload On Trigger + 18 + 1 + read-write + + + 0 + Counter is not reloaded due to a rising edge on the selected input trigger + #0 + + + 1 + Counter is reloaded when a rising edge is detected on the selected input trigger + #1 + + + + + CPOT + Counter Pause On Trigger + 19 + 1 + read-write + + + TRGPOL + Trigger Polarity + 22 + 1 + read-write + + + 0 + Trigger is active high. + #0 + + + 1 + Trigger is active low. + #1 + + + + + TRGSRC + Trigger Source + 23 + 1 + read-write + + + 0 + Trigger source selected by TRGSEL is external. + #0 + + + 1 + Trigger source selected by TRGSEL is internal (channel pin input capture). + #1 + + + + + TRGSEL + Trigger Select + 24 + 4 + read-write + + + 0001 + Channel 0 pin input capture + #0001 + + + 0010 + Channel 1 pin input capture + #0010 + + + 0011 + Channel 0 or Channel 1 pin input capture + #0011 + + + 0100 + Channel 2 pin input capture + #0100 + + + 0101 + Channel 0 or Channel 2 pin input capture + #0101 + + + 0110 + Channel 1 or Channel 2 pin input capture + #0110 + + + 0111 + Channel 0 or Channel 1 or Channel 2 pin input capture + #0111 + + + 1000 + Channel 3 pin input capture + #1000 + + + 1001 + Channel 0 or Channel 3 pin input capture + #1001 + + + 1010 + Channel 1 or Channel 3 pin input capture + #1010 + + + 1011 + Channel 0 or Channel 1 or Channel 3 pin input capture + #1011 + + + 1100 + Channel 2 or Channel 3 pin input capture + #1100 + + + 1101 + Channel 0 or Channel 2 or Channel 3 pin input capture + #1101 + + + 1110 + Channel 1 or Channel 2 or Channel 3 pin input capture + #1110 + + + 1111 + Channel 0 or Channel 1 or Channel 2 or Channel 3 pin input capture + #1111 + + + + + + + + + ADC0 + Analog-to-Digital Converter + ADC0_ + 0x4003B000 + + 0 + 0x70 + registers + + + ADC0 + 15 + + + + 2 + 0x4 + A,B + SC1%s + ADC Status and Control Registers 1 + 0 + 32 + read-write + 0x1F + 0xFFFFFFFF + + + ADCH + Input channel select + 0 + 5 + read-write + + + 00000 + When DIFF=0, DADP0 is selected as input; when DIFF=1, DAD0 is selected as input. + #00000 + + + 00001 + When DIFF=0, DADP1 is selected as input; when DIFF=1, DAD1 is selected as input. + #00001 + + + 00010 + When DIFF=0, DADP2 is selected as input; when DIFF=1, DAD2 is selected as input. + #00010 + + + 00011 + When DIFF=0, DADP3 is selected as input; when DIFF=1, DAD3 is selected as input. + #00011 + + + 00100 + When DIFF=0, AD4 is selected as input; when DIFF=1, it is reserved. + #00100 + + + 00101 + When DIFF=0, AD5 is selected as input; when DIFF=1, it is reserved. + #00101 + + + 00110 + When DIFF=0, AD6 is selected as input; when DIFF=1, it is reserved. + #00110 + + + 00111 + When DIFF=0, AD7 is selected as input; when DIFF=1, it is reserved. + #00111 + + + 01000 + When DIFF=0, AD8 is selected as input; when DIFF=1, it is reserved. + #01000 + + + 01001 + When DIFF=0, AD9 is selected as input; when DIFF=1, it is reserved. + #01001 + + + 01010 + When DIFF=0, AD10 is selected as input; when DIFF=1, it is reserved. + #01010 + + + 01011 + When DIFF=0, AD11 is selected as input; when DIFF=1, it is reserved. + #01011 + + + 01100 + When DIFF=0, AD12 is selected as input; when DIFF=1, it is reserved. + #01100 + + + 01101 + When DIFF=0, AD13 is selected as input; when DIFF=1, it is reserved. + #01101 + + + 01110 + When DIFF=0, AD14 is selected as input; when DIFF=1, it is reserved. + #01110 + + + 01111 + When DIFF=0, AD15 is selected as input; when DIFF=1, it is reserved. + #01111 + + + 10000 + When DIFF=0, AD16 is selected as input; when DIFF=1, it is reserved. + #10000 + + + 10001 + When DIFF=0, AD17 is selected as input; when DIFF=1, it is reserved. + #10001 + + + 10010 + When DIFF=0, AD18 is selected as input; when DIFF=1, it is reserved. + #10010 + + + 10011 + When DIFF=0, AD19 is selected as input; when DIFF=1, it is reserved. + #10011 + + + 10100 + When DIFF=0, AD20 is selected as input; when DIFF=1, it is reserved. + #10100 + + + 10101 + When DIFF=0, AD21 is selected as input; when DIFF=1, it is reserved. + #10101 + + + 10110 + When DIFF=0, AD22 is selected as input; when DIFF=1, it is reserved. + #10110 + + + 10111 + When DIFF=0, AD23 is selected as input; when DIFF=1, it is reserved. + #10111 + + + 11010 + When DIFF=0, Temp Sensor (single-ended) is selected as input; when DIFF=1, Temp Sensor (differential) is selected as input. + #11010 + + + 11011 + When DIFF=0, Bandgap (single-ended) is selected as input; when DIFF=1, Bandgap (differential) is selected as input. + #11011 + + + 11101 + When DIFF=0,VREFSH is selected as input; when DIFF=1, -VREFSH (differential) is selected as input. Voltage reference selected is determined by SC2[REFSEL]. + #11101 + + + 11110 + When DIFF=0,VREFSL is selected as input; when DIFF=1, it is reserved. Voltage reference selected is determined by SC2[REFSEL]. + #11110 + + + 11111 + Module is disabled. + #11111 + + + + + DIFF + Differential Mode Enable + 5 + 1 + read-write + + + 0 + Single-ended conversions and input channels are selected. + #0 + + + 1 + Differential conversions and input channels are selected. + #1 + + + + + AIEN + Interrupt Enable + 6 + 1 + read-write + + + 0 + Conversion complete interrupt is disabled. + #0 + + + 1 + Conversion complete interrupt is enabled. + #1 + + + + + COCO + Conversion Complete Flag + 7 + 1 + read-only + + + 0 + Conversion is not completed. + #0 + + + 1 + Conversion is completed. + #1 + + + + + + + CFG1 + ADC Configuration Register 1 + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADICLK + Input Clock Select + 0 + 2 + read-write + + + 00 + Bus clock + #00 + + + 01 + Bus clock divided by 2(BUSCLK/2) + #01 + + + 10 + Alternate clock (ALTCLK) + #10 + + + 11 + Asynchronous clock (ADACK) + #11 + + + + + MODE + Conversion mode selection + 2 + 2 + read-write + + + 00 + When DIFF=0:It is single-ended 8-bit conversion; when DIFF=1, it is differential 9-bit conversion with 2's complement output. + #00 + + + 01 + When DIFF=0:It is single-ended 12-bit conversion ; when DIFF=1, it is differential 13-bit conversion with 2's complement output. + #01 + + + 10 + When DIFF=0:It is single-ended 10-bit conversion. ; when DIFF=1, it is differential 11-bit conversion with 2's complement output + #10 + + + 11 + When DIFF=0:It is single-ended 16-bit conversion..; when DIFF=1, it is differential 16-bit conversion with 2's complement output + #11 + + + + + ADLSMP + Sample Time Configuration + 4 + 1 + read-write + + + 0 + Short sample time. + #0 + + + 1 + Long sample time. + #1 + + + + + ADIV + Clock Divide Select + 5 + 2 + read-write + + + 00 + The divide ratio is 1 and the clock rate is input clock. + #00 + + + 01 + The divide ratio is 2 and the clock rate is (input clock)/2. + #01 + + + 10 + The divide ratio is 4 and the clock rate is (input clock)/4. + #10 + + + 11 + The divide ratio is 8 and the clock rate is (input clock)/8. + #11 + + + + + ADLPC + Low-Power Configuration + 7 + 1 + read-write + + + 0 + Normal power configuration. + #0 + + + 1 + Low-power configuration. The power is reduced at the expense of maximum clock speed. + #1 + + + + + + + CFG2 + ADC Configuration Register 2 + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + ADLSTS + Long Sample Time Select + 0 + 2 + read-write + + + 00 + Default longest sample time; 20 extra ADCK cycles; 24 ADCK cycles total. + #00 + + + 01 + 12 extra ADCK cycles; 16 ADCK cycles total sample time. + #01 + + + 10 + 6 extra ADCK cycles; 10 ADCK cycles total sample time. + #10 + + + 11 + 2 extra ADCK cycles; 6 ADCK cycles total sample time. + #11 + + + + + ADHSC + High-Speed Configuration + 2 + 1 + read-write + + + 0 + Normal conversion sequence selected. + #0 + + + 1 + High-speed conversion sequence selected with 2 additional ADCK cycles to total conversion time. + #1 + + + + + ADACKEN + Asynchronous Clock Output Enable + 3 + 1 + read-write + + + 0 + Asynchronous clock output disabled; Asynchronous clock is enabled only if selected by ADICLK and a conversion is active. + #0 + + + 1 + Asynchronous clock and clock output is enabled regardless of the state of the ADC. + #1 + + + + + MUXSEL + ADC Mux Select + 4 + 1 + read-write + + + 0 + ADxxa channels are selected. + #0 + + + 1 + ADxxb channels are selected. + #1 + + + + + + + 2 + 0x4 + A,B + R%s + ADC Data Result Register + 0x10 + 32 + read-only + 0 + 0xFFFFFFFF + + + D + Data result + 0 + 16 + read-only + + + + + 2 + 0x4 + 1,2 + CV%s + Compare Value Registers + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + CV + Compare Value. + 0 + 16 + read-write + + + + + SC2 + Status and Control Register 2 + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + REFSEL + Voltage Reference Selection + 0 + 2 + read-write + + + 0 + Default voltage reference pin pair, that is, external pins VREFH and VREFL + #00 + + + 1 + Alternate reference pair, that is, VALTH and VALTL . This pair may be additional external pins or internal sources depending on the MCU configuration. See the chip configuration information for details specific to this MCU + #01 + + + + + DMAEN + DMA Enable + 2 + 1 + read-write + + + 0 + DMA is disabled. + #0 + + + 1 + DMA is enabled and will assert the ADC DMA request during an ADC conversion complete event noted when any of the SC1n[COCO] flags is asserted. + #1 + + + + + ACREN + Compare Function Range Enable + 3 + 1 + read-write + + + 0 + Range function disabled. Only CV1 is compared. + #0 + + + 1 + Range function enabled. Both CV1 and CV2 are compared. + #1 + + + + + ACFGT + Compare Function Greater Than Enable + 4 + 1 + read-write + + + 0 + Configures less than threshold, outside range not inclusive and inside range not inclusive; functionality based on the values placed in CV1 and CV2. + #0 + + + 1 + Configures greater than or equal to threshold, outside and inside ranges inclusive; functionality based on the values placed in CV1 and CV2. + #1 + + + + + ACFE + Compare Function Enable + 5 + 1 + read-write + + + 0 + Compare function disabled. + #0 + + + 1 + Compare function enabled. + #1 + + + + + ADTRG + Conversion Trigger Select + 6 + 1 + read-write + + + 0 + Software trigger selected. + #0 + + + 1 + Hardware trigger selected. + #1 + + + + + ADACT + Conversion Active + 7 + 1 + read-only + + + 0 + Conversion not in progress. + #0 + + + 1 + Conversion in progress. + #1 + + + + + + + SC3 + Status and Control Register 3 + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + AVGS + Hardware Average Select + 0 + 2 + read-write + + + 00 + 4 samples averaged. + #00 + + + 01 + 8 samples averaged. + #01 + + + 10 + 16 samples averaged. + #10 + + + 11 + 32 samples averaged. + #11 + + + + + AVGE + Hardware Average Enable + 2 + 1 + read-write + + + 0 + Hardware average function disabled. + #0 + + + 1 + Hardware average function enabled. + #1 + + + + + ADCO + Continuous Conversion Enable + 3 + 1 + read-write + + + 0 + One conversion or one set of conversions if the hardware average function is enabled, that is, AVGE=1, after initiating a conversion. + #0 + + + 1 + Continuous conversions or sets of conversions if the hardware average function is enabled, that is, AVGE=1, after initiating a conversion. + #1 + + + + + CALF + Calibration Failed Flag + 6 + 1 + read-write + + + 0 + Calibration completed normally. + #0 + + + 1 + Calibration failed. ADC accuracy specifications are not guaranteed. + #1 + + + + + CAL + Calibration + 7 + 1 + read-write + + + + + OFS + ADC Offset Correction Register + 0x28 + 32 + read-write + 0x4 + 0xFFFFFFFF + + + OFS + Offset Error Correction Value + 0 + 16 + read-write + + + + + PG + ADC Plus-Side Gain Register + 0x2C + 32 + read-write + 0x8200 + 0xFFFFFFFF + + + PG + Plus-Side Gain + 0 + 16 + read-write + + + + + MG + ADC Minus-Side Gain Register + 0x30 + 32 + read-write + 0x8200 + 0xFFFFFFFF + + + MG + Minus-Side Gain + 0 + 16 + read-write + + + + + CLPD + ADC Plus-Side General Calibration Value Register + 0x34 + 32 + read-write + 0xA + 0xFFFFFFFF + + + CLPD + Calibration Value + 0 + 6 + read-write + + + + + CLPS + ADC Plus-Side General Calibration Value Register + 0x38 + 32 + read-write + 0x20 + 0xFFFFFFFF + + + CLPS + Calibration Value + 0 + 6 + read-write + + + + + CLP4 + ADC Plus-Side General Calibration Value Register + 0x3C + 32 + read-write + 0x200 + 0xFFFFFFFF + + + CLP4 + Calibration Value + 0 + 10 + read-write + + + + + CLP3 + ADC Plus-Side General Calibration Value Register + 0x40 + 32 + read-write + 0x100 + 0xFFFFFFFF + + + CLP3 + Calibration Value + 0 + 9 + read-write + + + + + CLP2 + ADC Plus-Side General Calibration Value Register + 0x44 + 32 + read-write + 0x80 + 0xFFFFFFFF + + + CLP2 + Calibration Value + 0 + 8 + read-write + + + + + CLP1 + ADC Plus-Side General Calibration Value Register + 0x48 + 32 + read-write + 0x40 + 0xFFFFFFFF + + + CLP1 + Calibration Value + 0 + 7 + read-write + + + + + CLP0 + ADC Plus-Side General Calibration Value Register + 0x4C + 32 + read-write + 0x20 + 0xFFFFFFFF + + + CLP0 + Calibration Value + 0 + 6 + read-write + + + + + CLMD + ADC Minus-Side General Calibration Value Register + 0x54 + 32 + read-write + 0xA + 0xFFFFFFFF + + + CLMD + Calibration Value + 0 + 6 + read-write + + + + + CLMS + ADC Minus-Side General Calibration Value Register + 0x58 + 32 + read-write + 0x20 + 0xFFFFFFFF + + + CLMS + Calibration Value + 0 + 6 + read-write + + + + + CLM4 + ADC Minus-Side General Calibration Value Register + 0x5C + 32 + read-write + 0x200 + 0xFFFFFFFF + + + CLM4 + Calibration Value + 0 + 10 + read-write + + + + + CLM3 + ADC Minus-Side General Calibration Value Register + 0x60 + 32 + read-write + 0x100 + 0xFFFFFFFF + + + CLM3 + Calibration Value + 0 + 9 + read-write + + + + + CLM2 + ADC Minus-Side General Calibration Value Register + 0x64 + 32 + read-write + 0x80 + 0xFFFFFFFF + + + CLM2 + Calibration Value + 0 + 8 + read-write + + + + + CLM1 + ADC Minus-Side General Calibration Value Register + 0x68 + 32 + read-write + 0x40 + 0xFFFFFFFF + + + CLM1 + Calibration Value + 0 + 7 + read-write + + + + + CLM0 + ADC Minus-Side General Calibration Value Register + 0x6C + 32 + read-write + 0x20 + 0xFFFFFFFF + + + CLM0 + Calibration Value + 0 + 6 + read-write + + + + + + + RTC + Secure Real Time Clock + RTC_ + 0x4003D000 + + 0 + 0x20 + registers + + + RTC + 20 + + + RTC_Seconds + 21 + + + + TSR + RTC Time Seconds Register + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TSR + Time Seconds Register + 0 + 32 + read-write + + + + + TPR + RTC Time Prescaler Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + TPR + Time Prescaler Register + 0 + 16 + read-write + + + + + TAR + RTC Time Alarm Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + TAR + Time Alarm Register + 0 + 32 + read-write + + + + + TCR + RTC Time Compensation Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + TCR + Time Compensation Register + 0 + 8 + read-write + + + 10000000 + Time Prescaler Register overflows every 32896 clock cycles. + #10000000 + + + 11111111 + Time Prescaler Register overflows every 32769 clock cycles. + #11111111 + + + 00000000 + Time Prescaler Register overflows every 32768 clock cycles. + #0 + + + 00000001 + Time Prescaler Register overflows every 32767 clock cycles. + #1 + + + 01111111 + Time Prescaler Register overflows every 32641 clock cycles. + #1111111 + + + + + CIR + Compensation Interval Register + 8 + 8 + read-write + + + TCV + Time Compensation Value + 16 + 8 + read-only + + + CIC + Compensation Interval Counter + 24 + 8 + read-only + + + + + CR + RTC Control Register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + SWR + Software Reset + 0 + 1 + read-write + + + 0 + No effect. + #0 + + + 1 + Resets all RTC registers except for the SWR bit . The SWR bit is cleared by POR and by software explicitly clearing it. + #1 + + + + + WPE + Wakeup Pin Enable + 1 + 1 + read-write + + + 0 + Wakeup pin is disabled. + #0 + + + 1 + Wakeup pin is enabled and wakeup pin asserts if the RTC interrupt asserts or the wakeup pin is turned on. + #1 + + + + + SUP + Supervisor Access + 2 + 1 + read-write + + + 0 + Non-supervisor mode write accesses are not supported and generate a bus error. + #0 + + + 1 + Non-supervisor mode write accesses are supported. + #1 + + + + + UM + Update Mode + 3 + 1 + read-write + + + 0 + Registers cannot be written when locked. + #0 + + + 1 + Registers can be written when locked under limited conditions. + #1 + + + + + WPS + Wakeup Pin Select + 4 + 1 + read-write + + + 0 + Wakeup pin asserts (active low, open drain) if the RTC interrupt asserts or the wakeup pin is turned on. + #0 + + + 1 + Wakeup pin instead outputs the RTC 32kHz clock, provided the wakeup pin is turned on and the 32kHz clock is output to other peripherals. + #1 + + + + + OSCE + Oscillator Enable + 8 + 1 + read-write + + + 0 + 32.768 kHz oscillator is disabled. + #0 + + + 1 + 32.768 kHz oscillator is enabled. After setting this bit, wait the oscillator startup time before enabling the time counter to allow the 32.768 kHz clock time to stabilize. + #1 + + + + + SC16P + Oscillator 16pF Load Configure + 10 + 1 + read-write + + + 0 + Disable the load. + #0 + + + 1 + Enable the additional load. + #1 + + + + + SC8P + Oscillator 8pF Load Configure + 11 + 1 + read-write + + + 0 + Disable the load. + #0 + + + 1 + Enable the additional load. + #1 + + + + + SC4P + Oscillator 4pF Load Configure + 12 + 1 + read-write + + + 0 + Disable the load. + #0 + + + 1 + Enable the additional load. + #1 + + + + + SC2P + Oscillator 2pF Load Configure + 13 + 1 + read-write + + + 0 + Disable the load. + #0 + + + 1 + Enable the additional load. + #1 + + + + + + + SR + RTC Status Register + 0x14 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + TIF + Time Invalid Flag + 0 + 1 + read-only + + + 0 + Time is valid. + #0 + + + 1 + Time is invalid and time counter is read as zero. + #1 + + + + + TOF + Time Overflow Flag + 1 + 1 + read-only + + + 0 + Time overflow has not occurred. + #0 + + + 1 + Time overflow has occurred and time counter is read as zero. + #1 + + + + + TAF + Time Alarm Flag + 2 + 1 + read-only + + + 0 + Time alarm has not occurred. + #0 + + + 1 + Time alarm has occurred. + #1 + + + + + TCE + Time Counter Enable + 4 + 1 + read-write + + + 0 + Time counter is disabled. + #0 + + + 1 + Time counter is enabled. + #1 + + + + + + + LR + RTC Lock Register + 0x18 + 32 + read-write + 0xFF + 0xFFFFFFFF + + + TCL + Time Compensation Lock + 3 + 1 + read-write + + + 0 + Time Compensation Register is locked and writes are ignored. + #0 + + + 1 + Time Compensation Register is not locked and writes complete as normal. + #1 + + + + + CRL + Control Register Lock + 4 + 1 + read-write + + + 0 + Control Register is locked and writes are ignored. + #0 + + + 1 + Control Register is not locked and writes complete as normal. + #1 + + + + + SRL + Status Register Lock + 5 + 1 + read-write + + + 0 + Status Register is locked and writes are ignored. + #0 + + + 1 + Status Register is not locked and writes complete as normal. + #1 + + + + + LRL + Lock Register Lock + 6 + 1 + read-write + + + 0 + Lock Register is locked and writes are ignored. + #0 + + + 1 + Lock Register is not locked and writes complete as normal. + #1 + + + + + + + IER + RTC Interrupt Enable Register + 0x1C + 32 + read-write + 0x7 + 0xFFFFFFFF + + + TIIE + Time Invalid Interrupt Enable + 0 + 1 + read-write + + + 0 + Time invalid flag does not generate an interrupt. + #0 + + + 1 + Time invalid flag does generate an interrupt. + #1 + + + + + TOIE + Time Overflow Interrupt Enable + 1 + 1 + read-write + + + 0 + Time overflow flag does not generate an interrupt. + #0 + + + 1 + Time overflow flag does generate an interrupt. + #1 + + + + + TAIE + Time Alarm Interrupt Enable + 2 + 1 + read-write + + + 0 + Time alarm flag does not generate an interrupt. + #0 + + + 1 + Time alarm flag does generate an interrupt. + #1 + + + + + TSIE + Time Seconds Interrupt Enable + 4 + 1 + read-write + + + 0 + Seconds interrupt is disabled. + #0 + + + 1 + Seconds interrupt is enabled. + #1 + + + + + WPON + Wakeup Pin On + 7 + 1 + read-write + + + 0 + No effect. + #0 + + + 1 + If the wakeup pin is enabled, then the wakeup pin will assert. + #1 + + + + + + + + + LPTMR0 + Low Power Timer + LPTMR0_ + 0x40040000 + + 0 + 0x10 + registers + + + LPTMR0 + 28 + + + + CSR + Low Power Timer Control Status Register + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TEN + Timer Enable + 0 + 1 + read-write + + + 0 + LPTMR is disabled and internal logic is reset. + #0 + + + 1 + LPTMR is enabled. + #1 + + + + + TMS + Timer Mode Select + 1 + 1 + read-write + + + 0 + Time Counter mode. + #0 + + + 1 + Pulse Counter mode. + #1 + + + + + TFC + Timer Free-Running Counter + 2 + 1 + read-write + + + 0 + CNR is reset whenever TCF is set. + #0 + + + 1 + CNR is reset on overflow. + #1 + + + + + TPP + Timer Pin Polarity + 3 + 1 + read-write + + + 0 + Pulse Counter input source is active-high, and the CNR will increment on the rising-edge. + #0 + + + 1 + Pulse Counter input source is active-low, and the CNR will increment on the falling-edge. + #1 + + + + + TPS + Timer Pin Select + 4 + 2 + read-write + + + 00 + Pulse counter input 0 is selected. + #00 + + + 01 + Pulse counter input 1 is selected. + #01 + + + 10 + Pulse counter input 2 is selected. + #10 + + + 11 + Pulse counter input 3 is selected. + #11 + + + + + TIE + Timer Interrupt Enable + 6 + 1 + read-write + + + 0 + Timer interrupt disabled. + #0 + + + 1 + Timer interrupt enabled. + #1 + + + + + TCF + Timer Compare Flag + 7 + 1 + read-write + + + 0 + The value of CNR is not equal to CMR and increments. + #0 + + + 1 + The value of CNR is equal to CMR and increments. + #1 + + + + + + + PSR + Low Power Timer Prescale Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + PCS + Prescaler Clock Select + 0 + 2 + read-write + + + 00 + Prescaler/glitch filter clock 0 selected. + #00 + + + 01 + Prescaler/glitch filter clock 1 selected. + #01 + + + 10 + Prescaler/glitch filter clock 2 selected. + #10 + + + 11 + Prescaler/glitch filter clock 3 selected. + #11 + + + + + PBYP + Prescaler Bypass + 2 + 1 + read-write + + + 0 + Prescaler/glitch filter is enabled. + #0 + + + 1 + Prescaler/glitch filter is bypassed. + #1 + + + + + PRESCALE + Prescale Value + 3 + 4 + read-write + + + 0000 + Prescaler divides the prescaler clock by 2; glitch filter does not support this configuration. + #0000 + + + 0001 + Prescaler divides the prescaler clock by 4; glitch filter recognizes change on input pin after 2 rising clock edges. + #0001 + + + 0010 + Prescaler divides the prescaler clock by 8; glitch filter recognizes change on input pin after 4 rising clock edges. + #0010 + + + 0011 + Prescaler divides the prescaler clock by 16; glitch filter recognizes change on input pin after 8 rising clock edges. + #0011 + + + 0100 + Prescaler divides the prescaler clock by 32; glitch filter recognizes change on input pin after 16 rising clock edges. + #0100 + + + 0101 + Prescaler divides the prescaler clock by 64; glitch filter recognizes change on input pin after 32 rising clock edges. + #0101 + + + 0110 + Prescaler divides the prescaler clock by 128; glitch filter recognizes change on input pin after 64 rising clock edges. + #0110 + + + 0111 + Prescaler divides the prescaler clock by 256; glitch filter recognizes change on input pin after 128 rising clock edges. + #0111 + + + 1000 + Prescaler divides the prescaler clock by 512; glitch filter recognizes change on input pin after 256 rising clock edges. + #1000 + + + 1001 + Prescaler divides the prescaler clock by 1024; glitch filter recognizes change on input pin after 512 rising clock edges. + #1001 + + + 1010 + Prescaler divides the prescaler clock by 2048; glitch filter recognizes change on input pin after 1024 rising clock edges. + #1010 + + + 1011 + Prescaler divides the prescaler clock by 4096; glitch filter recognizes change on input pin after 2048 rising clock edges. + #1011 + + + 1100 + Prescaler divides the prescaler clock by 8192; glitch filter recognizes change on input pin after 4096 rising clock edges. + #1100 + + + 1101 + Prescaler divides the prescaler clock by 16,384; glitch filter recognizes change on input pin after 8192 rising clock edges. + #1101 + + + 1110 + Prescaler divides the prescaler clock by 32,768; glitch filter recognizes change on input pin after 16,384 rising clock edges. + #1110 + + + 1111 + Prescaler divides the prescaler clock by 65,536; glitch filter recognizes change on input pin after 32,768 rising clock edges. + #1111 + + + + + + + CMR + Low Power Timer Compare Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + COMPARE + Compare Value + 0 + 16 + read-write + + + + + CNR + Low Power Timer Counter Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + COUNTER + Counter Value + 0 + 16 + read-write + + + + + + + RFSYS + System register file + RFSYS_ + 0x40041000 + + 0 + 0x20 + registers + + + + 8 + 0x4 + 0,1,2,3,4,5,6,7 + REG%s + Register file register + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + LL + Low lower byte + 0 + 8 + read-write + + + LH + Low higher byte + 8 + 8 + read-write + + + HL + High lower byte + 16 + 8 + read-write + + + HH + High higher byte + 24 + 8 + read-write + + + + + + + SIM + System Integration Module + SIM_ + 0x40047000 + + 0 + 0x1108 + registers + + + + SOPT1 + System Options Register 1 + 0 + 32 + read-write + 0x9000 + 0xFFFFFFFF + + + OSC32KOUT + 32K oscillator clock output + 16 + 2 + read-write + + + 0 + ERCLK32K is not output. + #00 + + + 1 + ERCLK32K is output on PTB3. + #01 + + + + + OSC32KSEL + 32K Oscillator Clock Select + 18 + 2 + read-write + + + 00 + 32kHz oscillator (OSC32KCLK) + #00 + + + 10 + RTC_CLKIN + #10 + + + 11 + LPO 1kHz + #11 + + + + + SIM_MISCTL + This bit controls the function of BLE_RF_ACTIVE. + 20 + 1 + read-write + + + 0 + Chip low power mode output to PAD + #0 + + + 1 + Bluetooth LE active output to PAD + #1 + + + + + + + SOPT2 + System Options Register 2 + 0x1004 + 32 + read-write + 0 + 0xFFFFFFFF + + + CLKOUTSEL + CLKOUT select + 5 + 3 + read-write + + + 000 + OSCERCLK DIV2 + #000 + + + 001 + OSCERCLK DIV4 + #001 + + + 010 + Bus clock + #010 + + + 011 + LPO clock 1 kHz + #011 + + + 100 + MCGIRCLK + #100 + + + 101 + OSCERCLK DIV8 + #101 + + + 110 + OSCERCLK + #110 + + + + + TPMSRC + TPM Clock Source Select + 23 + 3 + read-write + + + 000 + Clock disabled + #000 + + + 001 + MCGFLLCLK clock + #001 + + + 010 + OSCERCLK clock + #010 + + + 011 + MCGIRCLK clock + #011 + + + 100 + LANT_SW + #100 + + + + + LPUART0SRC + LPUART0 Clock Source Select + 26 + 2 + read-write + + + 00 + Clock disabled + #00 + + + 01 + MCGFLLCLK clock + #01 + + + 10 + OSCERCLK clock + #10 + + + 11 + MCGIRCLK clock + #11 + + + + + LPUART1SRC + LPUART1 Clock Source Select + 28 + 2 + read-write + + + 00 + Clock disabled + #00 + + + 01 + MCGFLLCLK clock + #01 + + + 10 + OSCERCLK clock + #10 + + + 11 + MCGIRCLK clock + #11 + + + + + + + SOPT4 + System Options Register 4 + 0x100C + 32 + read-write + 0 + 0xFFFFFFFF + + + TPMOFSYN + TPMOFSYN + 1 + 1 + read-write + + + 0 + Enable TPM1 overflow output to TPM0 and TPM2 overflow in. + #0 + + + 1 + Disable TPM1 overflow output to TPM0 and TPM2 overflow in. + #1 + + + + + TPM1CH0SRC + TPM1 Channel 0 Input Capture Source Select + 18 + 1 + read-write + + + 0 + TPM1_CH0 signal + #0 + + + 1 + CMP0 output + #1 + + + + + TPM2CH0SRC + TPM2 Channel 0 Input Capture Source Select + 20 + 2 + read-write + + + 00 + TPM2_CH0 signal + #00 + + + 01 + CMP0 output + #01 + + + 10 + Radio time-of-flight timestamp trigger + #10 + + + + + TPM0CLKSEL + TPM0 External Clock Pin Select + 24 + 1 + read-write + + + 0 + TPM0 external clock driven by TPM_CLKIN0 pin. + #0 + + + 1 + TPM0 external clock driven by TPM_CLKIN1 pin. + #1 + + + + + TPM1CLKSEL + TPM1 External Clock Pin Select + 25 + 1 + read-write + + + 0 + TPM1 external clock driven by TPM_CLKIN0 pin. + #0 + + + 1 + TPM1 external clock driven by TPM_CLKIN1 pin. + #1 + + + + + TPM2CLKSEL + TPM2 External Clock Pin Select + 26 + 1 + read-write + + + 0 + TPM2 external clock driven by TPM_CLKIN0 pin. + #0 + + + 1 + TPM2 external clock driven by TPM_CLKIN1 pin. + #1 + + + + + + + SOPT5 + System Options Register 5 + 0x1010 + 32 + read-write + 0 + 0xFFFFFFFF + + + LPUART0TXSRC + LPUART0 Transmit Data Source Select + 0 + 2 + read-write + + + 00 + LPUART0_TX pin + #00 + + + 01 + LPUART0_TX pin modulated with TPM1 channel 0 output + #01 + + + 10 + LPUART0_TX pin modulated with TPM2 channel 0 output + #10 + + + + + LPUART0RXSRC + LPUART0 Receive Data Source Select + 2 + 1 + read-write + + + 0 + LPUART_RX pin + #0 + + + 1 + CMP0 output + #1 + + + + + LPUART1TXSRC + LPUART1 Transmit Data Source Select + 4 + 2 + read-write + + + 00 + LPUART1_TX pin + #00 + + + 01 + LPUART1_TX pin modulated with TPM1 channel 0 output + #01 + + + 10 + LPUART1_TX pin modulated with TPM2 channel 0 output + #10 + + + + + LPUART1RXSRC + LPUART1 Receive Data Source Select + 6 + 1 + read-write + + + 0 + LPUART1_RX pin + #0 + + + 1 + CMP0 output + #1 + + + + + LPUART0ODE + LPUART0 Open Drain Enable + 16 + 1 + read-write + + + 0 + Open drain is disabled on LPUART0. + #0 + + + 1 + Open drain is enabled on LPUART0. + #1 + + + + + LPUART1ODE + LPUART1 Open Drain Enable + 17 + 1 + read-write + + + 0 + Open drain is disabled on LPUART1. + #0 + + + 1 + Open drain is enabled on LPUART1 + #1 + + + + + + + SOPT7 + System Options Register 7 + 0x1018 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADC0TRGSEL + ADC0 Trigger Select + 0 + 4 + read-write + + + 0000 + External trigger pin input (EXTRG_IN) + #0000 + + + 0001 + CMP0 output + #0001 + + + 0100 + PIT trigger 0 + #0100 + + + 0101 + PIT trigger 1 + #0101 + + + 1000 + TPM0 overflow + #1000 + + + 1001 + TPM1 overflow + #1001 + + + 1010 + TPM2 overflow + #1010 + + + 1100 + RTC alarm interrupt and RTC seconds interrupt + #1100 + + + 1101 + RTC seconds + #1101 + + + 1110 + LPTMR0 trigger + #1110 + + + 1111 + Radio TSM + #1111 + + + + + ADC0PRETRGSEL + ADC0 Pretrigger Select + 4 + 1 + read-write + + + 0 + Pre-trigger ADHDWTSA is selected, thus ADC0 will use ADC0_SC1A configuration for the next ADC conversion and store the result in ADC0_RA register. + #0 + + + 1 + Pre-trigger ADHDWTSB is selected, thus ADC0 will use ADC0_SC1B configuration for the next ADC conversion and store the result in ADC0_RB register. + #1 + + + + + ADC0ALTTRGEN + ADC0 Alternate Trigger Enable + 7 + 1 + read-write + + + 0 + ADC ADHWT trigger comes from TPM1 channel 0 and channel1. Prior to the assertion of TPM1 channel 0, a pre-trigger pulse will be sent to ADHWTSA to initiate an ADC acquisition using ADCx_SC1A configuration and store ADC conversion in ADCx_RA Register. Prior to the assertion of TPM1 channel 1 a pre-trigger pulse will be sent to ADHWTSB to initiate an ADC acquisition using ADCx_SC1Bconfiguration and store ADC conversion in ADCx_RB Register. + #0 + + + 1 + ADC ADHWT trigger comes from a peripheral event selected by ADC0TRGSEL bits.ADC0PRETRGSEL bit will select the optional ADHWTSA or ADHWTSB select lines for choosing the ADCx_SC1x config and ADCx_Rx result regsiter to store the ADC conversion. + #1 + + + + + + + SDID + System Device Identification Register + 0x1024 + 32 + read-only + 0x5F0000 + 0xFFFFFFFF + + + PINID + Pin count Identification + 0 + 4 + read-only + + + 011 + 40-pin + #0011 + + + 100 + 48-pin (LGA) + #0100 + + + 101 + 48-pin (wettable flank) + #0101 + + + + + DIEID + Device Die Number + 7 + 5 + read-only + + + REVID + Device Revision Number + 12 + 4 + read-only + + + SRAMSIZE + System SRAM Size + 16 + 4 + read-only + + + 111 + 64 KB + #0111 + + + + + SERIESID + Kinetis Series ID + 20 + 4 + read-only + + + 101 + KW family + #0101 + + + + + SUBFAMID + Kinetis Sub-Family ID. + 24 + 3 + read-only + + + 111 + KWx9 Sub family + #111 + + + 110 + KWx7 Subfamily + #110 + + + 101 + KWx8 Subfamily + #101 + + + + + FAMID + Kinetis family ID + 28 + 4 + read-only + + + 11 + KW3x Family (BTLE) + #0011 + + + + + + + PMSRC + Peripheral Module Soft Reset Control Register(SIM_PMSRC) + 0x102C + 32 + read-write + 0 + 0xFFFFFFFF + + + TPM0SRC + TPM0 Soft Reset Control + 0 + 1 + write-only + + + TPM1SRC + TPM1 Soft Reset Control + 1 + 1 + write-only + + + TPM2SRC + TPM2 Soft Reset Control + 2 + 1 + write-only + + + + + SCGC4 + System Clock Gating Control Register 4 + 0x1034 + 32 + read-write + 0xF0000030 + 0xFFFFFFFF + + + CMT + CMT Clock Gate Control + 2 + 1 + read-write + + + 0 + Clock disabled + #0 + + + 1 + Clock enabled + #1 + + + + + I2C0 + I2C0 Clock Gate Control + 6 + 1 + read-write + + + 0 + Clock disabled + #0 + + + 1 + Clock enabled + #1 + + + + + I2C1 + I2C1 Clock Gate Control + 7 + 1 + read-write + + + 0 + Clock disabled + #0 + + + 1 + Clock enabled + #1 + + + + + CMP + Comparator Clock Gate Control + 19 + 1 + read-write + + + 0 + Clock disabled + #0 + + + 1 + Clock enabled + #1 + + + + + VREF + VREF Clock Gate Control + 20 + 1 + read-write + + + 0 + Clock disabled + #0 + + + 1 + Clock enabled + #1 + + + + + + + SCGC5 + System Clock Gating Control Register 5 + 0x1038 + 32 + read-write + 0x2000182 + 0xFFFFFFFF + + + LPTMR + Low Power Timer Access Control + 0 + 1 + read-write + + + 0 + Access disabled + #0 + + + 1 + Access enabled + #1 + + + + + PORTA + Port A Clock Gate Control + 9 + 1 + read-write + + + 0 + Clock disabled + #0 + + + 1 + Clock enabled + #1 + + + + + PORTB + Port B Clock Gate Control + 10 + 1 + read-write + + + 0 + Clock disabled + #0 + + + 1 + Clock enabled + #1 + + + + + PORTC + Port C Clock Gate Control + 11 + 1 + read-write + + + 0 + Clock disabled + #0 + + + 1 + Clock enabled + #1 + + + + + GFSK_REMAP0 + GFSK Remap0 Clock Gate Control + 16 + 1 + read-write + + + 0 + Clock disabled + #0 + + + 1 + Clock enabled + #1 + + + + + GFSK_REMAP1 + GFSK Remap1 Clock Gate Control + 17 + 1 + read-write + + + 0 + Clock disabled + #0 + + + 1 + Clock enabled + #1 + + + + + GFSK_REMAP2 + GFSK Remap2 Clock Gate Control + 18 + 1 + read-write + + + 0 + Clock disabled + #0 + + + 1 + Clock enabled + #1 + + + + + LPUART0 + LPUART0 Clock Gate Control + 20 + 1 + read-write + + + 0 + Clock disabled + #0 + + + 1 + Clock enabled + #1 + + + + + LPUART1 + LPUART1 Clock Gate Control + 21 + 1 + read-write + + + 0 + Clock disabled + #0 + + + 1 + Clock enabled + #1 + + + + + DSB + Data Stream Buffer Clock Gate Control + 23 + 1 + read-write + + + 0 + Clock disabled + #0 + + + 1 + Clock enabled + #1 + + + + + LTC + LTC Clock Gate Control + 24 + 1 + read-write + + + 0 + Clock disabled + #0 + + + 1 + Clock enabled + #1 + + + + + RSIM + RSIM Clock Gate Control + 25 + 1 + read-only + + + DCDC + DCDC Clock Gate Control + 26 + 1 + read-write + + + 0 + Clock disabled + #0 + + + 1 + Clock enabled + #1 + + + + + BTLL + BTLL System Clock Gate Control + 27 + 1 + read-write + + + 0 + Clock disabled + #0 + + + 1 + Clock enabled + #1 + + + + + PHYDIG + PHY Digital Clock Gate Control + 28 + 1 + read-write + + + 0 + Clock disabled + #0 + + + 1 + Clock enabled + #1 + + + + + GEN_FSK + Generic FSK enabled + 31 + 1 + read-write + + + 0 + GFSK CGC bit disabled. + #0 + + + 1 + GFSK CGC bit enabled. + #1 + + + + + + + SCGC6 + System Clock Gating Control Register 6 + 0x103C + 32 + read-write + 0x1 + 0xFFFFFFFF + + + FTF + Flash Memory Clock Gate Control + 0 + 1 + read-write + + + 0 + Clock disabled + #0 + + + 1 + Clock enabled + #1 + + + + + DMAMUX + DMA Mux Clock Gate Control + 1 + 1 + read-write + + + 0 + Clock disabled + #0 + + + 1 + Clock enabled + #1 + + + + + FLEXCAN0 + FLEXCAN0 Clock Gate Control + 4 + 1 + read-write + + + 0 + Clock disabled + #0 + + + 1 + Clock enabled + #1 + + + + + TRNG + TRNG Clock Gate Control + 9 + 1 + read-write + + + 0 + Clock disabled + #0 + + + 1 + Clock enabled + #1 + + + + + SPI0 + SPI0 Clock Gate Control + 12 + 1 + read-write + + + 0 + Clock disabled + #0 + + + 1 + Clock enabled + #1 + + + + + SPI1 + SPI1 Clock Gate Control + 13 + 1 + read-write + + + 0 + Clock disabled + #0 + + + 1 + Clock enabled + #1 + + + + + PIT + PIT Clock Gate Control + 23 + 1 + read-write + + + 0 + Clock disabled + #0 + + + 1 + Clock enabled + #1 + + + + + TPM0 + TPM0 Clock Gate Control + 24 + 1 + read-write + + + 0 + Clock disabled + #0 + + + 1 + Clock enabled + #1 + + + + + TPM1 + TPM1 Clock Gate Control + 25 + 1 + read-write + + + 0 + Clock disabled + #0 + + + 1 + Clock enabled + #1 + + + + + TPM2 + TPM2 Clock Gate Control + 26 + 1 + read-write + + + 0 + Clock disabled + #0 + + + 1 + Clock enabled + #1 + + + + + ADC0 + ADC0 Clock Gate Control + 27 + 1 + read-write + + + 0 + Clock disabled + #0 + + + 1 + Clock enabled + #1 + + + + + RTC + RTC Access Control + 29 + 1 + read-write + + + 0 + Access and interrupts disabled + #0 + + + 1 + Access and interrupts enabled + #1 + + + + + + + SCGC7 + System Clock Gating Control Register 7 + 0x1040 + 32 + read-write + 0x100 + 0xFFFFFFFF + + + DMA + DMA Clock Gate Control + 8 + 1 + read-write + + + 0 + Clock disabled + #0 + + + 1 + Clock enabled + #1 + + + + + + + CLKDIV1 + System Clock Divider Register 1 + 0x1044 + 32 + read-write + 0x10000 + 0xFFFFFFFF + + + OUTDIV4 + Clock 4 Output Divider value + 16 + 3 + read-write + + + 000 + Divide-by-1. + #000 + + + 001 + Divide-by-2. + #001 + + + 010 + Divide-by-3. + #010 + + + 011 + Divide-by-4. + #011 + + + 100 + Divide-by-5. + #100 + + + 101 + Divide-by-6. + #101 + + + 110 + Divide-by-7. + #110 + + + 111 + Divide-by-8. + #111 + + + + + OUTDIV1 + Clock 1 Output Divider value + 28 + 4 + read-write + + + 0000 + Divide-by-1. + #0000 + + + 0001 + Divide-by-2. + #0001 + + + 0010 + Divide-by-3. + #0010 + + + 0011 + Divide-by-4. + #0011 + + + 0100 + Divide-by-5. + #0100 + + + 0101 + Divide-by-6. + #0101 + + + 0110 + Divide-by-7. + #0110 + + + 0111 + Divide-by-8. + #0111 + + + 1000 + Divide-by-9. + #1000 + + + 1001 + Divide-by-10. + #1001 + + + 1010 + Divide-by-11. + #1010 + + + 1011 + Divide-by-12. + #1011 + + + 1100 + Divide-by-13. + #1100 + + + 1101 + Divide-by-14. + #1101 + + + 1110 + Divide-by-15. + #1110 + + + 1111 + Divide-by-16. + #1111 + + + + + + + FCFG1 + Flash Configuration Register 1 + 0x104C + 32 + read-write + 0 + 0xF0F0FF + + + FLASHDIS + Flash Disable + 0 + 1 + read-write + + + 0 + Flash is enabled. + #0 + + + 1 + Flash is disabled. + #1 + + + + + FLASHDOZE + Flash Doze + 1 + 1 + read-write + + + 0 + Flash remains enabled during Doze mode. + #0 + + + 1 + Flash is disabled for the duration of Doze mode. + #1 + + + + + DEPART + FlexNVM partition + 8 + 4 + read-only + + + EESIZE + EEPROM Size + 16 + 4 + read-only + + + 0001 + 8 KB + #0001 + + + 0010 + 4 KB + #0010 + + + 0011 + 2 KB + #0011 + + + 0100 + 1 KB + #0100 + + + 0101 + 512 bytes + #0101 + + + 0110 + 256 bytes + #0110 + + + 0111 + 128 bytes + #0111 + + + 1000 + 64 bytes + #1000 + + + 1001 + 32 bytes + #1001 + + + + + PFSIZE + Program Flash Size + 24 + 4 + read-only + + + 1001 + 256 KB of program flash memory + #1001 + + + 1011 + 512 KB of program flash memory + #1011 + + + + + NVMSIZE + FlexNVM Size + 28 + 4 + read-only + + + 0000 + 0 KB + #0000 + + + 1001 + 256 KB, 16 KB protection region + #1001 + + + 1111 + 256 KB, 16 KB protection region + #1111 + + + + + + + FCFG2 + Flash Configuration Register 2 + 0x1050 + 32 + read-only + 0x7F7F0000 + 0xFFFFFFFF + + + MAXADDR1 + This field concatenated with leading zeros plus the value of the MAXADDR1 field indicates the first invalid address of the second program flash block (flash block 1) + 16 + 7 + read-only + + + PFLSH + Program flash only + 23 + 1 + read-only + + + 0 + Device supports FlexNVM. + #0 + + + 1 + Program Flash only, device does not support FlexNVM. + #1 + + + + + MAXADDR0 + Max Address block 0 + 24 + 7 + read-only + + + SWAPPFLSH + Swap program flash + 31 + 1 + read-only + + + 0 + Swap is not active. + #0 + + + 1 + Swap is active. + #1 + + + + + + + UIDMH + Unique Identification Register Mid-High + 0x1058 + 32 + read-only + 0 + 0xFFFFFFFF + + + UID + Unique Identification + 0 + 16 + read-only + + + + + UIDML + Unique Identification Register Mid Low + 0x105C + 32 + read-only + 0 + 0xFFFFFFFF + + + UID + Unique Identification + 0 + 32 + read-only + + + + + UIDL + Unique Identification Register Low + 0x1060 + 32 + read-only + 0 + 0xFFFFFFFF + + + UID + Unique Identification + 0 + 32 + read-only + + + + + COPC + COP Control Register + 0x1100 + 32 + read-write + 0xC + 0xFFFFFFFF + + + COPW + COP Windowed Mode + 0 + 1 + read-write + + + 0 + Normal mode + #0 + + + 1 + Windowed mode + #1 + + + + + COPCLKS + COP Clock Select + 1 + 1 + read-write + + + 0 + COP configured for short timeout + #0 + + + 1 + COP configured for long timeout + #1 + + + + + COPT + COP Watchdog Timeout + 2 + 2 + read-write + + + 00 + COP disabled + #00 + + + 01 + COP timeout after 25 cycles for short timeout or 213 cycles for long timeout + #01 + + + 10 + COP timeout after 28 cycles for short timeout or 216 cycles for long timeout + #10 + + + 11 + COP timeout after 210 cycles for short timeout or 218 cycles for long timeout + #11 + + + + + COPSTPEN + COP Stop Enable + 4 + 1 + read-write + + + 0 + COP is disabled and the counter is reset in Stop modes + #0 + + + 1 + COP is enabled in Stop modes + #1 + + + + + COPDBGEN + COP Debug Enable + 5 + 1 + read-write + + + 0 + COP is disabled and the counter is reset in Debug mode + #0 + + + 1 + COP is enabled in Debug mode + #1 + + + + + COPCLKSEL + COP Clock Select + 6 + 2 + read-write + + + 00 + LPO clock (1 kHz) + #00 + + + 01 + MCGIRCLK + #01 + + + 10 + OSCERCLK + #10 + + + 11 + Bus clock + #11 + + + + + + + SRVCOP + Service COP + 0x1104 + 32 + write-only + 0 + 0xFFFFFFFF + + + SRVCOP + Service COP Register + 0 + 8 + write-only + + + + + + + PORTA + PORT + PORT + 0x40049000 + + 0 + 0xA4 + registers + + + + PCR0 + Pin Control Register 0 + 0 + 32 + read-write + 0x703 + 0xFFFFFFFF + + + PS + Pull Select + 0 + 1 + read-write + + + 0 + Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. + #0 + + + 1 + Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. + #1 + + + + + PE + Pull Enable + 1 + 1 + read-write + + + SRE + Slew Rate Enable + 2 + 1 + read-write + + + 0 + Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. + #0 + + + 1 + Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. + #1 + + + + + MUX + Pin Mux Control + 8 + 4 + read-write + + + 0000 + Pin disabled (Alternative 0) (analog). + #0000 + + + 0001 + Alternative 1 (GPIO). + #0001 + + + 0010 + Alternative 2 (chip-specific). + #0010 + + + 0011 + Alternative 3 (chip-specific). + #0011 + + + 0100 + Alternative 4 (chip-specific). + #0100 + + + 0101 + Alternative 5 (chip-specific). + #0101 + + + 0110 + Alternative 6 (chip-specific). + #0110 + + + 0111 + Alternative 7 (chip-specific). + #0111 + + + 1000 + Alternative 8 (chip-specific). + #1000 + + + 1001 + Alternative 9 (chip-specific). + #1001 + + + 1010 + Alternative 10 (chip-specific). + #1010 + + + 1011 + Alternative 11 (chip-specific). + #1011 + + + 1100 + Alternative 12 (chip-specific). + #1100 + + + 1101 + Alternative 13 (chip-specific). + #1101 + + + 1110 + Alternative 14 (chip-specific). + #1110 + + + 1111 + Alternative 15 (chip-specific). + #1111 + + + + + IRQC + Interrupt Configuration + 16 + 4 + read-write + + + 0000 + Interrupt Status Flag (ISF) is disabled. + #0000 + + + 0001 + ISF flag and DMA request on rising edge. + #0001 + + + 0010 + ISF flag and DMA request on falling edge. + #0010 + + + 0011 + ISF flag and DMA request on either edge. + #0011 + + + 1000 + ISF flag and Interrupt when logic 0. + #1000 + + + 1001 + ISF flag and Interrupt on rising-edge. + #1001 + + + 1010 + ISF flag and Interrupt on falling-edge. + #1010 + + + 1011 + ISF flag and Interrupt on either edge. + #1011 + + + 1100 + ISF flag and Interrupt when logic 1. + #1100 + + + + + ISF + Interrupt Status Flag + 24 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + + + + + PCR1 + Pin Control Register 1 + 0x4 + 32 + read-write + 0x706 + 0xFFFFFFFF + + + PS + Pull Select + 0 + 1 + read-write + + + 0 + Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. + #0 + + + 1 + Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. + #1 + + + + + PE + Pull Enable + 1 + 1 + read-write + + + SRE + Slew Rate Enable + 2 + 1 + read-write + + + 0 + Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. + #0 + + + 1 + Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. + #1 + + + + + MUX + Pin Mux Control + 8 + 4 + read-write + + + 0000 + Pin disabled (Alternative 0) (analog). + #0000 + + + 0001 + Alternative 1 (GPIO). + #0001 + + + 0010 + Alternative 2 (chip-specific). + #0010 + + + 0011 + Alternative 3 (chip-specific). + #0011 + + + 0100 + Alternative 4 (chip-specific). + #0100 + + + 0101 + Alternative 5 (chip-specific). + #0101 + + + 0110 + Alternative 6 (chip-specific). + #0110 + + + 0111 + Alternative 7 (chip-specific). + #0111 + + + 1000 + Alternative 8 (chip-specific). + #1000 + + + 1001 + Alternative 9 (chip-specific). + #1001 + + + 1010 + Alternative 10 (chip-specific). + #1010 + + + 1011 + Alternative 11 (chip-specific). + #1011 + + + 1100 + Alternative 12 (chip-specific). + #1100 + + + 1101 + Alternative 13 (chip-specific). + #1101 + + + 1110 + Alternative 14 (chip-specific). + #1110 + + + 1111 + Alternative 15 (chip-specific). + #1111 + + + + + IRQC + Interrupt Configuration + 16 + 4 + read-write + + + 0000 + Interrupt Status Flag (ISF) is disabled. + #0000 + + + 0001 + ISF flag and DMA request on rising edge. + #0001 + + + 0010 + ISF flag and DMA request on falling edge. + #0010 + + + 0011 + ISF flag and DMA request on either edge. + #0011 + + + 1000 + ISF flag and Interrupt when logic 0. + #1000 + + + 1001 + ISF flag and Interrupt on rising-edge. + #1001 + + + 1010 + ISF flag and Interrupt on falling-edge. + #1010 + + + 1011 + ISF flag and Interrupt on either edge. + #1011 + + + 1100 + ISF flag and Interrupt when logic 1. + #1100 + + + + + ISF + Interrupt Status Flag + 24 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + + + + + PCR2 + Pin Control Register 2 + 0x8 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + PS + Pull Select + 0 + 1 + read-write + + + 0 + Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. + #0 + + + 1 + Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. + #1 + + + + + PE + Pull Enable + 1 + 1 + read-write + + + SRE + Slew Rate Enable + 2 + 1 + read-write + + + 0 + Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. + #0 + + + 1 + Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. + #1 + + + + + MUX + Pin Mux Control + 8 + 4 + read-write + + + 0000 + Pin disabled (Alternative 0) (analog). + #0000 + + + 0001 + Alternative 1 (GPIO). + #0001 + + + 0010 + Alternative 2 (chip-specific). + #0010 + + + 0011 + Alternative 3 (chip-specific). + #0011 + + + 0100 + Alternative 4 (chip-specific). + #0100 + + + 0101 + Alternative 5 (chip-specific). + #0101 + + + 0110 + Alternative 6 (chip-specific). + #0110 + + + 0111 + Alternative 7 (chip-specific). + #0111 + + + 1000 + Alternative 8 (chip-specific). + #1000 + + + 1001 + Alternative 9 (chip-specific). + #1001 + + + 1010 + Alternative 10 (chip-specific). + #1010 + + + 1011 + Alternative 11 (chip-specific). + #1011 + + + 1100 + Alternative 12 (chip-specific). + #1100 + + + 1101 + Alternative 13 (chip-specific). + #1101 + + + 1110 + Alternative 14 (chip-specific). + #1110 + + + 1111 + Alternative 15 (chip-specific). + #1111 + + + + + IRQC + Interrupt Configuration + 16 + 4 + read-write + + + 0000 + Interrupt Status Flag (ISF) is disabled. + #0000 + + + 0001 + ISF flag and DMA request on rising edge. + #0001 + + + 0010 + ISF flag and DMA request on falling edge. + #0010 + + + 0011 + ISF flag and DMA request on either edge. + #0011 + + + 1000 + ISF flag and Interrupt when logic 0. + #1000 + + + 1001 + ISF flag and Interrupt on rising-edge. + #1001 + + + 1010 + ISF flag and Interrupt on falling-edge. + #1010 + + + 1011 + ISF flag and Interrupt on either edge. + #1011 + + + 1100 + ISF flag and Interrupt when logic 1. + #1100 + + + + + ISF + Interrupt Status Flag + 24 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + + + + + PCR16 + Pin Control Register 16 + 0x40 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + PS + Pull Select + 0 + 1 + read-write + + + 0 + Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. + #0 + + + 1 + Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. + #1 + + + + + PE + Pull Enable + 1 + 1 + read-write + + + SRE + Slew Rate Enable + 2 + 1 + read-write + + + 0 + Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. + #0 + + + 1 + Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. + #1 + + + + + MUX + Pin Mux Control + 8 + 4 + read-write + + + 0000 + Pin disabled (Alternative 0) (analog). + #0000 + + + 0001 + Alternative 1 (GPIO). + #0001 + + + 0010 + Alternative 2 (chip-specific). + #0010 + + + 0011 + Alternative 3 (chip-specific). + #0011 + + + 0100 + Alternative 4 (chip-specific). + #0100 + + + 0101 + Alternative 5 (chip-specific). + #0101 + + + 0110 + Alternative 6 (chip-specific). + #0110 + + + 0111 + Alternative 7 (chip-specific). + #0111 + + + 1000 + Alternative 8 (chip-specific). + #1000 + + + 1001 + Alternative 9 (chip-specific). + #1001 + + + 1010 + Alternative 10 (chip-specific). + #1010 + + + 1011 + Alternative 11 (chip-specific). + #1011 + + + 1100 + Alternative 12 (chip-specific). + #1100 + + + 1101 + Alternative 13 (chip-specific). + #1101 + + + 1110 + Alternative 14 (chip-specific). + #1110 + + + 1111 + Alternative 15 (chip-specific). + #1111 + + + + + IRQC + Interrupt Configuration + 16 + 4 + read-write + + + 0000 + Interrupt Status Flag (ISF) is disabled. + #0000 + + + 0001 + ISF flag and DMA request on rising edge. + #0001 + + + 0010 + ISF flag and DMA request on falling edge. + #0010 + + + 0011 + ISF flag and DMA request on either edge. + #0011 + + + 1000 + ISF flag and Interrupt when logic 0. + #1000 + + + 1001 + ISF flag and Interrupt on rising-edge. + #1001 + + + 1010 + ISF flag and Interrupt on falling-edge. + #1010 + + + 1011 + ISF flag and Interrupt on either edge. + #1011 + + + 1100 + ISF flag and Interrupt when logic 1. + #1100 + + + + + ISF + Interrupt Status Flag + 24 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + + + + + PCR17 + Pin Control Register 17 + 0x44 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + PS + Pull Select + 0 + 1 + read-write + + + 0 + Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. + #0 + + + 1 + Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. + #1 + + + + + PE + Pull Enable + 1 + 1 + read-write + + + SRE + Slew Rate Enable + 2 + 1 + read-write + + + 0 + Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. + #0 + + + 1 + Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. + #1 + + + + + MUX + Pin Mux Control + 8 + 4 + read-write + + + 0000 + Pin disabled (Alternative 0) (analog). + #0000 + + + 0001 + Alternative 1 (GPIO). + #0001 + + + 0010 + Alternative 2 (chip-specific). + #0010 + + + 0011 + Alternative 3 (chip-specific). + #0011 + + + 0100 + Alternative 4 (chip-specific). + #0100 + + + 0101 + Alternative 5 (chip-specific). + #0101 + + + 0110 + Alternative 6 (chip-specific). + #0110 + + + 0111 + Alternative 7 (chip-specific). + #0111 + + + 1000 + Alternative 8 (chip-specific). + #1000 + + + 1001 + Alternative 9 (chip-specific). + #1001 + + + 1010 + Alternative 10 (chip-specific). + #1010 + + + 1011 + Alternative 11 (chip-specific). + #1011 + + + 1100 + Alternative 12 (chip-specific). + #1100 + + + 1101 + Alternative 13 (chip-specific). + #1101 + + + 1110 + Alternative 14 (chip-specific). + #1110 + + + 1111 + Alternative 15 (chip-specific). + #1111 + + + + + IRQC + Interrupt Configuration + 16 + 4 + read-write + + + 0000 + Interrupt Status Flag (ISF) is disabled. + #0000 + + + 0001 + ISF flag and DMA request on rising edge. + #0001 + + + 0010 + ISF flag and DMA request on falling edge. + #0010 + + + 0011 + ISF flag and DMA request on either edge. + #0011 + + + 1000 + ISF flag and Interrupt when logic 0. + #1000 + + + 1001 + ISF flag and Interrupt on rising-edge. + #1001 + + + 1010 + ISF flag and Interrupt on falling-edge. + #1010 + + + 1011 + ISF flag and Interrupt on either edge. + #1011 + + + 1100 + ISF flag and Interrupt when logic 1. + #1100 + + + + + ISF + Interrupt Status Flag + 24 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + + + + + PCR18 + Pin Control Register 18 + 0x48 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + PS + Pull Select + 0 + 1 + read-write + + + 0 + Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. + #0 + + + 1 + Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. + #1 + + + + + PE + Pull Enable + 1 + 1 + read-write + + + SRE + Slew Rate Enable + 2 + 1 + read-write + + + 0 + Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. + #0 + + + 1 + Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. + #1 + + + + + MUX + Pin Mux Control + 8 + 4 + read-write + + + 0000 + Pin disabled (Alternative 0) (analog). + #0000 + + + 0001 + Alternative 1 (GPIO). + #0001 + + + 0010 + Alternative 2 (chip-specific). + #0010 + + + 0011 + Alternative 3 (chip-specific). + #0011 + + + 0100 + Alternative 4 (chip-specific). + #0100 + + + 0101 + Alternative 5 (chip-specific). + #0101 + + + 0110 + Alternative 6 (chip-specific). + #0110 + + + 0111 + Alternative 7 (chip-specific). + #0111 + + + 1000 + Alternative 8 (chip-specific). + #1000 + + + 1001 + Alternative 9 (chip-specific). + #1001 + + + 1010 + Alternative 10 (chip-specific). + #1010 + + + 1011 + Alternative 11 (chip-specific). + #1011 + + + 1100 + Alternative 12 (chip-specific). + #1100 + + + 1101 + Alternative 13 (chip-specific). + #1101 + + + 1110 + Alternative 14 (chip-specific). + #1110 + + + 1111 + Alternative 15 (chip-specific). + #1111 + + + + + IRQC + Interrupt Configuration + 16 + 4 + read-write + + + 0000 + Interrupt Status Flag (ISF) is disabled. + #0000 + + + 0001 + ISF flag and DMA request on rising edge. + #0001 + + + 0010 + ISF flag and DMA request on falling edge. + #0010 + + + 0011 + ISF flag and DMA request on either edge. + #0011 + + + 1000 + ISF flag and Interrupt when logic 0. + #1000 + + + 1001 + ISF flag and Interrupt on rising-edge. + #1001 + + + 1010 + ISF flag and Interrupt on falling-edge. + #1010 + + + 1011 + ISF flag and Interrupt on either edge. + #1011 + + + 1100 + ISF flag and Interrupt when logic 1. + #1100 + + + + + ISF + Interrupt Status Flag + 24 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + + + + + PCR19 + Pin Control Register 19 + 0x4C + 32 + read-write + 0x1 + 0xFFFFFFFF + + + PS + Pull Select + 0 + 1 + read-write + + + 0 + Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. + #0 + + + 1 + Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. + #1 + + + + + PE + Pull Enable + 1 + 1 + read-write + + + SRE + Slew Rate Enable + 2 + 1 + read-write + + + 0 + Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. + #0 + + + 1 + Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. + #1 + + + + + MUX + Pin Mux Control + 8 + 4 + read-write + + + 0000 + Pin disabled (Alternative 0) (analog). + #0000 + + + 0001 + Alternative 1 (GPIO). + #0001 + + + 0010 + Alternative 2 (chip-specific). + #0010 + + + 0011 + Alternative 3 (chip-specific). + #0011 + + + 0100 + Alternative 4 (chip-specific). + #0100 + + + 0101 + Alternative 5 (chip-specific). + #0101 + + + 0110 + Alternative 6 (chip-specific). + #0110 + + + 0111 + Alternative 7 (chip-specific). + #0111 + + + 1000 + Alternative 8 (chip-specific). + #1000 + + + 1001 + Alternative 9 (chip-specific). + #1001 + + + 1010 + Alternative 10 (chip-specific). + #1010 + + + 1011 + Alternative 11 (chip-specific). + #1011 + + + 1100 + Alternative 12 (chip-specific). + #1100 + + + 1101 + Alternative 13 (chip-specific). + #1101 + + + 1110 + Alternative 14 (chip-specific). + #1110 + + + 1111 + Alternative 15 (chip-specific). + #1111 + + + + + IRQC + Interrupt Configuration + 16 + 4 + read-write + + + 0000 + Interrupt Status Flag (ISF) is disabled. + #0000 + + + 0001 + ISF flag and DMA request on rising edge. + #0001 + + + 0010 + ISF flag and DMA request on falling edge. + #0010 + + + 0011 + ISF flag and DMA request on either edge. + #0011 + + + 1000 + ISF flag and Interrupt when logic 0. + #1000 + + + 1001 + ISF flag and Interrupt on rising-edge. + #1001 + + + 1010 + ISF flag and Interrupt on falling-edge. + #1010 + + + 1011 + ISF flag and Interrupt on either edge. + #1011 + + + 1100 + ISF flag and Interrupt when logic 1. + #1100 + + + + + ISF + Interrupt Status Flag + 24 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + + + + + GPCLR + Global Pin Control Low Register + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + GPWD + Global Pin Write Data + 0 + 16 + read-write + + + GPWE + Global Pin Write Enable + 16 + 16 + read-write + + + + + GPCHR + Global Pin Control High Register + 0x84 + 32 + read-write + 0 + 0xFFFFFFFF + + + GPWD + Global Pin Write Data + 0 + 16 + read-write + + + GPWE + Global Pin Write Enable + 16 + 16 + read-write + + + + + GICLR + Global Interrupt Control Low Register + 0x88 + 32 + read-write + 0 + 0xFFFFFFFF + + + GIWE + Global Interrupt Write Enable + 0 + 16 + read-write + + + GIWD + Global Interrupt Write Data + 16 + 16 + read-write + + + + + GICHR + Global Interrupt Control High Register + 0x8C + 32 + read-write + 0 + 0xFFFFFFFF + + + GIWE + Global Interrupt Write Enable + 0 + 16 + read-write + + + GIWD + Global Interrupt Write Data + 16 + 16 + read-write + + + + + ISFR + Interrupt Status Flag Register + 0xA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + ISF + Interrupt Status Flag + 0 + 32 + read-write + + + + + + + PORTB + PORT + PORT + 0x4004A000 + + 0 + 0xA4 + registers + + + + PCR0 + Pin Control Register 0 + 0 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + PS + Pull Select + 0 + 1 + read-write + + + 0 + Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. + #0 + + + 1 + Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. + #1 + + + + + PE + Pull Enable + 1 + 1 + read-write + + + SRE + Slew Rate Enable + 2 + 1 + read-write + + + 0 + Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. + #0 + + + 1 + Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. + #1 + + + + + DSE + Drive Strength Enable + 6 + 1 + read-write + + + 0 + Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. + #0 + + + 1 + High drive strength is configured on the corresponding pin, if pin is configured as a digital output. + #1 + + + + + MUX + Pin Mux Control + 8 + 4 + read-write + + + 0000 + Pin disabled (Alternative 0) (analog). + #0000 + + + 0001 + Alternative 1 (GPIO). + #0001 + + + 0010 + Alternative 2 (chip-specific). + #0010 + + + 0011 + Alternative 3 (chip-specific). + #0011 + + + 0100 + Alternative 4 (chip-specific). + #0100 + + + 0101 + Alternative 5 (chip-specific). + #0101 + + + 0110 + Alternative 6 (chip-specific). + #0110 + + + 0111 + Alternative 7 (chip-specific). + #0111 + + + 1000 + Alternative 8 (chip-specific). + #1000 + + + 1001 + Alternative 9 (chip-specific). + #1001 + + + 1010 + Alternative 10 (chip-specific). + #1010 + + + 1011 + Alternative 11 (chip-specific). + #1011 + + + 1100 + Alternative 12 (chip-specific). + #1100 + + + 1101 + Alternative 13 (chip-specific). + #1101 + + + 1110 + Alternative 14 (chip-specific). + #1110 + + + 1111 + Alternative 15 (chip-specific). + #1111 + + + + + IRQC + Interrupt Configuration + 16 + 4 + read-write + + + 0000 + Interrupt Status Flag (ISF) is disabled. + #0000 + + + 0001 + ISF flag and DMA request on rising edge. + #0001 + + + 0010 + ISF flag and DMA request on falling edge. + #0010 + + + 0011 + ISF flag and DMA request on either edge. + #0011 + + + 1000 + ISF flag and Interrupt when logic 0. + #1000 + + + 1001 + ISF flag and Interrupt on rising-edge. + #1001 + + + 1010 + ISF flag and Interrupt on falling-edge. + #1010 + + + 1011 + ISF flag and Interrupt on either edge. + #1011 + + + 1100 + ISF flag and Interrupt when logic 1. + #1100 + + + + + ISF + Interrupt Status Flag + 24 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + + + + + PCR1 + Pin Control Register 1 + 0x4 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + PS + Pull Select + 0 + 1 + read-write + + + 0 + Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. + #0 + + + 1 + Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. + #1 + + + + + PE + Pull Enable + 1 + 1 + read-write + + + SRE + Slew Rate Enable + 2 + 1 + read-write + + + 0 + Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. + #0 + + + 1 + Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. + #1 + + + + + DSE + Drive Strength Enable + 6 + 1 + read-write + + + 0 + Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. + #0 + + + 1 + High drive strength is configured on the corresponding pin, if pin is configured as a digital output. + #1 + + + + + MUX + Pin Mux Control + 8 + 4 + read-write + + + 0000 + Pin disabled (Alternative 0) (analog). + #0000 + + + 0001 + Alternative 1 (GPIO). + #0001 + + + 0010 + Alternative 2 (chip-specific). + #0010 + + + 0011 + Alternative 3 (chip-specific). + #0011 + + + 0100 + Alternative 4 (chip-specific). + #0100 + + + 0101 + Alternative 5 (chip-specific). + #0101 + + + 0110 + Alternative 6 (chip-specific). + #0110 + + + 0111 + Alternative 7 (chip-specific). + #0111 + + + 1000 + Alternative 8 (chip-specific). + #1000 + + + 1001 + Alternative 9 (chip-specific). + #1001 + + + 1010 + Alternative 10 (chip-specific). + #1010 + + + 1011 + Alternative 11 (chip-specific). + #1011 + + + 1100 + Alternative 12 (chip-specific). + #1100 + + + 1101 + Alternative 13 (chip-specific). + #1101 + + + 1110 + Alternative 14 (chip-specific). + #1110 + + + 1111 + Alternative 15 (chip-specific). + #1111 + + + + + IRQC + Interrupt Configuration + 16 + 4 + read-write + + + 0000 + Interrupt Status Flag (ISF) is disabled. + #0000 + + + 0001 + ISF flag and DMA request on rising edge. + #0001 + + + 0010 + ISF flag and DMA request on falling edge. + #0010 + + + 0011 + ISF flag and DMA request on either edge. + #0011 + + + 1000 + ISF flag and Interrupt when logic 0. + #1000 + + + 1001 + ISF flag and Interrupt on rising-edge. + #1001 + + + 1010 + ISF flag and Interrupt on falling-edge. + #1010 + + + 1011 + ISF flag and Interrupt on either edge. + #1011 + + + 1100 + ISF flag and Interrupt when logic 1. + #1100 + + + + + ISF + Interrupt Status Flag + 24 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + + + + + PCR2 + Pin Control Register 2 + 0x8 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + PS + Pull Select + 0 + 1 + read-write + + + 0 + Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. + #0 + + + 1 + Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. + #1 + + + + + PE + Pull Enable + 1 + 1 + read-write + + + SRE + Slew Rate Enable + 2 + 1 + read-write + + + 0 + Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. + #0 + + + 1 + Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. + #1 + + + + + MUX + Pin Mux Control + 8 + 4 + read-write + + + 0000 + Pin disabled (Alternative 0) (analog). + #0000 + + + 0001 + Alternative 1 (GPIO). + #0001 + + + 0010 + Alternative 2 (chip-specific). + #0010 + + + 0011 + Alternative 3 (chip-specific). + #0011 + + + 0100 + Alternative 4 (chip-specific). + #0100 + + + 0101 + Alternative 5 (chip-specific). + #0101 + + + 0110 + Alternative 6 (chip-specific). + #0110 + + + 0111 + Alternative 7 (chip-specific). + #0111 + + + 1000 + Alternative 8 (chip-specific). + #1000 + + + 1001 + Alternative 9 (chip-specific). + #1001 + + + 1010 + Alternative 10 (chip-specific). + #1010 + + + 1011 + Alternative 11 (chip-specific). + #1011 + + + 1100 + Alternative 12 (chip-specific). + #1100 + + + 1101 + Alternative 13 (chip-specific). + #1101 + + + 1110 + Alternative 14 (chip-specific). + #1110 + + + 1111 + Alternative 15 (chip-specific). + #1111 + + + + + IRQC + Interrupt Configuration + 16 + 4 + read-write + + + 0000 + Interrupt Status Flag (ISF) is disabled. + #0000 + + + 0001 + ISF flag and DMA request on rising edge. + #0001 + + + 0010 + ISF flag and DMA request on falling edge. + #0010 + + + 0011 + ISF flag and DMA request on either edge. + #0011 + + + 1000 + ISF flag and Interrupt when logic 0. + #1000 + + + 1001 + ISF flag and Interrupt on rising-edge. + #1001 + + + 1010 + ISF flag and Interrupt on falling-edge. + #1010 + + + 1011 + ISF flag and Interrupt on either edge. + #1011 + + + 1100 + ISF flag and Interrupt when logic 1. + #1100 + + + + + ISF + Interrupt Status Flag + 24 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + + + + + PCR3 + Pin Control Register 3 + 0xC + 32 + read-write + 0x1 + 0xFFFFFFFF + + + PS + Pull Select + 0 + 1 + read-write + + + 0 + Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. + #0 + + + 1 + Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. + #1 + + + + + PE + Pull Enable + 1 + 1 + read-write + + + SRE + Slew Rate Enable + 2 + 1 + read-write + + + 0 + Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. + #0 + + + 1 + Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. + #1 + + + + + MUX + Pin Mux Control + 8 + 4 + read-write + + + 0000 + Pin disabled (Alternative 0) (analog). + #0000 + + + 0001 + Alternative 1 (GPIO). + #0001 + + + 0010 + Alternative 2 (chip-specific). + #0010 + + + 0011 + Alternative 3 (chip-specific). + #0011 + + + 0100 + Alternative 4 (chip-specific). + #0100 + + + 0101 + Alternative 5 (chip-specific). + #0101 + + + 0110 + Alternative 6 (chip-specific). + #0110 + + + 0111 + Alternative 7 (chip-specific). + #0111 + + + 1000 + Alternative 8 (chip-specific). + #1000 + + + 1001 + Alternative 9 (chip-specific). + #1001 + + + 1010 + Alternative 10 (chip-specific). + #1010 + + + 1011 + Alternative 11 (chip-specific). + #1011 + + + 1100 + Alternative 12 (chip-specific). + #1100 + + + 1101 + Alternative 13 (chip-specific). + #1101 + + + 1110 + Alternative 14 (chip-specific). + #1110 + + + 1111 + Alternative 15 (chip-specific). + #1111 + + + + + IRQC + Interrupt Configuration + 16 + 4 + read-write + + + 0000 + Interrupt Status Flag (ISF) is disabled. + #0000 + + + 0001 + ISF flag and DMA request on rising edge. + #0001 + + + 0010 + ISF flag and DMA request on falling edge. + #0010 + + + 0011 + ISF flag and DMA request on either edge. + #0011 + + + 1000 + ISF flag and Interrupt when logic 0. + #1000 + + + 1001 + ISF flag and Interrupt on rising-edge. + #1001 + + + 1010 + ISF flag and Interrupt on falling-edge. + #1010 + + + 1011 + ISF flag and Interrupt on either edge. + #1011 + + + 1100 + ISF flag and Interrupt when logic 1. + #1100 + + + + + ISF + Interrupt Status Flag + 24 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + + + + + PCR16 + Pin Control Register 16 + 0x40 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + PS + Pull Select + 0 + 1 + read-write + + + 0 + Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. + #0 + + + 1 + Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. + #1 + + + + + PE + Pull Enable + 1 + 1 + read-write + + + SRE + Slew Rate Enable + 2 + 1 + read-write + + + 0 + Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. + #0 + + + 1 + Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. + #1 + + + + + MUX + Pin Mux Control + 8 + 4 + read-write + + + 0000 + Pin disabled (Alternative 0) (analog). + #0000 + + + 0001 + Alternative 1 (GPIO). + #0001 + + + 0010 + Alternative 2 (chip-specific). + #0010 + + + 0011 + Alternative 3 (chip-specific). + #0011 + + + 0100 + Alternative 4 (chip-specific). + #0100 + + + 0101 + Alternative 5 (chip-specific). + #0101 + + + 0110 + Alternative 6 (chip-specific). + #0110 + + + 0111 + Alternative 7 (chip-specific). + #0111 + + + 1000 + Alternative 8 (chip-specific). + #1000 + + + 1001 + Alternative 9 (chip-specific). + #1001 + + + 1010 + Alternative 10 (chip-specific). + #1010 + + + 1011 + Alternative 11 (chip-specific). + #1011 + + + 1100 + Alternative 12 (chip-specific). + #1100 + + + 1101 + Alternative 13 (chip-specific). + #1101 + + + 1110 + Alternative 14 (chip-specific). + #1110 + + + 1111 + Alternative 15 (chip-specific). + #1111 + + + + + IRQC + Interrupt Configuration + 16 + 4 + read-write + + + 0000 + Interrupt Status Flag (ISF) is disabled. + #0000 + + + 0001 + ISF flag and DMA request on rising edge. + #0001 + + + 0010 + ISF flag and DMA request on falling edge. + #0010 + + + 0011 + ISF flag and DMA request on either edge. + #0011 + + + 1000 + ISF flag and Interrupt when logic 0. + #1000 + + + 1001 + ISF flag and Interrupt on rising-edge. + #1001 + + + 1010 + ISF flag and Interrupt on falling-edge. + #1010 + + + 1011 + ISF flag and Interrupt on either edge. + #1011 + + + 1100 + ISF flag and Interrupt when logic 1. + #1100 + + + + + ISF + Interrupt Status Flag + 24 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + + + + + PCR17 + Pin Control Register 17 + 0x44 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + PS + Pull Select + 0 + 1 + read-write + + + 0 + Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. + #0 + + + 1 + Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. + #1 + + + + + PE + Pull Enable + 1 + 1 + read-write + + + SRE + Slew Rate Enable + 2 + 1 + read-write + + + 0 + Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. + #0 + + + 1 + Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. + #1 + + + + + MUX + Pin Mux Control + 8 + 4 + read-write + + + 0000 + Pin disabled (Alternative 0) (analog). + #0000 + + + 0001 + Alternative 1 (GPIO). + #0001 + + + 0010 + Alternative 2 (chip-specific). + #0010 + + + 0011 + Alternative 3 (chip-specific). + #0011 + + + 0100 + Alternative 4 (chip-specific). + #0100 + + + 0101 + Alternative 5 (chip-specific). + #0101 + + + 0110 + Alternative 6 (chip-specific). + #0110 + + + 0111 + Alternative 7 (chip-specific). + #0111 + + + 1000 + Alternative 8 (chip-specific). + #1000 + + + 1001 + Alternative 9 (chip-specific). + #1001 + + + 1010 + Alternative 10 (chip-specific). + #1010 + + + 1011 + Alternative 11 (chip-specific). + #1011 + + + 1100 + Alternative 12 (chip-specific). + #1100 + + + 1101 + Alternative 13 (chip-specific). + #1101 + + + 1110 + Alternative 14 (chip-specific). + #1110 + + + 1111 + Alternative 15 (chip-specific). + #1111 + + + + + IRQC + Interrupt Configuration + 16 + 4 + read-write + + + 0000 + Interrupt Status Flag (ISF) is disabled. + #0000 + + + 0001 + ISF flag and DMA request on rising edge. + #0001 + + + 0010 + ISF flag and DMA request on falling edge. + #0010 + + + 0011 + ISF flag and DMA request on either edge. + #0011 + + + 1000 + ISF flag and Interrupt when logic 0. + #1000 + + + 1001 + ISF flag and Interrupt on rising-edge. + #1001 + + + 1010 + ISF flag and Interrupt on falling-edge. + #1010 + + + 1011 + ISF flag and Interrupt on either edge. + #1011 + + + 1100 + ISF flag and Interrupt when logic 1. + #1100 + + + + + ISF + Interrupt Status Flag + 24 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + + + + + PCR18 + Pin Control Register 18 + 0x48 + 32 + read-write + 0x717 + 0xFFFFFFFF + + + PS + Pull Select + 0 + 1 + read-write + + + 0 + Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. + #0 + + + 1 + Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. + #1 + + + + + PE + Pull Enable + 1 + 1 + read-write + + + SRE + Slew Rate Enable + 2 + 1 + read-write + + + 0 + Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. + #0 + + + 1 + Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. + #1 + + + + + PFE + Passive Filter Enable + 4 + 1 + read-write + + + 0 + Passive input filter is disabled on the corresponding pin. + #0 + + + 1 + Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. + #1 + + + + + MUX + Pin Mux Control + 8 + 4 + read-write + + + 0000 + Pin disabled (Alternative 0) (analog). + #0000 + + + 0001 + Alternative 1 (GPIO). + #0001 + + + 0010 + Alternative 2 (chip-specific). + #0010 + + + 0011 + Alternative 3 (chip-specific). + #0011 + + + 0100 + Alternative 4 (chip-specific). + #0100 + + + 0101 + Alternative 5 (chip-specific). + #0101 + + + 0110 + Alternative 6 (chip-specific). + #0110 + + + 0111 + Alternative 7 (chip-specific). + #0111 + + + 1000 + Alternative 8 (chip-specific). + #1000 + + + 1001 + Alternative 9 (chip-specific). + #1001 + + + 1010 + Alternative 10 (chip-specific). + #1010 + + + 1011 + Alternative 11 (chip-specific). + #1011 + + + 1100 + Alternative 12 (chip-specific). + #1100 + + + 1101 + Alternative 13 (chip-specific). + #1101 + + + 1110 + Alternative 14 (chip-specific). + #1110 + + + 1111 + Alternative 15 (chip-specific). + #1111 + + + + + IRQC + Interrupt Configuration + 16 + 4 + read-write + + + 0000 + Interrupt Status Flag (ISF) is disabled. + #0000 + + + 0001 + ISF flag and DMA request on rising edge. + #0001 + + + 0010 + ISF flag and DMA request on falling edge. + #0010 + + + 0011 + ISF flag and DMA request on either edge. + #0011 + + + 1000 + ISF flag and Interrupt when logic 0. + #1000 + + + 1001 + ISF flag and Interrupt on rising-edge. + #1001 + + + 1010 + ISF flag and Interrupt on falling-edge. + #1010 + + + 1011 + ISF flag and Interrupt on either edge. + #1011 + + + 1100 + ISF flag and Interrupt when logic 1. + #1100 + + + + + ISF + Interrupt Status Flag + 24 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + + + + + GPCLR + Global Pin Control Low Register + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + GPWD + Global Pin Write Data + 0 + 16 + read-write + + + GPWE + Global Pin Write Enable + 16 + 16 + read-write + + + + + GPCHR + Global Pin Control High Register + 0x84 + 32 + read-write + 0 + 0xFFFFFFFF + + + GPWD + Global Pin Write Data + 0 + 16 + read-write + + + GPWE + Global Pin Write Enable + 16 + 16 + read-write + + + + + GICLR + Global Interrupt Control Low Register + 0x88 + 32 + read-write + 0 + 0xFFFFFFFF + + + GIWE + Global Interrupt Write Enable + 0 + 16 + read-write + + + GIWD + Global Interrupt Write Data + 16 + 16 + read-write + + + + + GICHR + Global Interrupt Control High Register + 0x8C + 32 + read-write + 0 + 0xFFFFFFFF + + + GIWE + Global Interrupt Write Enable + 0 + 16 + read-write + + + GIWD + Global Interrupt Write Data + 16 + 16 + read-write + + + + + ISFR + Interrupt Status Flag Register + 0xA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + ISF + Interrupt Status Flag + 0 + 32 + read-write + + + + + + + PORTC + PORT + PORT + 0x4004B000 + + 0x4 + 0xA0 + registers + + + + PCR1 + Pin Control Register 1 + 0x4 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + PS + Pull Select + 0 + 1 + read-write + + + 0 + Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. + #0 + + + 1 + Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. + #1 + + + + + PE + Pull Enable + 1 + 1 + read-write + + + SRE + Slew Rate Enable + 2 + 1 + read-write + + + 0 + Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. + #0 + + + 1 + Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. + #1 + + + + + DSE + Drive Strength Enable + 6 + 1 + read-write + + + 0 + Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. + #0 + + + 1 + High drive strength is configured on the corresponding pin, if pin is configured as a digital output. + #1 + + + + + MUX + Pin Mux Control + 8 + 4 + read-write + + + 0000 + Pin disabled (Alternative 0) (analog). + #0000 + + + 0001 + Alternative 1 (GPIO). + #0001 + + + 0010 + Alternative 2 (chip-specific). + #0010 + + + 0011 + Alternative 3 (chip-specific). + #0011 + + + 0100 + Alternative 4 (chip-specific). + #0100 + + + 0101 + Alternative 5 (chip-specific). + #0101 + + + 0110 + Alternative 6 (chip-specific). + #0110 + + + 0111 + Alternative 7 (chip-specific). + #0111 + + + 1000 + Alternative 8 (chip-specific). + #1000 + + + 1001 + Alternative 9 (chip-specific). + #1001 + + + 1010 + Alternative 10 (chip-specific). + #1010 + + + 1011 + Alternative 11 (chip-specific). + #1011 + + + 1100 + Alternative 12 (chip-specific). + #1100 + + + 1101 + Alternative 13 (chip-specific). + #1101 + + + 1110 + Alternative 14 (chip-specific). + #1110 + + + 1111 + Alternative 15 (chip-specific). + #1111 + + + + + IRQC + Interrupt Configuration + 16 + 4 + read-write + + + 0000 + Interrupt Status Flag (ISF) is disabled. + #0000 + + + 0001 + ISF flag and DMA request on rising edge. + #0001 + + + 0010 + ISF flag and DMA request on falling edge. + #0010 + + + 0011 + ISF flag and DMA request on either edge. + #0011 + + + 1000 + ISF flag and Interrupt when logic 0. + #1000 + + + 1001 + ISF flag and Interrupt on rising-edge. + #1001 + + + 1010 + ISF flag and Interrupt on falling-edge. + #1010 + + + 1011 + ISF flag and Interrupt on either edge. + #1011 + + + 1100 + ISF flag and Interrupt when logic 1. + #1100 + + + + + ISF + Interrupt Status Flag + 24 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + + + + + PCR2 + Pin Control Register 2 + 0x8 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + PS + Pull Select + 0 + 1 + read-write + + + 0 + Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. + #0 + + + 1 + Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. + #1 + + + + + PE + Pull Enable + 1 + 1 + read-write + + + SRE + Slew Rate Enable + 2 + 1 + read-write + + + 0 + Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. + #0 + + + 1 + Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. + #1 + + + + + DSE + Drive Strength Enable + 6 + 1 + read-write + + + 0 + Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. + #0 + + + 1 + High drive strength is configured on the corresponding pin, if pin is configured as a digital output. + #1 + + + + + MUX + Pin Mux Control + 8 + 4 + read-write + + + 0000 + Pin disabled (Alternative 0) (analog). + #0000 + + + 0001 + Alternative 1 (GPIO). + #0001 + + + 0010 + Alternative 2 (chip-specific). + #0010 + + + 0011 + Alternative 3 (chip-specific). + #0011 + + + 0100 + Alternative 4 (chip-specific). + #0100 + + + 0101 + Alternative 5 (chip-specific). + #0101 + + + 0110 + Alternative 6 (chip-specific). + #0110 + + + 0111 + Alternative 7 (chip-specific). + #0111 + + + 1000 + Alternative 8 (chip-specific). + #1000 + + + 1001 + Alternative 9 (chip-specific). + #1001 + + + 1010 + Alternative 10 (chip-specific). + #1010 + + + 1011 + Alternative 11 (chip-specific). + #1011 + + + 1100 + Alternative 12 (chip-specific). + #1100 + + + 1101 + Alternative 13 (chip-specific). + #1101 + + + 1110 + Alternative 14 (chip-specific). + #1110 + + + 1111 + Alternative 15 (chip-specific). + #1111 + + + + + IRQC + Interrupt Configuration + 16 + 4 + read-write + + + 0000 + Interrupt Status Flag (ISF) is disabled. + #0000 + + + 0001 + ISF flag and DMA request on rising edge. + #0001 + + + 0010 + ISF flag and DMA request on falling edge. + #0010 + + + 0011 + ISF flag and DMA request on either edge. + #0011 + + + 1000 + ISF flag and Interrupt when logic 0. + #1000 + + + 1001 + ISF flag and Interrupt on rising-edge. + #1001 + + + 1010 + ISF flag and Interrupt on falling-edge. + #1010 + + + 1011 + ISF flag and Interrupt on either edge. + #1011 + + + 1100 + ISF flag and Interrupt when logic 1. + #1100 + + + + + ISF + Interrupt Status Flag + 24 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + + + + + PCR3 + Pin Control Register 3 + 0xC + 32 + read-write + 0x5 + 0xFFFFFFFF + + + PS + Pull Select + 0 + 1 + read-write + + + 0 + Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. + #0 + + + 1 + Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. + #1 + + + + + PE + Pull Enable + 1 + 1 + read-write + + + SRE + Slew Rate Enable + 2 + 1 + read-write + + + 0 + Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. + #0 + + + 1 + Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. + #1 + + + + + DSE + Drive Strength Enable + 6 + 1 + read-write + + + 0 + Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. + #0 + + + 1 + High drive strength is configured on the corresponding pin, if pin is configured as a digital output. + #1 + + + + + MUX + Pin Mux Control + 8 + 4 + read-write + + + 0000 + Pin disabled (Alternative 0) (analog). + #0000 + + + 0001 + Alternative 1 (GPIO). + #0001 + + + 0010 + Alternative 2 (chip-specific). + #0010 + + + 0011 + Alternative 3 (chip-specific). + #0011 + + + 0100 + Alternative 4 (chip-specific). + #0100 + + + 0101 + Alternative 5 (chip-specific). + #0101 + + + 0110 + Alternative 6 (chip-specific). + #0110 + + + 0111 + Alternative 7 (chip-specific). + #0111 + + + 1000 + Alternative 8 (chip-specific). + #1000 + + + 1001 + Alternative 9 (chip-specific). + #1001 + + + 1010 + Alternative 10 (chip-specific). + #1010 + + + 1011 + Alternative 11 (chip-specific). + #1011 + + + 1100 + Alternative 12 (chip-specific). + #1100 + + + 1101 + Alternative 13 (chip-specific). + #1101 + + + 1110 + Alternative 14 (chip-specific). + #1110 + + + 1111 + Alternative 15 (chip-specific). + #1111 + + + + + IRQC + Interrupt Configuration + 16 + 4 + read-write + + + 0000 + Interrupt Status Flag (ISF) is disabled. + #0000 + + + 0001 + ISF flag and DMA request on rising edge. + #0001 + + + 0010 + ISF flag and DMA request on falling edge. + #0010 + + + 0011 + ISF flag and DMA request on either edge. + #0011 + + + 1000 + ISF flag and Interrupt when logic 0. + #1000 + + + 1001 + ISF flag and Interrupt on rising-edge. + #1001 + + + 1010 + ISF flag and Interrupt on falling-edge. + #1010 + + + 1011 + ISF flag and Interrupt on either edge. + #1011 + + + 1100 + ISF flag and Interrupt when logic 1. + #1100 + + + + + ISF + Interrupt Status Flag + 24 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + + + + + PCR4 + Pin Control Register 4 + 0x10 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + PS + Pull Select + 0 + 1 + read-write + + + 0 + Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. + #0 + + + 1 + Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. + #1 + + + + + PE + Pull Enable + 1 + 1 + read-write + + + SRE + Slew Rate Enable + 2 + 1 + read-write + + + 0 + Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. + #0 + + + 1 + Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. + #1 + + + + + DSE + Drive Strength Enable + 6 + 1 + read-write + + + 0 + Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. + #0 + + + 1 + High drive strength is configured on the corresponding pin, if pin is configured as a digital output. + #1 + + + + + MUX + Pin Mux Control + 8 + 4 + read-write + + + 0000 + Pin disabled (Alternative 0) (analog). + #0000 + + + 0001 + Alternative 1 (GPIO). + #0001 + + + 0010 + Alternative 2 (chip-specific). + #0010 + + + 0011 + Alternative 3 (chip-specific). + #0011 + + + 0100 + Alternative 4 (chip-specific). + #0100 + + + 0101 + Alternative 5 (chip-specific). + #0101 + + + 0110 + Alternative 6 (chip-specific). + #0110 + + + 0111 + Alternative 7 (chip-specific). + #0111 + + + 1000 + Alternative 8 (chip-specific). + #1000 + + + 1001 + Alternative 9 (chip-specific). + #1001 + + + 1010 + Alternative 10 (chip-specific). + #1010 + + + 1011 + Alternative 11 (chip-specific). + #1011 + + + 1100 + Alternative 12 (chip-specific). + #1100 + + + 1101 + Alternative 13 (chip-specific). + #1101 + + + 1110 + Alternative 14 (chip-specific). + #1110 + + + 1111 + Alternative 15 (chip-specific). + #1111 + + + + + IRQC + Interrupt Configuration + 16 + 4 + read-write + + + 0000 + Interrupt Status Flag (ISF) is disabled. + #0000 + + + 0001 + ISF flag and DMA request on rising edge. + #0001 + + + 0010 + ISF flag and DMA request on falling edge. + #0010 + + + 0011 + ISF flag and DMA request on either edge. + #0011 + + + 1000 + ISF flag and Interrupt when logic 0. + #1000 + + + 1001 + ISF flag and Interrupt on rising-edge. + #1001 + + + 1010 + ISF flag and Interrupt on falling-edge. + #1010 + + + 1011 + ISF flag and Interrupt on either edge. + #1011 + + + 1100 + ISF flag and Interrupt when logic 1. + #1100 + + + + + ISF + Interrupt Status Flag + 24 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + + + + + PCR5 + Pin Control Register 5 + 0x14 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + PS + Pull Select + 0 + 1 + read-write + + + 0 + Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. + #0 + + + 1 + Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. + #1 + + + + + PE + Pull Enable + 1 + 1 + read-write + + + SRE + Slew Rate Enable + 2 + 1 + read-write + + + 0 + Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. + #0 + + + 1 + Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. + #1 + + + + + MUX + Pin Mux Control + 8 + 4 + read-write + + + 0000 + Pin disabled (Alternative 0) (analog). + #0000 + + + 0001 + Alternative 1 (GPIO). + #0001 + + + 0010 + Alternative 2 (chip-specific). + #0010 + + + 0011 + Alternative 3 (chip-specific). + #0011 + + + 0100 + Alternative 4 (chip-specific). + #0100 + + + 0101 + Alternative 5 (chip-specific). + #0101 + + + 0110 + Alternative 6 (chip-specific). + #0110 + + + 0111 + Alternative 7 (chip-specific). + #0111 + + + 1000 + Alternative 8 (chip-specific). + #1000 + + + 1001 + Alternative 9 (chip-specific). + #1001 + + + 1010 + Alternative 10 (chip-specific). + #1010 + + + 1011 + Alternative 11 (chip-specific). + #1011 + + + 1100 + Alternative 12 (chip-specific). + #1100 + + + 1101 + Alternative 13 (chip-specific). + #1101 + + + 1110 + Alternative 14 (chip-specific). + #1110 + + + 1111 + Alternative 15 (chip-specific). + #1111 + + + + + IRQC + Interrupt Configuration + 16 + 4 + read-write + + + 0000 + Interrupt Status Flag (ISF) is disabled. + #0000 + + + 0001 + ISF flag and DMA request on rising edge. + #0001 + + + 0010 + ISF flag and DMA request on falling edge. + #0010 + + + 0011 + ISF flag and DMA request on either edge. + #0011 + + + 1000 + ISF flag and Interrupt when logic 0. + #1000 + + + 1001 + ISF flag and Interrupt on rising-edge. + #1001 + + + 1010 + ISF flag and Interrupt on falling-edge. + #1010 + + + 1011 + ISF flag and Interrupt on either edge. + #1011 + + + 1100 + ISF flag and Interrupt when logic 1. + #1100 + + + + + ISF + Interrupt Status Flag + 24 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + + + + + PCR6 + Pin Control Register 6 + 0x18 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + PS + Pull Select + 0 + 1 + read-write + + + 0 + Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. + #0 + + + 1 + Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. + #1 + + + + + PE + Pull Enable + 1 + 1 + read-write + + + SRE + Slew Rate Enable + 2 + 1 + read-write + + + 0 + Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. + #0 + + + 1 + Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. + #1 + + + + + DSE + Drive Strength Enable + 6 + 1 + read-write + + + 0 + Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. + #0 + + + 1 + High drive strength is configured on the corresponding pin, if pin is configured as a digital output. + #1 + + + + + MUX + Pin Mux Control + 8 + 4 + read-write + + + 0000 + Pin disabled (Alternative 0) (analog). + #0000 + + + 0001 + Alternative 1 (GPIO). + #0001 + + + 0010 + Alternative 2 (chip-specific). + #0010 + + + 0011 + Alternative 3 (chip-specific). + #0011 + + + 0100 + Alternative 4 (chip-specific). + #0100 + + + 0101 + Alternative 5 (chip-specific). + #0101 + + + 0110 + Alternative 6 (chip-specific). + #0110 + + + 0111 + Alternative 7 (chip-specific). + #0111 + + + 1000 + Alternative 8 (chip-specific). + #1000 + + + 1001 + Alternative 9 (chip-specific). + #1001 + + + 1010 + Alternative 10 (chip-specific). + #1010 + + + 1011 + Alternative 11 (chip-specific). + #1011 + + + 1100 + Alternative 12 (chip-specific). + #1100 + + + 1101 + Alternative 13 (chip-specific). + #1101 + + + 1110 + Alternative 14 (chip-specific). + #1110 + + + 1111 + Alternative 15 (chip-specific). + #1111 + + + + + IRQC + Interrupt Configuration + 16 + 4 + read-write + + + 0000 + Interrupt Status Flag (ISF) is disabled. + #0000 + + + 0001 + ISF flag and DMA request on rising edge. + #0001 + + + 0010 + ISF flag and DMA request on falling edge. + #0010 + + + 0011 + ISF flag and DMA request on either edge. + #0011 + + + 1000 + ISF flag and Interrupt when logic 0. + #1000 + + + 1001 + ISF flag and Interrupt on rising-edge. + #1001 + + + 1010 + ISF flag and Interrupt on falling-edge. + #1010 + + + 1011 + ISF flag and Interrupt on either edge. + #1011 + + + 1100 + ISF flag and Interrupt when logic 1. + #1100 + + + + + ISF + Interrupt Status Flag + 24 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + + + + + PCR7 + Pin Control Register 7 + 0x1C + 32 + read-write + 0x1 + 0xFFFFFFFF + + + PS + Pull Select + 0 + 1 + read-write + + + 0 + Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. + #0 + + + 1 + Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. + #1 + + + + + PE + Pull Enable + 1 + 1 + read-write + + + SRE + Slew Rate Enable + 2 + 1 + read-write + + + 0 + Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. + #0 + + + 1 + Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. + #1 + + + + + DSE + Drive Strength Enable + 6 + 1 + read-write + + + 0 + Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. + #0 + + + 1 + High drive strength is configured on the corresponding pin, if pin is configured as a digital output. + #1 + + + + + MUX + Pin Mux Control + 8 + 4 + read-write + + + 0000 + Pin disabled (Alternative 0) (analog). + #0000 + + + 0001 + Alternative 1 (GPIO). + #0001 + + + 0010 + Alternative 2 (chip-specific). + #0010 + + + 0011 + Alternative 3 (chip-specific). + #0011 + + + 0100 + Alternative 4 (chip-specific). + #0100 + + + 0101 + Alternative 5 (chip-specific). + #0101 + + + 0110 + Alternative 6 (chip-specific). + #0110 + + + 0111 + Alternative 7 (chip-specific). + #0111 + + + 1000 + Alternative 8 (chip-specific). + #1000 + + + 1001 + Alternative 9 (chip-specific). + #1001 + + + 1010 + Alternative 10 (chip-specific). + #1010 + + + 1011 + Alternative 11 (chip-specific). + #1011 + + + 1100 + Alternative 12 (chip-specific). + #1100 + + + 1101 + Alternative 13 (chip-specific). + #1101 + + + 1110 + Alternative 14 (chip-specific). + #1110 + + + 1111 + Alternative 15 (chip-specific). + #1111 + + + + + IRQC + Interrupt Configuration + 16 + 4 + read-write + + + 0000 + Interrupt Status Flag (ISF) is disabled. + #0000 + + + 0001 + ISF flag and DMA request on rising edge. + #0001 + + + 0010 + ISF flag and DMA request on falling edge. + #0010 + + + 0011 + ISF flag and DMA request on either edge. + #0011 + + + 1000 + ISF flag and Interrupt when logic 0. + #1000 + + + 1001 + ISF flag and Interrupt on rising-edge. + #1001 + + + 1010 + ISF flag and Interrupt on falling-edge. + #1010 + + + 1011 + ISF flag and Interrupt on either edge. + #1011 + + + 1100 + ISF flag and Interrupt when logic 1. + #1100 + + + + + ISF + Interrupt Status Flag + 24 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + + + + + PCR16 + Pin Control Register 16 + 0x40 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + PS + Pull Select + 0 + 1 + read-write + + + 0 + Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. + #0 + + + 1 + Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. + #1 + + + + + PE + Pull Enable + 1 + 1 + read-write + + + SRE + Slew Rate Enable + 2 + 1 + read-write + + + 0 + Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. + #0 + + + 1 + Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. + #1 + + + + + DSE + Drive Strength Enable + 6 + 1 + read-write + + + 0 + Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. + #0 + + + 1 + High drive strength is configured on the corresponding pin, if pin is configured as a digital output. + #1 + + + + + MUX + Pin Mux Control + 8 + 4 + read-write + + + 0000 + Pin disabled (Alternative 0) (analog). + #0000 + + + 0001 + Alternative 1 (GPIO). + #0001 + + + 0010 + Alternative 2 (chip-specific). + #0010 + + + 0011 + Alternative 3 (chip-specific). + #0011 + + + 0100 + Alternative 4 (chip-specific). + #0100 + + + 0101 + Alternative 5 (chip-specific). + #0101 + + + 0110 + Alternative 6 (chip-specific). + #0110 + + + 0111 + Alternative 7 (chip-specific). + #0111 + + + 1000 + Alternative 8 (chip-specific). + #1000 + + + 1001 + Alternative 9 (chip-specific). + #1001 + + + 1010 + Alternative 10 (chip-specific). + #1010 + + + 1011 + Alternative 11 (chip-specific). + #1011 + + + 1100 + Alternative 12 (chip-specific). + #1100 + + + 1101 + Alternative 13 (chip-specific). + #1101 + + + 1110 + Alternative 14 (chip-specific). + #1110 + + + 1111 + Alternative 15 (chip-specific). + #1111 + + + + + IRQC + Interrupt Configuration + 16 + 4 + read-write + + + 0000 + Interrupt Status Flag (ISF) is disabled. + #0000 + + + 0001 + ISF flag and DMA request on rising edge. + #0001 + + + 0010 + ISF flag and DMA request on falling edge. + #0010 + + + 0011 + ISF flag and DMA request on either edge. + #0011 + + + 1000 + ISF flag and Interrupt when logic 0. + #1000 + + + 1001 + ISF flag and Interrupt on rising-edge. + #1001 + + + 1010 + ISF flag and Interrupt on falling-edge. + #1010 + + + 1011 + ISF flag and Interrupt on either edge. + #1011 + + + 1100 + ISF flag and Interrupt when logic 1. + #1100 + + + + + ISF + Interrupt Status Flag + 24 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + + + + + PCR17 + Pin Control Register 17 + 0x44 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + PS + Pull Select + 0 + 1 + read-write + + + 0 + Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. + #0 + + + 1 + Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. + #1 + + + + + PE + Pull Enable + 1 + 1 + read-write + + + SRE + Slew Rate Enable + 2 + 1 + read-write + + + 0 + Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. + #0 + + + 1 + Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. + #1 + + + + + DSE + Drive Strength Enable + 6 + 1 + read-write + + + 0 + Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. + #0 + + + 1 + High drive strength is configured on the corresponding pin, if pin is configured as a digital output. + #1 + + + + + MUX + Pin Mux Control + 8 + 4 + read-write + + + 0000 + Pin disabled (Alternative 0) (analog). + #0000 + + + 0001 + Alternative 1 (GPIO). + #0001 + + + 0010 + Alternative 2 (chip-specific). + #0010 + + + 0011 + Alternative 3 (chip-specific). + #0011 + + + 0100 + Alternative 4 (chip-specific). + #0100 + + + 0101 + Alternative 5 (chip-specific). + #0101 + + + 0110 + Alternative 6 (chip-specific). + #0110 + + + 0111 + Alternative 7 (chip-specific). + #0111 + + + 1000 + Alternative 8 (chip-specific). + #1000 + + + 1001 + Alternative 9 (chip-specific). + #1001 + + + 1010 + Alternative 10 (chip-specific). + #1010 + + + 1011 + Alternative 11 (chip-specific). + #1011 + + + 1100 + Alternative 12 (chip-specific). + #1100 + + + 1101 + Alternative 13 (chip-specific). + #1101 + + + 1110 + Alternative 14 (chip-specific). + #1110 + + + 1111 + Alternative 15 (chip-specific). + #1111 + + + + + IRQC + Interrupt Configuration + 16 + 4 + read-write + + + 0000 + Interrupt Status Flag (ISF) is disabled. + #0000 + + + 0001 + ISF flag and DMA request on rising edge. + #0001 + + + 0010 + ISF flag and DMA request on falling edge. + #0010 + + + 0011 + ISF flag and DMA request on either edge. + #0011 + + + 1000 + ISF flag and Interrupt when logic 0. + #1000 + + + 1001 + ISF flag and Interrupt on rising-edge. + #1001 + + + 1010 + ISF flag and Interrupt on falling-edge. + #1010 + + + 1011 + ISF flag and Interrupt on either edge. + #1011 + + + 1100 + ISF flag and Interrupt when logic 1. + #1100 + + + + + ISF + Interrupt Status Flag + 24 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + + + + + PCR18 + Pin Control Register 18 + 0x48 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + PS + Pull Select + 0 + 1 + read-write + + + 0 + Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. + #0 + + + 1 + Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. + #1 + + + + + PE + Pull Enable + 1 + 1 + read-write + + + SRE + Slew Rate Enable + 2 + 1 + read-write + + + 0 + Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. + #0 + + + 1 + Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. + #1 + + + + + DSE + Drive Strength Enable + 6 + 1 + read-write + + + 0 + Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. + #0 + + + 1 + High drive strength is configured on the corresponding pin, if pin is configured as a digital output. + #1 + + + + + MUX + Pin Mux Control + 8 + 4 + read-write + + + 0000 + Pin disabled (Alternative 0) (analog). + #0000 + + + 0001 + Alternative 1 (GPIO). + #0001 + + + 0010 + Alternative 2 (chip-specific). + #0010 + + + 0011 + Alternative 3 (chip-specific). + #0011 + + + 0100 + Alternative 4 (chip-specific). + #0100 + + + 0101 + Alternative 5 (chip-specific). + #0101 + + + 0110 + Alternative 6 (chip-specific). + #0110 + + + 0111 + Alternative 7 (chip-specific). + #0111 + + + 1000 + Alternative 8 (chip-specific). + #1000 + + + 1001 + Alternative 9 (chip-specific). + #1001 + + + 1010 + Alternative 10 (chip-specific). + #1010 + + + 1011 + Alternative 11 (chip-specific). + #1011 + + + 1100 + Alternative 12 (chip-specific). + #1100 + + + 1101 + Alternative 13 (chip-specific). + #1101 + + + 1110 + Alternative 14 (chip-specific). + #1110 + + + 1111 + Alternative 15 (chip-specific). + #1111 + + + + + IRQC + Interrupt Configuration + 16 + 4 + read-write + + + 0000 + Interrupt Status Flag (ISF) is disabled. + #0000 + + + 0001 + ISF flag and DMA request on rising edge. + #0001 + + + 0010 + ISF flag and DMA request on falling edge. + #0010 + + + 0011 + ISF flag and DMA request on either edge. + #0011 + + + 1000 + ISF flag and Interrupt when logic 0. + #1000 + + + 1001 + ISF flag and Interrupt on rising-edge. + #1001 + + + 1010 + ISF flag and Interrupt on falling-edge. + #1010 + + + 1011 + ISF flag and Interrupt on either edge. + #1011 + + + 1100 + ISF flag and Interrupt when logic 1. + #1100 + + + + + ISF + Interrupt Status Flag + 24 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + + + + + PCR19 + Pin Control Register 19 + 0x4C + 32 + read-write + 0x1 + 0xFFFFFFFF + + + PS + Pull Select + 0 + 1 + read-write + + + 0 + Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. + #0 + + + 1 + Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. + #1 + + + + + PE + Pull Enable + 1 + 1 + read-write + + + SRE + Slew Rate Enable + 2 + 1 + read-write + + + 0 + Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. + #0 + + + 1 + Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. + #1 + + + + + DSE + Drive Strength Enable + 6 + 1 + read-write + + + 0 + Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. + #0 + + + 1 + High drive strength is configured on the corresponding pin, if pin is configured as a digital output. + #1 + + + + + MUX + Pin Mux Control + 8 + 4 + read-write + + + 0000 + Pin disabled (Alternative 0) (analog). + #0000 + + + 0001 + Alternative 1 (GPIO). + #0001 + + + 0010 + Alternative 2 (chip-specific). + #0010 + + + 0011 + Alternative 3 (chip-specific). + #0011 + + + 0100 + Alternative 4 (chip-specific). + #0100 + + + 0101 + Alternative 5 (chip-specific). + #0101 + + + 0110 + Alternative 6 (chip-specific). + #0110 + + + 0111 + Alternative 7 (chip-specific). + #0111 + + + 1000 + Alternative 8 (chip-specific). + #1000 + + + 1001 + Alternative 9 (chip-specific). + #1001 + + + 1010 + Alternative 10 (chip-specific). + #1010 + + + 1011 + Alternative 11 (chip-specific). + #1011 + + + 1100 + Alternative 12 (chip-specific). + #1100 + + + 1101 + Alternative 13 (chip-specific). + #1101 + + + 1110 + Alternative 14 (chip-specific). + #1110 + + + 1111 + Alternative 15 (chip-specific). + #1111 + + + + + IRQC + Interrupt Configuration + 16 + 4 + read-write + + + 0000 + Interrupt Status Flag (ISF) is disabled. + #0000 + + + 0001 + ISF flag and DMA request on rising edge. + #0001 + + + 0010 + ISF flag and DMA request on falling edge. + #0010 + + + 0011 + ISF flag and DMA request on either edge. + #0011 + + + 1000 + ISF flag and Interrupt when logic 0. + #1000 + + + 1001 + ISF flag and Interrupt on rising-edge. + #1001 + + + 1010 + ISF flag and Interrupt on falling-edge. + #1010 + + + 1011 + ISF flag and Interrupt on either edge. + #1011 + + + 1100 + ISF flag and Interrupt when logic 1. + #1100 + + + + + ISF + Interrupt Status Flag + 24 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + + + + + PCR31 + Pin Control Register 31 + 0x7C + 32 + read-write + 0 + 0xFFFFFFFF + + + IRQC + Interrupt Configuration + 16 + 4 + read-write + + + 0000 + Interrupt Status Flag (ISF) is disabled. + #0000 + + + 0001 + ISF flag and DMA request on rising edge. + #0001 + + + 0010 + ISF flag and DMA request on falling edge. + #0010 + + + 0011 + ISF flag and DMA request on either edge. + #0011 + + + 1000 + ISF flag and Interrupt when logic 0. + #1000 + + + 1001 + ISF flag and Interrupt on rising-edge. + #1001 + + + 1010 + ISF flag and Interrupt on falling-edge. + #1010 + + + 1011 + ISF flag and Interrupt on either edge. + #1011 + + + 1100 + ISF flag and Interrupt when logic 1. + #1100 + + + + + ISF + Interrupt Status Flag + 24 + 1 + read-write + + + 0 + Configured interrupt is not detected. + #0 + + + + + + + GPCLR + Global Pin Control Low Register + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + GPWD + Global Pin Write Data + 0 + 16 + read-write + + + GPWE + Global Pin Write Enable + 16 + 16 + read-write + + + + + GPCHR + Global Pin Control High Register + 0x84 + 32 + read-write + 0 + 0xFFFFFFFF + + + GPWD + Global Pin Write Data + 0 + 16 + read-write + + + GPWE + Global Pin Write Enable + 16 + 16 + read-write + + + + + GICLR + Global Interrupt Control Low Register + 0x88 + 32 + read-write + 0 + 0xFFFFFFFF + + + GIWE + Global Interrupt Write Enable + 0 + 16 + read-write + + + GIWD + Global Interrupt Write Data + 16 + 16 + read-write + + + + + GICHR + Global Interrupt Control High Register + 0x8C + 32 + read-write + 0 + 0xFFFFFFFF + + + GIWE + Global Interrupt Write Enable + 0 + 16 + read-write + + + GIWD + Global Interrupt Write Data + 16 + 16 + read-write + + + + + ISFR + Interrupt Status Flag Register + 0xA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + ISF + Interrupt Status Flag + 0 + 32 + read-write + + + + + + + LPUART0 + Universal Asynchronous Receiver/Transmitter + LPUART + LPUART0_ + 0x40054000 + + 0 + 0x20 + registers + + + LPUART0_LPUART1 + 12 + + + + BAUD + LPUART Baud Rate Register + 0 + 32 + read-write + 0xF000004 + 0xFFFFFFFF + + + SBR + Baud Rate Modulo Divisor. + 0 + 13 + read-write + + + SBNS + Stop Bit Number Select + 13 + 1 + read-write + + + 0 + One stop bit. + #0 + + + 1 + Two stop bits. + #1 + + + + + RXEDGIE + RX Input Active Edge Interrupt Enable + 14 + 1 + read-write + + + 0 + Hardware interrupts from LPUART_STAT[RXEDGIF] disabled (use polling). + #0 + + + 1 + Hardware interrupt requested when LPUART_STAT[RXEDGIF] flag is 1. + #1 + + + + + LBKDIE + LIN Break Detect Interrupt Enable + 15 + 1 + read-write + + + 0 + Hardware interrupts from LPUART_STAT[LBKDIF] disabled (use polling). + #0 + + + 1 + Hardware interrupt requested when LPUART_STAT[LBKDIF] flag is 1. + #1 + + + + + RESYNCDIS + Resynchronization Disable + 16 + 1 + read-write + + + 0 + Resynchronization during received data word is supported + #0 + + + 1 + Resynchronization during received data word is disabled + #1 + + + + + BOTHEDGE + Both Edge Sampling + 17 + 1 + read-write + + + 0 + Receiver samples input data using the rising edge of the baud rate clock. + #0 + + + 1 + Receiver samples input data using the rising and falling edge of the baud rate clock. + #1 + + + + + MATCFG + Match Configuration + 18 + 2 + read-write + + + 00 + Address Match Wakeup + #00 + + + 01 + Idle Match Wakeup + #01 + + + 10 + Match On and Match Off + #10 + + + 11 + Enables RWU on Data Match and Match On/Off for transmitter CTS input + #11 + + + + + RDMAE + Receiver Full DMA Enable + 21 + 1 + read-write + + + 0 + DMA request disabled. + #0 + + + 1 + DMA request enabled. + #1 + + + + + TDMAE + Transmitter DMA Enable + 23 + 1 + read-write + + + 0 + DMA request disabled. + #0 + + + 1 + DMA request enabled. + #1 + + + + + OSR + Oversampling Ratio + 24 + 5 + read-write + + + M10 + 10-bit Mode select + 29 + 1 + read-write + + + 0 + Receiver and transmitter use 8-bit or 9-bit data characters. + #0 + + + 1 + Receiver and transmitter use 10-bit data characters. + #1 + + + + + MAEN2 + Match Address Mode Enable 2 + 30 + 1 + read-write + + + 0 + Normal operation. + #0 + + + 1 + Enables automatic address matching or data matching mode for MATCH[MA2]. + #1 + + + + + MAEN1 + Match Address Mode Enable 1 + 31 + 1 + read-write + + + 0 + Normal operation. + #0 + + + 1 + Enables automatic address matching or data matching mode for MATCH[MA1]. + #1 + + + + + + + STAT + LPUART Status Register + 0x4 + 32 + read-write + 0xC00000 + 0xFFFFFFFF + + + MA2F + Match 2 Flag + 14 + 1 + read-write + + + 0 + Received data is not equal to MA2 + #0 + + + 1 + Received data is equal to MA2 + #1 + + + + + MA1F + Match 1 Flag + 15 + 1 + read-write + + + 0 + Received data is not equal to MA1 + #0 + + + 1 + Received data is equal to MA1 + #1 + + + + + PF + Parity Error Flag + 16 + 1 + read-write + + + 0 + No parity error. + #0 + + + 1 + Parity error. + #1 + + + + + FE + Framing Error Flag + 17 + 1 + read-write + + + 0 + No framing error detected. This does not guarantee the framing is correct. + #0 + + + 1 + Framing error. + #1 + + + + + NF + Noise Flag + 18 + 1 + read-write + + + 0 + No noise detected. + #0 + + + 1 + Noise detected in the received character in LPUART_DATA. + #1 + + + + + OR + Receiver Overrun Flag + 19 + 1 + read-write + + + 0 + No overrun. + #0 + + + 1 + Receive overrun (new LPUART data lost). + #1 + + + + + IDLE + Idle Line Flag + 20 + 1 + read-write + + + 0 + No idle line detected. + #0 + + + 1 + Idle line was detected. + #1 + + + + + RDRF + Receive Data Register Full Flag + 21 + 1 + read-only + + + 0 + Receive data buffer empty. + #0 + + + 1 + Receive data buffer full. + #1 + + + + + TC + Transmission Complete Flag + 22 + 1 + read-only + + + 0 + Transmitter active (sending data, a preamble, or a break). + #0 + + + 1 + Transmitter idle (transmission activity complete). + #1 + + + + + TDRE + Transmit Data Register Empty Flag + 23 + 1 + read-only + + + 0 + Transmit data buffer full. + #0 + + + 1 + Transmit data buffer empty. + #1 + + + + + RAF + Receiver Active Flag + 24 + 1 + read-only + + + 0 + LPUART receiver idle waiting for a start bit. + #0 + + + 1 + LPUART receiver active (LPUART_RX input not idle). + #1 + + + + + LBKDE + LIN Break Detection Enable + 25 + 1 + read-write + + + 0 + Break character is detected at length 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 13 (if M10 = 1, SNBS = 1). + #0 + + + 1 + Break character is detected at length of 11 bit times (if M = 0, SBNS = 0) or 12 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 14 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 15 (if M10 = 1, SNBS = 1). + #1 + + + + + BRK13 + Break Character Generation Length + 26 + 1 + read-write + + + 0 + Break character is transmitted with length of 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 13 (if M10 = 1, SNBS = 1). + #0 + + + 1 + Break character is transmitted with length of 13 bit times (if M = 0, SBNS = 0) or 14 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 15 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 16 (if M10 = 1, SNBS = 1). + #1 + + + + + RWUID + Receive Wake Up Idle Detect + 27 + 1 + read-write + + + 0 + During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle character. During address match wakeup, the IDLE bit does not get set when an address does not match. + #0 + + + 1 + During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character. During address match wakeup, the IDLE bit does get set when an address does not match. + #1 + + + + + RXINV + Receive Data Inversion + 28 + 1 + read-write + + + 0 + Receive data not inverted. + #0 + + + 1 + Receive data inverted. + #1 + + + + + MSBF + MSB First + 29 + 1 + read-write + + + 0 + LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0. + #0 + + + 1 + MSB (bit9, bit8, bit7 or bit6) is the first bit that is transmitted following the start bit depending on the setting of CTRL[M], CTRL[PE] and BAUD[M10]. Further, the first bit received after the start bit is identified as bit9, bit8, bit7 or bit6 depending on the setting of CTRL[M] and CTRL[PE]. + #1 + + + + + RXEDGIF + LPUART_RX Pin Active Edge Interrupt Flag + 30 + 1 + read-write + + + 0 + No active edge on the receive pin has occurred. + #0 + + + 1 + An active edge on the receive pin has occurred. + #1 + + + + + LBKDIF + LIN Break Detect Interrupt Flag + 31 + 1 + read-write + + + 0 + No LIN break character has been detected. + #0 + + + 1 + LIN break character has been detected. + #1 + + + + + + + CTRL + LPUART Control Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + PT + Parity Type + 0 + 1 + read-write + + + 0 + Even parity. + #0 + + + 1 + Odd parity. + #1 + + + + + PE + Parity Enable + 1 + 1 + read-write + + + 0 + No hardware parity generation or checking. + #0 + + + 1 + Parity enabled. + #1 + + + + + ILT + Idle Line Type Select + 2 + 1 + read-write + + + 0 + Idle character bit count starts after start bit. + #0 + + + 1 + Idle character bit count starts after stop bit. + #1 + + + + + WAKE + Receiver Wakeup Method Select + 3 + 1 + read-write + + + 0 + Configures RWU for idle-line wakeup. + #0 + + + 1 + Configures RWU with address-mark wakeup. + #1 + + + + + M + 9-Bit or 8-Bit Mode Select + 4 + 1 + read-write + + + 0 + Receiver and transmitter use 8-bit data characters. + #0 + + + 1 + Receiver and transmitter use 9-bit data characters. + #1 + + + + + RSRC + Receiver Source Select + 5 + 1 + read-write + + + 0 + Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the LPUART does not use the LPUART_RX pin. + #0 + + + 1 + Single-wire LPUART mode where the LPUART_TX pin is connected to the transmitter output and receiver input. + #1 + + + + + DOZEEN + Doze Enable + 6 + 1 + read-write + + + 0 + LPUART is enabled in Doze mode. + #0 + + + 1 + LPUART is disabled in Doze mode. + #1 + + + + + LOOPS + Loop Mode Select + 7 + 1 + read-write + + + 0 + Normal operation - LPUART_RX and LPUART_TX use separate pins. + #0 + + + 1 + Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input (see RSRC bit). + #1 + + + + + IDLECFG + Idle Configuration + 8 + 3 + read-write + + + 000 + 1 idle character + #000 + + + 001 + 2 idle characters + #001 + + + 010 + 4 idle characters + #010 + + + 011 + 8 idle characters + #011 + + + 100 + 16 idle characters + #100 + + + 101 + 32 idle characters + #101 + + + 110 + 64 idle characters + #110 + + + 111 + 128 idle characters + #111 + + + + + MA2IE + Match 2 Interrupt Enable + 14 + 1 + read-write + + + 0 + MA2F interrupt disabled + #0 + + + 1 + MA2F interrupt enabled + #1 + + + + + MA1IE + Match 1 Interrupt Enable + 15 + 1 + read-write + + + 0 + MA1F interrupt disabled + #0 + + + 1 + MA1F interrupt enabled + #1 + + + + + SBK + Send Break + 16 + 1 + read-write + + + 0 + Normal transmitter operation. + #0 + + + 1 + Queue break character(s) to be sent. + #1 + + + + + RWU + Receiver Wakeup Control + 17 + 1 + read-write + + + 0 + Normal receiver operation. + #0 + + + 1 + LPUART receiver in standby waiting for wakeup condition. + #1 + + + + + RE + Receiver Enable + 18 + 1 + read-write + + + 0 + Receiver disabled. + #0 + + + 1 + Receiver enabled. + #1 + + + + + TE + Transmitter Enable + 19 + 1 + read-write + + + 0 + Transmitter disabled. + #0 + + + 1 + Transmitter enabled. + #1 + + + + + ILIE + Idle Line Interrupt Enable + 20 + 1 + read-write + + + 0 + Hardware interrupts from IDLE disabled; use polling. + #0 + + + 1 + Hardware interrupt requested when IDLE flag is 1. + #1 + + + + + RIE + Receiver Interrupt Enable + 21 + 1 + read-write + + + 0 + Hardware interrupts from RDRF disabled; use polling. + #0 + + + 1 + Hardware interrupt requested when RDRF flag is 1. + #1 + + + + + TCIE + Transmission Complete Interrupt Enable for + 22 + 1 + read-write + + + 0 + Hardware interrupts from TC disabled; use polling. + #0 + + + 1 + Hardware interrupt requested when TC flag is 1. + #1 + + + + + TIE + Transmit Interrupt Enable + 23 + 1 + read-write + + + 0 + Hardware interrupts from TDRE disabled; use polling. + #0 + + + 1 + Hardware interrupt requested when TDRE flag is 1. + #1 + + + + + PEIE + Parity Error Interrupt Enable + 24 + 1 + read-write + + + 0 + PF interrupts disabled; use polling). + #0 + + + 1 + Hardware interrupt requested when PF is set. + #1 + + + + + FEIE + Framing Error Interrupt Enable + 25 + 1 + read-write + + + 0 + FE interrupts disabled; use polling. + #0 + + + 1 + Hardware interrupt requested when FE is set. + #1 + + + + + NEIE + Noise Error Interrupt Enable + 26 + 1 + read-write + + + 0 + NF interrupts disabled; use polling. + #0 + + + 1 + Hardware interrupt requested when NF is set. + #1 + + + + + ORIE + Overrun Interrupt Enable + 27 + 1 + read-write + + + 0 + OR interrupts disabled; use polling. + #0 + + + 1 + Hardware interrupt requested when OR is set. + #1 + + + + + TXINV + Transmit Data Inversion + 28 + 1 + read-write + + + 0 + Transmit data not inverted. + #0 + + + 1 + Transmit data inverted. + #1 + + + + + TXDIR + LPUART_TX Pin Direction in Single-Wire Mode + 29 + 1 + read-write + + + 0 + LPUART_TX pin is an input in single-wire mode. + #0 + + + 1 + LPUART_TX pin is an output in single-wire mode. + #1 + + + + + R9T8 + Receive Bit 9 / Transmit Bit 8 + 30 + 1 + read-write + + + R8T9 + Receive Bit 8 / Transmit Bit 9 + 31 + 1 + read-write + + + + + DATA + LPUART Data Register + 0xC + 32 + read-write + 0x1000 + 0xFFFFFFFF + + + R0T0 + Read receive data buffer 0 or write transmit data buffer 0. + 0 + 1 + read-write + + + R1T1 + Read receive data buffer 1 or write transmit data buffer 1. + 1 + 1 + read-write + + + R2T2 + Read receive data buffer 2 or write transmit data buffer 2. + 2 + 1 + read-write + + + R3T3 + Read receive data buffer 3 or write transmit data buffer 3. + 3 + 1 + read-write + + + R4T4 + Read receive data buffer 4 or write transmit data buffer 4. + 4 + 1 + read-write + + + R5T5 + Read receive data buffer 5 or write transmit data buffer 5. + 5 + 1 + read-write + + + R6T6 + Read receive data buffer 6 or write transmit data buffer 6. + 6 + 1 + read-write + + + R7T7 + Read receive data buffer 7 or write transmit data buffer 7. + 7 + 1 + read-write + + + R8T8 + Read receive data buffer 8 or write transmit data buffer 8. + 8 + 1 + read-write + + + R9T9 + Read receive data buffer 9 or write transmit data buffer 9. + 9 + 1 + read-write + + + IDLINE + Idle Line + 11 + 1 + read-only + + + 0 + Receiver was not idle before receiving this character. + #0 + + + 1 + Receiver was idle before receiving this character. + #1 + + + + + RXEMPT + Receive Buffer Empty + 12 + 1 + read-only + + + 0 + Receive buffer contains valid data. + #0 + + + 1 + Receive buffer is empty, data returned on read is not valid. + #1 + + + + + FRETSC + Frame Error / Transmit Special Character + 13 + 1 + read-write + + + 0 + The dataword was received without a frame error on read, transmit a normal character on write. + #0 + + + 1 + The dataword was received with a frame error, transmit an idle or break character on transmit. + #1 + + + + + PARITYE + The current received dataword contained in DATA[R9:R0] was received with a parity error. + 14 + 1 + read-only + + + 0 + The dataword was received without a parity error. + #0 + + + 1 + The dataword was received with a parity error. + #1 + + + + + NOISY + The current received dataword contained in DATA[R9:R0] was received with noise. + 15 + 1 + read-only + + + 0 + The dataword was received without noise. + #0 + + + 1 + The data was received with noise. + #1 + + + + + + + MATCH + LPUART Match Address Register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + MA1 + Match Address 1 + 0 + 10 + read-write + + + MA2 + Match Address 2 + 16 + 10 + read-write + + + + + MODIR + LPUART Modem IrDA Register + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + TXCTSE + Transmitter clear-to-send enable + 0 + 1 + read-write + + + 0 + CTS has no effect on the transmitter. + #0 + + + 1 + Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission. + #1 + + + + + TXRTSE + Transmitter request-to-send enable + 1 + 1 + read-write + + + 0 + The transmitter has no effect on RTS. + #0 + + + 1 + When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and shift register are completely sent, including the last stop bit. + #1 + + + + + TXRTSPOL + Transmitter request-to-send polarity + 2 + 1 + read-write + + + 0 + Transmitter RTS is active low. + #0 + + + 1 + Transmitter RTS is active high. + #1 + + + + + RXRTSE + Receiver request-to-send enable + 3 + 1 + read-write + + + 0 + The receiver has no effect on RTS. + #0 + + + 1 + RTS assertion is configured by the RTSWATER field + #1 + + + + + TXCTSC + Transmit CTS Configuration + 4 + 1 + read-write + + + 0 + CTS input is sampled at the start of each character. + #0 + + + 1 + CTS input is sampled when the transmitter is idle. + #1 + + + + + TXCTSSRC + Transmit CTS Source + 5 + 1 + read-write + + + 0 + CTS input is the LPUART_CTS pin. + #0 + + + 1 + CTS input is the inverted Receiver Match result. + #1 + + + + + RTSWATER + Receive RTS Configuration + 8 + 8 + read-write + + + 0 + RTS asserts when the receiver FIFO is full or receiving a character that causes the FIFO to become full. + #0 + + + 1 + RTS asserts when the receive FIFO is less than or equal to the RXWATER configuration and negates when the receive FIFO is greater than the RXWATER configuration. + #1 + + + + + TNP + Transmitter narrow pulse + 16 + 2 + read-write + + + 00 + 1/OSR. + #00 + + + 01 + 2/OSR. + #01 + + + 10 + 3/OSR. + #10 + + + 11 + 4/OSR. + #11 + + + + + IREN + Infrared enable + 18 + 1 + read-write + + + 0 + IR disabled. + #0 + + + 1 + IR enabled. + #1 + + + + + + + FIFO + LPUART FIFO Register + 0x18 + 32 + read-write + 0xC00022 + 0xFFFFFFFF + + + RXFIFOSIZE + Receive FIFO. Buffer Depth + 0 + 3 + read-only + + + 10 + Receive FIFO/Buffer depth = 8 datawords. + #010 + + + + + RXFE + Receive FIFO Enable + 3 + 1 + read-write + + + 0 + Receive FIFO is not enabled. Buffer is depth 1. (Legacy support) + #0 + + + 1 + Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE. + #1 + + + + + TXFIFOSIZE + Transmit FIFO. Buffer Depth + 4 + 3 + read-only + + + 10 + Transmit FIFO/Buffer depth = 8 datawords. + #010 + + + + + TXFE + Transmit FIFO Enable + 7 + 1 + read-write + + + 0 + Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support). + #0 + + + 1 + Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE. + #1 + + + + + RXUFE + Receive FIFO Underflow Interrupt Enable + 8 + 1 + read-write + + + 0 + RXUF flag does not generate an interrupt to the host. + #0 + + + 1 + RXUF flag generates an interrupt to the host. + #1 + + + + + TXOFE + Transmit FIFO Overflow Interrupt Enable + 9 + 1 + read-write + + + 0 + TXOF flag does not generate an interrupt to the host. + #0 + + + 1 + TXOF flag generates an interrupt to the host. + #1 + + + + + RXIDEN + Receiver Idle Empty Enable + 10 + 3 + read-write + + + 000 + Disable RDRF assertion due to partially filled FIFO when receiver is idle. + #000 + + + 001 + Enable RDRF assertion due to partially filled FIFO when receiver is idle for 1 character. + #001 + + + 010 + Enable RDRF assertion due to partially filled FIFO when receiver is idle for 2 characters. + #010 + + + 011 + Enable RDRF assertion due to partially filled FIFO when receiver is idle for 4 characters. + #011 + + + 100 + Enable RDRF assertion due to partially filled FIFO when receiver is idle for 8 characters. + #100 + + + 101 + Enable RDRF assertion due to partially filled FIFO when receiver is idle for 16 characters. + #101 + + + 110 + Enable RDRF assertion due to partially filled FIFO when receiver is idle for 32 characters. + #110 + + + 111 + Enable RDRF assertion due to partially filled FIFO when receiver is idle for 64 characters. + #111 + + + + + RXFLUSH + Receive FIFO/Buffer Flush + 14 + 1 + read-write + + + 0 + No flush operation occurs. + #0 + + + 1 + All data in the receive FIFO/buffer is cleared out. + #1 + + + + + TXFLUSH + Transmit FIFO/Buffer Flush + 15 + 1 + read-write + + + 0 + No flush operation occurs. + #0 + + + 1 + All data in the transmit FIFO/Buffer is cleared out. + #1 + + + + + RXUF + Receiver Buffer Underflow Flag + 16 + 1 + read-write + + + 0 + No receive buffer underflow has occurred since the last time the flag was cleared. + #0 + + + 1 + At least one receive buffer underflow has occurred since the last time the flag was cleared. + #1 + + + + + TXOF + Transmitter Buffer Overflow Flag + 17 + 1 + read-write + + + 0 + No transmit buffer overflow has occurred since the last time the flag was cleared. + #0 + + + 1 + At least one transmit buffer overflow has occurred since the last time the flag was cleared. + #1 + + + + + RXEMPT + Receive Buffer/FIFO Empty + 22 + 1 + read-only + + + 0 + Receive buffer is not empty. + #0 + + + 1 + Receive buffer is empty. + #1 + + + + + TXEMPT + Transmit Buffer/FIFO Empty + 23 + 1 + read-only + + + 0 + Transmit buffer is not empty. + #0 + + + 1 + Transmit buffer is empty. + #1 + + + + + + + WATER + LPUART Watermark Register + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + TXWATER + Transmit Watermark + 0 + 8 + read-write + + + TXCOUNT + Transmit Counter + 8 + 8 + read-only + + + RXWATER + Receive Watermark + 16 + 8 + read-write + + + RXCOUNT + Receive Counter + 24 + 8 + read-only + + + + + + + LPUART1 + Universal Asynchronous Receiver/Transmitter + LPUART + LPUART1_ + 0x40055000 + + 0 + 0x20 + registers + + + LPUART0_LPUART1 + 12 + + + + BAUD + LPUART Baud Rate Register + 0 + 32 + read-write + 0xF000004 + 0xFFFFFFFF + + + SBR + Baud Rate Modulo Divisor. + 0 + 13 + read-write + + + SBNS + Stop Bit Number Select + 13 + 1 + read-write + + + 0 + One stop bit. + #0 + + + 1 + Two stop bits. + #1 + + + + + RXEDGIE + RX Input Active Edge Interrupt Enable + 14 + 1 + read-write + + + 0 + Hardware interrupts from LPUART_STAT[RXEDGIF] disabled (use polling). + #0 + + + 1 + Hardware interrupt requested when LPUART_STAT[RXEDGIF] flag is 1. + #1 + + + + + LBKDIE + LIN Break Detect Interrupt Enable + 15 + 1 + read-write + + + 0 + Hardware interrupts from LPUART_STAT[LBKDIF] disabled (use polling). + #0 + + + 1 + Hardware interrupt requested when LPUART_STAT[LBKDIF] flag is 1. + #1 + + + + + RESYNCDIS + Resynchronization Disable + 16 + 1 + read-write + + + 0 + Resynchronization during received data word is supported + #0 + + + 1 + Resynchronization during received data word is disabled + #1 + + + + + BOTHEDGE + Both Edge Sampling + 17 + 1 + read-write + + + 0 + Receiver samples input data using the rising edge of the baud rate clock. + #0 + + + 1 + Receiver samples input data using the rising and falling edge of the baud rate clock. + #1 + + + + + MATCFG + Match Configuration + 18 + 2 + read-write + + + 00 + Address Match Wakeup + #00 + + + 01 + Idle Match Wakeup + #01 + + + 10 + Match On and Match Off + #10 + + + 11 + Enables RWU on Data Match and Match On/Off for transmitter CTS input + #11 + + + + + RDMAE + Receiver Full DMA Enable + 21 + 1 + read-write + + + 0 + DMA request disabled. + #0 + + + 1 + DMA request enabled. + #1 + + + + + TDMAE + Transmitter DMA Enable + 23 + 1 + read-write + + + 0 + DMA request disabled. + #0 + + + 1 + DMA request enabled. + #1 + + + + + OSR + Oversampling Ratio + 24 + 5 + read-write + + + M10 + 10-bit Mode select + 29 + 1 + read-write + + + 0 + Receiver and transmitter use 8-bit or 9-bit data characters. + #0 + + + 1 + Receiver and transmitter use 10-bit data characters. + #1 + + + + + MAEN2 + Match Address Mode Enable 2 + 30 + 1 + read-write + + + 0 + Normal operation. + #0 + + + 1 + Enables automatic address matching or data matching mode for MATCH[MA2]. + #1 + + + + + MAEN1 + Match Address Mode Enable 1 + 31 + 1 + read-write + + + 0 + Normal operation. + #0 + + + 1 + Enables automatic address matching or data matching mode for MATCH[MA1]. + #1 + + + + + + + STAT + LPUART Status Register + 0x4 + 32 + read-write + 0xC00000 + 0xFFFFFFFF + + + MA2F + Match 2 Flag + 14 + 1 + read-write + + + 0 + Received data is not equal to MA2 + #0 + + + 1 + Received data is equal to MA2 + #1 + + + + + MA1F + Match 1 Flag + 15 + 1 + read-write + + + 0 + Received data is not equal to MA1 + #0 + + + 1 + Received data is equal to MA1 + #1 + + + + + PF + Parity Error Flag + 16 + 1 + read-write + + + 0 + No parity error. + #0 + + + 1 + Parity error. + #1 + + + + + FE + Framing Error Flag + 17 + 1 + read-write + + + 0 + No framing error detected. This does not guarantee the framing is correct. + #0 + + + 1 + Framing error. + #1 + + + + + NF + Noise Flag + 18 + 1 + read-write + + + 0 + No noise detected. + #0 + + + 1 + Noise detected in the received character in LPUART_DATA. + #1 + + + + + OR + Receiver Overrun Flag + 19 + 1 + read-write + + + 0 + No overrun. + #0 + + + 1 + Receive overrun (new LPUART data lost). + #1 + + + + + IDLE + Idle Line Flag + 20 + 1 + read-write + + + 0 + No idle line detected. + #0 + + + 1 + Idle line was detected. + #1 + + + + + RDRF + Receive Data Register Full Flag + 21 + 1 + read-only + + + 0 + Receive data buffer empty. + #0 + + + 1 + Receive data buffer full. + #1 + + + + + TC + Transmission Complete Flag + 22 + 1 + read-only + + + 0 + Transmitter active (sending data, a preamble, or a break). + #0 + + + 1 + Transmitter idle (transmission activity complete). + #1 + + + + + TDRE + Transmit Data Register Empty Flag + 23 + 1 + read-only + + + 0 + Transmit data buffer full. + #0 + + + 1 + Transmit data buffer empty. + #1 + + + + + RAF + Receiver Active Flag + 24 + 1 + read-only + + + 0 + LPUART receiver idle waiting for a start bit. + #0 + + + 1 + LPUART receiver active (LPUART_RX input not idle). + #1 + + + + + LBKDE + LIN Break Detection Enable + 25 + 1 + read-write + + + 0 + Break character is detected at length 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 13 (if M10 = 1, SNBS = 1). + #0 + + + 1 + Break character is detected at length of 11 bit times (if M = 0, SBNS = 0) or 12 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 14 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 15 (if M10 = 1, SNBS = 1). + #1 + + + + + BRK13 + Break Character Generation Length + 26 + 1 + read-write + + + 0 + Break character is transmitted with length of 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 13 (if M10 = 1, SNBS = 1). + #0 + + + 1 + Break character is transmitted with length of 13 bit times (if M = 0, SBNS = 0) or 14 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 15 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 16 (if M10 = 1, SNBS = 1). + #1 + + + + + RWUID + Receive Wake Up Idle Detect + 27 + 1 + read-write + + + 0 + During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle character. During address match wakeup, the IDLE bit does not get set when an address does not match. + #0 + + + 1 + During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character. During address match wakeup, the IDLE bit does get set when an address does not match. + #1 + + + + + RXINV + Receive Data Inversion + 28 + 1 + read-write + + + 0 + Receive data not inverted. + #0 + + + 1 + Receive data inverted. + #1 + + + + + MSBF + MSB First + 29 + 1 + read-write + + + 0 + LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0. + #0 + + + 1 + MSB (bit9, bit8, bit7 or bit6) is the first bit that is transmitted following the start bit depending on the setting of CTRL[M], CTRL[PE] and BAUD[M10]. Further, the first bit received after the start bit is identified as bit9, bit8, bit7 or bit6 depending on the setting of CTRL[M] and CTRL[PE]. + #1 + + + + + RXEDGIF + LPUART_RX Pin Active Edge Interrupt Flag + 30 + 1 + read-write + + + 0 + No active edge on the receive pin has occurred. + #0 + + + 1 + An active edge on the receive pin has occurred. + #1 + + + + + LBKDIF + LIN Break Detect Interrupt Flag + 31 + 1 + read-write + + + 0 + No LIN break character has been detected. + #0 + + + 1 + LIN break character has been detected. + #1 + + + + + + + CTRL + LPUART Control Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + PT + Parity Type + 0 + 1 + read-write + + + 0 + Even parity. + #0 + + + 1 + Odd parity. + #1 + + + + + PE + Parity Enable + 1 + 1 + read-write + + + 0 + No hardware parity generation or checking. + #0 + + + 1 + Parity enabled. + #1 + + + + + ILT + Idle Line Type Select + 2 + 1 + read-write + + + 0 + Idle character bit count starts after start bit. + #0 + + + 1 + Idle character bit count starts after stop bit. + #1 + + + + + WAKE + Receiver Wakeup Method Select + 3 + 1 + read-write + + + 0 + Configures RWU for idle-line wakeup. + #0 + + + 1 + Configures RWU with address-mark wakeup. + #1 + + + + + M + 9-Bit or 8-Bit Mode Select + 4 + 1 + read-write + + + 0 + Receiver and transmitter use 8-bit data characters. + #0 + + + 1 + Receiver and transmitter use 9-bit data characters. + #1 + + + + + RSRC + Receiver Source Select + 5 + 1 + read-write + + + 0 + Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the LPUART does not use the LPUART_RX pin. + #0 + + + 1 + Single-wire LPUART mode where the LPUART_TX pin is connected to the transmitter output and receiver input. + #1 + + + + + DOZEEN + Doze Enable + 6 + 1 + read-write + + + 0 + LPUART is enabled in Doze mode. + #0 + + + 1 + LPUART is disabled in Doze mode. + #1 + + + + + LOOPS + Loop Mode Select + 7 + 1 + read-write + + + 0 + Normal operation - LPUART_RX and LPUART_TX use separate pins. + #0 + + + 1 + Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input (see RSRC bit). + #1 + + + + + IDLECFG + Idle Configuration + 8 + 3 + read-write + + + 000 + 1 idle character + #000 + + + 001 + 2 idle characters + #001 + + + 010 + 4 idle characters + #010 + + + 011 + 8 idle characters + #011 + + + 100 + 16 idle characters + #100 + + + 101 + 32 idle characters + #101 + + + 110 + 64 idle characters + #110 + + + 111 + 128 idle characters + #111 + + + + + MA2IE + Match 2 Interrupt Enable + 14 + 1 + read-write + + + 0 + MA2F interrupt disabled + #0 + + + 1 + MA2F interrupt enabled + #1 + + + + + MA1IE + Match 1 Interrupt Enable + 15 + 1 + read-write + + + 0 + MA1F interrupt disabled + #0 + + + 1 + MA1F interrupt enabled + #1 + + + + + SBK + Send Break + 16 + 1 + read-write + + + 0 + Normal transmitter operation. + #0 + + + 1 + Queue break character(s) to be sent. + #1 + + + + + RWU + Receiver Wakeup Control + 17 + 1 + read-write + + + 0 + Normal receiver operation. + #0 + + + 1 + LPUART receiver in standby waiting for wakeup condition. + #1 + + + + + RE + Receiver Enable + 18 + 1 + read-write + + + 0 + Receiver disabled. + #0 + + + 1 + Receiver enabled. + #1 + + + + + TE + Transmitter Enable + 19 + 1 + read-write + + + 0 + Transmitter disabled. + #0 + + + 1 + Transmitter enabled. + #1 + + + + + ILIE + Idle Line Interrupt Enable + 20 + 1 + read-write + + + 0 + Hardware interrupts from IDLE disabled; use polling. + #0 + + + 1 + Hardware interrupt requested when IDLE flag is 1. + #1 + + + + + RIE + Receiver Interrupt Enable + 21 + 1 + read-write + + + 0 + Hardware interrupts from RDRF disabled; use polling. + #0 + + + 1 + Hardware interrupt requested when RDRF flag is 1. + #1 + + + + + TCIE + Transmission Complete Interrupt Enable for + 22 + 1 + read-write + + + 0 + Hardware interrupts from TC disabled; use polling. + #0 + + + 1 + Hardware interrupt requested when TC flag is 1. + #1 + + + + + TIE + Transmit Interrupt Enable + 23 + 1 + read-write + + + 0 + Hardware interrupts from TDRE disabled; use polling. + #0 + + + 1 + Hardware interrupt requested when TDRE flag is 1. + #1 + + + + + PEIE + Parity Error Interrupt Enable + 24 + 1 + read-write + + + 0 + PF interrupts disabled; use polling). + #0 + + + 1 + Hardware interrupt requested when PF is set. + #1 + + + + + FEIE + Framing Error Interrupt Enable + 25 + 1 + read-write + + + 0 + FE interrupts disabled; use polling. + #0 + + + 1 + Hardware interrupt requested when FE is set. + #1 + + + + + NEIE + Noise Error Interrupt Enable + 26 + 1 + read-write + + + 0 + NF interrupts disabled; use polling. + #0 + + + 1 + Hardware interrupt requested when NF is set. + #1 + + + + + ORIE + Overrun Interrupt Enable + 27 + 1 + read-write + + + 0 + OR interrupts disabled; use polling. + #0 + + + 1 + Hardware interrupt requested when OR is set. + #1 + + + + + TXINV + Transmit Data Inversion + 28 + 1 + read-write + + + 0 + Transmit data not inverted. + #0 + + + 1 + Transmit data inverted. + #1 + + + + + TXDIR + LPUART_TX Pin Direction in Single-Wire Mode + 29 + 1 + read-write + + + 0 + LPUART_TX pin is an input in single-wire mode. + #0 + + + 1 + LPUART_TX pin is an output in single-wire mode. + #1 + + + + + R9T8 + Receive Bit 9 / Transmit Bit 8 + 30 + 1 + read-write + + + R8T9 + Receive Bit 8 / Transmit Bit 9 + 31 + 1 + read-write + + + + + DATA + LPUART Data Register + 0xC + 32 + read-write + 0x1000 + 0xFFFFFFFF + + + R0T0 + Read receive data buffer 0 or write transmit data buffer 0. + 0 + 1 + read-write + + + R1T1 + Read receive data buffer 1 or write transmit data buffer 1. + 1 + 1 + read-write + + + R2T2 + Read receive data buffer 2 or write transmit data buffer 2. + 2 + 1 + read-write + + + R3T3 + Read receive data buffer 3 or write transmit data buffer 3. + 3 + 1 + read-write + + + R4T4 + Read receive data buffer 4 or write transmit data buffer 4. + 4 + 1 + read-write + + + R5T5 + Read receive data buffer 5 or write transmit data buffer 5. + 5 + 1 + read-write + + + R6T6 + Read receive data buffer 6 or write transmit data buffer 6. + 6 + 1 + read-write + + + R7T7 + Read receive data buffer 7 or write transmit data buffer 7. + 7 + 1 + read-write + + + R8T8 + Read receive data buffer 8 or write transmit data buffer 8. + 8 + 1 + read-write + + + R9T9 + Read receive data buffer 9 or write transmit data buffer 9. + 9 + 1 + read-write + + + IDLINE + Idle Line + 11 + 1 + read-only + + + 0 + Receiver was not idle before receiving this character. + #0 + + + 1 + Receiver was idle before receiving this character. + #1 + + + + + RXEMPT + Receive Buffer Empty + 12 + 1 + read-only + + + 0 + Receive buffer contains valid data. + #0 + + + 1 + Receive buffer is empty, data returned on read is not valid. + #1 + + + + + FRETSC + Frame Error / Transmit Special Character + 13 + 1 + read-write + + + 0 + The dataword was received without a frame error on read, transmit a normal character on write. + #0 + + + 1 + The dataword was received with a frame error, transmit an idle or break character on transmit. + #1 + + + + + PARITYE + The current received dataword contained in DATA[R9:R0] was received with a parity error. + 14 + 1 + read-only + + + 0 + The dataword was received without a parity error. + #0 + + + 1 + The dataword was received with a parity error. + #1 + + + + + NOISY + The current received dataword contained in DATA[R9:R0] was received with noise. + 15 + 1 + read-only + + + 0 + The dataword was received without noise. + #0 + + + 1 + The data was received with noise. + #1 + + + + + + + MATCH + LPUART Match Address Register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + MA1 + Match Address 1 + 0 + 10 + read-write + + + MA2 + Match Address 2 + 16 + 10 + read-write + + + + + MODIR + LPUART Modem IrDA Register + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + TXCTSE + Transmitter clear-to-send enable + 0 + 1 + read-write + + + 0 + CTS has no effect on the transmitter. + #0 + + + 1 + Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission. + #1 + + + + + TXRTSE + Transmitter request-to-send enable + 1 + 1 + read-write + + + 0 + The transmitter has no effect on RTS. + #0 + + + 1 + When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and shift register are completely sent, including the last stop bit. + #1 + + + + + TXRTSPOL + Transmitter request-to-send polarity + 2 + 1 + read-write + + + 0 + Transmitter RTS is active low. + #0 + + + 1 + Transmitter RTS is active high. + #1 + + + + + RXRTSE + Receiver request-to-send enable + 3 + 1 + read-write + + + 0 + The receiver has no effect on RTS. + #0 + + + 1 + RTS assertion is configured by the RTSWATER field + #1 + + + + + TXCTSC + Transmit CTS Configuration + 4 + 1 + read-write + + + 0 + CTS input is sampled at the start of each character. + #0 + + + 1 + CTS input is sampled when the transmitter is idle. + #1 + + + + + TXCTSSRC + Transmit CTS Source + 5 + 1 + read-write + + + 0 + CTS input is the LPUART_CTS pin. + #0 + + + 1 + CTS input is the inverted Receiver Match result. + #1 + + + + + RTSWATER + Receive RTS Configuration + 8 + 8 + read-write + + + 0 + RTS asserts when the receiver FIFO is full or receiving a character that causes the FIFO to become full. + #0 + + + 1 + RTS asserts when the receive FIFO is less than or equal to the RXWATER configuration and negates when the receive FIFO is greater than the RXWATER configuration. + #1 + + + + + TNP + Transmitter narrow pulse + 16 + 2 + read-write + + + 00 + 1/OSR. + #00 + + + 01 + 2/OSR. + #01 + + + 10 + 3/OSR. + #10 + + + 11 + 4/OSR. + #11 + + + + + IREN + Infrared enable + 18 + 1 + read-write + + + 0 + IR disabled. + #0 + + + 1 + IR enabled. + #1 + + + + + + + FIFO + LPUART FIFO Register + 0x18 + 32 + read-write + 0xC00022 + 0xFFFFFFFF + + + RXFIFOSIZE + Receive FIFO. Buffer Depth + 0 + 3 + read-only + + + 10 + Receive FIFO/Buffer depth = 8 datawords. + #010 + + + + + RXFE + Receive FIFO Enable + 3 + 1 + read-write + + + 0 + Receive FIFO is not enabled. Buffer is depth 1. (Legacy support) + #0 + + + 1 + Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE. + #1 + + + + + TXFIFOSIZE + Transmit FIFO. Buffer Depth + 4 + 3 + read-only + + + 10 + Transmit FIFO/Buffer depth = 8 datawords. + #010 + + + + + TXFE + Transmit FIFO Enable + 7 + 1 + read-write + + + 0 + Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support). + #0 + + + 1 + Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE. + #1 + + + + + RXUFE + Receive FIFO Underflow Interrupt Enable + 8 + 1 + read-write + + + 0 + RXUF flag does not generate an interrupt to the host. + #0 + + + 1 + RXUF flag generates an interrupt to the host. + #1 + + + + + TXOFE + Transmit FIFO Overflow Interrupt Enable + 9 + 1 + read-write + + + 0 + TXOF flag does not generate an interrupt to the host. + #0 + + + 1 + TXOF flag generates an interrupt to the host. + #1 + + + + + RXIDEN + Receiver Idle Empty Enable + 10 + 3 + read-write + + + 000 + Disable RDRF assertion due to partially filled FIFO when receiver is idle. + #000 + + + 001 + Enable RDRF assertion due to partially filled FIFO when receiver is idle for 1 character. + #001 + + + 010 + Enable RDRF assertion due to partially filled FIFO when receiver is idle for 2 characters. + #010 + + + 011 + Enable RDRF assertion due to partially filled FIFO when receiver is idle for 4 characters. + #011 + + + 100 + Enable RDRF assertion due to partially filled FIFO when receiver is idle for 8 characters. + #100 + + + 101 + Enable RDRF assertion due to partially filled FIFO when receiver is idle for 16 characters. + #101 + + + 110 + Enable RDRF assertion due to partially filled FIFO when receiver is idle for 32 characters. + #110 + + + 111 + Enable RDRF assertion due to partially filled FIFO when receiver is idle for 64 characters. + #111 + + + + + RXFLUSH + Receive FIFO/Buffer Flush + 14 + 1 + read-write + + + 0 + No flush operation occurs. + #0 + + + 1 + All data in the receive FIFO/buffer is cleared out. + #1 + + + + + TXFLUSH + Transmit FIFO/Buffer Flush + 15 + 1 + read-write + + + 0 + No flush operation occurs. + #0 + + + 1 + All data in the transmit FIFO/Buffer is cleared out. + #1 + + + + + RXUF + Receiver Buffer Underflow Flag + 16 + 1 + read-write + + + 0 + No receive buffer underflow has occurred since the last time the flag was cleared. + #0 + + + 1 + At least one receive buffer underflow has occurred since the last time the flag was cleared. + #1 + + + + + TXOF + Transmitter Buffer Overflow Flag + 17 + 1 + read-write + + + 0 + No transmit buffer overflow has occurred since the last time the flag was cleared. + #0 + + + 1 + At least one transmit buffer overflow has occurred since the last time the flag was cleared. + #1 + + + + + RXEMPT + Receive Buffer/FIFO Empty + 22 + 1 + read-only + + + 0 + Receive buffer is not empty. + #0 + + + 1 + Receive buffer is empty. + #1 + + + + + TXEMPT + Transmit Buffer/FIFO Empty + 23 + 1 + read-only + + + 0 + Transmit buffer is not empty. + #0 + + + 1 + Transmit buffer is empty. + #1 + + + + + + + WATER + LPUART Watermark Register + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + TXWATER + Transmit Watermark + 0 + 8 + read-write + + + TXCOUNT + Transmit Counter + 8 + 8 + read-only + + + RXWATER + Receive Watermark + 16 + 8 + read-write + + + RXCOUNT + Receive Counter + 24 + 8 + read-only + + + + + + + LTC0 + LTC + 0x40058000 + + 0 + 0x7F4 + registers + + + LTC0 + 23 + + + + MD + Mode Register + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENC + Encrypt/Decrypt. + 0 + 1 + read-write + + + 0 + Decrypt. + #0 + + + 1 + Encrypt. + #1 + + + + + ICV_TEST + ICV Checking / Test AES fault detection. + 1 + 1 + read-write + + + AS + Algorithm State + 2 + 2 + read-write + + + 00 + Update + #00 + + + 01 + Initialize + #01 + + + 10 + Finalize + #10 + + + 11 + Initialize/Finalize + #11 + + + + + AAI + Additional Algorithm information + 4 + 9 + read-write + + + ALG + Algorithm + 16 + 8 + read-write + + + 10000 + AES + #10000 + + + + + + + KS + Key Size Register + 0x8 + 32 + read-write + 0x10 + 0xFFFFFFFF + + + KS + Key Size + 0 + 5 + write-only + + + + + DS + Data Size Register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + DS + Data Size + 0 + 12 + read-write + + + + + ICVS + ICV Size Register + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + ICVS + ICV Size, in Bytes + 0 + 5 + read-write + + + + + COM + Command Register + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + ALL + Reset All Internal Logic + 0 + 1 + write-only + + + 0 + Do Not Reset + #0 + + + 1 + Reset all CHAs in use by this CCB. + #1 + + + + + AES + Reset AESA + 1 + 1 + write-only + + + 0 + Do Not Reset + #0 + + + 1 + Reset AES Accelerator + #1 + + + + + + + CTL + Control Register + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + IM + Interrupt Mask + 0 + 1 + read-write + + + 0 + Interrupt not masked. + #0 + + + 1 + Interrupt masked + #1 + + + + + IFE + Input FIFO DMA Enable + 8 + 1 + read-write + + + 0 + DMA Request and Done signals disabled for the Input FIFO. + #0 + + + 1 + DMA Request and Done signals enabled for the Input FIFO. + #1 + + + + + IFR + Input FIFO DMA Request Size + 9 + 1 + read-write + + + 0 + DMA request size is 1 entry. + #0 + + + 1 + DMA request size is 4 entries. + #1 + + + + + OFE + Output FIFO DMA Enable + 12 + 1 + read-write + + + 0 + DMA Request and Done signals disabled for the Output FIFO. + #0 + + + 1 + DMA Request and Done signals enabled for the Output FIFO. + #1 + + + + + OFR + Output FIFO DMA Request Size + 13 + 1 + read-write + + + 0 + DMA request size is 1 entry. + #0 + + + 1 + DMA request size is 4 entries. + #1 + + + + + IFS + Input FIFO Byte Swap + 16 + 1 + read-write + + + 0 + Do Not Byte Swap Data. + #0 + + + 1 + Byte Swap Data. + #1 + + + + + OFS + Output FIFO Byte Swap + 17 + 1 + read-write + + + 0 + Do Not Byte Swap Data. + #0 + + + 1 + Byte Swap Data. + #1 + + + + + KIS + Key Register Input Byte Swap + 20 + 1 + read-write + + + 0 + Do Not Byte Swap Data. + #0 + + + 1 + Byte Swap Data. + #1 + + + + + KOS + Key Register Output Byte Swap + 21 + 1 + read-write + + + 0 + Do Not Byte Swap Data. + #0 + + + 1 + Byte Swap Data. + #1 + + + + + CIS + Context Register Input Byte Swap + 22 + 1 + read-write + + + 0 + Do Not Byte Swap Data. + #0 + + + 1 + Byte Swap Data. + #1 + + + + + COS + Context Register Output Byte Swap + 23 + 1 + read-write + + + 0 + Do Not Byte Swap Data. + #0 + + + 1 + Byte Swap Data. + #1 + + + + + KAL + Key Register Access Lock + 31 + 1 + read-write + + + 0 + Key Register is readable. + #0 + + + 1 + Key Register is not readable. + #1 + + + + + + + CW + Clear Written Register + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + CM + Clear the Mode Register + 0 + 1 + write-only + + + CDS + Clear the Data Size Register + 2 + 1 + write-only + + + CICV + Clear the ICV Size Register + 3 + 1 + write-only + + + CCR + Clear the Context Register + 5 + 1 + write-only + + + CKR + Clear the Key Register + 6 + 1 + write-only + + + COF + Clear Output FIFO + 30 + 1 + write-only + + + CIF + Clear Input FIFO + 31 + 1 + write-only + + + + + STA + Status Register + 0x48 + 32 + read-write + 0 + 0xFFFFFFFF + + + AB + AESA Busy + 1 + 1 + read-only + + + 0 + AESA Idle + #0 + + + 1 + AESA Busy. + #1 + + + + + DI + Done Interrupt + 16 + 1 + read-write + + + EI + Error Interrupt + 20 + 1 + read-only + + + 0 + Not Error. + #0 + + + 1 + Error Interrupt. + #1 + + + + + + + ESTA + Error Status Register + 0x4C + 32 + read-only + 0 + 0xFFFFFFFF + + + ERRID1 + Error ID 1 + 0 + 4 + read-only + + + 0001 + Mode Error + #0001 + + + 0010 + Data Size Error + #0010 + + + 0011 + Key Size Error + #0011 + + + 0110 + Data Arrived out of Sequence Error + #0110 + + + 1010 + ICV Check Failed + #1010 + + + 1011 + Internal Hardware Failure + #1011 + + + 1100 + CCM AAD Size Error (either 1. AAD flag in B0 =1 and no AAD type provided, 2. AAD flag in B0 = 0 and AAD povided, or 3. AAD flag in B0 =1 and not enough AAD provided - expecting more based on AAD size.) + #1100 + + + 1111 + Invalid Crypto Engine Selected + #1111 + + + + + CL1 + algorithms + 8 + 4 + read-only + + + 0 + General Error + #0000 + + + 1 + AES + #0001 + + + + + + + AADSZ + AAD Size Register + 0x58 + 32 + read-write + 0 + 0xFFFFFFFF + + + AADSZ + AAD size in Bytes, mod 16 + 0 + 4 + read-write + + + AL + AAD Last + 31 + 1 + read-write + + + + + CTX_0 + Context Register + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + CTX + CTX + 0 + 32 + read-write + + + + + CTX_1 + Context Register + 0x104 + 32 + read-write + 0 + 0xFFFFFFFF + + + CTX + CTX + 0 + 32 + read-write + + + + + CTX_2 + Context Register + 0x108 + 32 + read-write + 0 + 0xFFFFFFFF + + + CTX + CTX + 0 + 32 + read-write + + + + + CTX_3 + Context Register + 0x10C + 32 + read-write + 0 + 0xFFFFFFFF + + + CTX + CTX + 0 + 32 + read-write + + + + + CTX_4 + Context Register + 0x110 + 32 + read-write + 0 + 0xFFFFFFFF + + + CTX + CTX + 0 + 32 + read-write + + + + + CTX_5 + Context Register + 0x114 + 32 + read-write + 0 + 0xFFFFFFFF + + + CTX + CTX + 0 + 32 + read-write + + + + + CTX_6 + Context Register + 0x118 + 32 + read-write + 0 + 0xFFFFFFFF + + + CTX + CTX + 0 + 32 + read-write + + + + + CTX_7 + Context Register + 0x11C + 32 + read-write + 0 + 0xFFFFFFFF + + + CTX + CTX + 0 + 32 + read-write + + + + + CTX_8 + Context Register + 0x120 + 32 + read-write + 0 + 0xFFFFFFFF + + + CTX + CTX + 0 + 32 + read-write + + + + + CTX_9 + Context Register + 0x124 + 32 + read-write + 0 + 0xFFFFFFFF + + + CTX + CTX + 0 + 32 + read-write + + + + + CTX_10 + Context Register + 0x128 + 32 + read-write + 0 + 0xFFFFFFFF + + + CTX + CTX + 0 + 32 + read-write + + + + + CTX_11 + Context Register + 0x12C + 32 + read-write + 0 + 0xFFFFFFFF + + + CTX + CTX + 0 + 32 + read-write + + + + + CTX_12 + Context Register + 0x130 + 32 + read-write + 0 + 0xFFFFFFFF + + + CTX + CTX + 0 + 32 + read-write + + + + + CTX_13 + Context Register + 0x134 + 32 + read-write + 0 + 0xFFFFFFFF + + + CTX + CTX + 0 + 32 + read-write + + + + + KEY_0 + Key Registers + 0x200 + 32 + read-write + 0 + 0xFFFFFFFF + + + KEY + KEY + 0 + 32 + read-write + + + + + KEY_1 + Key Registers + 0x204 + 32 + read-write + 0 + 0xFFFFFFFF + + + KEY + KEY + 0 + 32 + read-write + + + + + KEY_2 + Key Registers + 0x208 + 32 + read-write + 0 + 0xFFFFFFFF + + + KEY + KEY + 0 + 32 + read-write + + + + + KEY_3 + Key Registers + 0x20C + 32 + read-write + 0 + 0xFFFFFFFF + + + KEY + KEY + 0 + 32 + read-write + + + + + VID1 + Version ID Register + 0x4F0 + 32 + read-only + 0x340100 + 0xFFFFFFFF + + + MIN_REV + Minor revision number. + 0 + 8 + read-only + + + MAJ_REV + Major revision number. + 8 + 8 + read-only + + + IP_ID + ID(0x0034). + 16 + 16 + read-only + + + + + VID2 + Version ID 2 Register + 0x4F4 + 32 + read-only + 0x101 + 0xFFFFFFFF + + + ECO_REV + ECO revision number. + 0 + 8 + read-only + + + ARCH_ERA + Architectural ERA. + 8 + 8 + read-only + + + + + CHAVID + CHA Version ID Register + 0x4F8 + 32 + read-only + 0x50 + 0xFFFFFFFF + + + AESREV + AES Revision Number + 0 + 4 + read-only + + + AESVID + AES Version ID + 4 + 4 + read-only + + + + + FIFOSTA + FIFO Status Register + 0x7C0 + 32 + read-only + 0 + 0xFFFFFFFF + + + IFL + Input FIFO Level + 0 + 7 + read-only + + + IFF + Input FIFO Full + 15 + 1 + read-only + + + OFL + Output FIFO Level + 16 + 7 + read-only + + + OFF + Output FIFO Full + 31 + 1 + read-only + + + + + IFIFO + Input Data FIFO + 0x7E0 + 32 + write-only + 0 + 0xFFFFFFFF + + + IFIFO + IFIFO + 0 + 32 + write-only + + + + + OFIFO + Output Data FIFO + 0x7F0 + 32 + read-only + 0 + 0xFFFFFFFF + + + OFIFO + Output FIFO + 0 + 32 + read-only + + + + + + + RSIM + RSIM + 0x40059000 + + 0 + 0x130 + registers + + + + CONTROL + Radio System Control + 0 + 32 + read-write + 0xC00002 + 0xFFFFFFFF + + + BLE_RF_OSC_REQ_EN + Bluetooth LE Ref Osc (Sysclk) Request Enable + 0 + 1 + read-write + + + BLE_RF_OSC_REQ_STAT + Bluetooth LE Ref Osc (Sysclk) Request Status + 1 + 1 + read-only + + + BLE_RF_OSC_REQ_INT_EN + Bluetooth LE Ref Osc (Sysclk) Request Interrupt Enable + 4 + 1 + read-write + + + BLE_RF_OSC_REQ_INT + Bluetooth LE Ref Osc (Sysclk) Request Interrupt Flag + 5 + 1 + read-write + + + RF_OSC_EN + RF Ref Osc Enable Select + 8 + 4 + read-write + + + 0000 + RF Ref Osc is controlled by the SoC, external pin, or a link layer + #0000 + + + 0001 + RF Ref Osc on in Run/Wait + #0001 + + + 0011 + RF Ref Osc on in Stop + #0011 + + + 0111 + RF Ref Osc on in VLPR/VLPW + #0111 + + + 1111 + RF Ref Osc on in VLPS + #1111 + + + + + TXRAMPO + Radio TX RAM Power Option + 18 + 1 + read-write + + + 0 + TX RAM not powered in VLLS2 + #0 + + + 1 + TX RAM powered in VLLS2 + #1 + + + + + RXRAMPO + Radio RX RAM Power Option + 19 + 1 + read-write + + + 0 + RX RAM not powered in VLLS2 + #0 + + + 1 + RX RAM powered in VLLS2 + #1 + + + + + RSIM_DSM_EXIT + Bluetooth LE Force Deep Sleep Mode Exit + 20 + 1 + read-write + + + RSIM_STOP_ACK_OVRD_EN + Stop Acknowledge Override Enable + 22 + 1 + read-write + + + RSIM_STOP_ACK_OVRD + Stop Acknowledge Override + 23 + 1 + read-write + + + RF_OSC_READY + RF Ref Osc Ready + 24 + 1 + read-only + + + RF_OSC_READY_OVRD_EN + RF Ref Osc Ready Override Enable + 25 + 1 + read-write + + + RF_OSC_READY_OVRD + RF Ref Osc Ready Override + 26 + 1 + read-write + + + BLOCK_SOC_RESETS + Block SoC Resets of the Radio + 28 + 1 + read-write + + + BLOCK_RADIO_OUTPUTS + Block Radio Outputs + 29 + 1 + read-write + + + RADIO_RESET_BIT + Software Reset for the Radio + 31 + 1 + read-write + + + + + DSM_WAKEUP + Deep Sleep Wake-up Sequence + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + FINE_DELAY + Deep Sleep Wake-up Fine Delay Time + 0 + 6 + read-write + + + COARSE_DELAY + Deep Sleep Wake-up Coarse Delay Time + 16 + 4 + read-write + + + ACTIVE_WARNING + Deep Sleep Wake-up RF Active Warning Time + 24 + 6 + read-write + + + + + MAC_MSB + Radio MAC Address + 0x8 + 32 + read-only + 0 + 0xFFFFFFFF + + + MAC_ADDR_MSB + Radio MAC Address MSB + 0 + 8 + read-only + + + + + MAC_LSB + Radio MAC Address + 0xC + 32 + read-only + 0 + 0xFFFFFFFF + + + MAC_ADDR_LSB + Radio MAC Address LSB + 0 + 32 + read-only + + + + + MISC + Radio Miscellaneous + 0x10 + 32 + read-write + 0x6000000 + 0xFFFFFFFF + + + RADIO_VERSION + Radio Version ID number + 24 + 8 + read-write + + + + + SW_CONFIG + Radio Software Configuration + 0x18 + 32 + read-write + 0xA0 + 0xFFFFFFFF + + + RADIO_CONFIGURED_POR_RESET + Radio Configuration Bit, cleared by Radio power-on reset + 0 + 1 + read-write + + + RADIO_CONFIGURED_SYS_RESET + Radio Configuration Bit, cleared by Radio System Reset + 1 + 1 + read-write + + + RSIM_RF_ACTIVE_OVRD + RF Active Internal Override + 4 + 1 + read-write + + + RSIM_RF_ACTIVE_OVRD_EN + RF Active Internal Override Enable + 5 + 1 + read-write + + + RF_OSC_EN_OVRD + Radio Osc Enable Override + 6 + 1 + read-write + + + RF_OSC_EN_OVRD_EN + Radio Osc Enable Override Enable + 7 + 1 + read-write + + + IPP_IBE_RF_NOT_ALLOWED + IPP_IBE_RF_NOT_ALLOWED + 8 + 1 + read-write + + + IPP_IBE_RF_EXT_OSC_EN + IPP_IBE_RF_EXT_OSC_EN + 9 + 1 + read-write + + + IPP_OBE_RF_OSC_EN + IPP_OBE_RF_OSC_EN + 11 + 1 + read-write + + + RADIO_RF_NOT_ALLOWED_SEL + Radio RF_NOT_ALLOWED Select + 12 + 1 + read-write + + + 0 + PTB2 + #0 + + + 1 + PTC5 + #1 + + + + + RADIO_BLE_EARLY_WARNING_SEL + Radio BLE_EARLY_WARNING Select + 14 + 1 + read-write + + + 0 + PTC19 + #0 + + + 1 + PTC1 + #1 + + + + + IPP_OBE_BLE_EARLY_WARNING + IPP_OBE_BLE_EARLY_WARNING + 15 + 1 + read-write + + + WIFI_COEXIST_1 + RF_ACTIVE Source + 16 + 1 + read-write + + + WIFI_COEXIST_2 + RF_STATUS Source + 17 + 1 + read-write + + + WIFI_COEXIST_3 + RF_EARLY_WARNING Source + 18 + 1 + read-write + + + RF_ACTIVE_ENDS_WITH_TSM + RF_ACTIVE clearing mechanism + 20 + 1 + read-write + + + SW_RF_ACTIVE_ENDS_WITH_TSM + Software RF_ACTIVE clearing mechanism + 21 + 1 + read-write + + + SW_RF_ACTIVE_BIT + Software RF_ACTIVE Control Bit + 22 + 1 + read-write + + + SW_RF_ACTIVE_EN + Software RF_ACTIVE Control Enable + 23 + 1 + read-write + + + IPP_OBE_RF_PRIORITY + IPP_OBE_RF_PRIORITY + 24 + 1 + read-write + + + IPP_OBE_RF_STATUS + IPP_OBE_RF_STATUS + 25 + 1 + read-write + + + IPP_OBE_RF_ACTIVE + IPP_OBE_RF_ACTIVE + 26 + 1 + read-write + + + RADIO_RF_PRIORITY_SEL + Radio RF_PRIORITY Select + 27 + 1 + read-write + + + 0 + PTB1 + #0 + + + 1 + PTC5 + #1 + + + + + RADIO_RF_STATUS_SEL + Radio RF_STATUS Select + 28 + 1 + read-write + + + 0 + PTC16 + #0 + + + 1 + PTA1 + #1 + + + + + RADIO_RF_ACTIVE_SEL + Radio RF_ACTIVE Select + 29 + 2 + read-write + + + 00 + PTC4 + #00 + + + 01 + PTB3 + #01 + + + 10 + PTA0 + #10 + + + + + BLOCK_EXT_OSC_PWR_REQ + Block External Requests for RF Ref OSC from starting a Radio Power Wake-up Sequence + 31 + 1 + read-write + + + + + DSM_TIMER + Deep Sleep Timer + 0x100 + 32 + read-only + 0 + 0xFFFFFFFF + + + DSM_TIMER + Deep Sleep Mode Timer + 0 + 24 + read-only + + + + + DSM_CONTROL + Deep Sleep Timer Control + 0x104 + 32 + read-write + 0 + 0xFFFFFFFF + + + DSM_GEN_READY + Generic FSK Ready for Deep Sleep Mode + 8 + 1 + read-only + + + GEN_DEEP_SLEEP_STATUS + Generic FSK Link Layer Deep Sleep Mode Status + 9 + 1 + read-only + + + DSM_GEN_FINISHED + Generic FSK Deep Sleep Time Finished + 10 + 1 + read-only + + + GEN_SYSCLK_REQUEST_EN + Enable Generic FSK Link Layer to Request RF Ref OSC + 11 + 1 + read-write + + + GEN_SLEEP_REQUEST + Generic FSK Link Layer Deep Sleep Requested + 12 + 1 + read-only + + + GEN_SYSCLK_REQ + Generic FSK Link Layer RF Ref OSC Request Status + 13 + 1 + read-only + + + GEN_SYSCLK_INTERRUPT_EN + Generic FSK Link Layer RF Ref OSC Request Interrupt Enable + 14 + 1 + read-write + + + GEN_SYSCLK_REQ_INT + Interrupt Flag from an Generic FSK Link Layer RF Ref OSC Request + 15 + 1 + read-write + + + GEN_FSM_STATE + GEN Deep Sleep State Machine State + 16 + 5 + read-only + + + DSM_TIMER_CLR + Deep Sleep Mode Timer Clear + 27 + 1 + read-write + + + DSM_TIMER_EN + Deep Sleep Mode Timer Enable + 31 + 1 + read-write + + + + + DSM_OSC_OFFSET + Deep Sleep Wake-up Time Offset + 0x108 + 32 + read-write + 0 + 0xFFFFFFFF + + + DSM_OSC_STABILIZE_TIME + Deep Sleep Wake-up RF Ref OSC Stabilize Time + 0 + 10 + read-write + + + + + GEN_SLEEP + Generic FSK Link Layer Sleep Time + 0x11C + 32 + read-write + 0 + 0xFFFFFFFF + + + GEN_SLEEP_TIME + Generic FSK Link Layer Sleep Time + 0 + 24 + read-write + + + + + GEN_WAKE + Generic FSK Link Layer Wake Time + 0x120 + 32 + read-write + 0 + 0xFFFFFFFF + + + GEN_WAKE_TIME + Generic FSK Link Layer Wake Time + 0 + 24 + read-write + + + + + RF_OSC_CTRL + Radio Oscillator Control + 0x124 + 32 + read-write + 0xA0203806 + 0xFFFFFFFF + + + BB_XTAL_ALC_COUNT_SEL + rmap_bb_xtal_alc_count_sel_hv[1:0] + 0 + 2 + read-write + + + 00 + 2048 (64 us @ 32 MHz) + #00 + + + 01 + 4096 (128 us @ 32 MHz) + #01 + + + 10 + 8192 (256 us @ 32 MHz) + #10 + + + 11 + 16384 (512 us @ 32 MHz) + #11 + + + + + BB_XTAL_ALC_ON + rmap_bb_xtal_alc_on_hv + 2 + 1 + read-write + + + RF_OSC_BYPASS_EN + RF Ref Osc Bypass Enable + 3 + 1 + read-write + + + BB_XTAL_COMP_BIAS + rmap_bb_xtal_comp_bias_hv[4:0] + 4 + 5 + read-write + + + BB_XTAL_DC_COUP_MODE_EN + rmap_bb_xtal_dc_coup_mode_en_hv + 9 + 1 + read-write + + + BB_XTAL_DIAGSEL + rmap_bb_xtal_diagsel_hv + 10 + 1 + read-write + + + BB_XTAL_DIG_CLK_ON + rmap_bb_xtal_dig_clk_on_hv + 11 + 1 + read-write + + + BB_XTAL_GM + rmap_bb_xtal_gm_hv[4:0] + 12 + 5 + read-write + + + BB_XTAL_ON_OVRD + rmap_bb_xtal_on_ovrd_hv + 17 + 1 + read-write + + + BB_XTAL_ON_OVRD_ON + rmap_bb_xtal_on_ovrd_on_hv + 18 + 1 + read-write + + + 0 + rfctrl_bb_xtal_on_hv is asserted + #0 + + + 1 + rfctrl_bb_xtal_on_ovrd_hv is asserted + #1 + + + + + BB_XTAL_READY_COUNT_SEL + rmap_bb_xtal_ready_count_sel_hv[1:0] + 20 + 2 + read-write + + + 00 + 1024 counts (32 us @ 32 MHz) + #00 + + + 01 + 2048 (64 us @ 32 MHz) + #01 + + + 10 + 4096 (128 us @ 32 MHz) + #10 + + + 11 + 8192 (256 us @ 32 MHz) + #11 + + + + + RADIO_EXT_OSC_RF_EN_SEL + Radio External Request for RF Ref OSC Select + 27 + 1 + read-write + + + 0 + PTC6 + #0 + + + 1 + PTB0 + #1 + + + + + RADIO_EXT_OSC_OVRD + Radio External Request for RF Ref OSC Override + 28 + 1 + read-write + + + RADIO_EXT_OSC_OVRD_EN + Radio External Request for RF Ref OSC Override Enable + 29 + 1 + read-write + + + RF_NOT_ALLOWED_OVRD + RF Not Allowed Override + 30 + 1 + read-write + + + RF_NOT_ALLOWED_OVRD_EN + RF Not Allowed Override Enable + 31 + 1 + read-write + + + + + ANA_TEST + Radio Analog Test Registers + 0x128 + 32 + read-write + 0 + 0xFFFFFFFF + + + XTAL_OUT_BUF_EN + XTAL Output Buffer Enable + 4 + 1 + read-write + + + + + ANA_TRIM + Radio Analog Trim Registers + 0x12C + 32 + read-write + 0x784B0000 + 0xFFFFFFFF + + + BB_LDO_LS_SPARE + rmap_bb_ldo_ls_spare_hv[1:0] + 0 + 2 + read-write + + + BG_1V_TRIM_OVRD + Bandgap 1V Trim Override + 2 + 1 + read-write + + + BB_LDO_LS_TRIM + rmap_bb_ldo_ls_trim_hv[2:0] + 3 + 3 + read-write + + + 000 + 1.20 V (Default) + #000 + + + 001 + 1.25 V + #001 + + + 010 + 1.28 V + #010 + + + 011 + 1.33 V + #011 + + + 100 + 1.40 V + #100 + + + 101 + 1.44 V + #101 + + + 110 + 1.50 V + #110 + + + 111 + 1.66 V + #111 + + + + + BB_LDO_XO_SPARE + rmap_bb_ldo_xo_spare_hv[1:0] + 6 + 2 + read-write + + + BB_LDO_XO_TRIM + rmap_bb_ldo_xo_trim_hv[2:0] + 8 + 3 + read-write + + + 000 + 1.20 V (Default) + #000 + + + 001 + 1.25 V + #001 + + + 010 + 1.28 V + #010 + + + 011 + 1.33 V + #011 + + + 100 + 1.40 V + #100 + + + 101 + 1.44 V + #101 + + + 110 + 1.50 V + #110 + + + 111 + 1.66 V + #111 + + + + + BB_XTAL_SPARE + rmap_bb_xtal_spare_hv[4:0] + 11 + 5 + read-write + + + BB_XTAL_TRIM + rmap_bb_xtal_trim_hv[7:0] + 16 + 8 + read-write + + + BG_1V_TRIM + rmap_bg_1v_trim_hv[3:0] + 24 + 4 + read-write + + + 0000 + 954.14 mV + #0000 + + + 0001 + 959.26 mV + #0001 + + + 0010 + 964.38 mV + #0010 + + + 0011 + 969.5 mV + #0011 + + + 0100 + 974.6 mV + #0100 + + + 0101 + 979.7 mV + #0101 + + + 0110 + 984.8 mV + #0110 + + + 0111 + 989.9 mV + #0111 + + + 1000 + 995 mV (Default) + #1000 + + + 1001 + 1 V + #1001 + + + 1010 + 1.005 V + #1010 + + + 1011 + 1.01 V + #1011 + + + 1100 + 1.015 V + #1100 + + + 1101 + 1.02 V + #1101 + + + 1110 + 1.025 V + #1110 + + + 1111 + 1.031 V + #1111 + + + + + BG_IBIAS_5U_TRIM + rmap_bg_ibias_5u_trim_hv[3:0] + 28 + 4 + read-write + + + 0000 + 3.55 uA + #0000 + + + 0001 + 3.73 uA + #0001 + + + 0010 + 4.04 uA + #0010 + + + 0011 + 4.22 uA + #0011 + + + 0100 + 4.39 uA + #0100 + + + 0101 + 4.57 uA + #0101 + + + 0110 + 4.89 uA + #0110 + + + 0111 + 5.06 (Default) + #0111 + + + 1000 + 5.23 uA + #1000 + + + 1001 + 5.41 uA + #1001 + + + 1010 + 5.72 uA + #1010 + + + 1011 + 5.9 uA + #1011 + + + 1100 + 6.07 uA + #1100 + + + 1101 + 6.25 uA + #1101 + + + 1110 + 6.56 uA + #1110 + + + 1111 + 6.74 uA + #1111 + + + + + + + + + DCDC + DC to DC Converter + DCDC_ + 0x4005A000 + + 0 + 0x20 + registers + + + LVD_LVW_DCDC + 6 + + + + REG0 + DCDC REGISTER 0 + 0 + 32 + read-write + 0x4180000 + 0xFFFFFFFF + + + DCDC_DISABLE_AUTO_CLK_SWITCH + Disable automatic clock switch. + 1 + 1 + read-write + + + 0 + Automatic clock switch feature is enabled + #0 + + + 1 + Automatic clock switch feature is disabled + #1 + + + + + DCDC_SEL_CLK + DCDC clock selection when DCDC_DISABLE_AUTO_CLK_SWITCH is set. + 2 + 1 + read-write + + + 0 + Internal oscillator is used as DCDC clock + #0 + + + 1 + External oscillator is used as DCDC clock (debug use only) + #1 + + + + + DCDC_PWD_OSC_INT + Power down internal oscillator. Only set this bit when 32M crystal oscillator is available. + 3 + 1 + read-write + + + 0 + Internal oscillator is powered up + #0 + + + 1 + Internal oscillator is powered down + #1 + + + + + DCDC_LP_DF_CMP_ENABLE + Enable low power differential comparators, to sense lower supply in pulsed mode + 9 + 1 + read-write + + + 1 + DCDC compare the lower supply(relative to target value) with DCDC_LP_STATE_HYS_L. When it is lower than DCDC_LP_STATE_HYS_L, re-charge output. This is the recommended configuration to guarantee optimal operation + #1 + + + 0 + DCDC compare the common mode sense of supply(relative to target value) with DCDC_LP_STATE_HYS_L. When it is lower than DCDC_LP_STATE_HYS_L, re-charge output. + #0 + + + + + DCDC_IN_DIV_CTRL + Controls DCDC_IN voltage divider + 10 + 2 + read-write + + + 00 + OFF + #00 + + + 01 + DCDC_IN + #01 + + + 10 + DCDC_IN / 2 + #10 + + + 11 + DCDC_IN / 4 + #11 + + + + + DCDC_LP_STATE_HYS_L + Configure the hysteretic lower threshold value in low power mode + 17 + 2 + read-write + + + 00 + Target voltage value - 0 mV + #00 + + + 01 + Target voltage value - 25 mV + #01 + + + 10 + Target voltage value - 50 mV + #10 + + + 11 + Target voltage value - 75 mV + #11 + + + + + DCDC_LP_STATE_HYS_H + Configure the hysteretic upper threshold value in low power mode + 19 + 2 + read-write + + + 00 + Target voltage value + 0 mV + #00 + + + 01 + Target voltage value + 25 mV + #01 + + + 10 + Target voltage value + 50 mV + #10 + + + 11 + Target voltage value + 75 mV + #11 + + + + + HYST_LP_COMP_ADJ + Adjust hysteretic value in low power comparator + 21 + 1 + read-write + + + 0 + Adjustment feature is disabled + #0 + + + 1 + Adjustment feature is enabled + #1 + + + + + HYST_LP_CMP_DISABLE + Disable hysteresis in low power comparator + 22 + 1 + read-write + + + 0 + Hysteresis feature is enabled + #0 + + + 1 + Hysteresis feature is disabled + #1 + + + + + OFFSET_RSNS_LP_ADJ + Adjust hysteretic value in low power voltage sense + 23 + 1 + read-write + + + 0 + Adjustment feature is disabled + #0 + + + 1 + Adjustment feature is enabled + #1 + + + + + OFFSET_RSNS_LP_DISABLE + Disable hysteresis in low power voltage sense + 24 + 1 + read-write + + + 0 + Hysteresis feature is enabled + #0 + + + 1 + Hysteresis feature is disabled + #1 + + + + + DCDC_LESS_I + Reduces DCDC current by reducing the analog reference current inside the DCDC Converter + 25 + 1 + read-write + + + 0 + Use normal current for analog references + #0 + + + 1 + Use reduced current for analog references + #1 + + + + + PWD_CMP_OFFSET + Output range comparator monitors the output voltage of DCDC + 26 + 1 + read-write + + + 0 + Output range comparator powered up. + #0 + + + 1 + Output range comparator powered down. + #1 + + + + + DCDC_XTALOK_DISABLE + Disable xtalok detection circuit + 27 + 1 + read-write + + + PSWITCH_STATUS + Status bit to indicate PSWITCH status + 28 + 1 + read-only + + + 0 + PSWITCH is low + #0 + + + 1 + PSWITCH is high + #1 + + + + + VLPS_CONFIG_DCDC_HP + Selects behavior of DCDC in device VLPS low power mode + 29 + 1 + read-write + + + 0 + DCDC works in pulsed mode when SOC is in VLPS modes. + #0 + + + 1 + DCDC works in continuous mode when SOC is in VLPS modes. + #1 + + + + + VLPR_VLPW_CONFIG_DCDC_HP + Selects behavior of DCDC in device VLPR and VLPW low power modes + 30 + 1 + read-write + + + 0 + DCDC works in pulsed mode when SoC is in VLPR / VLPW modes. + #0 + + + 1 + DCDC works in continuous mode when SoC is in VLPR / VLPW modes. + #1 + + + + + DCDC_STS_DC_OK + Status bit to indicate that the DCDC output voltage is stable + 31 + 1 + read-only + + + 0 + Unstable DCDC output voltage + #0 + + + 1 + Stable DCDC output voltage + #1 + + + + + + + REG1 + DCDC REGISTER 1 + 0x4 + 32 + read-write + 0x17C21C + 0xFFFFFFFF + + + POSLIMIT_BUCK_IN + Upper limit duty cycle limit in DCDC converter + 0 + 7 + read-write + + + DCDC_LOOPCTRL_CM_HST_THRESH + Enable hysteresis in switching converter common mode analog comparators + 21 + 1 + read-write + + + DCDC_LOOPCTRL_DF_HST_THRESH + Enable hysteresis in switching converter differential mode analog comparators + 22 + 1 + read-write + + + DCDC_LOOPCTRL_EN_CM_HYST + Enable hysteresis in switching converter common mode analog comparators + 23 + 1 + read-write + + + DCDC_LOOPCTRL_EN_DF_HYST + Enable hysteresis in switching converter differential mode analog comparators + 24 + 1 + read-write + + + + + REG2 + DCDC REGISTER 2 + 0x8 + 32 + read-write + 0x4009 + 0xFFFFFFFF + + + DCDC_LOOPCTRL_EN_RCSCALE + The DCDC_LOOPCTRL_EN_RCSCALE reduces the response time of the DCDC to transient loads. + 9 + 2 + read-write + + + 00 + Default response time + #00 + + + 01 + 2 times faster than default + #01 + + + 10 + 4 times faster than default + #10 + + + + + DCDC_LOOPCTRL_HYST_SIGN + This bit ensures proper switching of DCDC in Pulsed mode and is set in Pulsed mode. + 13 + 1 + read-write + + + 0 + Hysteresis sign not inverted + #0 + + + 1 + Hysteresis sign inverted (proper switching gauranteed) + #1 + + + + + DCDC_BATTMONITOR_EN_BATADJ + This bit enables the DCDC to improve efficiency and minimize ripple using the information from the BATT_VAL field + 15 + 1 + read-write + + + 0 + Disable the usage of the DCDC_BATTMONITOR_BATT_VAL value to calculate DCDC loop control + #0 + + + 1 + Enable the usage of DCDC_BATTMONITOR_BATT_VAL value to calculate DCDC loop control + #1 + + + + + DCDC_BATTMONITOR_BATT_VAL + Software should write the VDCDC_IN in this register measured with an 8 mV LSB resolution through the ADC + 16 + 10 + read-write + + + + + REG3 + DCDC REGISTER 3 + 0xC + 32 + read-write + 0xAA46 + 0xFFFFFFFF + + + DCDC_VDD1P8CTRL_TRG + Target value of VDD_1P8 : 25 mV each step in two ranges, from 0x00 to 0x11 and 0x20 to 0x3F and 50 mV each step in range from 0x12 to 0x1F + 0 + 6 + read-write + + + DCDC_VDD1P5CTRL_TRG_BUCK + Target value of VDD_1P5 in buck mode, 25 mV each step from 0x00 to 0x15 + 6 + 5 + read-write + + + DCDC_VDD1P5CTRL_ADJTN + Adjust value of duty cycle when switching between VDD_1P5 and VDD_1P8 + 17 + 4 + read-write + + + DCDC_MINPWR_DC_HALFCLK_PULSED + Set DCDC clock to half frequency for the Pulsed mode. + 21 + 1 + read-write + + + 0 + Pulsed mode uses normal operation for DCDC clock + #0 + + + 1 + Pulsed mode uses half frequency DCDC clock operation + #1 + + + + + DCDC_MINPWR_DOUBLE_FETS_PULSED + Use double switch FET for the Pulsed mode + 22 + 1 + read-write + + + 0 + Pulsed mode uses normal output configuration + #0 + + + 1 + Pulsed mode uses double FET output configuration + #1 + + + + + DCDC_MINPWR_HALF_FETS_PULSED + Use half switch FET for the Pulsed mode + 23 + 1 + read-write + + + 0 + Pulsed mode uses normal output configuration + #0 + + + 1 + Pulsed mode uses half FET output configuration + #1 + + + + + DCDC_MINPWR_DC_HALFCLK + Set DCDC clock to half frequency for the continuous mode. + 24 + 1 + read-write + + + 0 + Normal operation for DCDC clock + #0 + + + 1 + DCDC clock operates at half frequency + #1 + + + + + DCDC_MINPWR_DOUBLE_FETS + Use double switch FET for the continuous mode + 25 + 1 + read-write + + + 0 + Normal operation + #0 + + + 1 + Use Double FET + #1 + + + + + DCDC_MINPWR_HALF_FETS + Use half switch FET for the continuous mode + 26 + 1 + read-write + + + 0 + Normal operation + #0 + + + 1 + Use Half FET + #1 + + + + + DCDC_VDD1P5CTRL_DISABLE_STEP + Disable stepping for VDD_1P5. Must set this bit before enter low power modes. + 29 + 1 + read-write + + + 0 + VDD_1P5 stepping enabled + #0 + + + 1 + VDD_1P5 stepping disabled + #1 + + + + + DCDC_VDD1P8CTRL_DISABLE_STEP + Disable stepping for VDD_1P8. Must set this bit before enter low power modes. + 30 + 1 + read-write + + + 0 + VDD_1P8 stepping enabled + #0 + + + 1 + VDD_1P8 stepping disabled + #1 + + + + + + + REG4 + DCDC REGISTER 4 + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + DCDC_SW_SHUTDOWN + Shut down DCDC in buck mode. DCDC can be turned on by pulling PSWITCH to high momentarily (DCDC Turn on time (TDCDC_ON; refer to the data sheet for specific time). This bit should not be used in buck mode when PSWITCH is tied to DCDC_IN. + 0 + 1 + read-write + + + UNLOCK + 0x3E77 KEY-Key needed to unlock DCDC_REG4 register + 16 + 16 + read-write + + + + + REG6 + DCDC REGISTER 6 + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + PSWITCH_INT_RISE_EN + Enable rising edge detect for interrupt. + 0 + 1 + read-write + + + 0 + PSWITCH rising edge interrupt disabled + #0 + + + 1 + PSWITCH rising edge interrupt enabled + #1 + + + + + PSWITCH_INT_FALL_EN + Enable falling edge detect for interrupt. + 1 + 1 + read-write + + + 0 + PSWITCH falling edge interrupt disabled + #0 + + + 1 + PSWITCH falling edge interrupt enabled + #1 + + + + + PSWITCH_INT_CLEAR + This bit clears the PSWITCH interrupt. + 2 + 1 + read-write + + + 0 + No effect + #0 + + + 1 + Clear PSWITCH interrupt + #1 + + + + + PSWITCH_INT_MUTE + Mask interrupt to SoC, edge detection result can be read from PSIWTCH_INT_STS. + 3 + 1 + read-write + + + PSWITCH_INT_STS + PSWITCH edge detection interrupt status + 31 + 1 + read-only + + + 0 + PSWITCH interrupt has not occurred + #0 + + + 1 + PSWITCH interrupt has occurred + #1 + + + + + + + REG7 + DCDC REGISTER 7 + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + INTEGRATOR_VALUE + Integrator value which can be loaded in pulsed mode + 0 + 19 + read-write + + + INTEGRATOR_VALUE_SEL + Select the integrator value from above register or saved value in hardware. + 19 + 1 + read-write + + + 0 + Select the saved value in hardware. + #0 + + + 1 + Select the integrator value in this register. + #1 + + + + + PULSE_RUN_SPEEDUP + Enable pulse run speedup + 20 + 1 + read-write + + + 0 + Pulse run speedup feature disabled + #0 + + + 1 + Pulse run speedup feature enabled + #1 + + + + + + + + + DSB + DSB + 0x4005B000 + + 0 + 0x18 + registers + + + + CSR + Control Register + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + SFTRST + Soft Reset + 0 + 1 + read-write + + + 0 + No operation. + #0 + + + 1 + Reset the data stream buffer. + #1 + + + + + DSB_EN + Data Stream Buffer Enable + 1 + 1 + read-write + + + 0 + Buffer is disabled + #0 + + + 1 + Buffer is enabled. + #1 + + + + + DMA_EN + DMA Transfer Enable + 2 + 1 + read-write + + + 0 + DMA transfers are disabled + #0 + + + 1 + DMA transfers are enabled. + #1 + + + + + INT_EN + Interrupt Request Enable + 3 + 1 + read-write + + + 0 + Interrupt requests on data ready or DMA done are disabled + #0 + + + + + ERR_EN + Error Interrupt Request Enable + 4 + 1 + read-write + + + 0 + Error interrupt requests on overflow, underrun, or bus error are disabled + #0 + + + 1 + Error interrupt requests on overflow, underrun, or bus error are enabled. + #1 + + + + + + + INT + Interrupt Request Status Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DRDY + Data Ready + 0 + 1 + read-only + + + 0 + No data to read (watermark has not been reached) + #0 + + + 1 + Data is ready to read (watermark has been reached) + #1 + + + + + OVRF + Overflow Error + 1 + 1 + read-write + + + 0 + No overflow error + #0 + + + 1 + The last recorded error is a buffer overflow + #1 + + + + + UNDR + Underrun Error + 2 + 1 + read-write + + + 0 + No underrun error + #0 + + + 1 + The last recorded error is an underrun on a read + #1 + + + + + DBE + Destination Bus Error + 3 + 1 + read-write + + + 0 + No destination bus error + #0 + + + 1 + The last recorded error is bus error on a write + #1 + + + + + DONE + DMA Packet Transfer Complete + 4 + 1 + read-write + + + 0 + Packet transfer not done; CCNT less than TCNT + #0 + + + 1 + Packet transfer is done; TCNT 32-bit words transferred + #1 + + + + + + + WMC + Watermark Configuration Register + 0x8 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + WMRK + Watermark + 0 + 4 + read-write + + + CNT + FIFO Count + 16 + 5 + read-only + + + SIZE + FIFO size + 24 + 5 + read-only + + + + + RDATA + FIFO Read Data Register + 0xC + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA + FIFO Data + 0 + 32 + read-only + + + + + DADDR + DMA Destination Address Register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + XCR + DMA Transfer Count Register + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + TCNT + Total Transfer Count + 0 + 16 + read-write + + + CCNT + Current Transfer Count + 16 + 16 + read-only + + + + + + + CMT + Carrier Modulator Transmitter + CMT_ + 0x40062000 + + 0 + 0xC + registers + + + CMT + 14 + + + + CGH1 + CMT Carrier Generator High Data Register 1 + 0 + 8 + read-write + 0 + 0 + + + PH + Primary Carrier High Time Data Value + 0 + 8 + read-write + + + + + CGL1 + CMT Carrier Generator Low Data Register 1 + 0x1 + 8 + read-write + 0 + 0 + + + PL + Primary Carrier Low Time Data Value + 0 + 8 + read-write + + + + + CGH2 + CMT Carrier Generator High Data Register 2 + 0x2 + 8 + read-write + 0 + 0 + + + SH + Secondary Carrier High Time Data Value + 0 + 8 + read-write + + + + + CGL2 + CMT Carrier Generator Low Data Register 2 + 0x3 + 8 + read-write + 0 + 0 + + + SL + Secondary Carrier Low Time Data Value + 0 + 8 + read-write + + + + + OC + CMT Output Control Register + 0x4 + 8 + read-write + 0 + 0xFF + + + IROPEN + IRO Pin Enable + 5 + 1 + read-write + + + 0 + The IRO signal is disabled. + #0 + + + 1 + The IRO signal is enabled as output. + #1 + + + + + CMTPOL + CMT Output Polarity + 6 + 1 + read-write + + + 0 + The IRO signal is active-low. + #0 + + + 1 + The IRO signal is active-high. + #1 + + + + + IROL + IRO Latch Control + 7 + 1 + read-write + + + + + MSC + CMT Modulator Status and Control Register + 0x5 + 8 + read-write + 0 + 0xFF + + + MCGEN + Modulator and Carrier Generator Enable + 0 + 1 + read-write + + + 0 + Modulator and carrier generator disabled + #0 + + + 1 + Modulator and carrier generator enabled + #1 + + + + + EOCIE + End of Cycle Interrupt Enable + 1 + 1 + read-write + + + 0 + CPU interrupt is disabled. + #0 + + + 1 + CPU interrupt is enabled. + #1 + + + + + FSK + FSK Mode Select + 2 + 1 + read-write + + + 0 + The CMT operates in Time or Baseband mode. + #0 + + + 1 + The CMT operates in FSK mode. + #1 + + + + + BASE + Baseband Enable + 3 + 1 + read-write + + + 0 + Baseband mode is disabled. + #0 + + + 1 + Baseband mode is enabled. + #1 + + + + + EXSPC + Extended Space Enable + 4 + 1 + read-write + + + 0 + Extended space is disabled. + #0 + + + 1 + Extended space is enabled. + #1 + + + + + CMTDIV + CMT Clock Divide Prescaler + 5 + 2 + read-write + + + 00 + IF / 1 + #00 + + + 01 + IF / 2 + #01 + + + 10 + IF / 4 + #10 + + + 11 + IF / 8 + #11 + + + + + EOCF + End Of Cycle Status Flag + 7 + 1 + read-only + + + 0 + End of modulation cycle has not occured since the flag last cleared. + #0 + + + 1 + End of modulator cycle has occurred. + #1 + + + + + + + CMD1 + CMT Modulator Data Register Mark High + 0x6 + 8 + read-write + 0 + 0 + + + MB + MB[15:8] + 0 + 8 + read-write + + + + + CMD2 + CMT Modulator Data Register Mark Low + 0x7 + 8 + read-write + 0 + 0 + + + MB + MB[7:0] + 0 + 8 + read-write + + + + + CMD3 + CMT Modulator Data Register Space High + 0x8 + 8 + read-write + 0 + 0 + + + SB + SB[15:8] + 0 + 8 + read-write + + + + + CMD4 + CMT Modulator Data Register Space Low + 0x9 + 8 + read-write + 0 + 0 + + + SB + SB[7:0] + 0 + 8 + read-write + + + + + PPS + CMT Primary Prescaler Register + 0xA + 8 + read-write + 0 + 0xFF + + + PPSDIV + Primary Prescaler Divider + 0 + 4 + read-write + + + 0000 + Bus clock / 1 + #0000 + + + 0001 + Bus clock / 2 + #0001 + + + 0010 + Bus clock / 3 + #0010 + + + 0011 + Bus clock / 4 + #0011 + + + 0100 + Bus clock / 5 + #0100 + + + 0101 + Bus clock / 6 + #0101 + + + 0110 + Bus clock / 7 + #0110 + + + 0111 + Bus clock / 8 + #0111 + + + 1000 + Bus clock / 9 + #1000 + + + 1001 + Bus clock / 10 + #1001 + + + 1010 + Bus clock / 11 + #1010 + + + 1011 + Bus clock / 12 + #1011 + + + 1100 + Bus clock / 13 + #1100 + + + 1101 + Bus clock / 14 + #1101 + + + 1110 + Bus clock / 15 + #1110 + + + 1111 + Bus clock / 16 + #1111 + + + + + + + DMA + CMT Direct Memory Access Register + 0xB + 8 + read-write + 0 + 0xFF + + + DMA + DMA Enable + 0 + 1 + read-write + + + 0 + DMA transfer request and done are disabled. + #0 + + + 1 + DMA transfer request and done are enabled. + #1 + + + + + + + + + MCG + Multipurpose Clock Generator module + MCG_ + 0x40064000 + + 0 + 0xE + registers + + + MCG + 27 + + + + C1 + MCG Control 1 Register + 0 + 8 + read-write + 0x4 + 0xFF + + + IREFSTEN + Internal Reference Stop Enable + 0 + 1 + read-write + + + 0 + Internal reference clock is disabled in Stop mode. + #0 + + + 1 + Internal reference clock is enabled in Stop mode if IRCLKEN is set or if MCG is in FEI, FBI, or BLPI modes before entering Stop mode. + #1 + + + + + IRCLKEN + Internal Reference Clock Enable + 1 + 1 + read-write + + + 0 + MCGIRCLK inactive. + #0 + + + 1 + MCGIRCLK active. + #1 + + + + + IREFS + Internal Reference Select + 2 + 1 + read-write + + + 0 + External reference clock is selected. + #0 + + + 1 + The slow internal reference clock is selected. + #1 + + + + + FRDIV + FLL External Reference Divider + 3 + 3 + read-write + + + 000 + If RANGE = 0 or OSCSEL=1 , Divide Factor is 1; for all other RANGE values, Divide Factor is 32. + #000 + + + 001 + If RANGE = 0 or OSCSEL=1 , Divide Factor is 2; for all other RANGE values, Divide Factor is 64. + #001 + + + 010 + If RANGE = 0 or OSCSEL=1 , Divide Factor is 4; for all other RANGE values, Divide Factor is 128. + #010 + + + 011 + If RANGE = 0 or OSCSEL=1 , Divide Factor is 8; for all other RANGE values, Divide Factor is 256. + #011 + + + 100 + If RANGE = 0 or OSCSEL=1 , Divide Factor is 16; for all other RANGE values, Divide Factor is 512. + #100 + + + 101 + If RANGE = 0 or OSCSEL=1 , Divide Factor is 32; for all other RANGE values, Divide Factor is 1024. + #101 + + + 110 + If RANGE = 0 or OSCSEL=1 , Divide Factor is 64; for all other RANGE values, Divide Factor is 1280 . + #110 + + + 111 + If RANGE = 0 or OSCSEL=1 , Divide Factor is 128; for all other RANGE values, Divide Factor is 1536 . + #111 + + + + + CLKS + Clock Source Select + 6 + 2 + read-write + + + 00 + Encoding 0 - Output of FLL is selected. + #00 + + + 01 + Encoding 1 - Internal reference clock is selected. + #01 + + + 10 + Encoding 2 - External reference clock is selected. + #10 + + + 11 + Encoding 3 - Reserved. + #11 + + + + + + + C2 + MCG Control 2 Register + 0x1 + 8 + read-write + 0x80 + 0xBF + + + IRCS + Internal Reference Clock Select + 0 + 1 + read-write + + + 0 + Slow internal reference clock selected. + #0 + + + 1 + Fast internal reference clock selected. + #1 + + + + + LP + Low Power Select + 1 + 1 + read-write + + + 0 + FLL is not disabled in bypass modes. + #0 + + + 1 + FLL is disabled in bypass modes (lower power) + #1 + + + + + EREFS + External Reference Select + 2 + 1 + read-write + + + 0 + External reference clock requested. + #0 + + + 1 + Oscillator requested. + #1 + + + + + HGO + High Gain Oscillator Select + 3 + 1 + read-write + + + 0 + Configure crystal oscillator for low-power operation. + #0 + + + 1 + Configure crystal oscillator for high-gain operation. + #1 + + + + + RANGE + Frequency Range Select + 4 + 2 + read-write + + + 0 + Encoding 0 - Low frequency range selected for the crystal oscillator . + #00 + + + 1 + Encoding 1 - High frequency range selected for the crystal oscillator . + #01 + + + + + FCFTRIM + Fast Internal Reference Clock Fine Trim + 6 + 1 + read-write + + + LOCRE0 + Loss of Clock Reset Enable + 7 + 1 + read-write + + + 0 + Interrupt request is generated on a loss of OSC0 external reference clock. + #0 + + + 1 + Generate a reset request on a loss of OSC0 external reference clock. + #1 + + + + + + + C3 + MCG Control 3 Register + 0x2 + 8 + read-write + 0 + 0 + + + SCTRIM + Slow Internal Reference Clock Trim Setting + 0 + 8 + read-write + + + + + C4 + MCG Control 4 Register + 0x3 + 8 + read-write + 0 + 0xE0 + + + SCFTRIM + Slow Internal Reference Clock Fine Trim + 0 + 1 + read-write + + + FCTRIM + Fast Internal Reference Clock Trim Setting + 1 + 4 + read-write + + + DRST_DRS + DCO Range Select + 5 + 2 + read-write + + + 00 + Encoding 0 - Low range (reset default). + #00 + + + 01 + Encoding 1 - Mid range. + #01 + + + 10 + Encoding 2 - Mid-high range. + #10 + + + 11 + Encoding 3 - High range. + #11 + + + + + DMX32 + DCO Maximum Frequency with 32.768 kHz Reference + 7 + 1 + read-write + + + 0 + DCO has a default range of 25%. + #0 + + + 1 + DCO is fine-tuned for maximum frequency with 32.768 kHz reference. + #1 + + + + + + + C5 + MCG Control 5 Register + 0x4 + 8 + read-only + 0 + 0xFF + + + C6 + MCG Control 6 Register + 0x5 + 8 + read-write + 0 + 0xFF + + + CME0 + Clock Monitor Enable + 5 + 1 + read-write + + + 0 + External clock monitor is disabled. + #0 + + + 1 + Generate an interrupt or a reset request (see MCG_C2[LOCRE0]) on loss of external clock. + #1 + + + + + + + S + MCG Status Register + 0x6 + 8 + read-only + 0x10 + 0xFF + + + IRCST + Internal Reference Clock Status + 0 + 1 + read-only + + + 0 + Source of internal reference clock is the slow clock (32 kHz IRC). + #0 + + + 1 + Source of internal reference clock is the fast clock (4 MHz IRC). + #1 + + + + + OSCINIT0 + OSC Initialization + 1 + 1 + read-only + + + CLKST + Clock Mode Status + 2 + 2 + read-only + + + 00 + Encoding 0 - Output of the FLL is selected (reset default). + #00 + + + 01 + Encoding 1 - Internal reference clock is selected. + #01 + + + 10 + Encoding 2 - External reference clock is selected. + #10 + + + + + IREFST + Internal Reference Status + 4 + 1 + read-only + + + 0 + Source of FLL reference clock is the external reference clock. + #0 + + + 1 + Source of FLL reference clock is the internal reference clock. + #1 + + + + + + + SC + MCG Status and Control Register + 0x8 + 8 + read-write + 0x2 + 0xFF + + + LOCS0 + OSC0 Loss of Clock Status + 0 + 1 + read-write + + + 0 + Loss of OSC0 has not occurred. + #0 + + + 1 + Loss of OSC0 has occurred. + #1 + + + + + FCRDIV + Fast Clock Internal Reference Divider + 1 + 3 + read-write + + + 000 + Divide Factor is 1 + #000 + + + 001 + Divide Factor is 2. + #001 + + + 010 + Divide Factor is 4. + #010 + + + 011 + Divide Factor is 8. + #011 + + + 100 + Divide Factor is 16 + #100 + + + 101 + Divide Factor is 32 + #101 + + + 110 + Divide Factor is 64 + #110 + + + 111 + Divide Factor is 128. + #111 + + + + + FLTPRSRV + FLL Filter Preserve Enable + 4 + 1 + read-write + + + 0 + FLL filter and FLL frequency will reset on changes to currect clock mode. + #0 + + + 1 + Fll filter and FLL frequency retain their previous values during new clock mode change. + #1 + + + + + ATMF + Automatic Trim Machine Fail Flag + 5 + 1 + read-write + + + 0 + Automatic Trim Machine completed normally. + #0 + + + 1 + Automatic Trim Machine failed. + #1 + + + + + ATMS + Automatic Trim Machine Select + 6 + 1 + read-write + + + 0 + 32 kHz Internal Reference Clock selected. + #0 + + + 1 + 4 MHz Internal Reference Clock selected. + #1 + + + + + ATME + Automatic Trim Machine Enable + 7 + 1 + read-write + + + 0 + Auto Trim Machine disabled. + #0 + + + 1 + Auto Trim Machine enabled. + #1 + + + + + + + ATCVH + MCG Auto Trim Compare Value High Register + 0xA + 8 + read-write + 0 + 0xFF + + + ATCVH + ATM Compare Value High + 0 + 8 + read-write + + + + + ATCVL + MCG Auto Trim Compare Value Low Register + 0xB + 8 + read-write + 0 + 0xFF + + + ATCVL + ATM Compare Value Low + 0 + 8 + read-write + + + + + C7 + MCG Control 7 Register + 0xC + 8 + read-write + 0 + 0xFF + + + OSCSEL + MCG OSC Clock Select + 0 + 1 + read-write + + + 0 + Selects Oscillator (OSCCLK). + #0 + + + 1 + Selects 32 kHz RTC Oscillator. + #1 + + + + + + + C8 + MCG Control 8 Register + 0xD + 8 + read-write + 0x80 + 0xFF + + + LOCS1 + RTC Loss of Clock Status + 0 + 1 + read-write + + + 0 + Loss of RTC has not occur. + #0 + + + 1 + Loss of RTC has occur + #1 + + + + + CME1 + Clock Monitor Enable1 + 5 + 1 + read-write + + + 0 + External clock monitor is disabled for RTC clock. + #0 + + + 1 + External clock monitor is enabled for RTC clock. + #1 + + + + + LOCRE1 + Loss of Clock Reset Enable + 7 + 1 + read-write + + + 0 + Interrupt request is generated on a loss of RTC external reference clock. + #0 + + + 1 + Generate a reset request on a loss of RTC external reference clock + #1 + + + + + + + + + I2C0 + Inter-Integrated Circuit + I2C + I2C0_ + 0x40066000 + + 0 + 0xD + registers + + + I2C0 + 8 + + + + A1 + I2C Address Register 1 + 0 + 8 + read-write + 0 + 0xFF + + + AD + Address + 1 + 7 + read-write + + + + + F + I2C Frequency Divider register + 0x1 + 8 + read-write + 0 + 0xFF + + + ICR + ClockRate + 0 + 6 + read-write + + + MULT + Multiplier Factor + 6 + 2 + read-write + + + 00 + mul = 1 + #00 + + + 01 + mul = 2 + #01 + + + 10 + mul = 4 + #10 + + + + + + + C1 + I2C Control Register 1 + 0x2 + 8 + read-write + 0 + 0xFF + + + DMAEN + DMA Enable + 0 + 1 + read-write + + + 0 + All DMA signalling disabled. + #0 + + + 1 + DMA transfer is enabled. While SMB[FACK] = 0, the following conditions trigger the DMA request: a data byte is received, and either address or data is transmitted. (ACK/NACK is automatic) the first byte received matches the A1 register or is a general call address. If any address matching occurs, S[IAAS] and S[TCF] are set. If the direction of transfer is known from master to slave, then it is not required to check S[SRW]. With this assumption, DMA can also be used in this case. In other cases, if the master reads data from the slave, then it is required to rewrite the C1 register operation. With this assumption, DMA cannot be used. When FACK = 1, an address or a data byte is transmitted. + #1 + + + + + WUEN + Wakeup Enable + 1 + 1 + read-write + + + 0 + Normal operation. No interrupt generated when address matching in low power mode. + #0 + + + 1 + Enables the wakeup function in low power mode. + #1 + + + + + RSTA + Repeat START + 2 + 1 + read-write + + + TXAK + Transmit Acknowledge Enable + 3 + 1 + read-write + + + 0 + An acknowledge signal is sent to the bus on the following receiving byte (if FACK is cleared) or the current receiving byte (if FACK is set). + #0 + + + 1 + No acknowledge signal is sent to the bus on the following receiving data byte (if FACK is cleared) or the current receiving data byte (if FACK is set). + #1 + + + + + TX + Transmit Mode Select + 4 + 1 + read-write + + + 0 + Receive + #0 + + + 1 + Transmit + #1 + + + + + MST + Master Mode Select + 5 + 1 + read-write + + + 0 + Slave mode + #0 + + + 1 + Master mode + #1 + + + + + IICIE + I2C Interrupt Enable + 6 + 1 + read-write + + + 0 + Disabled + #0 + + + 1 + Enabled + #1 + + + + + IICEN + I2C Enable + 7 + 1 + read-write + + + 0 + Disabled + #0 + + + 1 + Enabled + #1 + + + + + + + S + I2C Status register + 0x3 + 8 + read-write + 0x80 + 0xFF + + + RXAK + Receive Acknowledge + 0 + 1 + read-only + + + 0 + Acknowledge signal was received after the completion of one byte of data transmission on the bus + #0 + + + 1 + No acknowledge signal detected + #1 + + + + + IICIF + Interrupt Flag + 1 + 1 + read-write + + + 0 + No interrupt pending + #0 + + + 1 + Interrupt pending + #1 + + + + + SRW + Slave Read/Write + 2 + 1 + read-only + + + 0 + Slave receive, master writing to slave + #0 + + + 1 + Slave transmit, master reading from slave + #1 + + + + + RAM + Range Address Match + 3 + 1 + read-write + + + 0 + Not addressed + #0 + + + 1 + Addressed as a slave + #1 + + + + + ARBL + Arbitration Lost + 4 + 1 + read-write + + + 0 + Standard bus operation. + #0 + + + 1 + Loss of arbitration. + #1 + + + + + BUSY + Bus Busy + 5 + 1 + read-only + + + 0 + Bus is idle + #0 + + + 1 + Bus is busy + #1 + + + + + IAAS + Addressed As A Slave + 6 + 1 + read-write + + + 0 + Not addressed + #0 + + + 1 + Addressed as a slave + #1 + + + + + TCF + Transfer Complete Flag + 7 + 1 + read-only + + + 0 + Transfer in progress + #0 + + + 1 + Transfer complete + #1 + + + + + + + D + I2C Data I/O register + 0x4 + 8 + read-write + 0 + 0xFF + + + DATA + Data + 0 + 8 + read-write + + + + + C2 + I2C Control Register 2 + 0x5 + 8 + read-write + 0 + 0xFF + + + AD + Slave Address + 0 + 3 + read-write + + + RMEN + Range Address Matching Enable + 3 + 1 + read-write + + + 0 + Range mode disabled. No address matching occurs for an address within the range of values of the A1 and RA registers. + #0 + + + 1 + Range mode enabled. Address matching occurs when a slave receives an address within the range of values of the A1 and RA registers. + #1 + + + + + SBRC + Slave Baud Rate Control + 4 + 1 + read-write + + + 0 + The slave baud rate follows the master baud rate and clock stretching may occur + #0 + + + 1 + Slave baud rate is independent of the master baud rate + #1 + + + + + HDRS + High Drive Select + 5 + 1 + read-write + + + 0 + Normal drive mode + #0 + + + 1 + High drive mode + #1 + + + + + ADEXT + Address Extension + 6 + 1 + read-write + + + 0 + 7-bit address scheme + #0 + + + 1 + 10-bit address scheme + #1 + + + + + GCAEN + General Call Address Enable + 7 + 1 + read-write + + + 0 + Disabled + #0 + + + 1 + Enabled + #1 + + + + + + + FLT + I2C Programmable Input Glitch Filter Register + 0x6 + 8 + read-write + 0 + 0xFF + + + FLT + I2C Programmable Filter Factor + 0 + 4 + read-write + + + 0 + No filter/bypass + #0000 + + + + + STARTF + I2C Bus Start Detect Flag + 4 + 1 + read-write + + + 0 + No start happens on I2C bus + #0 + + + 1 + Start detected on I2C bus + #1 + + + + + SSIE + I2C Bus Stop or Start Interrupt Enable + 5 + 1 + read-write + + + 0 + Stop or start detection interrupt is disabled + #0 + + + 1 + Stop or start detection interrupt is enabled + #1 + + + + + STOPF + I2C Bus Stop Detect Flag + 6 + 1 + read-write + + + 0 + No stop happens on I2C bus + #0 + + + 1 + Stop detected on I2C bus + #1 + + + + + SHEN + Stop Hold Enable + 7 + 1 + read-write + + + 0 + Stop holdoff is disabled. The MCU's entry to stop mode is not gated. + #0 + + + 1 + Stop holdoff is enabled. + #1 + + + + + + + RA + I2C Range Address register + 0x7 + 8 + read-write + 0 + 0xFF + + + RAD + Range Slave Address + 1 + 7 + read-write + + + + + SMB + I2C SMBus Control and Status register + 0x8 + 8 + read-write + 0 + 0xFF + + + SHTF2IE + SHTF2 Interrupt Enable + 0 + 1 + read-write + + + 0 + SHTF2 interrupt is disabled + #0 + + + 1 + SHTF2 interrupt is enabled + #1 + + + + + SHTF2 + SCL High Timeout Flag 2 + 1 + 1 + read-write + + + 0 + No SCL high and SDA low timeout occurs + #0 + + + 1 + SCL high and SDA low timeout occurs + #1 + + + + + SHTF1 + SCL High Timeout Flag 1 + 2 + 1 + read-only + + + 0 + No SCL high and SDA high timeout occurs + #0 + + + 1 + SCL high and SDA high timeout occurs + #1 + + + + + SLTF + SCL Low Timeout Flag + 3 + 1 + read-write + + + 0 + No low timeout occurs + #0 + + + 1 + Low timeout occurs + #1 + + + + + TCKSEL + Timeout Counter Clock Select + 4 + 1 + read-write + + + 0 + Timeout counter counts at the frequency of the I2C module clock / 64 + #0 + + + 1 + Timeout counter counts at the frequency of the I2C module clock + #1 + + + + + SIICAEN + Second I2C Address Enable + 5 + 1 + read-write + + + 0 + I2C address register 2 matching is disabled + #0 + + + 1 + I2C address register 2 matching is enabled + #1 + + + + + ALERTEN + SMBus Alert Response Address Enable + 6 + 1 + read-write + + + 0 + SMBus alert response address matching is disabled + #0 + + + 1 + SMBus alert response address matching is enabled + #1 + + + + + FACK + Fast NACK/ACK Enable + 7 + 1 + read-write + + + 0 + An ACK or NACK is sent on the following receiving data byte + #0 + + + 1 + Writing 0 to TXAK after receiving a data byte generates an ACK. Writing 1 to TXAK after receiving a data byte generates a NACK. Enable I2C_S2[DFEN] in the master receive mode. + #1 + + + + + + + A2 + I2C Address Register 2 + 0x9 + 8 + read-write + 0xC2 + 0xFF + + + SAD + SMBus Address + 1 + 7 + read-write + + + + + SLTH + I2C SCL Low Timeout Register High + 0xA + 8 + read-write + 0 + 0xFF + + + SSLT + SSLT[15:8] + 0 + 8 + read-write + + + + + SLTL + I2C SCL Low Timeout Register Low + 0xB + 8 + read-write + 0 + 0xFF + + + SSLT + SSLT[7:0] + 0 + 8 + read-write + + + + + S2 + I2C Status register 2 + 0xC + 8 + read-write + 0x1 + 0xFF + + + EMPTY + Empty flag + 0 + 1 + read-only + + + 0 + Tx or Rx buffer is not empty and cannot be written to, that is new data cannot be loaded into the buffer. + #0 + + + 1 + Tx or Rx buffer is empty and can be written to, that is new data can be loaded into the buffer. + #1 + + + + + ERROR + Error flag + 1 + 1 + read-write + + + 0 + The buffer is not full and all write/read operations have no errors. + #0 + + + 1 + There are 3 or more write/read errors during the data transfer phase (when the Empty flag is not set and the buffer is busy). + #1 + + + + + DFEN + Double Buffer Enable + 2 + 1 + read-write + + + 0 + Disables the double buffer mode; clock stretch is enabled. + #0 + + + 1 + Enables the double buffer mode; clock stretch is disabled. In the slave mode, the I2C will not hold bus between data transfers. + #1 + + + + + + + + + I2C1 + Inter-Integrated Circuit + I2C + I2C1_ + 0x40067000 + + 0 + 0xD + registers + + + I2C1 + 9 + + + + A1 + I2C Address Register 1 + 0 + 8 + read-write + 0 + 0xFF + + + AD + Address + 1 + 7 + read-write + + + + + F + I2C Frequency Divider register + 0x1 + 8 + read-write + 0 + 0xFF + + + ICR + ClockRate + 0 + 6 + read-write + + + MULT + Multiplier Factor + 6 + 2 + read-write + + + 00 + mul = 1 + #00 + + + 01 + mul = 2 + #01 + + + 10 + mul = 4 + #10 + + + + + + + C1 + I2C Control Register 1 + 0x2 + 8 + read-write + 0 + 0xFF + + + DMAEN + DMA Enable + 0 + 1 + read-write + + + 0 + All DMA signalling disabled. + #0 + + + 1 + DMA transfer is enabled. While SMB[FACK] = 0, the following conditions trigger the DMA request: a data byte is received, and either address or data is transmitted. (ACK/NACK is automatic) the first byte received matches the A1 register or is a general call address. If any address matching occurs, S[IAAS] and S[TCF] are set. If the direction of transfer is known from master to slave, then it is not required to check S[SRW]. With this assumption, DMA can also be used in this case. In other cases, if the master reads data from the slave, then it is required to rewrite the C1 register operation. With this assumption, DMA cannot be used. When FACK = 1, an address or a data byte is transmitted. + #1 + + + + + WUEN + Wakeup Enable + 1 + 1 + read-write + + + 0 + Normal operation. No interrupt generated when address matching in low power mode. + #0 + + + 1 + Enables the wakeup function in low power mode. + #1 + + + + + RSTA + Repeat START + 2 + 1 + read-write + + + TXAK + Transmit Acknowledge Enable + 3 + 1 + read-write + + + 0 + An acknowledge signal is sent to the bus on the following receiving byte (if FACK is cleared) or the current receiving byte (if FACK is set). + #0 + + + 1 + No acknowledge signal is sent to the bus on the following receiving data byte (if FACK is cleared) or the current receiving data byte (if FACK is set). + #1 + + + + + TX + Transmit Mode Select + 4 + 1 + read-write + + + 0 + Receive + #0 + + + 1 + Transmit + #1 + + + + + MST + Master Mode Select + 5 + 1 + read-write + + + 0 + Slave mode + #0 + + + 1 + Master mode + #1 + + + + + IICIE + I2C Interrupt Enable + 6 + 1 + read-write + + + 0 + Disabled + #0 + + + 1 + Enabled + #1 + + + + + IICEN + I2C Enable + 7 + 1 + read-write + + + 0 + Disabled + #0 + + + 1 + Enabled + #1 + + + + + + + S + I2C Status register + 0x3 + 8 + read-write + 0x80 + 0xFF + + + RXAK + Receive Acknowledge + 0 + 1 + read-only + + + 0 + Acknowledge signal was received after the completion of one byte of data transmission on the bus + #0 + + + 1 + No acknowledge signal detected + #1 + + + + + IICIF + Interrupt Flag + 1 + 1 + read-write + + + 0 + No interrupt pending + #0 + + + 1 + Interrupt pending + #1 + + + + + SRW + Slave Read/Write + 2 + 1 + read-only + + + 0 + Slave receive, master writing to slave + #0 + + + 1 + Slave transmit, master reading from slave + #1 + + + + + RAM + Range Address Match + 3 + 1 + read-write + + + 0 + Not addressed + #0 + + + 1 + Addressed as a slave + #1 + + + + + ARBL + Arbitration Lost + 4 + 1 + read-write + + + 0 + Standard bus operation. + #0 + + + 1 + Loss of arbitration. + #1 + + + + + BUSY + Bus Busy + 5 + 1 + read-only + + + 0 + Bus is idle + #0 + + + 1 + Bus is busy + #1 + + + + + IAAS + Addressed As A Slave + 6 + 1 + read-write + + + 0 + Not addressed + #0 + + + 1 + Addressed as a slave + #1 + + + + + TCF + Transfer Complete Flag + 7 + 1 + read-only + + + 0 + Transfer in progress + #0 + + + 1 + Transfer complete + #1 + + + + + + + D + I2C Data I/O register + 0x4 + 8 + read-write + 0 + 0xFF + + + DATA + Data + 0 + 8 + read-write + + + + + C2 + I2C Control Register 2 + 0x5 + 8 + read-write + 0 + 0xFF + + + AD + Slave Address + 0 + 3 + read-write + + + RMEN + Range Address Matching Enable + 3 + 1 + read-write + + + 0 + Range mode disabled. No address matching occurs for an address within the range of values of the A1 and RA registers. + #0 + + + 1 + Range mode enabled. Address matching occurs when a slave receives an address within the range of values of the A1 and RA registers. + #1 + + + + + SBRC + Slave Baud Rate Control + 4 + 1 + read-write + + + 0 + The slave baud rate follows the master baud rate and clock stretching may occur + #0 + + + 1 + Slave baud rate is independent of the master baud rate + #1 + + + + + HDRS + High Drive Select + 5 + 1 + read-write + + + 0 + Normal drive mode + #0 + + + 1 + High drive mode + #1 + + + + + ADEXT + Address Extension + 6 + 1 + read-write + + + 0 + 7-bit address scheme + #0 + + + 1 + 10-bit address scheme + #1 + + + + + GCAEN + General Call Address Enable + 7 + 1 + read-write + + + 0 + Disabled + #0 + + + 1 + Enabled + #1 + + + + + + + FLT + I2C Programmable Input Glitch Filter Register + 0x6 + 8 + read-write + 0 + 0xFF + + + FLT + I2C Programmable Filter Factor + 0 + 4 + read-write + + + 0 + No filter/bypass + #0000 + + + + + STARTF + I2C Bus Start Detect Flag + 4 + 1 + read-write + + + 0 + No start happens on I2C bus + #0 + + + 1 + Start detected on I2C bus + #1 + + + + + SSIE + I2C Bus Stop or Start Interrupt Enable + 5 + 1 + read-write + + + 0 + Stop or start detection interrupt is disabled + #0 + + + 1 + Stop or start detection interrupt is enabled + #1 + + + + + STOPF + I2C Bus Stop Detect Flag + 6 + 1 + read-write + + + 0 + No stop happens on I2C bus + #0 + + + 1 + Stop detected on I2C bus + #1 + + + + + SHEN + Stop Hold Enable + 7 + 1 + read-write + + + 0 + Stop holdoff is disabled. The MCU's entry to stop mode is not gated. + #0 + + + 1 + Stop holdoff is enabled. + #1 + + + + + + + RA + I2C Range Address register + 0x7 + 8 + read-write + 0 + 0xFF + + + RAD + Range Slave Address + 1 + 7 + read-write + + + + + SMB + I2C SMBus Control and Status register + 0x8 + 8 + read-write + 0 + 0xFF + + + SHTF2IE + SHTF2 Interrupt Enable + 0 + 1 + read-write + + + 0 + SHTF2 interrupt is disabled + #0 + + + 1 + SHTF2 interrupt is enabled + #1 + + + + + SHTF2 + SCL High Timeout Flag 2 + 1 + 1 + read-write + + + 0 + No SCL high and SDA low timeout occurs + #0 + + + 1 + SCL high and SDA low timeout occurs + #1 + + + + + SHTF1 + SCL High Timeout Flag 1 + 2 + 1 + read-only + + + 0 + No SCL high and SDA high timeout occurs + #0 + + + 1 + SCL high and SDA high timeout occurs + #1 + + + + + SLTF + SCL Low Timeout Flag + 3 + 1 + read-write + + + 0 + No low timeout occurs + #0 + + + 1 + Low timeout occurs + #1 + + + + + TCKSEL + Timeout Counter Clock Select + 4 + 1 + read-write + + + 0 + Timeout counter counts at the frequency of the I2C module clock / 64 + #0 + + + 1 + Timeout counter counts at the frequency of the I2C module clock + #1 + + + + + SIICAEN + Second I2C Address Enable + 5 + 1 + read-write + + + 0 + I2C address register 2 matching is disabled + #0 + + + 1 + I2C address register 2 matching is enabled + #1 + + + + + ALERTEN + SMBus Alert Response Address Enable + 6 + 1 + read-write + + + 0 + SMBus alert response address matching is disabled + #0 + + + 1 + SMBus alert response address matching is enabled + #1 + + + + + FACK + Fast NACK/ACK Enable + 7 + 1 + read-write + + + 0 + An ACK or NACK is sent on the following receiving data byte + #0 + + + 1 + Writing 0 to TXAK after receiving a data byte generates an ACK. Writing 1 to TXAK after receiving a data byte generates a NACK. Enable I2C_S2[DFEN] in the master receive mode. + #1 + + + + + + + A2 + I2C Address Register 2 + 0x9 + 8 + read-write + 0xC2 + 0xFF + + + SAD + SMBus Address + 1 + 7 + read-write + + + + + SLTH + I2C SCL Low Timeout Register High + 0xA + 8 + read-write + 0 + 0xFF + + + SSLT + SSLT[15:8] + 0 + 8 + read-write + + + + + SLTL + I2C SCL Low Timeout Register Low + 0xB + 8 + read-write + 0 + 0xFF + + + SSLT + SSLT[7:0] + 0 + 8 + read-write + + + + + S2 + I2C Status register 2 + 0xC + 8 + read-write + 0x1 + 0xFF + + + EMPTY + Empty flag + 0 + 1 + read-only + + + 0 + Tx or Rx buffer is not empty and cannot be written to, that is new data cannot be loaded into the buffer. + #0 + + + 1 + Tx or Rx buffer is empty and can be written to, that is new data can be loaded into the buffer. + #1 + + + + + ERROR + Error flag + 1 + 1 + read-write + + + 0 + The buffer is not full and all write/read operations have no errors. + #0 + + + 1 + There are 3 or more write/read errors during the data transfer phase (when the Empty flag is not set and the buffer is busy). + #1 + + + + + DFEN + Double Buffer Enable + 2 + 1 + read-write + + + 0 + Disables the double buffer mode; clock stretch is enabled. + #0 + + + 1 + Enables the double buffer mode; clock stretch is disabled. In the slave mode, the I2C will not hold bus between data transfers. + #1 + + + + + + + + + CMP0 + High-Speed Comparator (CMP), Voltage Reference (VREF) Digital-to-Analog Converter (DAC), and Analog Mux (ANMUX) + CMP0_ + 0x40073000 + + 0 + 0x6 + registers + + + CMP0 + 16 + + + + CR0 + CMP Control Register 0 + 0 + 8 + read-write + 0 + 0xFF + + + HYSTCTR + Comparator hard block hysteresis control + 0 + 2 + read-write + + + 00 + Level 0 + #00 + + + 01 + Level 1 + #01 + + + 10 + Level 2 + #10 + + + 11 + Level 3 + #11 + + + + + FILTER_CNT + Filter Sample Count + 4 + 3 + read-write + + + 000 + Filter is disabled. SE = 0, COUT = COUTA. + #000 + + + 001 + One sample must agree. The comparator output is simply sampled. + #001 + + + 010 + 2 consecutive samples must agree. + #010 + + + 011 + 3 consecutive samples must agree. + #011 + + + 100 + 4 consecutive samples must agree. + #100 + + + 101 + 5 consecutive samples must agree. + #101 + + + 110 + 6 consecutive samples must agree. + #110 + + + 111 + 7 consecutive samples must agree. + #111 + + + + + + + CR1 + CMP Control Register 1 + 0x1 + 8 + read-write + 0 + 0xFF + + + EN + Comparator Module Enable + 0 + 1 + read-write + + + 0 + Analog Comparator is disabled. + #0 + + + 1 + Analog Comparator is enabled. + #1 + + + + + OPE + Comparator Output Pin Enable + 1 + 1 + read-write + + + 0 + CMPO is not available on the associated CMPO output pin. If the comparator does not own the pin, this field has no effect. + #0 + + + 1 + CMPO is available on the associated CMPO output pin. The comparator output (CMPO) is driven out on the associated CMPO output pin if the comparator owns the pin. If the comparator does not own the field, this bit has no effect. + #1 + + + + + COS + Comparator Output Select + 2 + 1 + read-write + + + 0 + Set the filtered comparator output (CMPO) to equal COUT. + #0 + + + 1 + Set the unfiltered comparator output (CMPO) to equal COUTA. + #1 + + + + + INV + Comparator INVERT + 3 + 1 + read-write + + + 0 + Does not invert the comparator output. + #0 + + + 1 + Inverts the comparator output. + #1 + + + + + PMODE + Power Mode Select + 4 + 1 + read-write + + + 0 + Low-Speed (LS) Comparison mode selected. In this mode, CMP has slower output propagation delay and lower current consumption. + #0 + + + 1 + High-Speed (HS) Comparison mode selected. In this mode, CMP has faster output propagation delay and higher current consumption. + #1 + + + + + TRIGM + Trigger Mode Enable + 5 + 1 + read-write + + + 0 + Trigger mode is disabled. + #0 + + + 1 + Trigger mode is enabled. + #1 + + + + + WE + Windowing Enable + 6 + 1 + read-write + + + 0 + Windowing mode is not selected. + #0 + + + 1 + Windowing mode is selected. + #1 + + + + + SE + Sample Enable + 7 + 1 + read-write + + + 0 + Sampling mode is not selected. + #0 + + + 1 + Sampling mode is selected. + #1 + + + + + + + FPR + CMP Filter Period Register + 0x2 + 8 + read-write + 0 + 0xFF + + + FILT_PER + Filter Sample Period + 0 + 8 + read-write + + + + + SCR + CMP Status and Control Register + 0x3 + 8 + read-write + 0 + 0xFF + + + COUT + Analog Comparator Output + 0 + 1 + read-only + + + CFF + Analog Comparator Flag Falling + 1 + 1 + read-write + + + 0 + Falling-edge on COUT has not been detected. + #0 + + + 1 + Falling-edge on COUT has occurred. + #1 + + + + + CFR + Analog Comparator Flag Rising + 2 + 1 + read-write + + + 0 + Rising-edge on COUT has not been detected. + #0 + + + 1 + Rising-edge on COUT has occurred. + #1 + + + + + IEF + Comparator Interrupt Enable Falling + 3 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IER + Comparator Interrupt Enable Rising + 4 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + DMAEN + DMA Enable Control + 6 + 1 + read-write + + + 0 + DMA is disabled. + #0 + + + 1 + DMA is enabled. + #1 + + + + + + + DACCR + DAC Control Register + 0x4 + 8 + read-write + 0 + 0xFF + + + VOSEL + DAC Output Voltage Select + 0 + 6 + read-write + + + VRSEL + Supply Voltage Reference Source Select + 6 + 1 + read-write + + + 0 + Vin1 is selected as resistor ladder network supply reference. + #0 + + + 1 + Vin2 is selected as resistor ladder network supply reference. + #1 + + + + + DACEN + DAC Enable + 7 + 1 + read-write + + + 0 + DAC is disabled. + #0 + + + 1 + DAC is enabled. + #1 + + + + + + + MUXCR + MUX Control Register + 0x5 + 8 + read-write + 0 + 0xFF + + + MSEL + Minus Input Mux Control + 0 + 3 + read-write + + + 000 + IN0 + #000 + + + 001 + IN1 + #001 + + + 010 + IN2 + #010 + + + 011 + IN3 + #011 + + + 100 + IN4 + #100 + + + 101 + IN5 + #101 + + + 110 + IN6 + #110 + + + 111 + IN7 + #111 + + + + + PSEL + Plus Input Mux Control + 3 + 3 + read-write + + + 000 + IN0 + #000 + + + 001 + IN1 + #001 + + + 010 + IN2 + #010 + + + 011 + IN3 + #011 + + + 100 + IN4 + #100 + + + 101 + IN5 + #101 + + + 110 + IN6 + #110 + + + 111 + IN7 + #111 + + + + + PSTM + Pass Through Mode Enable + 7 + 1 + read-write + + + 0 + Pass Through Mode is disabled. + #0 + + + 1 + Pass Through Mode is enabled. + #1 + + + + + + + + + VREF + Voltage Reference + VREF_ + 0x40074000 + + 0 + 0x2 + registers + + + + TRM + VREF Trim Register + 0 + 8 + read-write + 0 + 0x40 + + + TRIM + Trim bits + 0 + 6 + read-write + + + 000000 + Min + #0 + + + 111111 + Max + #111111 + + + + + CHOPEN + Chop oscillator enable. When set, internal chopping operation is enabled and the internal analog offset will be minimized. + 6 + 1 + read-write + + + 0 + Chop oscillator is disabled. + #0 + + + 1 + Chop oscillator is enabled. + #1 + + + + + + + SC + VREF Status and Control Register + 0x1 + 8 + read-write + 0 + 0xFF + + + MODE_LV + Buffer Mode selection + 0 + 2 + read-write + + + 00 + Bandgap on only, for stabilization and startup + #00 + + + 01 + High power buffer mode enabled + #01 + + + 10 + Low-power buffer mode enabled + #10 + + + + + VREFST + Internal Voltage Reference stable + 2 + 1 + read-only + + + 0 + The module is disabled or not stable. + #0 + + + 1 + The module is stable. + #1 + + + + + ICOMPEN + Second order curvature compensation enable + 5 + 1 + read-write + + + 0 + Disabled + #0 + + + 1 + Enabled + #1 + + + + + REGEN + Regulator enable + 6 + 1 + read-write + + + 0 + Internal 1.75 V regulator is disabled. + #0 + + + 1 + Internal 1.75 V regulator is enabled. + #1 + + + + + VREFEN + Internal Voltage Reference enable + 7 + 1 + read-write + + + 0 + The module is disabled. + #0 + + + 1 + The module is enabled. + #1 + + + + + + + + + LLWU + Low leakage wakeup unit + LLWU_ + 0x4007C000 + + 0 + 0xA + registers + + + LLWU + 7 + + + + PE1 + LLWU Pin Enable 1 register + 0 + 8 + read-write + 0 + 0xFF + + + WUPE0 + Wakeup Pin Enable For LLWU_P0 + 0 + 2 + read-write + + + 00 + External input pin disabled as wakeup input + #00 + + + 01 + External input pin enabled with rising edge detection + #01 + + + 10 + External input pin enabled with falling edge detection + #10 + + + 11 + External input pin enabled with any change detection + #11 + + + + + WUPE1 + Wakeup Pin Enable For LLWU_P1 + 2 + 2 + read-write + + + 00 + External input pin disabled as wakeup input + #00 + + + 01 + External input pin enabled with rising edge detection + #01 + + + 10 + External input pin enabled with falling edge detection + #10 + + + 11 + External input pin enabled with any change detection + #11 + + + + + WUPE2 + Wakeup Pin Enable For LLWU_P2 + 4 + 2 + read-write + + + 00 + External input pin disabled as wakeup input + #00 + + + 01 + External input pin enabled with rising edge detection + #01 + + + 10 + External input pin enabled with falling edge detection + #10 + + + 11 + External input pin enabled with any change detection + #11 + + + + + WUPE3 + Wakeup Pin Enable For LLWU_P3 + 6 + 2 + read-write + + + 00 + External input pin disabled as wakeup input + #00 + + + 01 + External input pin enabled with rising edge detection + #01 + + + 10 + External input pin enabled with falling edge detection + #10 + + + 11 + External input pin enabled with any change detection + #11 + + + + + + + PE2 + LLWU Pin Enable 2 register + 0x1 + 8 + read-write + 0 + 0xFF + + + WUPE4 + Wakeup Pin Enable For LLWU_P4 + 0 + 2 + read-write + + + 00 + External input pin disabled as wakeup input + #00 + + + 01 + External input pin enabled with rising edge detection + #01 + + + 10 + External input pin enabled with falling edge detection + #10 + + + 11 + External input pin enabled with any change detection + #11 + + + + + WUPE5 + Wakeup Pin Enable For LLWU_P5 + 2 + 2 + read-write + + + 00 + External input pin disabled as wakeup input + #00 + + + 01 + External input pin enabled with rising edge detection + #01 + + + 10 + External input pin enabled with falling edge detection + #10 + + + 11 + External input pin enabled with any change detection + #11 + + + + + WUPE6 + Wakeup Pin Enable For LLWU_P6 + 4 + 2 + read-write + + + 00 + External input pin disabled as wakeup input + #00 + + + 01 + External input pin enabled with rising edge detection + #01 + + + 10 + External input pin enabled with falling edge detection + #10 + + + 11 + External input pin enabled with any change detection + #11 + + + + + WUPE7 + Wakeup Pin Enable For LLWU_P7 + 6 + 2 + read-write + + + 00 + External input pin disabled as wakeup input + #00 + + + 01 + External input pin enabled with rising edge detection + #01 + + + 10 + External input pin enabled with falling edge detection + #10 + + + 11 + External input pin enabled with any change detection + #11 + + + + + + + PE3 + LLWU Pin Enable 3 register + 0x2 + 8 + read-write + 0 + 0xFF + + + WUPE8 + Wakeup Pin Enable For LLWU_P8 + 0 + 2 + read-write + + + 00 + External input pin disabled as wakeup input + #00 + + + 01 + External input pin enabled with rising edge detection + #01 + + + 10 + External input pin enabled with falling edge detection + #10 + + + 11 + External input pin enabled with any change detection + #11 + + + + + WUPE9 + Wakeup Pin Enable For LLWU_P9 + 2 + 2 + read-write + + + 00 + External input pin disabled as wakeup input + #00 + + + 01 + External input pin enabled with rising edge detection + #01 + + + 10 + External input pin enabled with falling edge detection + #10 + + + 11 + External input pin enabled with any change detection + #11 + + + + + WUPE10 + Wakeup Pin Enable For LLWU_P10 + 4 + 2 + read-write + + + 00 + External input pin disabled as wakeup input + #00 + + + 01 + External input pin enabled with rising edge detection + #01 + + + 10 + External input pin enabled with falling edge detection + #10 + + + 11 + External input pin enabled with any change detection + #11 + + + + + WUPE11 + Wakeup Pin Enable For LLWU_P11 + 6 + 2 + read-write + + + 00 + External input pin disabled as wakeup input + #00 + + + 01 + External input pin enabled with rising edge detection + #01 + + + 10 + External input pin enabled with falling edge detection + #10 + + + 11 + External input pin enabled with any change detection + #11 + + + + + + + PE4 + LLWU Pin Enable 4 register + 0x3 + 8 + read-write + 0 + 0xFF + + + WUPE12 + Wakeup Pin Enable For LLWU_P12 + 0 + 2 + read-write + + + 00 + External input pin disabled as wakeup input + #00 + + + 01 + External input pin enabled with rising edge detection + #01 + + + 10 + External input pin enabled with falling edge detection + #10 + + + 11 + External input pin enabled with any change detection + #11 + + + + + WUPE13 + Wakeup Pin Enable For LLWU_P13 + 2 + 2 + read-write + + + 00 + External input pin disabled as wakeup input + #00 + + + 01 + External input pin enabled with rising edge detection + #01 + + + 10 + External input pin enabled with falling edge detection + #10 + + + 11 + External input pin enabled with any change detection + #11 + + + + + WUPE14 + Wakeup Pin Enable For LLWU_P14 + 4 + 2 + read-write + + + 00 + External input pin disabled as wakeup input + #00 + + + 01 + External input pin enabled with rising edge detection + #01 + + + 10 + External input pin enabled with falling edge detection + #10 + + + 11 + External input pin enabled with any change detection + #11 + + + + + WUPE15 + Wakeup Pin Enable For LLWU_P15 + 6 + 2 + read-write + + + 00 + External input pin disabled as wakeup input + #00 + + + 01 + External input pin enabled with rising edge detection + #01 + + + 10 + External input pin enabled with falling edge detection + #10 + + + 11 + External input pin enabled with any change detection + #11 + + + + + + + ME + LLWU Module Enable register + 0x4 + 8 + read-write + 0 + 0xFF + + + WUME0 + Wakeup Module Enable For Module 0 + 0 + 1 + read-write + + + 0 + Internal module flag not used as wakeup source + #0 + + + 1 + Internal module flag used as wakeup source + #1 + + + + + WUME1 + Wakeup Module Enable for Module 1 + 1 + 1 + read-write + + + 0 + Internal module flag not used as wakeup source + #0 + + + 1 + Internal module flag used as wakeup source + #1 + + + + + WUME2 + Wakeup Module Enable For Module 2 + 2 + 1 + read-write + + + 0 + Internal module flag not used as wakeup source + #0 + + + 1 + Internal module flag used as wakeup source + #1 + + + + + WUME3 + Wakeup Module Enable For Module 3 + 3 + 1 + read-write + + + 0 + Internal module flag not used as wakeup source + #0 + + + 1 + Internal module flag used as wakeup source + #1 + + + + + WUME4 + Wakeup Module Enable For Module 4 + 4 + 1 + read-write + + + 0 + Internal module flag not used as wakeup source + #0 + + + 1 + Internal module flag used as wakeup source + #1 + + + + + WUME5 + Wakeup Module Enable For Module 5 + 5 + 1 + read-write + + + 0 + Internal module flag not used as wakeup source + #0 + + + 1 + Internal module flag used as wakeup source + #1 + + + + + WUME6 + Wakeup Module Enable For Module 6 + 6 + 1 + read-write + + + 0 + Internal module flag not used as wakeup source + #0 + + + 1 + Internal module flag used as wakeup source + #1 + + + + + WUME7 + Wakeup Module Enable For Module 7 + 7 + 1 + read-write + + + 0 + Internal module flag not used as wakeup source + #0 + + + 1 + Internal module flag used as wakeup source + #1 + + + + + + + F1 + LLWU Flag 1 register + 0x5 + 8 + read-write + 0 + 0xFF + + + WUF0 + Wakeup Flag For LLWU_P0 + 0 + 1 + read-write + + + 0 + LLWU_P0 input was not a wakeup source + #0 + + + 1 + LLWU_P0 input was a wakeup source + #1 + + + + + WUF1 + Wakeup Flag For LLWU_P1 + 1 + 1 + read-write + + + 0 + LLWU_P1 input was not a wakeup source + #0 + + + 1 + LLWU_P1 input was a wakeup source + #1 + + + + + WUF2 + Wakeup Flag For LLWU_P2 + 2 + 1 + read-write + + + 0 + LLWU_P2 input was not a wakeup source + #0 + + + 1 + LLWU_P2 input was a wakeup source + #1 + + + + + WUF3 + Wakeup Flag For LLWU_P3 + 3 + 1 + read-write + + + 0 + LLWU_P3 input was not a wake-up source + #0 + + + 1 + LLWU_P3 input was a wake-up source + #1 + + + + + WUF4 + Wakeup Flag For LLWU_P4 + 4 + 1 + read-write + + + 0 + LLWU_P4 input was not a wakeup source + #0 + + + 1 + LLWU_P4 input was a wakeup source + #1 + + + + + WUF5 + Wakeup Flag For LLWU_P5 + 5 + 1 + read-write + + + 0 + LLWU_P5 input was not a wakeup source + #0 + + + 1 + LLWU_P5 input was a wakeup source + #1 + + + + + WUF6 + Wakeup Flag For LLWU_P6 + 6 + 1 + read-write + + + 0 + LLWU_P6 input was not a wakeup source + #0 + + + 1 + LLWU_P6 input was a wakeup source + #1 + + + + + WUF7 + Wakeup Flag For LLWU_P7 + 7 + 1 + read-write + + + 0 + LLWU_P7 input was not a wakeup source + #0 + + + 1 + LLWU_P7 input was a wakeup source + #1 + + + + + + + F2 + LLWU Flag 2 register + 0x6 + 8 + read-write + 0 + 0xFF + + + WUF8 + Wakeup Flag For LLWU_P8 + 0 + 1 + read-write + + + 0 + LLWU_P8 input was not a wakeup source + #0 + + + 1 + LLWU_P8 input was a wakeup source + #1 + + + + + WUF9 + Wakeup Flag For LLWU_P9 + 1 + 1 + read-write + + + 0 + LLWU_P9 input was not a wakeup source + #0 + + + 1 + LLWU_P9 input was a wakeup source + #1 + + + + + WUF10 + Wakeup Flag For LLWU_P10 + 2 + 1 + read-write + + + 0 + LLWU_P10 input was not a wakeup source + #0 + + + 1 + LLWU_P10 input was a wakeup source + #1 + + + + + WUF11 + Wakeup Flag For LLWU_P11 + 3 + 1 + read-write + + + 0 + LLWU_P11 input was not a wakeup source + #0 + + + 1 + LLWU_P11 input was a wakeup source + #1 + + + + + WUF12 + Wakeup Flag For LLWU_P12 + 4 + 1 + read-write + + + 0 + LLWU_P12 input was not a wakeup source + #0 + + + 1 + LLWU_P12 input was a wakeup source + #1 + + + + + WUF13 + Wakeup Flag For LLWU_P13 + 5 + 1 + read-write + + + 0 + LLWU_P13 input was not a wakeup source + #0 + + + 1 + LLWU_P13 input was a wakeup source + #1 + + + + + WUF14 + Wakeup Flag For LLWU_P14 + 6 + 1 + read-write + + + 0 + LLWU_P14 input was not a wakeup source + #0 + + + 1 + LLWU_P14 input was a wakeup source + #1 + + + + + WUF15 + Wakeup Flag For LLWU_P15 + 7 + 1 + read-write + + + 0 + LLWU_P15 input was not a wakeup source + #0 + + + 1 + LLWU_P15 input was a wakeup source + #1 + + + + + + + F3 + LLWU Flag 3 register + 0x7 + 8 + read-only + 0 + 0xFF + + + MWUF0 + Wakeup flag For module 0 + 0 + 1 + read-only + + + 0 + Module 0 input was not a wakeup source + #0 + + + 1 + Module 0 input was a wakeup source + #1 + + + + + MWUF1 + Wakeup flag For module 1 + 1 + 1 + read-only + + + 0 + Module 1 input was not a wakeup source + #0 + + + 1 + Module 1 input was a wakeup source + #1 + + + + + MWUF2 + Wakeup flag For module 2 + 2 + 1 + read-only + + + 0 + Module 2 input was not a wakeup source + #0 + + + 1 + Module 2 input was a wakeup source + #1 + + + + + MWUF3 + Wakeup flag For module 3 + 3 + 1 + read-only + + + 0 + Module 3 input was not a wakeup source + #0 + + + 1 + Module 3 input was a wakeup source + #1 + + + + + MWUF4 + Wakeup flag For module 4 + 4 + 1 + read-only + + + 0 + Module 4 input was not a wakeup source + #0 + + + 1 + Module 4 input was a wakeup source + #1 + + + + + MWUF5 + Wakeup flag For module 5 + 5 + 1 + read-only + + + 0 + Module 5 input was not a wakeup source + #0 + + + 1 + Module 5 input was a wakeup source + #1 + + + + + MWUF6 + Wakeup flag For module 6 + 6 + 1 + read-only + + + 0 + Module 6 input was not a wakeup source + #0 + + + 1 + Module 6 input was a wakeup source + #1 + + + + + MWUF7 + Wakeup flag For module 7 + 7 + 1 + read-only + + + 0 + Module 7 input was not a wakeup source + #0 + + + 1 + Module 7 input was a wakeup source + #1 + + + + + + + FILT1 + LLWU Pin Filter 1 register + 0x8 + 8 + read-write + 0 + 0xFF + + + FILTSEL + Filter Pin Select + 0 + 4 + read-write + + + 0000 + Select LLWU_P0 for filter + #0000 + + + 1111 + Select LLWU_P15 for filter + #1111 + + + + + FILTE + Digital Filter On External Pin + 5 + 2 + read-write + + + 00 + Filter disabled + #00 + + + 01 + Filter posedge detect enabled + #01 + + + 10 + Filter negedge detect enabled + #10 + + + 11 + Filter any edge detect enabled + #11 + + + + + FILTF + Filter Detect Flag + 7 + 1 + read-write + + + 0 + Pin Filter 1 was not a wakeup source + #0 + + + 1 + Pin Filter 1 was a wakeup source + #1 + + + + + + + FILT2 + LLWU Pin Filter 2 register + 0x9 + 8 + read-write + 0 + 0xFF + + + FILTSEL + Filter Pin Select + 0 + 4 + read-write + + + 0000 + Select LLWU_P0 for filter + #0000 + + + 1111 + Select LLWU_P15 for filter + #1111 + + + + + FILTE + Digital Filter On External Pin + 5 + 2 + read-write + + + 00 + Filter disabled + #00 + + + 01 + Filter posedge detect enabled + #01 + + + 10 + Filter negedge detect enabled + #10 + + + 11 + Filter any edge detect enabled + #11 + + + + + FILTF + Filter Detect Flag + 7 + 1 + read-write + + + 0 + Pin Filter 2 was not a wakeup source + #0 + + + 1 + Pin Filter 2 was a wakeup source + #1 + + + + + + + + + PMC + Power Management Controller + PMC_ + 0x4007D000 + + 0 + 0x3 + registers + + + LVD_LVW_DCDC + 6 + + + + LVDSC1 + Low Voltage Detect Status And Control 1 register + 0 + 8 + read-write + 0x10 + 0xFF + + + LVDV + Low-Voltage Detect Voltage Select + 0 + 2 + read-write + + + 0 + Low trip point selected (V LVD = V LVDL ) + #00 + + + 1 + High trip point selected (V LVD = V LVDH ) + #01 + + + + + LVDRE + Low-Voltage Detect Reset Enable + 4 + 1 + read-write + + + 0 + LVDF does not generate hardware resets + #0 + + + 1 + Force an MCU reset when LVDF = 1 + #1 + + + + + LVDIE + Low-Voltage Detect Interrupt Enable + 5 + 1 + read-write + + + 0 + Hardware interrupt disabled (use polling) + #0 + + + 1 + Request a hardware interrupt when LVDF = 1 + #1 + + + + + LVDACK + Low-Voltage Detect Acknowledge + 6 + 1 + read-write + + + LVDF + Low-Voltage Detect Flag + 7 + 1 + read-only + + + 0 + Low-voltage event not detected + #0 + + + 1 + Low-voltage event detected + #1 + + + + + + + LVDSC2 + Low Voltage Detect Status And Control 2 register + 0x1 + 8 + read-write + 0 + 0xFF + + + LVWV + Low-Voltage Warning Voltage Select + 0 + 2 + read-write + + + 00 + Low trip point selected (VLVW = VLVW1) + #00 + + + 01 + Mid 1 trip point selected (VLVW = VLVW2) + #01 + + + 10 + Mid 2 trip point selected (VLVW = VLVW3) + #10 + + + 11 + High trip point selected (VLVW = VLVW4) + #11 + + + + + LVWIE + Low-Voltage Warning Interrupt Enable + 5 + 1 + read-write + + + 0 + Hardware interrupt disabled (use polling) + #0 + + + 1 + Request a hardware interrupt when LVWF = 1 + #1 + + + + + LVWACK + Low-Voltage Warning Acknowledge + 6 + 1 + read-write + + + LVWF + Low-Voltage Warning Flag + 7 + 1 + read-only + + + 0 + Low-voltage warning event not detected + #0 + + + 1 + Low-voltage warning event detected + #1 + + + + + + + REGSC + Regulator Status And Control register + 0x2 + 8 + read-write + 0x4 + 0xFF + + + BGBE + Bandgap Buffer Enable + 0 + 1 + read-write + + + 0 + Bandgap buffer not enabled + #0 + + + 1 + Bandgap buffer enabled + #1 + + + + + REGONS + Regulator In Run Regulation Status + 2 + 1 + read-only + + + 0 + Regulator is in stop regulation or in transition to/from it + #0 + + + 1 + Regulator is in run regulation + #1 + + + + + ACKISO + Acknowledge Isolation + 3 + 1 + read-write + + + 0 + Peripherals and I/O pads are in normal run state. + #0 + + + 1 + Certain peripherals and I/O pads are in an isolated and latched state. + #1 + + + + + BGEN + Bandgap Enable In VLPx Operation + 4 + 1 + read-write + + + 0 + Bandgap voltage reference is disabled in VLPx , LLS , and VLLSx modes. + #0 + + + 1 + Bandgap voltage reference is enabled in VLPx , LLS , and VLLSx modes. + #1 + + + + + VLPO + VLPx Option + 6 + 1 + read-write + + + 0 + Operating frequencies and MCG clocking modes are restricted during VLPx modes as listed in the Power Management chapter. + #0 + + + 1 + If BGEN is also set, operating frequencies and MCG clocking modes are unrestricted during VLPx modes. Note that flash access frequency is still restricted however. + #1 + + + + + + + + + SMC + System Mode Controller + SMC_ + 0x4007E000 + + 0 + 0x4 + registers + + + + PMPROT + Power Mode Protection register + 0 + 8 + read-write + 0 + 0xFF + + + AVLLS + Allow Very-Low-Leakage Stop Mode + 1 + 1 + read-write + + + 0 + Any VLLSx mode is not allowed + #0 + + + 1 + Any VLLSx mode is allowed + #1 + + + + + ALLS + Allow Low-Leakage Stop Mode + 3 + 1 + read-write + + + 0 + Any LLSx mode is not allowed + #0 + + + 1 + Any LLSx mode is allowed + #1 + + + + + AVLP + Allow Very-Low-Power Modes + 5 + 1 + read-write + + + 0 + VLPR, VLPW, and VLPS are not allowed. + #0 + + + 1 + VLPR, VLPW, and VLPS are allowed. + #1 + + + + + + + PMCTRL + Power Mode Control register + 0x1 + 8 + read-write + 0 + 0xFF + + + STOPM + Stop Mode Control + 0 + 3 + read-write + + + 000 + Normal Stop (STOP) + #000 + + + 010 + Very-Low-Power Stop (VLPS) + #010 + + + 011 + Low-Leakage Stop (LLSx) + #011 + + + 100 + Very-Low-Leakage Stop (VLLSx) + #100 + + + 110 + Reseved + #110 + + + + + STOPA + Stop Aborted + 3 + 1 + read-only + + + 0 + The previous stop mode entry was successful. + #0 + + + 1 + The previous stop mode entry was aborted. + #1 + + + + + RUNM + Run Mode Control + 5 + 2 + read-write + + + 00 + Normal Run mode (RUN) + #00 + + + 10 + Very-Low-Power Run mode (VLPR) + #10 + + + + + + + STOPCTRL + Stop Control Register + 0x2 + 8 + read-write + 0x3 + 0xFF + + + LLSM + LLS or VLLS Mode Control + 0 + 3 + read-write + + + 00 + VLLS0 if PMCTRL[STOPM]=VLLSx, reserved if PMCTRL[STOPM]=LLSx + #000 + + + 01 + VLLS1 if PMCTRL[STOPM]=VLLSx, reserved if PMCTRL[STOPM]=LLSx + #001 + + + 10 + VLLS2 if PMCTRL[STOPM]=VLLSx, LLS2 if PMCTRL[STOPM]=LLSx + #010 + + + 11 + VLLS3 if PMCTRL[STOPM]=VLLSx, LLS3 if PMCTRL[STOPM]=LLSx + #011 + + + + + RAM2PO + RAM2 Power Option + 4 + 1 + read-write + + + 0 + RAM2 not powered in LLS2/VLLS2 + #0 + + + 1 + RAM2 powered in LLS2/VLLS2 + #1 + + + + + PORPO + POR Power Option + 5 + 1 + read-write + + + 0 + POR detect circuit is enabled in VLLS0 + #0 + + + 1 + POR detect circuit is disabled in VLLS0 + #1 + + + + + PSTOPO + Partial Stop Option + 6 + 2 + read-write + + + 00 + STOP - Normal Stop mode + #00 + + + 01 + PSTOP1 - Partial Stop with both system and bus clocks disabled + #01 + + + 10 + PSTOP2 - Partial Stop with system clock disabled and bus clock enabled + #10 + + + + + + + PMSTAT + Power Mode Status register + 0x3 + 8 + read-only + 0x1 + 0xFF + + + PMSTAT + Power Mode Status + 0 + 8 + read-only + + + + + + + RCM + Reset Control Module + RCM_ + 0x4007F000 + + 0 + 0x6 + registers + + + + SRS0 + System Reset Status Register 0 + 0 + 8 + read-only + 0x82 + 0xFF + + + WAKEUP + Low Leakage Wakeup Reset + 0 + 1 + read-only + + + 0 + Reset not caused by LLWU module wakeup source + #0 + + + 1 + Reset caused by LLWU module wakeup source + #1 + + + + + LVD + Low-Voltage Detect Reset + 1 + 1 + read-only + + + 0 + Reset not caused by LVD trip or POR + #0 + + + 1 + Reset caused by LVD trip or POR + #1 + + + + + LOC + Loss-of-Clock Reset + 2 + 1 + read-only + + + 0 + Reset not caused by a loss of external clock. + #0 + + + 1 + Reset caused by a loss of external clock. + #1 + + + + + WDOG + Watchdog + 5 + 1 + read-only + + + 0 + Reset not caused by watchdog timeout + #0 + + + 1 + Reset caused by watchdog timeout + #1 + + + + + PIN + External Reset Pin + 6 + 1 + read-only + + + 0 + Reset not caused by external reset pin + #0 + + + 1 + Reset caused by external reset pin + #1 + + + + + POR + Power-On Reset + 7 + 1 + read-only + + + 0 + Reset not caused by POR + #0 + + + 1 + Reset caused by POR + #1 + + + + + + + SRS1 + System Reset Status Register 1 + 0x1 + 8 + read-only + 0 + 0xFF + + + LOCKUP + Core Lockup + 1 + 1 + read-only + + + 0 + Reset not caused by core LOCKUP event + #0 + + + 1 + Reset caused by core LOCKUP event + #1 + + + + + SW + Software + 2 + 1 + read-only + + + 0 + Reset not caused by software setting of SYSRESETREQ bit + #0 + + + 1 + Reset caused by software setting of SYSRESETREQ bit + #1 + + + + + MDM_AP + MDM-AP System Reset Request + 3 + 1 + read-only + + + 0 + Reset not caused by host debugger system setting of the System Reset Request bit + #0 + + + 1 + Reset caused by host debugger system setting of the System Reset Request bit + #1 + + + + + SACKERR + Stop Mode Acknowledge Error Reset + 5 + 1 + read-only + + + 0 + Reset not caused by peripheral failure to acknowledge attempt to enter stop mode + #0 + + + 1 + Reset caused by peripheral failure to acknowledge attempt to enter stop mode + #1 + + + + + + + RPFC + Reset Pin Filter Control register + 0x4 + 8 + read-write + 0 + 0xFF + + + RSTFLTSRW + Reset Pin Filter Select in Run and Wait Modes + 0 + 2 + read-write + + + 00 + All filtering disabled + #00 + + + 01 + Bus clock filter enabled for normal operation + #01 + + + 10 + LPO clock filter enabled for normal operation + #10 + + + + + RSTFLTSS + Reset Pin Filter Select in Stop Mode + 2 + 1 + read-write + + + 0 + All filtering disabled + #0 + + + 1 + LPO clock filter enabled + #1 + + + + + + + RPFW + Reset Pin Filter Width register + 0x5 + 8 + read-write + 0 + 0xFF + + + RSTFLTSEL + Reset Pin Filter Bus Clock Select + 0 + 5 + read-write + + + 00000 + Bus clock filter count is 1 + #00000 + + + 00001 + Bus clock filter count is 2 + #00001 + + + 00010 + Bus clock filter count is 3 + #00010 + + + 00011 + Bus clock filter count is 4 + #00011 + + + 00100 + Bus clock filter count is 5 + #00100 + + + 00101 + Bus clock filter count is 6 + #00101 + + + 00110 + Bus clock filter count is 7 + #00110 + + + 00111 + Bus clock filter count is 8 + #00111 + + + 01000 + Bus clock filter count is 9 + #01000 + + + 01001 + Bus clock filter count is 10 + #01001 + + + 01010 + Bus clock filter count is 11 + #01010 + + + 01011 + Bus clock filter count is 12 + #01011 + + + 01100 + Bus clock filter count is 13 + #01100 + + + 01101 + Bus clock filter count is 14 + #01101 + + + 01110 + Bus clock filter count is 15 + #01110 + + + 01111 + Bus clock filter count is 16 + #01111 + + + 10000 + Bus clock filter count is 17 + #10000 + + + 10001 + Bus clock filter count is 18 + #10001 + + + 10010 + Bus clock filter count is 19 + #10010 + + + 10011 + Bus clock filter count is 20 + #10011 + + + 10100 + Bus clock filter count is 21 + #10100 + + + 10101 + Bus clock filter count is 22 + #10101 + + + 10110 + Bus clock filter count is 23 + #10110 + + + 10111 + Bus clock filter count is 24 + #10111 + + + 11000 + Bus clock filter count is 25 + #11000 + + + 11001 + Bus clock filter count is 26 + #11001 + + + 11010 + Bus clock filter count is 27 + #11010 + + + 11011 + Bus clock filter count is 28 + #11011 + + + 11100 + Bus clock filter count is 29 + #11100 + + + 11101 + Bus clock filter count is 30 + #11101 + + + 11110 + Bus clock filter count is 31 + #11110 + + + 11111 + Bus clock filter count is 32 + #11111 + + + + + + + + + BTLE_RF + Bluetooth LE RF + 0x40080000 + + 0x600 + 0xA + registers + + + + BLE_PART_ID + BluetoothLE LOW ENERGY PART ID + 0x600 + 16 + read-only + 0x6 + 0xFFFF + + + BLE_PART_ID + BluetoothLE Part ID + 0 + 16 + read-only + + + 000 + Pre-production + #0 + + + 001 + Pre-production + #1 + + + 010 + KW40 + #10 + + + 011 + KW41 + #11 + + + 100 + K3S + #100 + + + 101 + KW35/36 + #101 + + + 110 + KW37/38, K4 + #110 + + + + + + + DSM_STATUS + BluetoothLE DSM STATUS + 0x604 + 16 + read-only + 0 + 0xFFF8 + + + ORF_SYSCLK_REQ + RF Oscillator Requested + 0 + 1 + read-only + + + RIF_LL_ACTIVE + Link Layer Active + 1 + 1 + read-only + + + XCVR_BUSY + Transceiver Busy Status Bit + 2 + 1 + read-only + + + 0 + RF Channel in available (TSM is idle) + #0 + + + 1 + RF Channel in use (TSM is busy) + #1 + + + + + BTLE_ABORT + Btle Abort Status Bit + 3 + 1 + read-only + + + 0 + BluetoothLE protocol engine has access to the RF channel + #0 + + + 1 + BluetoothLE protocol engine has relinquish access to the RF channel + #1 + + + + + + + MISC_CTRL + BluetoothLE MISCELLANEOUS CONTROL + 0x608 + 16 + read-write + 0 + 0xFFFF + + + BLE_RELINQUISH + BluetoothLE Relinquish Control + 0 + 1 + read-write + + + 0 + Not force BluetoothLE protocol engine relinquish access to RF channel + #0 + + + 1 + force BluetoothLE protocol engine relinquish access to RF channel + #1 + + + + + TSM_INTR_EN + TSM Interrupt Enable + 1 + 1 + read-write + + + RX_ABORT_EN + enable pll_abort/ble_relinquish in rx process + 2 + 1 + read-write + + + 1 + enable pll_abort/ble_relinquish in rx process + #1 + + + 0 + disable pll_abort/ble_relinquish in rx process + #0 + + + + + DTM_RX_DISABLE + DTM_RX gating bit + 3 + 1 + read-write + + + 1 + Gate off the DTM_RX + #1 + + + 0 + pass through the DTM_RX + #0 + + + + + + + + + GENFSK + GENERIC FSK + 0x40082000 + + 0 + 0x100 + registers + + + + IRQ_CTRL + IRQ CONTROL + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + SEQ_END_IRQ + Sequence End Interrupt + 0 + 1 + read-write + + + 0 + Sequence End Interrupt is not asserted. + #0 + + + 1 + Sequence End Interrupt is asserted. + #1 + + + + + TX_IRQ + TX Interrupt + 1 + 1 + read-write + + + 0 + TX Interrupt is not asserted. + #0 + + + 1 + TX Interrupt is asserted. + #1 + + + + + RX_IRQ + RX Interrupt + 2 + 1 + read-write + + + 0 + RX Interrupt is not asserted. + #0 + + + 1 + RX Interrupt is asserted. + #1 + + + + + NTW_ADR_IRQ + Network Address Match Interrupt + 3 + 1 + read-write + + + 0 + Network Address Match Interrupt is not asserted. + #0 + + + 1 + Network Address Match Interrupt is asserted. + #1 + + + + + T1_IRQ + Timer1 (T1) Compare Interrupt + 4 + 1 + read-write + + + 0 + Timer1 (T1) Compare Interrupt is not asserted. + #0 + + + 1 + Timer1 (T1) Compare Interrupt is asserted. + #1 + + + + + T2_IRQ + Timer2 (T2) Compare Interrupt + 5 + 1 + read-write + + + 0 + Timer2 (T2) Compare Interrupt is not asserted. + #0 + + + 1 + Timer2 (T2) Compare Interrupt is asserted. + #1 + + + + + PLL_UNLOCK_IRQ + PLL Unlock Interrupt + 6 + 1 + read-write + + + 0 + PLL Unlock Interrupt is not asserted. + #0 + + + 1 + PLL Unlock Interrupt is asserted. + #1 + + + + + WAKE_IRQ + Wake Interrrupt + 7 + 1 + read-write + + + 0 + Wake Interrupt is not asserted. + #0 + + + 1 + Wake Interrupt is asserted. + #1 + + + + + RX_WATERMARK_IRQ + RX Watermark Interrupt + 8 + 1 + read-write + + + 0 + RX Watermark Interrupt is not asserted. + #0 + + + 1 + RX Watermark Interrupt is asserted. + #1 + + + + + TSM_IRQ + TSM Interrupt + 9 + 1 + read-only + + + 0 + TSM0_IRQ and TSM1_IRQ are both clear. + #0 + + + 1 + Indicates TSM0_IRQ or TSM1_IRQ is set in XCVR_STATUS. + #1 + + + + + CRC_VALID + CRC Valid + 10 + 1 + read-only + + + ACK_IRQ + Auto ACK Interrupt + 11 + 1 + read-write + + + 0 + Auto ACK Interrupt is not asserted. + #0 + + + 1 + Auto ACK Interrupt is asserted. + #1 + + + + + PHRFFAIL_IRQ + Received Frame PHR Fail Interrupt + 12 + 1 + read-write + + + 0 + Received frame PHR Fail Interrupt is not asserted. + #0 + + + 1 + Received frame PHR Fail Interrupt is asserted. + #1 + + + + + FILTERFAIL_IRQ + Received Frame Filter Fail Interrupt + 13 + 1 + read-write + + + 0 + A Filter Fail Interrupt has not occurred. + #0 + + + 1 + A Filter Fail Interrupt has occurred. + #1 + + + + + CCA_IRQ + CCA Interrupt + 14 + 1 + read-write + + + 0 + A CCA Interrupt has not occurred + #0 + + + 1 + A CCA Interrupt has occurred + #1 + + + + + MS_IRQ + Mode Switch Interrupt + 15 + 1 + read-write + + + 0 + A Mode Switch frame is not received + #0 + + + 1 + A Mode Switch frame is received + #1 + + + + + SEQ_END_IRQ_EN + SEQ_END_IRQ Enable + 16 + 1 + read-write + + + 0 + Sequence End Interrupt is not enabled. + #0 + + + 1 + Sequence End Interrupt is enabled. + #1 + + + + + TX_IRQ_EN + TX_IRQ Enable + 17 + 1 + read-write + + + 0 + TX Interrupt is not enabled. + #0 + + + 1 + TX Interrupt is enabled. + #1 + + + + + RX_IRQ_EN + RX_IRQ Enable + 18 + 1 + read-write + + + 0 + RX Interrupt is not enabled. + #0 + + + 1 + RX Interrupt is enabled. + #1 + + + + + NTW_ADR_IRQ_EN + NTW_ADR_IRQ Enable + 19 + 1 + read-write + + + 0 + Network Address Match Interrupt is not enabled. + #0 + + + 1 + Network Address Match Interrupt is enabled. + #1 + + + + + T1_IRQ_EN + T1_IRQ Enable + 20 + 1 + read-write + + + 0 + Timer1 (T1) Compare Interrupt is not enabled. + #0 + + + 1 + Timer1 (T1) Compare Interrupt is enabled. + #1 + + + + + T2_IRQ_EN + T2_IRQ Enable + 21 + 1 + read-write + + + 0 + Timer1 (T2) Compare Interrupt is not enabled. + #0 + + + 1 + Timer1 (T2) Compare Interrupt is enabled. + #1 + + + + + PLL_UNLOCK_IRQ_EN + PLL_UNLOCK_IRQ Enable + 22 + 1 + read-write + + + 0 + PLL Unlock Interrupt is not enabled. + #0 + + + 1 + PLL Unlock Interrupt is enabled. + #1 + + + + + WAKE_IRQ_EN + WAKE_IRQ Enable + 23 + 1 + read-write + + + 0 + Wake Interrupt is not enabled. + #0 + + + 1 + Wake Interrupt is enabled. + #1 + + + + + RX_WATERMARK_IRQ_EN + RX_WATERMARK_IRQ Enable + 24 + 1 + read-write + + + 0 + RX Watermark Interrupt is not enabled. + #0 + + + 1 + RX Watermark Interrupt is enabled. + #1 + + + + + TSM_IRQ_EN + TSM_IRQ Enable + 25 + 1 + read-write + + + 0 + TSM Interrupt is not enabled. + #0 + + + 1 + TSM Interrupt is enabled. + #1 + + + + + GENERIC_FSK_IRQ_EN + GENERIC_FSK_IRQ Master Enable + 26 + 1 + read-write + + + 0 + All GENERIC_FSK Interrupts are disabled. + #0 + + + 1 + All GENERIC_FSK Interrupts can be enabled. + #1 + + + + + ACK_IRQ_EN + ACK_IRQ Enable + 27 + 1 + read-write + + + 0 + Auto ACK Interrupt is not enabled. + #0 + + + 1 + Auto ACK Interrupt is enabled. + #1 + + + + + PHRFAIL_IRQ_EN + PHRFAIL_IRQ Enable + 28 + 1 + read-write + + + 0 + PHRFAIL Interrupt is not enabled. + #0 + + + 1 + PHRFAIL Interrupt is enabled. + #1 + + + + + FILTERFAIL_IRQ_EN + FILTERFAIL_IRQ Enable + 29 + 1 + read-write + + + 0 + FILTERFAIL Interrupt is not enabled. + #0 + + + 1 + FILTERFAIL Interrupt is enabled. + #1 + + + + + CCA_IRQ_EN + CCA_IRQ Enable + 30 + 1 + read-write + + + 0 + CCA Interrupt is not enabled. + #0 + + + 1 + CCA Interrupt is enabled. + #1 + + + + + MS_IRQ_EN + MS_IRQ Enable + 31 + 1 + read-write + + + 0 + MS Interrupt is not enabled. + #0 + + + 1 + MS Interrupt is enabled. + #1 + + + + + + + EVENT_TMR + EVENT TIMER + 0x4 + 32 + read-write + 0 + 0xFF000000 + + + EVENT_TMR + Event Timer + 0 + 24 + read-write + + + EVENT_TMR_LD + Event Timer Load + 24 + 1 + write-only + + + EVENT_TMR_ADD + Event Timer Add + 25 + 1 + write-only + + + + + T1_CMP + T1 COMPARE + 0x8 + 32 + read-write + 0xFFFFFF + 0xFFFFFFFF + + + T1_CMP + Timer1 (T1) Compare Value + 0 + 24 + read-write + + + T1_CMP_EN + Timer1 (T1) Compare Enable + 24 + 1 + read-write + + + + + T2_CMP + T2 COMPARE + 0xC + 32 + read-write + 0xFFFFFF + 0xFFFFFFFF + + + T2_CMP + Timer2 (T2) Compare Value + 0 + 24 + read-write + + + T2_CMP_EN + Timer2 (T2) Compare Enable + 24 + 1 + read-write + + + + + TIMESTAMP + TIMESTAMP + 0x10 + 32 + read-only + 0 + 0xFF000000 + + + TIMESTAMP + Received Packet Timestamp + 0 + 24 + read-only + + + + + XCVR_CTRL + TRANSCEIVER CONTROL + 0x14 + 32 + read-write + 0 + 0x60F800FF + + + SEQCMD + Sequence Commands, also named as "XCVSEQ(Transceiver Sequence)" + 0 + 5 + read-write + + + 00000 + Same as command ABORT + #00000 + + + 00001 + TX Start Now + #00001 + + + 00010 + TX Start @ T1 Timer Compare Match (EVENT_TMR = T1_CMP) + #00010 + + + 00011 + TX Start @ T2 Timer Compare Match (EVENT_TMR = T2_CMP) + #00011 + + + 00100 + TX Cancel -- Cancels pending TX events but do not abort a TX-in-progress + #00100 + + + 00101 + RX Start Now + #00101 + + + 00110 + RX Start @ T1 Timer Compare Match (EVENT_TMR = T1_CMP) + #00110 + + + 00111 + RX Start @ T2 Timer Compare Match (EVENT_TMR = T2_CMP) + #00111 + + + 01000 + RX Stop @ T1 Timer Compare Match (EVENT_TMR = T1_CMP) + #01000 + + + 01001 + RX Stop @ T2 Timer Compare Match (EVENT_TMR = T2_CMP) + #01001 + + + 01010 + RX Cancel -- Cancels pending RX events but do not abort a RX-in-progress + #01010 + + + 01011 + Abort All - Cancels all pending events and abort any sequence-in-progress + #01011 + + + 01100 + TR Start Now + #01100 + + + 01101 + TR Start @ T1 Timer Compare Match (EVENT_TMR = T1_CMP) + #01101 + + + 01110 + TR Start @ T2 Timer Compare Match (EVENT_TMR = T2_CMP) + #01110 + + + 01111 + TR Cancel -- Cancels pending TR events but do not abort a TR-in-progress + #01111 + + + 10000 + CCA Start Now + #10000 + + + 10001 + CCA Start @ T1 Timer Compare Match (EVENT_TMR = T1_CMP) + #10001 + + + 10010 + CCA Start @ T2 Timer Compare Match (EVENT_TMR = T2_CMP) + #10010 + + + 10011 + CCA Cancel -- Cancels pending CCA events but do not abort a CCA-in-progress + #10011 + + + + + LENGTH_EXT + Extracted Length Field + 8 + 11 + read-only + + + CMDDEC_CS + Command Decode + 24 + 5 + read-only + + + XCVR_BUSY + Transceiver Busy + 31 + 1 + read-only + + + 0 + IDLE + #0 + + + 1 + BUSY + #1 + + + + + + + XCVR_STS + TRANSCEIVER STATUS + 0x18 + 32 + read-only + 0 + 0xFF007F00 + + + LQI + Link Quality Indicator + 0 + 8 + read-only + + + LQI_VALID + LQI Valid Indicator + 15 + 1 + read-only + + + 0 + LQI is not yet valid for RX packet. + #0 + + + 1 + LQI is valid for RX packet. + #1 + + + + + RSSI + RSSI Value + 16 + 8 + read-only + + + + + XCVR_CFG + TRANSCEIVER CONFIGURATION + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + TX_WHITEN_DIS + TX Whitening Disable + 0 + 1 + read-write + + + RX_DEWHITEN_DIS + RX De-Whitening Disable + 1 + 1 + read-write + + + SW_CRC_EN + Software CRC Enable + 2 + 1 + read-write + + + STOP_POSTPONE_ON_AA + Postpone Stop Command Timeout On Access Address Match Enable + 3 + 1 + read-write + + + 0 + STOP Abort will occur on RX_STOP_T1 or RX_STOP_T1 Event Timer match, regardless of NTW_ADR_MCH + #0 + + + 1 + STOP Abort will be deferred on RX_STOP_T1 or RX_STOP_T1 Event Timer match, if NTW_ADR_MCH is asserted; otherwise the RX_STOP Abort will occur immediately + #1 + + + + + PREAMBLE_SZ + Preamble Size + 4 + 9 + read-write + + + GEN_PREAMBLE + Preamble pattern + 16 + 8 + read-write + + + PREAMBLE_SEL + Preamble Select + 24 + 3 + read-write + + + 00 + The controller hardware selects the preamble pattern based on the first transmitted bit of Network Address, such that the last bit of preamble is the opposite polarity from the first bit of Network Address, forcing a bit transition at this boundary. + #000 + + + 01 + Preamble is programmed by register GEN_PREAMBLE[7:0] + #001 + + + 10 + Preamble is 0b01 + #010 + + + 11 + Preamble is 0b10 + #011 + + + + + + + CHANNEL_NUM0 + CHANNEL NUMBER 0 + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + CHANNEL_NUM0 + Channel Number for PAN0 + 0 + 7 + read-write + + + + + TX_POWER + TRANSMIT POWER + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + TX_POWER + Transmit Power + 0 + 6 + read-write + + + + + NTW_ADR_CTRL + NETWORK ADDRESS CONTROL + 0x28 + 32 + read-write + 0x100 + 0xFFFFFF0F + + + NTW_ADR_EN + Network Address Enable + 0 + 4 + read-write + + + 0001 + Enable Network Address 0 for correlation + #0001 + + + 0010 + Enable Network Address 1 for correlation + #0010 + + + 0100 + Enable Network Address 2 for correlation + #0100 + + + 1000 + Enable Network Address 3 for correlation + #1000 + + + + + NTW_ADR_MCH + Network Address Match + 4 + 4 + read-only + + + 0001 + Network Address 0 has matched + #0001 + + + 0010 + Network Address 1 has matched + #0010 + + + 0100 + Network Address 2 has matched + #0100 + + + 1000 + Network Address 3 has matched + #1000 + + + + + NTW_ADR_SZ + Network Address Size + 8 + 2 + read-write + + + 00 + Network Address 0/1/2/3 requires a 8-bit correlation + #00 + + + 01 + Network Address 0/1/2/3 requires a 16-bit correlation + #01 + + + 10 + Network Address 0/1/2/3 requires a 24-bit correlation + #10 + + + 11 + Network Address 0/1/2/3 requires a 32-bit correlation + #11 + + + + + NTW_ADR_THR + Network Address Threshold + 16 + 3 + read-write + + + + + NTW_ADR_0 + NETWORK ADDRESS 0 + 0x2C + 32 + read-write + 0x55555555 + 0xFFFFFFFF + + + NTW_ADR_0 + Network Address 0 + 0 + 32 + read-write + + + + + NTW_ADR_1 + NETWORK ADDRESS 1 + 0x30 + 32 + read-write + 0x55555555 + 0xFFFFFFFF + + + NTW_ADR_1 + Network Address 1 + 0 + 32 + read-write + + + + + NTW_ADR_2 + NETWORK ADDRESS 2 + 0x34 + 32 + read-write + 0x55555555 + 0xFFFFFFFF + + + NTW_ADR_2 + Network Address 2 + 0 + 32 + read-write + + + + + NTW_ADR_3 + NETWORK ADDRESS 3 + 0x38 + 32 + read-write + 0x55555555 + 0xFFFFFFFF + + + NTW_ADR_3 + Network Address 2 + 0 + 32 + read-write + + + + + RX_WATERMARK + RECEIVE WATERMARK + 0x3C + 32 + read-write + 0xFFF + 0xE000FFFF + + + RX_WATERMARK + Receive Watermark + 0 + 13 + read-write + + + BYTE_COUNTER + Byte Counter + 16 + 13 + read-only + + + + + DSM_CTRL + DSM CONTROL + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + GEN_SLEEP_REQUEST + GENERIC_FSK Deep Sleep Mode Request + 0 + 1 + read-write + + + + + PART_ID + PART ID + 0x44 + 32 + read-only + 0x2 + 0xFFFFFFFF + + + PART_ID + Part ID + 0 + 8 + read-only + + + + + SLOT_PRELOAD + SLOT PRELOAD + 0x48 + 32 + read-write + 0x2A8 + 0xFFFFFFFF + + + SLOT_PRELOAD + Slotted Mode Preload + 0 + 16 + read-write + + + + + SLOT_TIME + SLOT TIME + 0x4C + 32 + read-write + 0x8E8 + 0xFFFFFFFF + + + SLOT_TIME + Duration of the Backoff Slot + 0 + 16 + read-write + + + + + TURNAROUND_TIME + TURNAROUND TIME + 0x50 + 32 + read-write + 0x3E8 + 0xFFFFFFFF + + + TURNAROUND_TIME + RX-to-TX or TX-to-RX turnaround time + 0 + 16 + read-write + + + + + ACKDELAY + ACK DELAY + 0x54 + 32 + read-write + 0 + 0xFFFFFFFF + + + ACKDELAY + ACK Delay + 0 + 10 + read-write + + + + + RXDELAY + RX DELAY + 0x58 + 32 + read-write + 0 + 0xFFFFFFFF + + + RXDELAY + RX Delay + 0 + 10 + read-write + + + + + TXDELAY + TX DELAY + 0x5C + 32 + read-write + 0 + 0xFFFFFFFF + + + TXDELAY + TX Delay + 0 + 10 + read-write + + + + + PACKET_CFG + PACKET CONFIGURATION + 0x60 + 32 + read-write + 0xC00040 + 0x1FFFFFFF + + + LENGTH_SZ + LENGTH Size + 0 + 5 + read-write + + + LENGTH_BIT_ORD + LENGTH Bit Order + 5 + 1 + read-write + + + 0 + LS Bit First + #0 + + + 1 + MS Bit First + #1 + + + + + SYNC_ADDR_SZ + Sync Address Size + 6 + 2 + read-write + + + H0_SZ + H0 Size + 16 + 5 + read-write + + + AA_PLAYBACK_CNT + AA PLAYBACK COUNT + 22 + 1 + read-write + + + 0 + AA is not through CRC and not playback to Link layer. + #0 + + + 1 + AA is through CRC and palyback to Link Layer. + #1 + + + + + LL_FETCH_AA + Link layer fetches AA from PHY + 23 + 1 + read-write + + + 0 + Link layer does not fetch AA from PHY + #0 + + + 1 + Link layer fetches AA from PHY when AA_PLAYBACK_CNT is 0 + #1 + + + + + H1_SZ + H1 Size + 24 + 5 + read-write + + + H1_FAIL + H1 Violated Status Bit + 29 + 1 + read-only + + + H0_FAIL + H0 Violated Status Bit + 30 + 1 + read-only + + + LENGTH_FAIL + Maximum Length Violated Status Bit + 31 + 1 + read-only + + + + + H0_CFG + H0 CONFIGURATION + 0x64 + 32 + read-write + 0 + 0xFFFFFFFF + + + H0_MATCH + H0 Match Register + 0 + 16 + read-write + + + H0_MASK + H0 Mask Register + 16 + 16 + read-write + + + + + H1_CFG + H1 CONFIGURATION + 0x68 + 32 + read-write + 0 + 0xFFFFFFFF + + + H1_MATCH + H1 Match Register + 0 + 16 + read-write + + + H1_MASK + H1 Mask Register + 16 + 16 + read-write + + + + + CRC_CFG + CRC CONFIGURATION + 0x6C + 32 + read-write + 0 + 0xFFFFFFF + + + CRC_IGNORE + CRC Ignore + 24 + 1 + read-write + + + 0 + RX_IRQ will not be asserted for a received packet which fails CRC verification. + #0 + + + 1 + RX_IRQ will be asserted even for a received packet which fails CRC verification. + #1 + + + + + CRC_VALID + CRC Valid + 28 + 1 + read-only + + + 0 + CRC of RX packet is not valid. + #0 + + + 1 + CRC of RX packet is valid. + #1 + + + + + + + LENGTH_ADJ + LENGTH ADJUSTMENT + 0x70 + 32 + read-write + 0 + 0xFFFFFFFF + + + LENGTH_ADJ + Length Adjustment + 0 + 11 + read-write + + + + + LENGTH_MAX + MAXIMUM LENGTH + 0x84 + 32 + read-write + 0 + 0xFFFFFFFF + + + LENGTH_MAX + Maximum Length for Received Packets + 16 + 7 + read-write + + + REC_BAD_PKT + Receive Bad Packets + 23 + 1 + read-write + + + 0 + packets which fail H0, H1, or LENGTH_MAX result in an automatic recycle after the header is received and parsed + #0 + + + 1 + packets which fail H0, H1, or LENGTH_MAX are received in their entirety + #1 + + + + + + + ENH_FEATURE + ENHANCED FEATURES + 0x90 + 32 + read-write + 0 + 0xFFFFFFFF + + + GENLL_MODE + Linklayer Mode Select + 0 + 4 + read-write + + + 0000 + GLL Mode + #0000 + + + 0001 + PAN Mode + #0001 + + + 0010 + FAN Mode + #0010 + + + 0011 + Hybrid Dual PAN Mode + #0011 + + + 0110 + FCP Mode + #0110 + + + 1001 + Bluetooth LE Uncoded Mode + #1001 + + + 1010 + Bluetooth LE LR Mode + #1010 + + + 1011 + Bluetooth LE Concurrent Mode (RX configuration only; TX uses either Bluetooth LE UNCODED or Bluetooth LE LR configuration) + #1011 + + + 1111 + GTM Mode + #1111 + + + + + SEL_RXIRQ + Select the RX IRQ assert time + 5 + 1 + read-write + + + 0 + RX_IRQ is asserted at the end of RX_PKT state. + #0 + + + 1 + RX_IRQ is asserted at the end of RXEN_DLY state. This to be used for delaying RX_IRQ to accept TERM2 bits in Bluetooth LE-LR and CTE bits as needed. + #1 + + + + + DATARATE_CONFIG_SEL + Select the data rate configuration bank + 6 + 1 + read-write + + + 0 + Select the data rate as per configuration bank 0 + #0 + + + 1 + Select the data rate as per configuration bank 1 + #1 + + + + + STAY_IN_RX + Stay in receive + 7 + 1 + read-write + + + 0 + Linklayer will warmdown after an RX_IRQ + #0 + + + 1 + Linklayer will recycle and stay in receive even after an RX_IRQ. + #1 + + + + + PHR_TYPE + PHR Type + 8 + 3 + read-write + + + 00 + The packet type is GFSK + #000 + + + 01 + The packet type is MSK + #001 + + + 10 + The packet type is SUN FSK + #010 + + + 11 + The packet type is LECIM FSK + #011 + + + + + SW_BUILD_ACK + Software builds the ACK packet in RAM + 11 + 1 + read-write + + + 0 + Hardware builds part of or the whole of the auto ACK frame + #0 + + + 1 + Software builds the whole auto ACK frame in RAM. + #1 + + + + + ACKBUF_SEL + ACK frame is in 64-byte dedicated RAM or TX buffer RAM + 12 + 1 + read-write + + + 0 + ACK frame is in 64-byte dedicated RAM + #0 + + + 1 + ACK frame is in TX buffer RAM + #1 + + + + + AUTOACK + Auto Acknowledge Enable + 13 + 1 + read-write + + + 0 + sequence manager will not follow a receive frame with a Tx Ack frame, under any conditions; the autosequence will terminate after the receive frame. + #0 + + + 1 + sequence manager will follow a receive frame with an automatic hardware-generated Tx Ack frame, assuming other necessary conditions are met. + #1 + + + + + RXACKRQD + Receive Acknowledge Frame required + 14 + 1 + read-write + + + 0 + An ordinary receive frame (any type of frame) follows the transmit frame. + #0 + + + 1 + A receive Ack frame is expected to follow the transmit frame (non-Ack frames are rejected). + #1 + + + + + SLOTTED + Slotted Mode + 15 + 1 + read-write + + + LENGTH_ACK + Length of the ACK frame(or part of the ACK frame) in RAM + 16 + 11 + read-write + + + BLE_V5P1_CTE_EN + Bluetooth LE version 5.1 CTE feature enable + 31 + 1 + read-write + + + 0 + Do not support Bluetooth LE version 5.1 CTE feature. + #0 + + + 1 + Support Bluetooth LE version 5.1 CTE feature, which means the link layer hardware can parse the CTE field length and extend the RX_EN signal accordingly. + #1 + + + + + + + RX_FRAME_FILTER + RECEIVE FRAME FILTER + 0x94 + 32 + read-write + 0x60F + 0x7F00FFFF + + + BEACON_FT + Beacon Frame Type Enable + 0 + 1 + read-write + + + 0 + reject all Beacon frames + #0 + + + 1 + Beacon frame type enabled. + #1 + + + + + DATA_FT + Data Frame Type Enable + 1 + 1 + read-write + + + 0 + reject all Beacon frames + #0 + + + 1 + Data frame type enabled. + #1 + + + + + ACK_FT + Ack Frame Type Enable + 2 + 1 + read-write + + + 0 + reject all Acknowledge frames + #0 + + + 1 + Acknowledge frame type enabled. + #1 + + + + + CMD_FT + MAC Command Frame Type Enable + 3 + 1 + read-write + + + 0 + reject all MAC Command frames + #0 + + + 1 + MAC Command frame type enabled. + #1 + + + + + LLDN_FT + LLDN Frame Type Enable + 4 + 1 + read-write + + + 0 + reject all LLDN frames + #0 + + + 1 + LLDN frame type enabled (Frame Type 4). + #1 + + + + + MULTIPURPOSE_FT + Multipurpose Frame Type Enable + 5 + 1 + read-write + + + 0 + reject all Multipurpose frames + #0 + + + 1 + Multipurpose frame type enabled (Frame Type 5). + #1 + + + + + FRAGMENT_FT + Fragment Frame Type Enable + 6 + 1 + read-write + + + 0 + reject all Fragment frames + #0 + + + 1 + Fragment frame type enabled (Frame Type 6). + #1 + + + + + EXTENDED_FT + Extended Frame Type Enable + 7 + 1 + read-write + + + 0 + reject all Extended frames + #0 + + + 1 + Extended frame type enabled (Frame Type 7). + #1 + + + + + NS_FT + "Not Specified" Frame Type Enable + 8 + 1 + read-write + + + 0 + reject all "Not Specified" frames + #0 + + + 1 + Not-specified (reserved) frame type enabled. Applies to Frame Type 6. No packet filtering is performed, except for frame length checking (FrameLength>=5 and FrameLength<=127). No AUTOACK is transmitted for this Frame Type + #1 + + + + + FRM_VER_FILTER + Frame Version selector. + 9 + 4 + read-write + + + EXTENDED_FCS_CHK + Verify FCS on Frame Type Extended + 15 + 1 + read-write + + + 0 + Packet Processor will not check FCS for Frame Type EXTENDED (default) + #0 + + + 1 + Packet Processor will check FCS at end-of-packet based on packet length derived from PHR, for Frame Type EXTENDED + #1 + + + + + FV2_BEACON_RECD + Frame Version 2 Beacon Packet Received + 16 + 1 + read-only + + + 0 + The last packet received was not Frame Type Beacon with Frame Version 2 + #0 + + + 1 + The last packet received was Frame Type Beacon with Frame Version 2, and FRM_VER_FILTER[2]=1 to allow such packets + #1 + + + + + FV2_DATA_RECD + Frame Version 2 Data Packet Received + 17 + 1 + read-only + + + 0 + The last packet received was not Frame Type Data with Frame Version 2 + #0 + + + 1 + The last packet received was Frame Type Data with Frame Version 2, and FRM_VER_FILTER[2]=1 to allow such packets + #1 + + + + + FV2_ACK_RECD + Frame Version 2 Acknowledge Packet Received + 18 + 1 + read-only + + + 0 + The last packet received was not Frame Type Ack with Frame Version 2 + #0 + + + 1 + The last packet received was Frame Type Ack with Frame Version 2, and FRM_VER_FILTER[2]=1 to allow such packets + #1 + + + + + FV2_CMD_RECD + Frame Version 2 MAC Command Packet Received + 19 + 1 + read-only + + + 0 + The last packet received was not Frame Type MAC Command with Frame Version 2 + #0 + + + 1 + The last packet received was Frame Type MAC Command with Frame Version 2, and FRM_VER_FILTER[2]=1 to allow such packets + #1 + + + + + LLDN_RECD + LLDN Packet Received + 20 + 1 + read-only + + + 0 + The last packet received was not Frame Type LLDN + #0 + + + 1 + The last packet received was Frame Type LLDN, and LLDN_FT=1 to allow such packets. + #1 + + + + + MULTIPURPOSE_RECD + Multipurpose Packet Received + 21 + 1 + read-only + + + 0 + last packet received was not Frame Type MULTIPURPOSE + #0 + + + 1 + The last packet received was Frame Type MULTIPURPOSE, and MULTIPURPOSE_FT=1 to allow such packets. + #1 + + + + + FRAGMENT_RECD + Fragment Packet Received + 22 + 1 + read-only + + + 0 + last packet received was not Frame Type FRAGMENT + #0 + + + 1 + The last packet received was Frame Type FRAGMENT, and FRAGMENT_FT=1 to allow such packets. + #1 + + + + + EXTENDED_RECD + Extended Packet Received + 23 + 1 + read-only + + + 0 + The last packet received was not Frame Type EXTENDED + #0 + + + 1 + The last packet received was Frame Type EXTENDED, and EXTENDED_FT=1 to allow such packets. + #1 + + + + + RXCYC_SEL + Rx Recycle Time Select + 28 + 1 + read-write + + + 0 + Recycle when fail happens. + #0 + + + 1 + Recycle when Rx done and fail happens. + #1 + + + + + FILTER_FAIL_IGNORE + Filter Fail Ignore + 29 + 1 + read-write + + + 0 + RX_IRQ will not be asserted when filter fail. + #0 + + + 1 + RX_IRQ will be asserted when filter fail. + #1 + + + + + PROMISCUOUS + Promiscuous Mode Enable + 30 + 1 + read-write + + + 0 + normal mode + #0 + + + 1 + all packet filtering except frame length checking (FrameLength>=5) is bypassed. + #1 + + + + + ENH_PKT_STATUS + Enhanced Packet Status + 31 + 1 + read-only + + + 0 + The last packet received was not 2015-compliant + #0 + + + 1 + The last packet received was 2015-compliant (RX_FRAME_FILTER register should be queried for additional status bits) + #1 + + + + + + + FILTERFAIL_CODE + FILTER FAIL CODE + 0x98 + 32 + read-write + 0 + 0x7FFCFC00 + + + FILTERFAIL_CODE_PAN + Filter Fail Code When in PAN Mode + 0 + 10 + read-only + + + FILTERFAIL_CODE_FAN + Filter Fail Code When in FAN Mode + 16 + 2 + read-only + + + FILTERFAIL_PAN_SEL + PAN Selector for Filter Fail Code + 30 + 1 + read-write + + + 0 + FILTERFAIL_CODE_PAN/FILTERFAIL_CODE_FAN will report the FILTERFAIL status of PAN0 + #0 + + + 1 + FILTERFAIL_CODE_PAN/FILTERFAIL_CODE_FAN will report the FILTERFAIL status of PAN1 + #1 + + + + + FILTERFAIL_FLAG_SEL + Consolidated Filter Fail Flag + 31 + 1 + read-only + + + + + LENIENCY_LSB + LENIENCY LSB + 0x9C + 32 + read-write + 0 + 0xFFFFFFFF + + + LENIENCY_LSB + Leniency LSB Register + 0 + 32 + read-write + + + + + LENIENCY_MSB + LENIENCY MSB + 0xA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + LENIENCY_MSB + Leniency MSB Register + 0 + 13 + read-write + + + + + DUAL_PAN_CTRL + DUAL PAN CONTROL + 0xA4 + 32 + read-write + 0 + 0x3FC0FFFB + + + ACTIVE_NETWORK + Active Network Selector + 0 + 1 + read-write + + + 0 + Select PAN0 + #0 + + + 1 + Select PAN1 + #1 + + + + + DUAL_PAN_AUTO + Activates automatic Dual PAN operating mode + 1 + 1 + read-write + + + CURRENT_NETWORK + Indicates which PAN is currently selected by hardware + 2 + 1 + read-only + + + 0 + PAN0 is selected + #0 + + + 1 + PAN1 is selected + #1 + + + + + DUAL_PAN_DWELL + Dual PAN Channel Frequency Dwell Time + 8 + 8 + read-write + + + DUAL_PAN_REMAIN + Time Remaining before next PAN switch in auto Dual PAN mode + 16 + 6 + read-only + + + MODE_PAN0 + PAN0 Mode Select + 24 + 1 + read-write + + + 0 + PAN0 is in PAN mode + #0 + + + 1 + PAN0 is in FAN mode + #1 + + + + + MODE_PAN1 + PAN1 Mode Select + 25 + 1 + read-write + + + 0 + PAN1 is in PAN mode + #0 + + + 1 + PAN1 is in FAN mode + #1 + + + + + DP_CHAN_OVRD_EN + Dual PAN Channel Override Enable + 26 + 1 + read-write + + + DP_CHAN_OVRD_SEL + Dual PAN Channel Override Selector + 27 + 1 + read-write + + + PANCORDNTR0 + Device is a PAN Coordinator on PAN0 + 28 + 1 + read-write + + + PANCORDNTR1 + Device is a PAN Coordinator on PAN1 + 29 + 1 + read-write + + + RECD_ON_PAN0 + Last Packet was Received on PAN0 + 30 + 1 + read-only + + + RECD_ON_PAN1 + Last Packet was Received on PAN1 + 31 + 1 + read-only + + + + + GTM_PDU + GTM MODE PDU + GENFSK + 0xA8 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + GTM_PDU + GTM MODE PDU + 0 + 32 + read-write + + + + + MACSHORTADDRS1 + MAC SHORT ADDRESS FOR PAN1 + GENFSK + 0xA8 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + MACPANID1 + MAC PAN ID for PAN1 + 0 + 16 + read-write + + + MACSHORTADDRS1 + MAC SHORT ADDRESS for PAN1 + 16 + 16 + read-write + + + + + GTM_CFG + GTM MODE CONFIGURATION + GENFSK + 0xAC + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + GTM_PKT_NUM + GTM MODE PACKET NUMBER + 0 + 12 + read-write + + + GTM_PDU_TYPE + GTM MODE PDU TYPE SELECTION + 24 + 4 + read-write + + + 000 + PRBS9 Sequence + #0000 + + + 001 + Programmable 8-bit Pattern (from register GTM_PDU[7:0], reused from MACSHORTADDRS1[7:0]) + #0001 + + + 010 + PRBS-13 Sequence + #0010 + + + 011 + PRBS-15 Sequence + #0011 + + + 100 + Programmable 32-bit Pattern (from register GTM_PDU[31:0], reused from {MACSHORTADDRS1,MACPANID1}) + #0100 + + + 101 + Programmable packet from Packet RAM (in this case, PKT_LEN is ignored) + #0101 + + + + + GTM_IPD_CHECK_DIS + GTM MODE INTER-PACKET DURATION CHECK DISABLE + 30 + 1 + read-write + + + GTM_PKT_COUNT_CHECK_DIS + GTM MODE PACKET NUMBER CHECK DISABLE + 31 + 1 + read-write + + + + + MACLONGADDRS1_LSB + MAC LONG ADDRESS 1 LSB + GENFSK + 0xAC + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + MACLONGADDRS1_LSB + MAC LONG ADDRESS for PAN1 LSB + 0 + 32 + read-write + + + + + GTM_IPD + GTM MODE INTER-PACKET DURATION + GENFSK + 0xB0 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + GTM_IPD + GTM MODE INTER-PACKET DURATION + 0 + 20 + read-write + + + + + MACLONGADDRS1_MSB + MAC LONG ADDRESS 1 MSB + GENFSK + 0xB0 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + MACLONGADDRS1_MSB + MAC LONG ADDRESS for PAN1 MSB + 0 + 32 + read-write + + + + + CHANNEL_NUM1 + CHANNEL NUMBER 1 + 0xB4 + 32 + read-write + 0 + 0xFFFFFFFF + + + CHANNEL_NUM1 + Channel Number for PAN1 + 0 + 7 + read-write + + + + + MACSHORTADDRS0 + MAC SHORT ADDRESS 0 + 0xB8 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + MACPANID0 + MAC PAN ID for PAN0 + 0 + 16 + read-write + + + MACSHORTADDRS0 + MAC SHORT ADDRESS FOR PAN0 + 16 + 16 + read-write + + + + + GTM_FIRST_SFD2WD + GTM MODE TIME OF FIRST SFD FOUND TO FORCE RX WARMDOWN + GENFSK + 0xBC + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + GTM_FIRST_SFD2WD + GTM MODE TIME OF FIRST SFD FOUND TO FORCE RX WARMDOWN + 0 + 20 + read-write + + + + + MACLONGADDRS0_LSB + MAC LONG ADDRESS 0 LSB + GENFSK + 0xBC + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + MACLONGADDRS0_LSB + MAC LONG ADDRESS for PAN0 LSB + 0 + 32 + read-write + + + + + GTM_RX_RECYCLE_TIME + GTM MODE RX RECYCLE TIME + GENFSK + 0xC0 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + GTM_RX_RECYCLE_TIME + GTM MODE RX RECYCLE TIME + 0 + 20 + read-write + + + + + MACLONGADDRS0_MSB + MAC LONG ADDRESS 0 MSB + GENFSK + 0xC0 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + MACLONGADDRS0_MSB + MAC LONG ADDRESS for PAN0 MSB + 0 + 32 + read-write + + + + + CCA_LQI_CTRL + CCA AND LQI CONTROL + 0xC4 + 32 + read-write + 0x4B00 + 0xFF00FF7F + + + CCABFRTX + CCA Before TX + 0 + 1 + read-write + + + 0 + no CCA required, transmit operation begins immediately. + #0 + + + 1 + at least one CCA measurement is required prior to the transmit operation (see also SLOTTED). + #1 + + + + + SIMUL_CCA_RX + Simultaneous CCA and Receive Enable + 1 + 1 + read-write + + + 0 + Packets can't be received during CCA measurement + #0 + + + 1 + Packet reception is enabled during CCA measurement if preamble and SFD are detected + #1 + + + + + CCA + CCA Status + 7 + 1 + read-only + + + 0 + IDLE + #0 + + + 1 + BUSY + #1 + + + + + CCA1_THRESH + CCA Mode 1 Threshold + 8 + 8 + read-write + + + CCA1_ED_FNL + Final Result for CCA Mode 1 and Energy Detect + 16 + 8 + read-only + + + + + WARMUP_TIME + TX/RX WARMUP TIME + 0xC8 + 32 + read-only + 0 + 0xFF00FF00 + + + RX_WARMUP + Receive Warmup Time + 0 + 8 + read-only + + + TX_WARMUP + Transmit Warmup Time + 16 + 8 + read-only + + + + + RXEN_DLY + RX_EN Delay Time + 0xCC + 32 + read-write + 0 + 0xFFFFFFFF + + + RXEN_DLY + When RXEN_DLY is not zero, the RX_EN signal will delay (RXEN_DLY +1) microseconds to de-assert after packet is received + 0 + 10 + read-write + + + RXEN_DLY_OVERRIDE + RX_EN delay to de-assert time override enable. + 31 + 1 + read-write + + + 0 + For Bluetooth LE case, RX_EN signal will delay to de-assert accroding to the length of TERM2 or CTE(when BLE_V5P1_CTE_EN is enabled) field parsed by hardware + #0 + + + 1 + For all receive case, RX_EN signal will delay to de-assert accroding to register RXEN_DLY[9:0]. + #1 + + + + + + + SAM_CTRL + SAM CONTROL + 0xD4 + 32 + read-write + 0x80804000 + 0xFFFFFFFF + + + SAP0_EN + Enables SAP0 Partition of the SAM Table + 0 + 1 + read-write + + + 0 + Disables SAP0 Partition + #0 + + + 1 + Enables SAP0 Partition + #1 + + + + + SAA0_EN + Enables SAA0 Partition of the SAM Table + 1 + 1 + read-write + + + 0 + Disables SAA0 Partition + #0 + + + 1 + Enables SAA0 Partition + #1 + + + + + SAP1_EN + Enables SAP1 Partition of the SAM Table + 2 + 1 + read-write + + + 0 + Disables SAP1 Partition + #0 + + + 1 + Enables SAP1 Partition + #1 + + + + + SAA1_EN + Enables SAA1 Partition of the SAM Table + 3 + 1 + read-write + + + 0 + Disables SAA1 Partition + #0 + + + 1 + Enables SAA1 Partition + #1 + + + + + SAA0_START + First Index of SAA0 partition + 8 + 8 + read-write + + + SAP1_START + First Index of SAP1 partition + 16 + 8 + read-write + + + SAA1_START + First Index of SAA1 partition + 24 + 8 + read-write + + + + + SAM_TABLE + SOURCE ADDRESS MANAGEMENT TABLE + 0xD8 + 32 + read-write + 0 + 0xC00007F + + + SAM_INDEX + Contains the SAM table index to be enabled or invalidated + 0 + 7 + read-write + + + SAM_INDEX_WR + Enables SAM Table Contents to be updated + 7 + 1 + write-only + + + SAM_CHECKSUM + Software-computed source address checksum, to be installed into a table index + 8 + 16 + read-write + + + SAM_INDEX_INV + Invalidate the SAM table index selected by SAM_INDEX + 24 + 1 + write-only + + + SAM_INDEX_EN + Enable the SAM table index selected by SAM_INDEX + 25 + 1 + write-only + + + ACK_FRM_PND + State of AutoTxAck FramePending field when SAM Accelleration is Disabled + 26 + 1 + read-write + + + ACK_FRM_PND_CTRL + Manual Control for AutoTxAck FramePending field + 27 + 1 + read-write + + + 0 + the FramePending field of the Frame Control Field of the next automatic TX acknowledge packet is determined by hardware + #0 + + + 1 + the FramePending field of the Frame Control Field of the next automatic TX acknowledge packet tracks ACK_FRM_PEND + #1 + + + + + FIND_FREE_IDX + Find First Free Index + 28 + 1 + write-only + + + INVALIDATE_ALL + Invalidate Entire SAM Table + 29 + 1 + write-only + + + SRCADDR + Source Address Match Status + 30 + 1 + read-only + + + SAM_BUSY + SAM Table Update Status Bit + 31 + 1 + read-only + + + + + SAM_MATCH + SOURCE ADDRESS MANAGEMENT MATCH + 0xDC + 32 + read-only + 0 + 0 + + + SAP0_MATCH + Index in the SAP0 Partition of the SAM Table corresponding to the first checksum match + 0 + 7 + read-only + + + SAP0_ADDR_PRESENT + A Checksum Match is Present in the SAP0 Partition of the SAM Table + 7 + 1 + read-only + + + SAA0_MATCH + Index in the SAA0 Partition of the SAM Table corresponding to the first checksum match + 8 + 7 + read-only + + + SAA0_ADDR_ABSENT + A Checksum Match is Absent in the SAA0 Partition of the SAM Table + 15 + 1 + read-only + + + SAP1_MATCH + Index in the SAP1 Partition of the SAM Table corresponding to the first checksum match + 16 + 7 + read-only + + + SAP1_ADDR_PRESENT + A Checksum Match is Present in the SAP1 Partition of the SAM Table + 23 + 1 + read-only + + + SAA1_MATCH + Index in the SAA1 Partition of the SAM Table corresponding to the first checksum match + 24 + 7 + read-only + + + SAA1_ADDR_ABSENT + A Checksum Match is Absent in the SAP1 Partition of the SAM Table + 31 + 1 + read-only + + + + + SAM_FREE_IDX + SAM FREE INDEX + 0xE0 + 32 + read-only + 0 + 0 + + + SAP0_1ST_FREE_IDX + First non-enabled (invalid) index in the SAP0 partition + 0 + 8 + read-only + + + SAA0_1ST_FREE_IDX + First non-enabled (invalid) index in the SAA0 partition + 8 + 8 + read-only + + + SAP1_1ST_FREE_IDX + First non-enabled (invalid) index in the SAP1 partition + 16 + 8 + read-only + + + SAA1_1ST_FREE_IDX + First non-enabled (invalid) index in the SAA1 partition + 24 + 8 + read-only + + + + + MISC1 + MISCELLANEOUS(1) + 0xE4 + 32 + read-write + 0 + 0x3FFC0000 + + + SRC_ADDR_CHECKSUM + Hardware-computed received source address checksum + 0 + 16 + read-only + + + SW_ABORTED + Autosequence has terminated due to a Software abort. + 16 + 1 + read-only + + + PLL_ABORTED + Autosequence has terminated due to an PLL unlock event. + 17 + 1 + read-only + + + FAST_TX_WU_OVRD + FAST_TX_WU override + 28 + 1 + read-write + + + 0 + If TSM enables Fast Warmup Capability, LL will request it when TX in RT or (CCA+TX) + #0 + + + 1 + If TSM enables Fast Warmup Capability, LL will request it at every TX. User should insure channel is not changed since last sequence. + #1 + + + + + FAST_RX_WU_OVRD + FAST_RX_WU override + 29 + 1 + read-write + + + 0 + If TSM enables Fast Warmup Capability, LL will request it when RX in TR + #0 + + + 1 + If TSM enables Fast Warmup Capability, LL will request it at every RX. User should insure channel is not changed since last sequence. + #1 + + + + + PI + Poll Indication + 30 + 1 + read-only + + + 0 + the received packet was not a data request + #0 + + + 1 + the received packet was a data request, regardless of whether a Source Address table match occurred, or whether Source Address Management is enabled or not + #1 + + + + + RX_FRM_PEND + RX Frame Pending + 31 + 1 + read-only + + + + + SEQ_STS + SEQUENCE STATUS + 0xE8 + 32 + read-only + 0 + 0xE0FFFFFF + + + TX_START_T1_PEND + TX T1 Start Pending Status + 0 + 1 + read-only + + + TX_START_T2_PEND + TX T2 Start Pending Status + 1 + 1 + read-only + + + TX_IN_WARMUP + TX Warmup Status + 2 + 1 + read-only + + + TX_IN_PROGRESS + TX in Progress Status + 3 + 1 + read-only + + + TX_IN_WARMDN + TX Warmdown Status + 4 + 1 + read-only + + + RX_START_T1_PEND + RX T1 Start Pending Status + 5 + 1 + read-only + + + RX_START_T2_PEND + RX T2 Start Pending Status + 6 + 1 + read-only + + + RX_STOP_T1_PEND + RX T1 Stop Pending Status + 7 + 1 + read-only + + + RX_STOP_T2_PEND + RX T2 Start Pending Status + 8 + 1 + read-only + + + RX_IN_WARMUP + RX Warmup Status + 9 + 1 + read-only + + + RX_IN_SEARCH + RX Search Status + 10 + 1 + read-only + + + RX_IN_PROGRESS + RX in Progress Status + 11 + 1 + read-only + + + RX_IN_WARMDN + RX Warmdown Status + 12 + 1 + read-only + + + TR_START_T1_PEND + TR T1 Start Pending Status + 13 + 1 + read-only + + + TR_START_T2_PEND + TR T2 Start Pending Status + 14 + 1 + read-only + + + CCA_START_T1_PEND + CCA T1 Start Pending Status + 15 + 1 + read-only + + + CCA_START_T2_PEND + CCA T2 Start Pending Status + 16 + 1 + read-only + + + SEQ_T_STATUS + Status of the just-completed or ongoing Sequence T or Sequence TR + 24 + 5 + read-only + + + + + PHR_MISC + PHR MISCELLANEOUS + 0xEC + 32 + read-write + 0 + 0xFFFFFFFF + + + SUNFSK_MS + Mode Switch Bit + 0 + 1 + read-only + + + SUNFSK_MSP + Mode Switch Parameter Bit + 1 + 2 + read-only + + + SUNFSK_FEC + New Mode FEC Bit + 3 + 1 + read-only + + + SUNFSK_NM + New Mode Bit + 4 + 7 + read-only + + + PHR_FAIL_IGNORE + Ignore PHR Fail + 24 + 1 + read-write + + + + + GTM_CTRL + GTM CONTROL + 0xF0 + 32 + read-write + 0 + 0xFFFFFFFF + + + GTM_IN_RX + Enable GTM Receive Mode + 0 + 1 + read-write + + + 0 + GTM receive mode is not enabled. + #0 + + + 1 + GTM receive mode is enabled. + #1 + + + + + GTM_IN_TX + Enable GTM Transmit Mode + 1 + 1 + read-write + + + 0 + GTM transmit mode is not enabled. + #0 + + + 1 + GTM transmit mode is enabled. + #1 + + + + + + + GTM_BAD_CNT + GTM BAD PACKET COUNTER + 0xF4 + 32 + read-only + 0 + 0xFFFFFFFF + + + GTM_BAD_PKT_COUNT + GTM Bad Packet Counter + 0 + 12 + read-only + + + + + GTM_GOOD_CNT + GTM GOOD PACKET COUNTER + 0xF8 + 32 + read-only + 0 + 0xFFFFFFFF + + + GTM_GOOD_PKT_COUNT + GTM Good Packet Counter + 0 + 12 + read-only + + + + + GTM_PKT_CNT + GTM PACKET COUNTER + 0xFC + 32 + read-only + 0 + 0xFFFFFFFF + + + GTM_PKT_COUNT + GTM Packet Counter + 0 + 13 + read-only + + + + + + + RADIO_CTRL + RADIO_MISC + 0x40086000 + + 0 + 0x10 + registers + + + + LL_STATUS + Radio LL STATUS + 0 + 32 + read-only + 0 + 0xFFFFFFC0 + + + LL_PRESENT + Link Layer (LL) present status + 0 + 6 + read-only + + + + + LL_CTRL + Radio control register + 0x4 + 32 + read-write + 0x3 + 0xFFFFFFFF + + + ACTIVE_LL + Link layer select register + 0 + 2 + read-write + + + 00 + Bluetooth LE LL is selected + #00 + + + 10 + GENERIC LL is selected + #10 + + + 11 + Disabled (default) + #11 + + + + + + + PACKET_RAM_CTRL + PACKET_RAM_CTRL register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + PB_PROTECT + PB_PROTECT + 0 + 1 + read-write + + + 0 + Incoming receive data can overwrite the existing contents of the RX section of the Packet Buffer. + #0 + + + 1 + Incoming receive data is been blocked from overwriting the existing contents of the RX section of the Packet Buffer. + #1 + + + + + RAM_IPS_WAIT_DISABLE + RAM_IPS_WAIT_DISABLE + 1 + 1 + read-write + + + 0 + ips_xfr_wait is asserted when LL is accessing packet RAM + #0 + + + 1 + ips_xfr_wait is not asserted when LL is accessing packet RAM + #1 + + + + + RX_RAM_CLK_ON_OVRD_EN + Override control for RX_RAM Clock Gate Enable + 4 + 1 + read-write + + + 0 + Normal operation. + #0 + + + 1 + Use the state of RX_RAM_CLK_ON_OVRD_EN to override the RAM Clock Gate Enable. + #1 + + + + + RX_RAM_CLK_ON_OVRD + Override value for RX_RAM Clock Gate Enable + 5 + 1 + read-write + + + RX_RAM_CE_ON_OVRD_EN + Override control for RX RAM CE + 6 + 1 + read-write + + + 0 + Normal operation. + #0 + + + 1 + Use the state of RX_RAM_CE_ON_OVRD to override the RX RAM CE. + #1 + + + + + RX_RAM_CE_ON_OVRD + Override value for RAM CE + 7 + 1 + read-write + + + TX_RAM_CLK_ON_OVRD_EN + Override control for TX_RAM1 Clock Gate Enable + 8 + 1 + read-write + + + 0 + Normal operation. + #0 + + + 1 + Use the state of TX_RAM1_CLK_ON_OVRD_EN to override the TX RAM1 Clock Gate Enable. + #1 + + + + + TX_RAM_CLK_ON_OVRD + Override value for RAM Clock Gate Enable + 9 + 1 + read-write + + + TX_RAM_CE_ON_OVRD_EN + Override control for RAM CE + 10 + 1 + read-write + + + 0 + Normal operation. + #0 + + + 1 + Use the state of TX_RAM_CE_ON_OVRD_EN to override the RAM CE. + #1 + + + + + TX_RAM_CE_ON_OVRD + Override value for RAM CE (Chip Enable) + 11 + 1 + read-write + + + + + RF_CTRL_OVRD + Radio Control Override Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + RBME_MODE_OVRD_EN + RBME Mode Override Enable + 0 + 1 + read-write + + + 0 + RBME Mode Override Disable + #0 + + + 1 + RBME Mode Override Enable + #1 + + + + + RBME_MODE_OVRD + RBME Mode Override + 1 + 3 + read-write + + + RX_CON_EN_OVRD_EN + rx_con_en Override Enable + 4 + 1 + read-write + + + 0 + rx_con_en Override Disable + #0 + + + 1 + rx_con_en Override Enable + #1 + + + + + RX_CON_EN_OVRD + rx_con_en Override + 5 + 1 + read-write + + + BLE_LR_EN_OVRD_EN + ble_lr_en Override Enable + 6 + 1 + read-write + + + 0 + ble_lr_en Override Disable + #0 + + + 1 + ble_lr_en Override Enable + #1 + + + + + BLE_LR_EN_OVRD + ble_lr_en Override + 7 + 1 + read-write + + + RIF_SEL_2MBPS_OVRD_EN + rif_sel_2mbps Override Enable + 8 + 1 + read-write + + + 0 + rif_sel_2mbps Override Disable + #0 + + + 1 + rif_sel_2mbps Override Enable + #1 + + + + + RIF_SEL_2MBPS_OVRD + rif_sel_2mbps Override + 9 + 1 + read-write + + + RBME_CLK_EN_OVRD + RBME Clock Enable Override + 16 + 1 + read-write + + + 0 + RBME clock force on is disabled. + #0 + + + 1 + RBME clock force on is enabled. + #1 + + + + + BTLL_CLK_EN_OVRD + BTLL Clock Enable Override + 17 + 1 + read-write + + + 0 + BTLL clock force on is disabled. + #0 + + + 1 + BTLL clock force on is enabled. + #1 + + + + + GENLL_CLK_EN_OVRD + GENLL Clock Enable Override + 18 + 1 + read-write + + + 0 + GENLL clock force on is disabled. + #0 + + + 1 + GENLL clock force on is enabled. + #1 + + + + + + + + + RBME + RBME + 0x40086200 + + 0 + 0x70 + registers + + + + CRCW_CFG + CRC/WHITENER CONFIG REGISTER + 0 + 32 + read-write + 0x4 + 0xFFFFFFFF + + + CRCW_EN + CRC calculation enable + 0 + 1 + read-write + + + CRCW_EC_EN + CRC Error Correction Enable + 1 + 1 + read-write + + + CRC_ZERO + CRC zero + 2 + 1 + read-only + + + CRC_EARLY_FAIL + CRC error correction fail + 3 + 1 + read-only + + + CRC_RES_OUT_VLD + CRC result output valid + 4 + 1 + read-only + + + CRC_EC_OFFSET + CRC error correction offset + 16 + 11 + read-only + + + CRC_EC_DONE + CRC error correction done + 28 + 1 + read-only + + + CRC_EC_FAIL + CRC error correction fail + 29 + 1 + read-only + + + + + CRC_EC_MASK + CRC ERROR CORRECTION MASK + 0x4 + 32 + read-only + 0 + 0xFFFFFFFF + + + CRC_EC_MASK + CRC error correction mask + 0 + 32 + read-only + + + + + CRC_RES_OUT + CRC RESULT + 0x8 + 32 + read-only + 0 + 0xFFFFFFFF + + + CRC_RES_OUT + CRC result output + 0 + 32 + read-only + + + + + CRCW_CFG2 + CRC/WHITENER CONFIG 2 REGISTER + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + CRC_EC_SPKT_BYTES + Error Correction Short Packet Bytes + 0 + 8 + read-write + + + CRC_EC_SPKT_WND + Error correction short packet burst error window + 8 + 4 + read-write + + + CRC_EC_LPKT_WND + Error correction long packet burst error window + 12 + 4 + read-write + + + + + CRCW_CFG3 + CRC CONFIGURATION + 0x10 + 32 + read-write + 0x2 + 0xFFFFFFFF + + + CRC_SZ + CRC Size (in octets) + 0 + 3 + read-write + + + CRC_START_BYTE + Configure CRC Start Point + 8 + 4 + read-write + + + CRC_REF_IN + CRC Reflect In + 16 + 1 + read-write + + + 0 + Does not manipulate input data stream + #0 + + + 1 + reflect each byte in the input stream bitwise + #1 + + + + + CRC_REF_OUT + CRC Reflect Out + 17 + 1 + read-write + + + 0 + Does not manipulate CRC result + #0 + + + 1 + CRC result is to be reflected bitwise (operated on entire word) + #1 + + + + + CRC_BYTE_ORD + CRC Byte Order + 18 + 1 + read-write + + + 0 + LS Byte First + #0 + + + 1 + MS Byte First + #1 + + + + + + + CRC_INIT + CRC INITIALIZATION + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + CRC_SEED + CRC Seed Value + 0 + 32 + read-write + + + + + CRC_POLY + CRC POLYNOMIAL + 0x18 + 32 + read-write + 0x10210000 + 0xFFFFFFFF + + + CRC_POLY + CRC Polynomial. + 0 + 32 + read-write + + + + + CRC_XOR_OUT + CRC XOR OUT + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + CRC_XOR_OUT + CRC XOR OUT Register + 0 + 32 + read-write + + + + + WHITEN_CFG + WHITENER CONFIGURATION + 0x20 + 32 + read-write + 0x1FF0918 + 0xFFFFFFFF + + + WHITEN_START + Configure Whitener Start Point + 0 + 2 + read-write + + + 00 + no whitening + #00 + + + 01 + start whitening at start-of-H0 + #01 + + + 10 + start whitening at start-of-H1 but only if LENGTH > WHITEN_SZ_THR + #10 + + + 11 + start whitening at start-of-payload but only if LENGTH > WHITEN_SZ_THR + #11 + + + + + WHITEN_END + Configure end-of-whitening + 2 + 1 + read-write + + + 0 + end whiten at end-of-payload + #0 + + + 1 + end whiten at end-of-crc + #1 + + + + + WHITEN_B4_CRC + Congifure for Whitening-before-CRC + 3 + 1 + read-write + + + 0 + CRC before whiten/de-whiten + #0 + + + 1 + Whiten/de-whiten before CRC + #1 + + + + + WHITEN_POLY_TYPE + Whiten Polynomial Type + 4 + 1 + read-write + + + WHITEN_REF_IN + Whiten Reflect Input + 5 + 1 + read-write + + + WHITEN_PAYLOAD_REINIT + Configure for Whitener re-initialization + 6 + 1 + read-write + + + 0 + Does not re-initialize Whitener LFSR at start-of-payload + #0 + + + 1 + Re-initialize Whitener LFSR at start-of-payload + #1 + + + + + WHITEN_SIZE + Length of Whitener LFSR + 8 + 4 + read-write + + + WHITEN_INIT + Initialization value for whitening/de-whitening + 16 + 9 + read-write + + + + + WHITEN_POLY + WHITENER POLYNOMIAL + 0x24 + 32 + read-write + 0x21 + 0xFFFFFFFF + + + WHITEN_POLY + Whitener Polynomial + 0 + 9 + read-write + + + + + WHITEN_SZ_THR + WHITENER SIZE THRESHOLD + 0x28 + 32 + read-write + 0x800 + 0xFFFFFFFF + + + WHITEN_SZ_THR + Whitener Size Threshold + 0 + 12 + read-write + + + + + FEC_CFG1 + FEC CONFIG REGISTER 1 + 0x2C + 32 + read-write + 0x301 + 0xFFFFFFFF + + + FEC_EN + FEC enable + 0 + 1 + read-write + + + 0 + Disable FEC encoder and decoder + #0 + + + 1 + Enable FEC encoder and decoder + #1 + + + + + FEC_SWAP + Choose 802.15.4 swap mode of FEC operation + 1 + 1 + read-write + + + 0 + Disable Swap operation for FEC + #0 + + + 1 + Swap for 802.15.4 and LEG0 + #1 + + + + + FECOV_EN + Enable dynamic overide of FEC + 2 + 1 + read-write + + + 1 + The override of FEC is only used in 802.15.4, dynamically depending on the SFD pattern received + #1 + + + 0 + Disable FEC override + #0 + + + + + INTV_EN + Enable interleaver reigster + 4 + 1 + read-write + + + 1 + Enable interleaver for 15.4 and LEG0 + #1 + + + 0 + Disable interleaver for 802.15.4 and LEG0 + #0 + + + + + NTERM + Number of term bits + 8 + 3 + read-write + + + + + RBME_RST + RBME SOFT RESET REGISTER + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + RBME_RST + RBME reset signal + 0 + 1 + read-write + + + 0 + Disable soft reset + #0 + + + 1 + Enable soft reset. When this bit is write to 1, the soft reset to RBME happens immediately. Then all internal registers and functions will be reset. + #1 + + + + + + + FEC_CFG2 + FEC CONFIG REGISTER 2 + 0x34 + 32 + read-write + 0x3F7F0F + 0xFFFFFFFF + + + TB_LENGTH + Trace-back length + 0 + 5 + read-write + + + SAT_VL + Saturation value for PM + 8 + 8 + read-write + + + LARGE_VL + Large value used at startup phase, assigned to the initial PMs. + 16 + 7 + read-write + + + SDIDX + Index of startup state. PM(startStIdx)=0 + 24 + 3 + read-write + + + + + FLUSH_CFG + FEC FLUSH CONFIG REGISTER + 0x38 + 32 + read-write + 0 + 0xFFFFFFFF + + + FLUSH_CFG + FLUSH CLOCK CONFIG BIT + 0 + 1 + read-write + + + 0 + 32M flush clock + #0 + + + 1 + 26M flush clock + #1 + + + + + + + SPREAD_CFG + SPREADER CONFIG REGISTER + 0x3C + 32 + read-write + 0x200 + 0xFFFFFFFF + + + SP_EN + Spreader Enable bit + 0 + 1 + read-write + + + 0 + Disable spreader + #0 + + + 1 + Enable spreader + #1 + + + + + SPOV_EN + Spreader Override Enable + 1 + 1 + read-write + + + 0 + Does not allow active override of the spreading enable + #0 + + + 1 + Allows active override of the spreading enable + #1 + + + + + CI_TX + Bluetooth LE + 2 + 1 + read-write + + + 0 + FEC Block 2 coded using S=8 + #0 + + + 1 + FEC Block 2 coded using S=2 + #1 + + + + + SP_FACTOR + Spreading Factor + 8 + 4 + read-write + + + SP_SEQ + Spreading Bit Sequence + 16 + 16 + read-write + + + + + WHT_CFG + WHITEN CONFIG REGISTER + 0x40 + 32 + read-write + 0x2001000 + 0xFFFFFFFF + + + W1_EN + Enable first whitener + 0 + 1 + read-write + + + WFIRST + Whitens before CRC + 2 + 1 + read-write + + + WTOV_EN + Allows overwrite of the whitening + 3 + 1 + read-write + + + WT_OUT_SEL + Selected Output + 12 + 4 + read-write + + + WT_TPOGY + Whiten 1 Polynomial Type + 24 + 2 + read-write + + + + + PKT_SZ + PACKET SIZE REGISTER + 0x44 + 32 + read-write + 0x224000 + 0xFFFFFFFF + + + MAX_PKT_SZ + Maximum Packet Size In Bits + 0 + 16 + read-write + + + DEF_PKT_SZ + Default Packet Size + 16 + 16 + read-write + + + + + CRC_PHR_SZ + LENGTH OF PHR CONFIG REGISTER + 0x48 + 32 + read-write + 0x3 + 0xFFFFFFFF + + + PHR_SZ + PHR Size Config + 0 + 3 + read-write + + + + + FCP_CFG + FCP SUPPORT CONFIG REGISTER + 0x4C + 32 + read-write + 0 + 0xFFFFFFFF + + + FCP_SUPPORT + FCP Suppport + 0 + 1 + read-write + + + 0 + Disable FCP support + #0 + + + 1 + Enable FCP support + #1 + + + + + + + FRAME_OVER_SZ + FRAME OVERRIDE SIZE REGISTER + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + STD_FRM_OV_EN + Overrides actvie STD frame length from link layer enable bit + 0 + 1 + read-write + + + 0 + Disable override actvie STD frame length from link layer + #0 + + + 1 + Enable override actvie STD frame length from link layer + #1 + + + + + STD_FRM_OV + Value to overide the STD frame length (bits) + 16 + 11 + read-write + + + + + FEC_BSZ_OV_B4SP + OVERRIDE OF FEC BLOCK SIZE REGISTER + 0x54 + 32 + read-write + 0 + 0xFFFFFFFF + + + FEC_BSZ_OV_B4SP_EN + Override of the FEC block size for data + 0 + 1 + read-write + + + 0 + Disable Override actvie STD frame length from link layer + #0 + + + 1 + Enable Override actvie STD frame length from link layer + #1 + + + + + FEC_BSZ_OV + Value of the override in bits. It is for test purpose. + 16 + 16 + read-write + + + + + LEG0_CFG + LEG0 CONFIG REGISTER + 0x58 + 32 + read-write + 0xF202DD00 + 0xFFFFFFFF + + + LEG0_INV_EN + Whiten invert enable bit + 0 + 1 + read-write + + + 0 + Disable whiten invert for LEG0 + #0 + + + 1 + Enable whiten invert for LEG0 + #1 + + + + + LEG0_SUP + LEG0 support register + 1 + 1 + read-write + + + 0 + Disable LEG0 support + #0 + + + 1 + Enable LEG0 support + #1 + + + + + LEG0_XOR_BYTE + LEG0 whitening masking byte + 8 + 8 + read-write + + + LEG0_XOR_RP_BYTE + LEG0 repeat bytes masking + 16 + 8 + read-write + + + LEG0_XOR_FST_BYTE + FEC first byte masking + 24 + 8 + read-write + + + + + NPAYL_OVER_SZ + OVERRIDE PAYLOAD LENGTH REGISTER + 0x5C + 32 + read-write + 0 + 0xFFFFFFFF + + + NPAYL_OV_EN + Override the internal payload length computation + 0 + 1 + read-write + + + 0 + Disable override the internal payload length + #0 + + + 1 + Enable override the internal payload length + #1 + + + + + FT_FEC_FLUSH + Value to overide the payload length (bits) + 8 + 5 + read-write + + + NPAYL_OV + no description available + 16 + 11 + read-write + + + + + DATALL_CFG + DATA TO LINK LAYER CONFIG REGISTER + 0x60 + 32 + read-write + 0 + 0xFFFFFFFF + + + DELAY_EN + Data to link layer delay enable bit + 0 + 1 + read-write + + + 0 + Disable delay in 32M + #0 + + + 1 + Enable delay in 26M + #1 + + + + + + + RAM_S_ADDR + PACKET RAM SOURCE ADDRESS + 0x64 + 32 + read-write + 0 + 0xFFFFFFFF + + + RAM_S_ADDR + Packet RAM source address. This address is ram physical address. + 0 + 14 + read-write + + + + + RAM_D_ADDR + PACKET RAM DESTINATION ADDRESS + 0x68 + 32 + read-write + 0 + 0xFFFFFFFF + + + RAM_D_ADDR + Packet RAM destination address, this address is ram physical address. + 0 + 14 + read-write + + + + + RAM_IF_CFG + PACKET RAM INTERFACE CONFIG REGISTER + 0x6C + 32 + read-write + 0 + 0xFFFFFFFF + + + RAM_IF_TX_EN + RAM interface TX enable bit + 0 + 1 + read-write + + + 0 + Disable RAM interface TX + #0 + + + 1 + Enable RAM interface TX + #1 + + + + + RAM_IF_RX_EN + RAM interface RX enable + 1 + 1 + read-write + + + 0 + Disable RAM interface RX + #0 + + + 1 + Enable RAM interface RX + #1 + + + + + RAM_IF_IE + RAM interface interrupt enable bit + 4 + 1 + read-write + + + 0 + Disable RAM interface interrupt + #0 + + + 1 + Enable RAM interface interrupt + #1 + + + + + RAM_IF_IC + RAM interface interrupt clear + 5 + 1 + read-write + + + 0 + To do nothing to RAM interface interrupt + #0 + + + 1 + To clear RAM interface interrupt + #1 + + + + + H2S_EN + Hard bit convert to soft bit enable + 6 + 1 + read-write + + + 0 + Disable hard bit to soft bits coversion + #0 + + + 1 + Enable hard bit to soft bits coversion + #1 + + + + + SOFT_HD_SEL_RD + Soft and hard bit selection of write operation + 8 + 1 + read-write + + + 0 + Hard bit selection of write operation + #0 + + + 1 + Soft bit selection of write operation + #1 + + + + + SOFT_HD_SEL_WR + Soft and hard bit selection of read operation + 9 + 1 + read-write + + + 0 + Hard bit selection of read operation + #0 + + + 1 + Soft bit selection of read operation + #1 + + + + + WR_IRQ + Write to RAM complete flag + 10 + 1 + read-only + + + 0 + Writing to RAM not complete + #0 + + + 1 + Writing to RAM complete + #1 + + + + + RD_IRQ + Read to RAM complete flag + 11 + 1 + read-only + + + 0 + Reading to RAM not complete + #0 + + + 1 + Reading to RAM complete + #1 + + + + + + + + + XCVR_RX_DIG + XCVR_RX_DIG + 0x40087000 + + 0 + 0x264 + registers + + + + RX_DIG_CTRL + RX Digital Control + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + RX_ADC_NEGEDGE + Receive ADC Negative Edge Selection + 0 + 1 + read-write + + + 0 + Register ADC data on positive edge of clock + #0 + + + 1 + Register ADC data on negative edge of clock + #1 + + + + + RX_CH_FILT_BYPASS + Receive Channel Filter Bypass + 1 + 1 + read-write + + + 0 + Channel filter is enabled. + #0 + + + 1 + Disable and bypass channel filter. + #1 + + + + + RX_ADC_RAW_EN + ADC Raw Mode selection + 2 + 1 + read-write + + + 0 + Normal operation. + #0 + + + 1 + The decimation filter's 12bit output consists of ADC samples in the 8 LSBs. This is for test purposes only to observe ADC output via XCVR DMA or DTEST. + #1 + + + + + RX_ADC_POL + Receive ADC Polarity + 3 + 1 + read-write + + + 0 + ADC output of 1'b0 maps to -1, 1'b1 maps to +1 (default) + #0 + + + 1 + ADC output of 1'b0 maps to +1, 1'b1 maps to -1 + #1 + + + + + RX_DEC_FILT_OSR + Decimation Filter Oversampling + 4 + 4 + read-write + + + 0000 + OSR 4 + #0000 + + + 0001 + OSR 8 + #0001 + + + 0010 + OSR 16 + #0010 + + + 0100 + OSR 32 + #0100 + + + 1000 + OSR 64 + #1000 + + + 0011 + OSR 6 + #0011 + + + 0101 + OSR 12 + #0101 + + + 0110 + OSR 24 + #0110 + + + 0111 + OSR 48 + #0111 + + + + + RX_FSK_ZB_SEL + Demodulator select + 8 + 1 + read-write + + + 0 + FSK demodulator. + #0 + + + + + RX_D_CH_FILT_BYPASS + Receive Demod Channel Filter Bypass + 9 + 1 + read-write + + + 0 + Demod channel filter is enabled. + #0 + + + 1 + Disable and bypass demod channel filter. + #1 + + + + + RX_RSSI_EN + RSSI Measurement Enable + 10 + 1 + read-write + + + 0 + RSSI measurement is disabled. + #0 + + + 1 + RSSI measurement is enabled. + #1 + + + + + RX_AGC_EN + AGC Global Enable + 11 + 1 + read-write + + + 0 + AGC is disabled. + #0 + + + 1 + AGC is enabled. + #1 + + + + + RX_DCOC_EN + DCOC Enable + 12 + 1 + read-write + + + 0 + DCOC is disabled. + #0 + + + 1 + DCOC is enabled. + #1 + + + + + RX_DCOC_CAL_EN + DCOC Calibration Enable + 13 + 1 + read-write + + + 0 + DCOC calibration is disabled. + #0 + + + 1 + DCOC calibration is enabled. + #1 + + + + + RX_IQ_SWAP + RX IQ Swap + 14 + 1 + read-write + + + 0 + IQ swap is disabled. + #0 + + + 1 + IQ swap is enabled. + #1 + + + + + RX_DC_RESID_EN + DC Residual Enable + 15 + 1 + read-write + + + 0 + DC Residual block is disabled. + #0 + + + 1 + DC Residual block is enabled. + #1 + + + + + RX_SRC_EN + RX Sample Rate Converter Enable + 16 + 1 + read-write + + + 0 + SRC is disabled. + #0 + + + 1 + SRC is enabled. + #1 + + + + + RX_SRC_RATE + RX Sample Rate Converter Rate Selections + 17 + 1 + read-write + + + 0 + SRC is configured for a First Order Hold rate of 8/13. + #0 + + + 1 + SRC is configured for a Zero Order Hold rate of 12/13. + #1 + + + + + RX_DMA_DTEST_EN + RX DMA and DTEST enable + 18 + 1 + read-write + + + RX_DEC_FILT_LP + RX Decimator Low Power + 19 + 1 + read-write + + + 0 + Decimator operates in normal mode. + #0 + + + 1 + Decimator operates in low power mode. + #1 + + + + + RX_DEC_FILT_GAIN + Decimation Filter Fractional Gain + 20 + 5 + read-write + + + RX_DEC_FILT_HZD_CORR_DIS + Decimator filter hazard correction disable + 25 + 1 + read-write + + + 0 + Hazard correction is enabled + #0 + + + 1 + Hazard correction is disabled + #1 + + + + + RX_CH_FILT_LEN + RX Channel Filter Length + 26 + 1 + read-write + + + 0 + Channel filter length is 24. + #0 + + + 1 + Channel filter length is 16. Only RX_CHF_COEF_4 - RX_CHF_COEF_11 are used in this mode. + #1 + + + + + RX_SAMPLE_BUF_DIS + RX Sample Buffer Disable + 27 + 1 + read-write + + + 0 + Buffer is enabled. + #0 + + + 1 + Buffer is disabled. + #1 + + + + + RX_DEC_FILT_HAZARD + Decimator output, hazard condition detected + 28 + 1 + read-only + + + 0 + A hazard condition has not been detected + #0 + + + 1 + A hazard condition has been detected + #1 + + + + + RX_RSSI_FILT_HAZARD + Decimator output for RSSI, hazard condition detected + 29 + 1 + read-only + + + 0 + A hazard condition has not been detected + #0 + + + 1 + A hazard condition has been detected + #1 + + + + + RX_DEC_FILT_SAT_I + Decimator output, saturation detected for I channel + 30 + 1 + read-only + + + 0 + A saturation condition has not occurred. + #0 + + + 1 + A saturation condition has occurred. + #1 + + + + + RX_DEC_FILT_SAT_Q + Decimator output, saturation detected for Q channel + 31 + 1 + read-only + + + 0 + A saturation condition has not occurred. + #0 + + + 1 + A saturation condition has occurred. + #1 + + + + + + + AGC_CTRL_0 + AGC Control 0 + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + SLOW_AGC_EN + Slow AGC Enable + 0 + 1 + read-write + + + SLOW_AGC_SRC + Slow AGC Source Selection + 1 + 2 + read-write + + + 00 + Access Address match (for active protocol) + #00 + + + 01 + Preamble Detect (for active protocol) + #01 + + + 10 + Fast AGC expire timer + #10 + + + + + AGC_FREEZE_EN + AGC Freeze Enable + 3 + 1 + read-write + + + AGC_FREEZE_SRC + AGC Freeze Source Selection + 4 + 2 + read-write + + + 00 + Access Address match (for active protocol) + #00 + + + 01 + Preamble Detect (for active protocol) + #01 + + + 10 + PD confirmation / Access Address match (for active protocol) + #10 + + + + + AGC_UP_EN + AGC Up Enable + 6 + 1 + read-write + + + AGC_UP_SRC + AGC Up Source + 7 + 1 + read-write + + + 0 + PDET LO + #0 + + + 1 + RSSI + #1 + + + + + AGC_DOWN_BBA_STEP_SZ + AGC_DOWN_BBA_STEP_SZ + 8 + 4 + read-write + + + AGC_DOWN_LNA_STEP_SZ + AGC_DOWN_LNA_STEP_SZ + 12 + 4 + read-write + + + AGC_UP_RSSI_THRESH + AGC UP RSSI Threshold + 16 + 8 + read-write + + + AGC_DOWN_RSSI_THRESH + AGC DOWN RSSI Threshold + 24 + 8 + read-write + + + + + AGC_CTRL_1 + AGC Control 1 + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRESLOW_UP_THRESH + PRESLOW_UP_THRESH + 0 + 4 + read-write + + + PRESLOW_DOWN_THRESH + PRESLOW_DOWN_THRESH + 4 + 4 + read-write + + + LNA_USER_GAIN + LNA_USER_GAIN + 12 + 4 + read-write + + + BBA_USER_GAIN + BBA_USER_GAIN + 16 + 4 + read-write + + + USER_LNA_GAIN_EN + User LNA Gain Enable + 20 + 1 + read-write + + + USER_BBA_GAIN_EN + User BBA Gain Enable + 21 + 1 + read-write + + + PRESLOW_EN + Pre-slow Enable + 22 + 1 + read-write + + + 0 + Pre-slow is disabled. + #0 + + + 1 + Pre-slow is enabled. + #1 + + + + + PDET_HI_SEL_HOLD + AGC HOLD hysteresis + 23 + 1 + read-write + + + 0 + Disabled. + #0 + + + 1 + Enabled. + #1 + + + + + LNA_GAIN_SETTLE_TIME + LNA_GAIN_SETTLE_TIME + 24 + 8 + read-write + + + + + AGC_CTRL_2 + AGC Control 2 + 0xC + 32 + read-write + 0xA69000 + 0xFFFFFFFF + + + BBA_PDET_RST + BBA PDET Reset + 0 + 1 + read-write + + + TZA_PDET_RST + TZA PDET Reset + 1 + 1 + read-write + + + MAN_PDET_RST + MAN PDET Reset + 2 + 1 + read-write + + + 0 + The peak detector reset signals are controlled automatically by the AGC. + #0 + + + 1 + The BBA_PDET_RST and TZA_PDET_RST are used to manually control the peak detector reset signals. + #1 + + + + + IGNORE_PDET_HI_IN_HOLD + Ignore PDET_HI in HOLD State + 3 + 1 + read-write + + + BBA_GAIN_SETTLE_TIME + BBA Gain Settle Time + 4 + 8 + read-write + + + BBA_PDET_SEL_LO + BBA PDET Threshold Low + 12 + 3 + read-write + + + 000 + 0.600V + #000 + + + 001 + 0.615V + #001 + + + 010 + 0.630V + #010 + + + 011 + 0.645V + #011 + + + 100 + 0.660V + #100 + + + 101 + 0.675V + #101 + + + 110 + 0.690V + #110 + + + 111 + 0.705V + #111 + + + + + BBA_PDET_SEL_HI + BBA PDET Threshold High + 15 + 3 + read-write + + + 000 + 0.600V + #000 + + + 001 + 0.795V + #001 + + + 010 + 0.900V + #010 + + + 011 + 0.945V + #011 + + + 100 + 1.005V + #100 + + + 101 + 1.050V + #101 + + + 110 + 1.095V + #110 + + + 111 + 1.155V + #111 + + + + + TZA_PDET_SEL_LO + TZA PDET Threshold Low + 18 + 3 + read-write + + + 000 + 0.600V + #000 + + + 001 + 0.615V + #001 + + + 010 + 0.630V + #010 + + + 011 + 0.645V + #011 + + + 100 + 0.660V + #100 + + + 101 + 0.675V + #101 + + + 110 + 0.690V + #110 + + + 111 + 0.705V + #111 + + + + + TZA_PDET_SEL_HI + TZA PDET Threshold High + 21 + 3 + read-write + + + 000 + 0.600V + #000 + + + 001 + 0.645V + #001 + + + 010 + 0.705V + #010 + + + 011 + 0.750V + #011 + + + 100 + 0.795V + #100 + + + 101 + 0.855V + #101 + + + 110 + 0.900V + #110 + + + 111 + 0.945V + #111 + + + + + AGC_FAST_EXPIRE + AGC Fast Expire + 24 + 6 + read-write + + + LNA_LG_ON_OVR + LNA_LG_ON override + 30 + 1 + read-write + + + LNA_HG_ON_OVR + LNA_HG_ON override + 31 + 1 + read-write + + + + + AGC_CTRL_3 + AGC Control 3 + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + AGC_UNFREEZE_TIME + AGC Unfreeze Time + 0 + 13 + read-write + + + AGC_PDET_LO_DLY + AGC Peak Detect Low Delay + 13 + 3 + read-write + + + AGC_RSSI_DELT_H2S + AGC_RSSI_DELT_H2S + 16 + 7 + read-write + + + AGC_H2S_STEP_SZ + AGC_H2S_STEP_SZ + 23 + 5 + read-write + + + AGC_UP_STEP_SZ + AGC Up Step Size + 28 + 4 + read-write + + + + + AGC_STAT + AGC Status + 0x14 + 32 + read-only + 0 + 0xFFFFFFFF + + + BBA_PDET_LO_STAT + BBA Peak Detector Low Status + 0 + 1 + read-only + + + BBA_PDET_HI_STAT + BBA Peak Detector High Status + 1 + 1 + read-only + + + TZA_PDET_LO_STAT + TZA Peak Detector Low Status + 2 + 1 + read-only + + + TZA_PDET_HI_STAT + TZA Peak Detector High Status + 3 + 1 + read-only + + + CURR_AGC_IDX + Current AGC Gain Index + 4 + 5 + read-only + + + AGC_FROZEN + AGC Frozen Status + 9 + 1 + read-only + + + 0 + AGC is not frozen. + #0 + + + 1 + AGC is frozen. + #1 + + + + + AGC_IDX_AA_MATCH + AGC Gain Index at AA Match + 10 + 5 + read-only + + + RSSI_ADC_RAW + ADC RAW RSSI Reading + 16 + 8 + read-only + + + + + RSSI_CTRL_0 + RSSI Control 0 + 0x18 + 32 + read-write + 0x600000 + 0xFFFFFFFF + + + RSSI_USE_VALS + RSSI Values Selection + 0 + 1 + read-write + + + 0 + RSSI calculation uses BBA_RES_TUNE_VAL registers + #0 + + + 1 + RSSI calculation does not use BBA_RES_TUNE_VAL registers + #1 + + + + + RSSI_HOLD_SRC + RSSI Hold Source Selection + 1 + 2 + read-write + + + 0 + Access Address match + #00 + + + 1 + Preamble Detect + #01 + + + + + RSSI_HOLD_EN + RSSI Hold Enable + 3 + 1 + read-write + + + RSSI_IIR_CW_WEIGHT + RSSI IIR CW Weighting + 5 + 2 + read-write + + + 00 + Bypass + #00 + + + 01 + 1/8 + #01 + + + 10 + 1/16 + #10 + + + 11 + 1/32 + #11 + + + + + RSSI_N_WINDOW_NB + RSSI N Window Average Narrowband + 7 + 3 + read-write + + + 000 + No averaging + #000 + + + 001 + Averaging window length is 2 samples + #001 + + + 010 + Averaging window length is 4 samples + #010 + + + 011 + Averaging window length is 8 samples + #011 + + + 100 + Averaging window length is 16 samples + #100 + + + 101 + Averaging window length is 32 samples + #101 + + + + + RSSI_HOLD_DELAY + RSSI Hold Delay + 10 + 6 + read-write + + + RSSI_IIR_WT_NB + RSSI IIR Weighting Narrowband + 16 + 3 + read-write + + + 000 + Bypass + #000 + + + 001 + 1/2 + #001 + + + 010 + 1/4 + #010 + + + 011 + 1/8 + #011 + + + 100 + 1/16 + #100 + + + 101 + 1/32 + #101 + + + + + RSSI_VLD_SETTLE + RSSI Valid Settle + 19 + 5 + read-write + + + RSSI_ADJ + RSSI Adjustment + 24 + 8 + read-write + + + + + RSSI_CTRL_1 + RSSI Control 1 + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + RSSI_N_WINDOW_WB + RSSI N Window Average Wideband + 0 + 3 + read-write + + + 000 + No averaging + #000 + + + 001 + Averaging window length is 2 samples + #001 + + + 010 + Averaging window length is 4 samples + #010 + + + 011 + Averaging window length is 8 samples + #011 + + + 100 + Averaging window length is 16 samples + #100 + + + 101 + Averaging window length is 32 samples + #101 + + + + + RSSI_IIR_WT_WB + RSSI IIR Weighting Wideband + 4 + 3 + read-write + + + 000 + Bypass + #000 + + + 001 + 1/2 + #001 + + + 010 + 1/4 + #010 + + + 011 + 1/8 + #011 + + + 100 + 1/16 + #100 + + + 101 + 1/32 + #101 + + + + + RSSI_OUT + RSSI Reading + 24 + 8 + read-only + + + + + DCOC_CTRL_0 + DCOC Control 0 + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + DCOC_MIDPWR_TRK_DIS + DCOC Mid Power Tracking Disable + 0 + 1 + read-write + + + 0 + Tracking corrections are enabled as determined by DCOC_CORRECT_SRC and DCOC_TRK_MIN_AGC_IDX. + #0 + + + 1 + Tracking corrections are disabled when either the TZA or BBA lo peak detector asserts. + #1 + + + + + DCOC_MAN + DCOC Manual Override + 1 + 1 + read-write + + + DCOC_TRK_EST_OVR + Override for the DCOC tracking estimator + 2 + 1 + read-write + + + 0 + The tracking estimator is enabled only as needed by the corrector + #0 + + + 1 + The tracking estimator remains enabled whenever the DCOC is active + #1 + + + + + DCOC_CORRECT_SRC + DCOC Corrector Source + 3 + 1 + read-write + + + 0 + If correction is enabled, the DCOC will use only the DCOC calibration table to correct the DC offset. + #0 + + + 1 + If correction is enabled, the DCOC will use the DCOC calibration table and then the tracking estimator to correct the DC offset. + #1 + + + + + DCOC_CORRECT_EN + DCOC Correction Enable + 4 + 1 + read-write + + + 0 + Correction disabled. The DCOC will not correct the DC offset. + #0 + + + 1 + Correction enabled. The DCOC will use the TZA and BBA DACs, and apply digital corrections (if DCOC_CORRECT_SRC=1) to correct the DC offset. + #1 + + + + + TRACK_FROM_ZERO + Track from Zero + 5 + 1 + read-write + + + 0 + Track from current I/Q sample. + #0 + + + 1 + Track from zero. + #1 + + + + + BBA_CORR_POL + BBA Correction Polarity + 6 + 1 + read-write + + + 0 + Normal polarity. + #0 + + + 1 + Negative polarity. This should be set if the ADC output is inverted, or if the BBA DACs were implemented with negative polarity. + #1 + + + + + TZA_CORR_POL + TZA Correction Polarity + 7 + 1 + read-write + + + 0 + Normal polarity. + #0 + + + 1 + Negative polarity. This should be set if the ADC output is inverted, or if the TZA DACs were implemented with negative polarity. + #1 + + + + + DCOC_CAL_DURATION + DCOC Calibration Duration + 8 + 5 + read-write + + + DCOC_CAL_CHECK_EN + DCOC Calibration Check Enable + 15 + 1 + read-write + + + 0 + Calibration checking disabled. The DCOC_OFFSET_n registers are always updated during calibration. + #0 + + + 1 + Calibration checking enabled. The DCOC_OFFSET_n registers are updated conditionally depending on the outcome of the pass/fail threshold checks performed on the alpha-hat and beta-hat estimates during calibration. + #1 + + + + + DCOC_CORR_DLY + DCOC Correction Delay + 16 + 5 + read-write + + + DCOC_CORR_HOLD_TIME + DCOC Correction Hold Time + 24 + 7 + read-write + + + 1111111 + The DC correction is not frozen. + #1111111 + + + + + + + DCOC_CTRL_1 + DCOC Control 1 + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + DCOC_SIGN_SCALE_IDX + DCOC Sign Scaling + 0 + 2 + read-write + + + 00 + 1/8 + #00 + + + 01 + 1/16 + #01 + + + 10 + 1/32 + #10 + + + 11 + 1/64 + #11 + + + + + DCOC_ALPHAC_SCALE_IDX + DCOC Alpha-C Scaling + 2 + 3 + read-write + + + 000 + 1/2 + #000 + + + 001 + 1/4 + #001 + + + 010 + 1/8 + #010 + + + 011 + 1/16 + #011 + + + 100 + 1/32 + #100 + + + 101 + 1/64 + #101 + + + + + DCOC_ALPHA_RADIUS_IDX + Alpha-R Scaling + 5 + 3 + read-write + + + 000 + 1 + #000 + + + 001 + 1/2 + #001 + + + 010 + 1/4 + #010 + + + 011 + 1/8 + #011 + + + 100 + 1/16 + #100 + + + 101 + 1/32 + #101 + + + 110 + 1/64 + #110 + + + + + DCOC_SIGN_SCALE_ALT_IDX + DCOC Sign Scaling Alternate + 16 + 2 + read-write + + + 00 + 1/8 + #00 + + + 01 + 1/16 + #01 + + + 10 + 1/32 + #10 + + + 11 + 1/64 + #11 + + + + + DCOC_ALPHAC_SCALE_ALT_IDX + DCOC Alpha-C Scaling Alternate + 18 + 3 + read-write + + + 000 + 1/2 + #000 + + + 001 + 1/4 + #001 + + + 010 + 1/8 + #010 + + + 011 + 1/16 + #011 + + + 100 + 1/32 + #100 + + + 101 + 1/64 + #101 + + + + + DCOC_ALPHA_RADIUS_ALT_IDX + Alpha-R Scaling Alternate + 21 + 3 + read-write + + + 000 + 1 + #000 + + + 001 + 1/2 + #001 + + + 010 + 1/4 + #010 + + + 011 + 1/8 + #011 + + + 100 + 1/16 + #100 + + + 101 + 1/32 + #101 + + + 110 + 1/64 + #110 + + + + + DCOC_TRK_MIN_AGC_IDX + DCOC Tracking Minimum AGC Table Index + 24 + 5 + read-write + + + DCOC_TRK_MIN_AGC_IDX_CFG + DCOC_TRK_MIN_AGC_IDX Configuration + 31 + 1 + read-write + + + 0 + Tracking is disabled when the AGC index is less than DCOC_TRK_MIN_AGC_IDX + #0 + + + 1 + Tracking is enabled when AGC index is less than DCOC_TRK_MIN_AGC_IDX, but {DCOC_CORR_DLY_ALT, DCOC_CORR_HOLD_TIME_ALT, DCOC_ALPHA_RADIUS_ALT_IDX, DCOC_ALPHAC_SCALE_ALT_IDX, DCOC_SIGN_SCALE_ALT_IDX} are used instead of {DCOC_CORR_DLY, DCOC_CORR_HOLD_TIME, DCOC_ALPHA_RADIUS_IDX, DCOC_ALPHAC_SCALE_IDX, DCOC_SIGN_SCALE_IDX}. + #1 + + + + + + + DCOC_DAC_INIT + DCOC DAC Initialization + 0x2C + 32 + read-write + 0x80802020 + 0xFFFFFFFF + + + BBA_DCOC_INIT_I + DCOC BBA Init I + 0 + 6 + read-write + + + BBA_DCOC_INIT_Q + DCOC BBA Init Q + 8 + 6 + read-write + + + TZA_DCOC_INIT_I + DCOC TZA Init I + 16 + 8 + read-write + + + TZA_DCOC_INIT_Q + DCOC TZA Init Q + 24 + 8 + read-write + + + + + DCOC_DIG_MAN + DCOC Digital Correction Manual Override + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + DIG_DCOC_INIT_I + DCOC DIG Init I + 0 + 12 + read-write + + + DIG_DCOC_INIT_Q + DCOC DIG Init Q + 16 + 12 + read-write + + + + + DCOC_CAL_GAIN + DCOC Calibration Gain + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + DCOC_BBA_CAL_GAIN1 + DCOC BBA Calibration Gain 1 + 8 + 4 + read-write + + + DCOC_LNA_CAL_GAIN1 + DCOC LNA Calibration Gain 1 + 12 + 4 + read-write + + + DCOC_BBA_CAL_GAIN2 + DCOC BBA Calibration Gain 2 + 16 + 4 + read-write + + + DCOC_LNA_CAL_GAIN2 + DCOC LNA Calibration Gain 2 + 20 + 4 + read-write + + + DCOC_BBA_CAL_GAIN3 + DCOC BBA Calibration Gain 3 + 24 + 4 + read-write + + + DCOC_LNA_CAL_GAIN3 + DCOC LNA Calibration Gain 3 + 28 + 4 + read-write + + + + + DCOC_STAT + DCOC Status + 0x38 + 32 + read-only + 0x80802020 + 0xFFFFFFFF + + + BBA_DCOC_I + DCOC BBA DAC I + 0 + 6 + read-only + + + DCOC_CAL_GTWSR + DCOC calibration Good Table Written Since Reset + 7 + 1 + read-only + + + 0 + A Passing calibration result has not occurred since the last radio reset. + #0 + + + 1 + A Passing calibration result has occurred since the last radio reset. + #1 + + + + + BBA_DCOC_Q + DCOC BBA DAC Q + 8 + 6 + read-only + + + DCOC_CAL_RESULT + DCOC_CAL_RESULT + 14 + 2 + read-only + + + 00 + Calibration checks failed. DCOC_OFFSET_n tables not updated. + #00 + + + 01 + Calibration checks neither passed nor failed, DCOC_OFFSET_n tables not updated. + #01 + + + 10 + Calibration checks neither passed nor failed, DCOC_OFFSET_n tables updated since no previous Pass condition has occurred since the last radio reset. + #10 + + + 11 + Calibration checks passed. DCOC_OFFSET_n tables updated + #11 + + + + + TZA_DCOC_I + DCOC TZA DAC I + 16 + 8 + read-only + + + TZA_DCOC_Q + DCOC TZA DAC Q + 24 + 8 + read-only + + + + + DCOC_DC_EST + DCOC DC Estimate + 0x3C + 32 + read-only + 0 + 0xFFFFFFFF + + + DC_EST_I + DCOC DC Estimate I + 0 + 12 + read-only + + + DC_EST_Q + DCOC DC Estimate Q + 16 + 12 + read-only + + + + + DCOC_CAL_RCP + DCOC Calibration Reciprocals + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + DCOC_TMP_CALC_RECIP + DCOC Calculation Reciprocal + 0 + 11 + read-write + + + ALPHA_CALC_RECIP + Alpha Calculation Reciprocal + 16 + 11 + read-write + + + + + DCOC_CTRL_2 + DCOC Control 2 + 0x44 + 32 + read-write + 0 + 0xFFFFFFFF + + + DCOC_CORR_DLY_ALT + DCOC Correction Delay Alternate + 16 + 5 + read-write + + + DCOC_CORR_HOLD_TIME_ALT + DCOC Correction Hold Time Alternate + 24 + 7 + read-write + + + 1111111 + The DC correction is not frozen. + #1111111 + + + + + + + IQMC_CTRL + IQMC Control + 0x48 + 32 + read-write + 0x4008000 + 0xFFFFFFFF + + + IQMC_CAL_EN + IQ Mismatch Cal Enable + 0 + 1 + read-write + + + IQMC_NUM_ITER + IQ Mismatch Cal Num Iter + 8 + 8 + read-write + + + IQMC_DC_GAIN_ADJ + IQ Mismatch Correction DC Gain Coeff + 16 + 11 + read-write + + + + + IQMC_CAL + IQMC Calibration + 0x4C + 32 + read-write + 0x400 + 0xFFFFFFFF + + + IQMC_GAIN_ADJ + IQ Mismatch Correction Gain Coeff + 0 + 11 + read-write + + + IQMC_PHASE_ADJ + IQ Mismatch Correction Phase Coeff + 16 + 12 + read-write + + + + + LNA_GAIN_VAL_3_0 + LNA_GAIN Step Values 3..0 + 0x50 + 32 + read-write + 0x3809321D + 0xFFFFFFFF + + + LNA_GAIN_VAL_0 + LNA_GAIN step 0 + 0 + 8 + read-write + + + LNA_GAIN_VAL_1 + LNA_GAIN step 1 + 8 + 8 + read-write + + + LNA_GAIN_VAL_2 + LNA_GAIN step 2 + 16 + 8 + read-write + + + LNA_GAIN_VAL_3 + LNA_GAIN step 3 + 24 + 8 + read-write + + + + + LNA_GAIN_VAL_7_4 + LNA_GAIN Step Values 7..4 + 0x54 + 32 + read-write + 0x8B745D4F + 0xFFFFFFFF + + + LNA_GAIN_VAL_4 + LNA_GAIN step 4 + 0 + 8 + read-write + + + LNA_GAIN_VAL_5 + LNA_GAIN step 5 + 8 + 8 + read-write + + + LNA_GAIN_VAL_6 + LNA_GAIN step 6 + 16 + 8 + read-write + + + LNA_GAIN_VAL_7 + LNA_GAIN step 7 + 24 + 8 + read-write + + + + + LNA_GAIN_VAL_9_8 + LNA_GAIN Step Values 9..8 + 0x58 + 32 + read-write + 0xB6A1 + 0xFFFFFFFF + + + LNA_GAIN_VAL_8 + LNA_GAIN step 8 + 0 + 8 + read-write + + + LNA_GAIN_VAL_9 + LNA_GAIN step 9 + 8 + 8 + read-write + + + + + BBA_RES_TUNE_VAL_7_0 + BBA Resistor Tune Values 7..0 + 0x5C + 32 + read-write + 0 + 0xFFFFFFFF + + + BBA_RES_TUNE_VAL_0 + BBA Resistor Tune Step 0 + 0 + 4 + read-write + + + BBA_RES_TUNE_VAL_1 + BBA Resistor Tune Step 1 + 4 + 4 + read-write + + + BBA_RES_TUNE_VAL_2 + BBA Resistor Tune Step 2 + 8 + 4 + read-write + + + BBA_RES_TUNE_VAL_3 + BBA Resistor Tune Step 3 + 12 + 4 + read-write + + + BBA_RES_TUNE_VAL_4 + BBA Resistor Tune Step 4 + 16 + 4 + read-write + + + BBA_RES_TUNE_VAL_5 + BBA Resistor Tune Step 5 + 20 + 4 + read-write + + + BBA_RES_TUNE_VAL_6 + BBA Resistor Tune Step 6 + 24 + 4 + read-write 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+ DCOC_TZA_OFFSET_I + DCOC TZA I-channel offset + 16 + 8 + read-write + + + DCOC_TZA_OFFSET_Q + DCOC TZA Q-channel offset + 24 + 8 + read-write + + + + + DCOC_BBA_STEP + DCOC BBA DAC Step + 0x10C + 32 + read-write + 0 + 0xFFFFFFFF + + + BBA_DCOC_STEP_RECIP + DCOC BBA Reciprocal of Step Size + 0 + 13 + read-write + + + BBA_DCOC_STEP + DCOC BBA Step Size + 16 + 9 + read-write + + + + + DCOC_TZA_STEP_0 + DCOC TZA DAC Step 0 + 0x110 + 32 + read-write + 0 + 0xFFFFFFFF + + + DCOC_TZA_STEP_RCP_0 + DCOC_TZA_STEP_RCP_0 + 0 + 13 + read-write + + + DCOC_TZA_STEP_GAIN_0 + DCOC_TZA_STEP_GAIN_0 + 16 + 12 + read-write + + + + + DCOC_TZA_STEP_1 + DCOC TZA DAC Step 1 + 0x114 + 32 + read-write + 0 + 0xFFFFFFFF + + + DCOC_TZA_STEP_RCP_1 + DCOC_TZA_STEP_RCP_1 + 0 + 13 + read-write + + + DCOC_TZA_STEP_GAIN_1 + DCOC_TZA_STEP_GAIN_1 + 16 + 12 + read-write + + + + + DCOC_TZA_STEP_2 + DCOC TZA DAC Step 2 + 0x118 + 32 + read-write + 0 + 0xFFFFFFFF + + + DCOC_TZA_STEP_RCP_2 + DCOC_TZA_STEP_RCP_2 + 0 + 13 + read-write + + + DCOC_TZA_STEP_GAIN_2 + DCOC_TZA_STEP_GAIN_2 + 16 + 12 + read-write + + + + + DCOC_TZA_STEP_3 + DCOC TZA DAC Step 3 + 0x11C + 32 + read-write + 0 + 0xFFFFFFFF + + + DCOC_TZA_STEP_RCP_3 + DCOC_TZA_STEP_RCP_3 + 0 + 13 + read-write + + + DCOC_TZA_STEP_GAIN_3 + DCOC_TZA_STEP_GAIN_3 + 16 + 12 + read-write + + + + + DCOC_TZA_STEP_4 + DCOC TZA DAC Step 4 + 0x120 + 32 + read-write + 0 + 0xFFFFFFFF + + + DCOC_TZA_STEP_RCP_4 + DCOC_TZA_STEP_RCP_4 + 0 + 13 + read-write + + + DCOC_TZA_STEP_GAIN_4 + DCOC_TZA_STEP_GAIN_4 + 16 + 12 + read-write + + + + + DCOC_TZA_STEP_5 + DCOC TZA DAC Step 5 + 0x124 + 32 + read-write + 0 + 0xFFFFFFFF + + + DCOC_TZA_STEP_RCP_5 + DCOC_TZA_STEP_RCP_5 + 0 + 13 + read-write + + + DCOC_TZA_STEP_GAIN_5 + DCOC_TZA_STEP_GAIN_5 + 16 + 12 + read-write + + + + + DCOC_TZA_STEP_6 + DCOC TZA DAC Step 6 + 0x128 + 32 + read-write + 0 + 0xFFFFFFFF + + + DCOC_TZA_STEP_RCP_6 + DCOC_TZA_STEP_RCP_6 + 0 + 13 + read-write + + + DCOC_TZA_STEP_GAIN_6 + DCOC_TZA_STEP_GAIN_6 + 16 + 12 + read-write + + + + + DCOC_TZA_STEP_7 + DCOC TZA DAC Step 7 + 0x12C + 32 + read-write + 0 + 0xFFFFFFFF + + + DCOC_TZA_STEP_RCP_7 + DCOC_TZA_STEP_RCP_7 + 0 + 13 + read-write + + + DCOC_TZA_STEP_GAIN_7 + DCOC_TZA_STEP_GAIN_7 + 16 + 13 + read-write + + + + + DCOC_TZA_STEP_8 + DCOC TZA DAC Step 5 + 0x130 + 32 + read-write + 0 + 0xFFFFFFFF + + + DCOC_TZA_STEP_RCP_8 + DCOC_TZA_STEP_RCP_8 + 0 + 13 + read-write + + + DCOC_TZA_STEP_GAIN_8 + DCOC_TZA_STEP_GAIN_8 + 16 + 13 + read-write + + + + + DCOC_TZA_STEP_9 + DCOC TZA DAC Step 9 + 0x134 + 32 + read-write + 0 + 0xFFFFFFFF + + + DCOC_TZA_STEP_RCP_9 + DCOC_TZA_STEP_RCP_9 + 0 + 13 + read-write + + + DCOC_TZA_STEP_GAIN_9 + DCOC_TZA_STEP_GAIN_9 + 16 + 14 + read-write + + + + + DCOC_TZA_STEP_10 + DCOC TZA DAC Step 10 + 0x138 + 32 + read-write + 0 + 0xFFFFFFFF + + + DCOC_TZA_STEP_RCP_10 + DCOC_TZA_STEP_RCP_10 + 0 + 13 + read-write + + + DCOC_TZA_STEP_GAIN_10 + DCOC_TZA_STEP_GAIN_10 + 16 + 14 + read-write + + + + + FRAC_CORR_OVRD + FRAC CORR Override + 0x140 + 32 + read-write + 0 + 0xFFFFFFFF + + + FRAC_CORR_OVRD_EN + FRAC CORR Override Enable + 0 + 1 + read-write + + + FRAC_CORR_OVRD + FRAC CORR Override Value + 4 + 3 + read-write + + + + + CFO_EST_OVRD + CFO Estimate Override + 0x144 + 32 + read-write + 0 + 0xFFFFFFFF + + + CFO_EST_OVRD_EN + CFO Estimate Override Enable + 0 + 1 + read-write + + + CFO_EST_OVRD + CFO Estimate Override Value + 4 + 10 + read-write + + + + + RX_D_CHF_COEF_0 + Receive Demod Channel Filter Coef 0 + 0x148 + 32 + read-write + 0 + 0xFFFFFFFF + + + RX_D_CH_FILT_H0 + RX Demod Channel Filter Coefficient 0 + 0 + 9 + read-write + + + + + RX_D_CHF_COEF_1 + Receive Demod Channel Filter Coef 1 + 0x14C + 32 + read-write + 0 + 0xFFFFFFFF + + + RX_D_CH_FILT_H1 + RX Demod Channel Filter Coefficient 1 + 0 + 9 + read-write + + + + + RX_D_CHF_COEF_2 + Receive Demod Channel Filter Coef 2 + 0x150 + 32 + read-write + 0 + 0xFFFFFFFF + + + RX_D_CH_FILT_H2 + RX Demod Channel Filter Coefficient 2 + 0 + 10 + read-write + + + + + RX_D_CHF_COEF_3 + Receive Demod Channel Filter Coef 3 + 0x154 + 32 + read-write + 0 + 0xFFFFFFFF + + + RX_D_CH_FILT_H3 + RX Demod Channel Filter Coefficient 3 + 0 + 10 + read-write + + + + + RX_D_CHF_COEF_4 + Receive Demod Channel Filter Coef 4 + 0x158 + 32 + read-write + 0 + 0xFFFFFFFF + + + RX_D_CH_FILT_H4 + RX Demod Channel Filter Coefficient 4 + 0 + 10 + read-write + + + + + DCOC_CAL_FAIL_TH + DCOC Calibration Fail Thresholds + 0x160 + 32 + read-write + 0 + 0xFFFFFFFF + + + DCOC_CAL_BETA_F_TH + DCOC Calibration Beta Fail Threshold + 0 + 11 + read-write + + + DCOC_CAL_ALPHA_F_TH + DCOC Calibration Alpha Fail Threshold + 16 + 10 + read-write + + + + + DCOC_CAL_PASS_TH + DCOC Calibration Pass Thresholds + 0x164 + 32 + read-write + 0 + 0xFFFFFFFF + + + DCOC_CAL_BETA_P_TH + DCOC Calibration Beta Pass Threshold + 0 + 11 + read-write + + + DCOC_CAL_ALPHA_P_TH + DCOC Calibration Alpha Pass Threshold + 16 + 10 + read-write + + + + + DCOC_CAL_ALPHA + DCOC Calibration Alpha + 0x168 + 32 + read-only + 0 + 0xFFFFFFFF + + + DCOC_CAL_ALPHA_I + DCOC Calibration I-channel ALPHA constant + 0 + 11 + read-only + + + DCOC_CAL_ALPHA_Q + DCOC_CAL_ALPHA_Q + 16 + 11 + read-only + + + + + DCOC_CAL_BETA_Q + DCOC Calibration Beta Q + 0x16C + 32 + read-only + 0 + 0xFFFFFFFF + + + DCOC_CAL_BETA_Q + DCOC_CAL_BETA_Q + 0 + 17 + read-only + + + + + DCOC_CAL_BETA_I + DCOC Calibration Beta I + 0x170 + 32 + read-only + 0 + 0xFFFFFFFF + + + DCOC_CAL_BETA_I + DCOC_CAL_BETA_I + 0 + 17 + read-only + + + + + DCOC_CAL_GAMMA + DCOC Calibration Gamma + 0x174 + 32 + read-only + 0 + 0xFFFFFFFF + + + DCOC_CAL_GAMMA_I + DCOC_CAL_GAMMA_I + 0 + 16 + read-only + + + DCOC_CAL_GAMMA_Q + DCOC_CAL_GAMMA_Q + 16 + 16 + read-only + + + + + DCOC_CAL_IIR + DCOC Calibration IIR + 0x178 + 32 + read-write + 0 + 0xFFFFFFFF + + + DCOC_CAL_IIR1A_IDX + DCOC Calibration IIR 1A Index + 0 + 2 + read-write + + + 00 + 1/1 + #00 + + + 01 + 1/4 + #01 + + + 10 + 1/8 + #10 + + + 11 + 1/16 + #11 + + + + + DCOC_CAL_IIR2A_IDX + DCOC Calibration IIR 2A Index + 2 + 2 + read-write + + + 00 + 1/1 + #00 + + + 01 + 1/4 + #01 + + + 10 + 1/8 + #10 + + + 11 + 1/16 + #11 + + + + + DCOC_CAL_IIR3A_IDX + DCOC Calibration IIR 3A Index + 4 + 2 + read-write + + + 00 + 1/4 + #00 + + + 01 + 1/8 + #01 + + + 10 + 1/16 + #10 + + + 11 + 1/32 + #11 + + + + + + + DCOC_CAL1 + DCOC Calibration Result + 0x180 + 32 + read-only + 0 + 0xFFFFFFFF + + + DCOC_CAL_RES_I + DCOC Calibration Result - I Channel + 0 + 12 + read-only + + + DCOC_CAL_RES_Q + DCOC Calibration Result - Q Channel + 16 + 12 + read-only + + + + + DCOC_CAL2 + DCOC Calibration Result + 0x184 + 32 + read-only + 0 + 0xFFFFFFFF + + + DCOC_CAL_RES_I + DCOC Calibration Result - I Channel + 0 + 12 + read-only + + + DCOC_CAL_RES_Q + DCOC Calibration Result - Q Channel + 16 + 12 + read-only + + + + + DCOC_CAL3 + DCOC Calibration Result + 0x188 + 32 + read-only + 0 + 0xFFFFFFFF + + + DCOC_CAL_RES_I + DCOC Calibration Result - I Channel + 0 + 12 + read-only + + + DCOC_CAL_RES_Q + DCOC Calibration Result - Q Channel + 16 + 12 + read-only + + + + + DC_RESID_CTRL2 + DC Residual Control2 + 0x18C + 32 + read-write + 0 + 0xFFFFFFFF + + + DC_RESID_NWIN2 + DC Residual NWIN, for Second Run + 0 + 9 + read-write + + + DC_RESID_PHY_STOP_EN + DC Residual PHY Stop Enable + 9 + 1 + read-write + + + DC_RESID_CC_EN + DC Residual Continuous Correction Enable + 10 + 1 + read-write + + + DC_RESID_SR2_EN + DC Residual Slewrate Enable, for Second Run + 11 + 1 + read-write + + + DC_RESID_ALPHA2 + DC Residual Alpha, for Second Run + 12 + 3 + read-write + + + 000 + Update factor is 1 + #000 + + + 001 + Update factor is 1/2 + #001 + + + 010 + Update factor is 1/4 + 1/8 + #010 + + + 011 + Update factor is 1/4 + #011 + + + 100 + Update factor is 1/8 + 16 + #100 + + + 101 + Update factor is 1/8 + #101 + + + 110 + Update factor is 1/16 + 1/32 + #110 + + + 111 + Update factor is 1/16 + #111 + + + + + DC_RESID_GS2_EN + DC Residual Gearshift Enable, for Second Run + 15 + 1 + read-write + + + 0 + Gearshifting disabled for Second Run + #0 + + + 1 + Gearshifting enabled for Second Run + #1 + + + + + DC_RESID_ITER_FREEZE2 + DC Residual Iteration Freeze, for Second Run + 16 + 5 + read-write + + + DC_RESID_SLEWRATE2 + DC Residual Slewrate, for Second Run + 21 + 3 + read-write + + + DC_RESID_MIN_AGC_IDX2 + DC Residual Minimum AGC Table Index, for Second Run + 24 + 5 + read-write + + + DC_RESID_GEARSHIFT2 + DC Residual Gearshift, for Second Run + 29 + 3 + read-write + + + + + CCA_ED_LQI_CTRL_0 + RX_DIG CCA ED LQI Control Register 0 + 0x190 + 32 + read-write + 0 + 0xFFFFFFFF + + + LQI_CORR_THRESH + LQI Correlation Threshold + 0 + 8 + read-write + + + CORR_CNTR_THRESH + Correlation Count Threshold + 8 + 8 + read-write + + + LQI_CNTR + LQI Counter + 16 + 8 + read-write + + + SNR_ADJ + SNR calculation adjustment + 24 + 6 + read-write + + + + + CCA_ED_LQI_CTRL_1 + RX_DIG CCA ED LQI Control Register 1 + 0x194 + 32 + read-write + 0 + 0xFFFFFFFF + + + RSSI_NOISE_AVG_DELAY + RSSI Noise Averaging Delay + 0 + 6 + read-write + + + RSSI_NOISE_AVG_FACTOR + RSSI Noise Averaging Factor + 6 + 3 + read-write + + + 000 + 1 + #000 + + + 001 + 64 + #001 + + + 010 + 70 + #010 + + + 011 + 128 + #011 + + + 100 + 139 + #100 + + + 101 + 256 + #101 + + + 110 + 277 + #110 + + + 111 + 512 + #111 + + + + + LQI_RSSI_WEIGHT + LQI RSSI Weight + 9 + 3 + read-write + + + 000 + 2.0 + #000 + + + 001 + 2.125 + #001 + + + 010 + 2.25 + #010 + + + 011 + 2.375 + #011 + + + 100 + 2.5 + #100 + + + 101 + 2.625 + #101 + + + 110 + 2.75 + #110 + + + 111 + 2.875 + #111 + + + + + LQI_RSSI_SENS + LQI RSSI Sensitivity + 12 + 4 + read-write + + + SNR_LQI_DIS + SNR LQI Disable + 16 + 1 + read-write + + + 0 + Normal operation. + #0 + + + 1 + The RX_DIG CCA/ED/LQI block ignores the AA match input which starts an LQI measurement. + #1 + + + + + SEL_SNR_MODE + Select SNR Mode + 17 + 1 + read-write + + + 0 + SNR estimate + #0 + + + 1 + Mapped correlation magnitude + #1 + + + + + MEAS_TRANS_TO_IDLE + Measurement Transition to IDLE + 18 + 1 + read-write + + + 0 + Module transitions to RSSI state + #0 + + + 1 + Module transitions to IDLE state + #1 + + + + + CCA1_ED_EN_DIS + CCA1_ED_EN Disable + 19 + 1 + read-write + + + 0 + Normal operation + #0 + + + 1 + CCA1_ED_EN input is disabled + #1 + + + + + MAN_MEAS_COMPLETE + Manual measurement complete + 20 + 1 + read-write + + + 0 + Normal operation + #0 + + + 1 + Manually asserts the measurement complete signal for the RX_DIG CCA/ED/LQI blocks. Intended to be used only for debug. + #1 + + + + + NB_WB_OVRD + Narrowband Wideband Override + 21 + 1 + read-write + + + 0 + RSSI forced to be in Wideband mode if NB_WB_OVRD_EN is set + #0 + + + 1 + RSSI forced to be in Narrowband mode if NB_WB_OVRD_EN is set + #1 + + + + + NB_WB_OVRD_EN + Narrowband Wideband Override Enable + 22 + 1 + read-write + + + 0 + Normal operation + #0 + + + 1 + RSSI narrowband/wideband selection is via NB_WB_OVRD + #1 + + + + + CORR_FLAG_SEL + CORR_FLAG_SEL + 23 + 1 + read-write + + + 0 + Internal (RXDIG-generated correlation flag) + #0 + + + 1 + External (PHY-generated correlation flag) + #1 + + + + + SNR_LQI_WEIGHT + SNR LQI Weight + 24 + 4 + read-write + + + 0000 + 0.0 + #0000 + + + 0001 + 1.0 + #0001 + + + 0010 + 1.125 + #0010 + + + 0011 + 1.25 + #0011 + + + 0100 + 1.375 + #0100 + + + 0101 + 1.5 + #0101 + + + 0110 + 1.625 + #0110 + + + 0111 + 1.75 + #0111 + + + 1000 + 1.875 + #1000 + + + 1001 + 2.0 + #1001 + + + 1010 + 2.125 + #1010 + + + 1011 + 2.25 + #1011 + + + 1100 + 2.375 + #1100 + + + 1101 + 2.5 + #1101 + + + 1110 + 2.625 + #1110 + + + 1111 + 2.75 + #1111 + + + + + LQI_BIAS + LQI Bias. + 28 + 4 + read-write + + + + + CCA_ED_LQI_STAT_0 + RX_DIG CCA ED LQI Status Register 0 + 0x198 + 32 + read-only + 0 + 0xFFFFFFFF + + + LQI_OUT + LQI output + 0 + 8 + read-only + + + ED_OUT + ED output + 8 + 8 + read-only + + + SNR_OUT + SNR output + 16 + 8 + read-only + + + CCA1_STATE + CCA1 State + 24 + 1 + read-only + + + MEAS_COMPLETE + Measurement Complete + 25 + 1 + read-only + + + + + RX_CHF_COEF_0 + Receive Channel Filter Coefficient 0 + 0x1A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + RX_CH_FILT_H0 + RX Channel Filter Coefficient 0 + 0 + 6 + read-write + + + + + RX_CHF_COEF_1 + Receive Channel Filter Coefficient 1 + 0x1A4 + 32 + read-write + 0 + 0xFFFFFFFF + + + RX_CH_FILT_H1 + RX Channel Filter Coefficient 1 + 0 + 6 + read-write + + + + + RX_CHF_COEF_2 + Receive Channel Filter Coefficient 2 + 0x1A8 + 32 + read-write + 0 + 0xFFFFFFFF + + + RX_CH_FILT_H2 + RX Channel Filter Coefficient 2 + 0 + 7 + read-write + + + + + RX_CHF_COEF_3 + Receive Channel Filter Coefficient 3 + 0x1AC + 32 + read-write + 0 + 0xFFFFFFFF + + + RX_CH_FILT_H3 + RX Channel Filter Coefficient 3 + 0 + 7 + read-write + + + + + RX_CHF_COEF_4 + Receive Channel Filter Coefficient 4 + 0x1B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + RX_CH_FILT_H4 + RX Channel Filter Coefficient 4 + 0 + 7 + read-write + + + + + RX_CHF_COEF_5 + Receive Channel Filter Coefficient 5 + 0x1B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + RX_CH_FILT_H5 + RX Channel Filter Coefficient 5 + 0 + 7 + read-write + + + + + RX_CHF_COEF_6 + Receive Channel Filter Coefficient 6 + 0x1B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + RX_CH_FILT_H6 + RX Channel Filter Coefficient 6 + 0 + 8 + read-write + + + + + RX_CHF_COEF_7 + Receive Channel Filter Coefficient 7 + 0x1BC + 32 + read-write + 0 + 0xFFFFFFFF + + + RX_CH_FILT_H7 + RX Channel Filter Coefficient 7 + 0 + 8 + read-write + + + + + RX_CHF_COEF_8 + Receive Channel Filter Coefficient 8 + 0x1C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + RX_CH_FILT_H8 + RX Channel Filter Coefficient 8 + 0 + 9 + read-write + + + + + RX_CHF_COEF_9 + Receive Channel Filter Coefficient 9 + 0x1C4 + 32 + read-write + 0 + 0xFFFFFFFF + + + RX_CH_FILT_H9 + RX Channel Filter Coefficient 9 + 0 + 9 + read-write + + + + + RX_CHF_COEF_10 + Receive Channel Filter Coefficient 10 + 0x1C8 + 32 + read-write + 0 + 0xFFFFFFFF + + + RX_CH_FILT_H10 + RX Channel Filter Coefficient 10 + 0 + 10 + read-write + + + + + RX_CHF_COEF_11 + Receive Channel Filter Coefficient 11 + 0x1CC + 32 + read-write + 0 + 0xFFFFFFFF + + + RX_CH_FILT_H11 + RX Channel Filter Coefficient 11 + 0 + 10 + read-write + + + + + AGC_MAN_AGC_IDX + AGC Manual AGC Index + 0x1D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + AGC_IDX_CMP_PHY + AGC Index Compare threshold for PHY + 0 + 5 + read-write + + + AGC_MAN_IDX + AGC Manual Index + 16 + 5 + read-write + + + AGC_MAN_IDX_EN + AGC Manual Index Enable + 24 + 1 + read-write + + + AGC_DCOC_START_PT + AGC DCOC Start Point + 25 + 1 + read-write + + + + + DC_RESID_CTRL + DC Residual Control + 0x1D4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DC_RESID_NWIN + DC Residual NWIN + 0 + 7 + read-write + + + DC_RESID_ITER_FREEZE + DC Residual Iteration Freeze + 8 + 4 + read-write + + + DC_RESID_ALPHA + DC Residual Alpha + 12 + 3 + read-write + + + 000 + Update factor is 1 + #000 + + + 001 + Update factor is 1/2 + #001 + + + 010 + Update factor is 1/4 + 1/8 + #010 + + + 011 + Update factor is 1/4 + #011 + + + 100 + Update factor is 1/8 + 16 + #100 + + + 101 + Update factor is 1/8 + #101 + + + 110 + Update factor is 1/16 + 1/32 + #110 + + + 111 + Update factor is 1/16 + #111 + + + + + DC_RESID_GS_EN + DC Residual Gearshift Enable + 15 + 1 + read-write + + + 0 + Gearshifting disabled + #0 + + + 1 + Gearshifting enabled + #1 + + + + + DC_RESID_DLY + DC Residual Delay + 16 + 3 + read-write + + + DC_RESID_SECOND_RUN_EN + DC Residual Second Run Enable + 19 + 1 + read-write + + + 0 + Second Run disabled + #0 + + + 1 + Second Run enabled + #1 + + + + + DC_RESID_EXT_DC_EN + DC Residual External DC Enable + 20 + 1 + read-write + + + DC_RESID_MIN_AGC_IDX + DC Residual Minimum AGC Table Index + 24 + 5 + read-write + + + DC_RESID_GEARSHIFT + DC Residual Gearshift + 29 + 3 + read-write + + + + + DC_RESID_EST + DC Residual Estimate + 0x1D8 + 32 + read-only + 0 + 0xFFFFFFFF + + + DC_RESID_OFFSET_I + DC Residual Offset I + 0 + 13 + read-only + + + DC_RESID_OFFSET_Q + DC Residual Offset Q + 16 + 13 + read-only + + + + + RX_RCCAL_CTRL0 + RX RC Calibration Control0 + 0x1DC + 32 + read-write + 0 + 0xFFFFFFFF + + + BBA_RCCAL_OFFSET + BBA RC Calibration value offset + 0 + 4 + read-write + + + BBA_RCCAL_MANUAL + BBA RC Calibration manual value + 4 + 5 + read-write + + + BBA_RCCAL_DIS + BBA RC Calibration Disable + 9 + 1 + read-write + + + 0 + BBA RC Calibration is enabled + #0 + + + 1 + BBA RC Calibration is disabled + #1 + + + + + RCCAL_SMP_DLY + RC Calibration Sample Delay + 12 + 2 + read-write + + + 00 + The comp_out signal is sampled 0 clk cycle after sample signal is deasserted + #00 + + + 01 + The comp_out signal is sampled 1 clk cycle after sample signal is deasserted + #01 + + + 10 + The comp_out signal is sampled 2 clk cycle after sample signal is deasserted + #10 + + + 11 + The comp_out signal is sampled 3 clk cycle after sample signal is deasserted + #11 + + + + + RCCAL_COMP_INV + RC Calibration comp_out Invert + 15 + 1 + read-write + + + 0 + The comp_out signal polarity is NOT inverted + #0 + + + 1 + The comp_out signal polarity is inverted + #1 + + + + + TZA_RCCAL_OFFSET + TZA RC Calibration value offset + 16 + 4 + read-write + + + TZA_RCCAL_MANUAL + TZA RC Calibration manual value + 20 + 5 + read-write + + + TZA_RCCAL_DIS + TZA RC Calibration Disable + 25 + 1 + read-write + + + 0 + TZA RC Calibration is enabled + #0 + + + 1 + TZA RC Calibration is disabled + #1 + + + + + + + RX_RCCAL_CTRL1 + RX RC Calibration Control1 + 0x1E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADC_RCCAL_OFFSET + ADC RC Calibration value offset + 0 + 4 + read-write + + + ADC_RCCAL_MANUAL + ADC RC Calibration manual value + 4 + 5 + read-write + + + ADC_RCCAL_DIS + ADC RC Calibration Disable + 9 + 1 + read-write + + + 0 + ADC RC Calibration is enabled + #0 + + + 1 + ADC RC Calibration is disabled + #1 + + + + + BBA2_RCCAL_OFFSET + BBA2 RC Calibration value offset + 16 + 4 + read-write + + + BBA2_RCCAL_MANUAL + BBA2 RC Calibration manual value + 20 + 5 + read-write + + + BBA2_RCCAL_DIS + BBA2 RC Calibration Disable + 25 + 1 + read-write + + + 0 + BBA2 RC Calibration is enabled + #0 + + + 1 + BBA2 RC Calibration is disabled + #1 + + + + + + + RX_RCCAL_STAT + RX RC Calibration Status + 0x1E4 + 32 + read-only + 0x2104210 + 0xFFFFFFFF + + + RCCAL_CODE + RC Calibration code + 0 + 5 + read-only + + + ADC_RCCAL + ADC RC Calibration + 5 + 5 + read-only + + + BBA2_RCCAL + BBA2 RC Calibration + 10 + 5 + read-only + + + BBA_RCCAL + BBA RC Calibration + 16 + 5 + read-only + + + TZA_RCCAL + TZA RC Calibration + 21 + 5 + read-only + + + + + AUXPLL_FCAL_CTRL + Aux PLL Frequency Calibration Control + 0x1E8 + 32 + read-write + 0x400000 + 0xFFFFFFFF + + + DAC_CAL_ADJUST_MANUAL + Aux PLL Frequency DAC Calibration Adjust Manual value + 0 + 7 + read-write + + + AUXPLL_DAC_CAL_ADJUST_DIS + Aux PLL Frequency Calibration Disable + 7 + 1 + read-write + + + 0 + Calibration is enabled + #0 + + + 1 + Calibration is disabled + #1 + + + + + FCAL_RUN_CNT + Aux PLL Frequency Calibration Run Count + 8 + 1 + read-write + + + 0 + Run count is 256 clock cycles + #0 + + + 1 + Run count is 512 clock cycles + #1 + + + + + FCAL_COMP_INV + Aux PLL Frequency Calibration Comparison Invert + 9 + 1 + read-write + + + 0 + (Default) The comparison associated with the count is not inverted. + #0 + + + 1 + The comparison associated with the count is inverted + #1 + + + + + FCAL_SMP_DLY + Aux PLL Frequency Calibration Sample Delay + 10 + 2 + read-write + + + 00 + The count signal is sampled 1 clk cycle after fcal_run signal is deasserted + #00 + + + 01 + The count signal is sampled 2 clk cycle after fcal_run signal is deasserted + #01 + + + 10 + The count signal is sampled 3 clk cycle after fcal_run signal is deasserted + #10 + + + 11 + The count signal is sampled 4 clk cycle after fcal_run signal is deasserted + #11 + + + + + DAC_CAL_ADJUST + Aux PLL DAC Calibration Adjust value + 16 + 7 + read-only + + + + + AUXPLL_FCAL_CNT6 + Aux PLL Frequency Calibration Count 6 + 0x1EC + 32 + read-only + 0 + 0xFFFFFFFF + + + FCAL_COUNT_6 + Aux PLL Frequency Calibration Count 6 + 0 + 10 + read-only + + + FCAL_BESTDIFF + Aux PLL Frequency Calibration Best Difference + 16 + 10 + read-only + + + + + AUXPLL_FCAL_CNT5_4 + Aux PLL Frequency Calibration Count 5 and 4 + 0x1F0 + 32 + read-only + 0 + 0xFFFFFFFF + + + FCAL_COUNT_4 + Aux PLL Frequency Calibration Count 4 + 0 + 10 + read-only + + + FCAL_COUNT_5 + Aux PLL Frequency Calibration Count 5 + 16 + 10 + read-only + + + + + AUXPLL_FCAL_CNT3_2 + Aux PLL Frequency Calibration Count 3 and 2 + 0x1F4 + 32 + read-only + 0 + 0xFFFFFFFF + + + FCAL_COUNT_2 + Aux PLL Frequency Calibration Count 2 + 0 + 10 + read-only + + + FCAL_COUNT_3 + Aux PLL Frequency Calibration Count 3 + 16 + 10 + read-only + + + + + AUXPLL_FCAL_CNT1_0 + Aux PLL Frequency Calibration Count 1 and 0 + 0x1F8 + 32 + read-only + 0 + 0xFFFFFFFF + + + FCAL_COUNT_0 + Frequency Calibration Count 0 + 0 + 10 + read-only + + + FCAL_COUNT_1 + Frequency Calibration Count 1 + 16 + 10 + read-only + + + + + RXDIG_DFT + RXDIG DFT + 0x1FC + 32 + read-write + 0x8500 + 0xFFFFFFFF + + + IQ_MUX_SEL + DMA DTEST IQ Mux Select + 8 + 4 + read-write + + + 0000 + Decimation filter I/Q output + #0000 + + + 0001 + IQMC I/Q output + #0001 + + + 0010 + DCOC I/Q output + #0010 + + + 0011 + Channel filter I/Q output + #0011 + + + 0100 + SRC I/Q output + #0100 + + + 0101 + DC Residual I/Q output + #0101 + + + 0110 + Sample Buffer I/Q output + #0110 + + + 0111 + CFO Mixer I/Q output + #0111 + + + 1000 + Demod Channel filter I/Q output + #1000 + + + 1001 + Frac Corr I/Q output + #1001 + + + 1010 + DC Residual I/Q Correction (12 LSBs, includes 1 fractional bit) + #1010 + + + + + PH_MUX_SEL + DMA DTEST Phase Mux Select + 12 + 2 + read-write + + + 00 + Wideband Phase + #00 + + + 01 + Narrowband Phase + #01 + + + 10 + Hi Resolution Phase + #10 + + + + + HI_RES_PH_EN + Hi Resolution Phase Enable + 14 + 1 + read-write + + + SRC_OUT_VLD_DLY_EN + SRC Out Valid Delay Enable + 15 + 1 + read-write + + + + + RX_DIG_CTRL_DRS + RX Digital Control DataRate1 + 0x200 + 32 + read-write + 0 + 0xFFFFFFFF + + + RX_DEC_FILT_OSR + Decimation Filter Oversampling + 4 + 4 + read-write + + + 0000 + OSR 4 + #0000 + + + 0001 + OSR 8 + #0001 + + + 0010 + OSR 16 + #0010 + + + 0100 + OSR 32 + #0100 + + + 1000 + OSR 64 + #1000 + + + 0011 + OSR 6 + #0011 + + + 0101 + OSR 12 + #0101 + + + 0110 + OSR 24 + #0110 + + + 0111 + OSR 48 + #0111 + + + + + + + AGC_CTRL_0_DRS + AGC Control 0 DataRate1 + 0x204 + 32 + read-write + 0 + 0xFFFFFFFF + + + LNA_GAIN_SETTLE_TIME + LNA_GAIN_SETTLE_TIME + 0 + 8 + read-write + + + BBA_GAIN_SETTLE_TIME + BBA Gain Settle Time + 8 + 8 + read-write + + + AGC_UP_RSSI_THRESH + AGC UP RSSI Threshold + 16 + 8 + read-write + + + AGC_DOWN_RSSI_THRESH + AGC DOWN RSSI Threshold + 24 + 8 + read-write + + + + + AGC_CTRL_1_DRS + AGC Control 1 DataRate1 + 0x208 + 32 + read-write + 0 + 0xFFFFFFFF + + + AGC_UNFREEZE_TIME + AGC Unfreeze Time + 0 + 13 + read-write + + + AGC_FAST_EXPIRE + AGC Fast Expire + 16 + 6 + read-write + + + SLOW_AGC_SRC + Slow AGC Source Selection + 24 + 2 + read-write + + + 00 + Access Address match (for active protocol) + #00 + + + 01 + Preamble Detect (for active protocol) + #01 + + + 10 + Fast AGC expire timer + #10 + + + + + AGC_UP_SRC + AGC Up Source + 26 + 1 + read-write + + + 0 + PDET LO + #0 + + + 1 + RSSI + #1 + + + + + + + AGC_CTRL_2_DRS + AGC Control 2 DataRate1 + 0x20C + 32 + read-write + 0x55 + 0xFFFFFFFF + + + TZA_PDET_SEL_HI + TZA PDET Threshold High + 0 + 3 + read-write + + + 000 + 0.600V + #000 + + + 001 + 0.645V + #001 + + + 010 + 0.705V + #010 + + + 011 + 0.750V + #011 + + + 100 + 0.795V + #100 + + + 101 + 0.855V + #101 + + + 110 + 0.900V + #110 + + + 111 + 0.945V + #111 + + + + + BBA_PDET_SEL_HI + BBA PDET Threshold High + 4 + 3 + read-write + + + 000 + 0.600V + #000 + + + 001 + 0.795V + #001 + + + 010 + 0.900V + #010 + + + 011 + 0.945V + #011 + + + 100 + 1.005V + #100 + + + 101 + 1.050V + #101 + + + 110 + 1.095V + #110 + + + 111 + 1.155V + #111 + + + + + + + DCOC_CTRL_DRS + DCOC Control DataRate1 + 0x210 + 32 + read-write + 0 + 0xFFFFFFFF + + + DCOC_CORR_DLY + DCOC Correction Delay + 0 + 5 + read-write + + + DCOC_CORR_DLY_ALT + DCOC Correction Delay Alternate + 8 + 5 + read-write + + + DCOC_ALPHA_RADIUS_IDX + Alpha-R Scaling + 16 + 3 + read-write + + + 000 + 1 + #000 + + + 001 + 1/2 + #001 + + + 010 + 1/4 + #010 + + + 011 + 1/8 + #011 + + + 100 + 1/16 + #100 + + + 101 + 1/32 + #101 + + + 110 + 1/64 + #110 + + + + + + + DC_RESID_CTRL_DRS + DC Residual Control DataRate1 + 0x214 + 32 + read-write + 0 + 0xFFFFFFFF + + + DC_RESID_NWIN + DC Residual NWIN + 0 + 7 + read-write + + + DC_RESID_DLY + DC Residual Delay + 16 + 3 + read-write + + + DC_RESID_NWIN2 + DC Residual NWIN, for Second Run + 20 + 9 + read-write + + + + + RX_CHF_COEF_0_DRS + Receive Channel Filter Coefficient 0 DataRate1 + 0x220 + 32 + read-write + 0 + 0xFFFFFFFF + + + RX_CH_FILT_H0 + RX Channel Filter Coefficient 0 + 0 + 6 + read-write + + + + + RX_CHF_COEF_1_DRS + Receive Channel Filter Coefficient 1 DataRate1 + 0x224 + 32 + read-write + 0 + 0xFFFFFFFF + + + RX_CH_FILT_H1 + RX Channel Filter Coefficient 1 + 0 + 6 + read-write + + + + + RX_CHF_COEF_2_DRS + Receive Channel Filter Coefficient 2 DataRate1 + 0x228 + 32 + read-write + 0 + 0xFFFFFFFF + + + RX_CH_FILT_H2 + RX Channel Filter Coefficient 2 + 0 + 7 + read-write + + + + + RX_CHF_COEF_3_DRS + Receive Channel Filter Coefficient 3 DataRate1 + 0x22C + 32 + read-write + 0 + 0xFFFFFFFF + + + RX_CH_FILT_H3 + RX Channel Filter Coefficient 3 + 0 + 7 + read-write + + + + + RX_CHF_COEF_4_DRS + Receive Channel Filter Coefficient 4 DataRate1 + 0x230 + 32 + read-write + 0 + 0xFFFFFFFF + + + RX_CH_FILT_H4 + RX Channel Filter Coefficient 4 + 0 + 7 + read-write + + + + + RX_CHF_COEF_5_DRS + Receive Channel Filter Coefficient 5 DataRate1 + 0x234 + 32 + read-write + 0 + 0xFFFFFFFF + + + RX_CH_FILT_H5 + RX Channel Filter Coefficient 5 + 0 + 7 + read-write + + + + + RX_CHF_COEF_6_DRS + Receive Channel Filter Coefficient 6 DataRate1 + 0x238 + 32 + read-write + 0 + 0xFFFFFFFF + + + RX_CH_FILT_H6 + RX Channel Filter Coefficient 6 + 0 + 8 + read-write + + + + + RX_CHF_COEF_7_DRS + Receive Channel Filter Coefficient 7 DataRate1 + 0x23C + 32 + read-write + 0 + 0xFFFFFFFF + + + RX_CH_FILT_H7 + RX Channel Filter Coefficient 7 + 0 + 8 + read-write + + + + + RX_CHF_COEF_8_DRS + Receive Channel Filter Coefficient 8 DataRate1 + 0x240 + 32 + read-write + 0 + 0xFFFFFFFF + + + RX_CH_FILT_H8 + RX Channel Filter Coefficient 8 + 0 + 9 + read-write + + + + + RX_CHF_COEF_9_DRS + Receive Channel Filter Coefficient 9 DataRate1 + 0x244 + 32 + read-write + 0 + 0xFFFFFFFF + + + RX_CH_FILT_H9 + RX Channel Filter Coefficient 9 + 0 + 9 + read-write + + + + + RX_CHF_COEF_10_DRS + Receive Channel Filter Coefficient 10 DataRate1 + 0x248 + 32 + read-write + 0 + 0xFFFFFFFF + + + RX_CH_FILT_H10 + RX Channel Filter Coefficient 10 + 0 + 10 + read-write + + + + + RX_CHF_COEF_11_DRS + Receive Channel Filter Coefficient 11 DataRate1 + 0x24C + 32 + read-write + 0 + 0xFFFFFFFF + + + RX_CH_FILT_H11 + RX Channel Filter Coefficient 11 + 0 + 10 + read-write + + + + + RX_D_CHF_COEF_0_DRS + Receive Demod Channel Filter Coef 0 + 0x250 + 32 + read-write + 0 + 0xFFFFFFFF + + + RX_D_CH_FILT_H0 + RX Demod Channel Filter Coefficient 0 + 0 + 9 + read-write + + + + + RX_D_CHF_COEF_1_DRS + Receive Demod Channel Filter Coef 1 DataRate1 + 0x254 + 32 + read-write + 0 + 0xFFFFFFFF + + + RX_D_CH_FILT_H1 + RX Demod Channel Filter Coefficient 1 + 0 + 9 + read-write + + + + + RX_D_CHF_COEF_2_DRS + Receive Demod Channel Filter Coef 2 DataRate1 + 0x258 + 32 + read-write + 0 + 0xFFFFFFFF + + + RX_D_CH_FILT_H2 + RX Demod Channel Filter Coefficient 2 + 0 + 10 + read-write + + + + + RX_D_CHF_COEF_3_DRS + Receive Demod Channel Filter Coef 3 DataRate1 + 0x25C + 32 + read-write + 0 + 0xFFFFFFFF + + + RX_D_CH_FILT_H3 + RX Demod Channel Filter Coefficient 3 + 0 + 10 + read-write + + + + + RX_D_CHF_COEF_4_DRS + Receive Demod Channel Filter Coef 4 DataRate1 + 0x260 + 32 + read-write + 0 + 0xFFFFFFFF + + + RX_D_CH_FILT_H4 + RX Demod Channel Filter Coefficient 4 + 0 + 10 + read-write + + + + + + + XCVR_MISC + XCVR_MISC + 0x40087280 + + 0 + 0xB0 + registers + + + + XCVR_CTRL + TRANSCEIVER CONTROL + 0 + 32 + read-write + 0x300001 + 0xFFFFFFFF + + + TX_DATA_RATE + Radio data rate setting + 0 + 3 + read-write + + + 00 + 2Mbps + #000 + + + 01 + 1Mbps + #001 + + + 10 + 500Kbps + #010 + + + 11 + 250Kbps + #011 + + + + + TX_DATA_RATE_DRS + Radio data rate setting, Data Rate Switch + 4 + 3 + read-write + + + 00 + 2Mbps + #000 + + + 01 + 1Mbps + #001 + + + 10 + 500Kbps + #010 + + + 11 + 250Kbps + #011 + + + + + REF_CLK_FREQ + Radio Reference Clock Frequency + 8 + 2 + read-write + + + 0 + 32 MHz + #00 + + + 1 + 26 MHz + #01 + + + + + SOC_RF_OSC_CLK_GATE_EN + SOC_RF_OSC_CLK_GATE_EN + 11 + 1 + read-write + + + FO_RX_EN + Fast Overwrite RX Enable + 14 + 1 + read-write + + + FO_TX_EN + Fast Overwrite TX Enable + 15 + 1 + read-write + + + RADIO0_IRQ_SEL + RADIO0_IRQ_SEL + 16 + 3 + read-write + + + 000 + Assign Radio #0 Interrupt to Bluetooth LE + #000 + + + 001 + Radio #0 Interrupt unassigned + #001 + + + 010 + Radio #0 Interrupt unassigned + #010 + + + 011 + Assign Radio #0 Interrupt to GENERIC_FSK + #011 + + + 100 + Radio #0 Interrupt unassigned + #100 + + + 101 + Radio #0 Interrupt unassigned + #101 + + + 110 + Radio #0 Interrupt unassigned + #110 + + + 111 + Radio #0 Interrupt unassigned + #111 + + + + + RADIO1_IRQ_SEL + RADIO1_IRQ_SEL + 20 + 3 + read-write + + + 000 + Assign Radio #1 Interrupt to Bluetooth LE + #000 + + + 001 + Radio #1 Interrupt unassigned + #001 + + + 010 + Radio #1 Interrupt unassigned + #010 + + + 011 + Assign Radio #1 Interrupt to GENERIC_FSK + #011 + + + 100 + Radio #1 Interrupt unassigned + #100 + + + 101 + Radio #1 Interrupt unassigned + #101 + + + 110 + Radio #1 Interrupt unassigned + #110 + + + 111 + Radio #1 Interrupt unassigned + #111 + + + + + TSM_LL_INHIBIT + TSM Per-Link-Layer Inhibit + 24 + 4 + read-write + + + TOF_RX_SEL + Time-of-Flight RX Select + 28 + 1 + read-write + + + 0 + PHY: aa_fnd_to_ll + #0 + + + 1 + Localization Control: pattern_found + #1 + + + + + TOF_TX_SEL + Time-of-Flight TX Select + 29 + 1 + read-write + + + 0 + TSM: tx_dig_en + #0 + + + 1 + TXDIG: pa_wu_complete + #1 + + + + + LL_CFG_CAPT_DIS + Link Layer Configuration Capture Disable + 30 + 1 + read-write + + + 0 + Enabled. Link Layer configuration inputs are captured. + #0 + + + 1 + Disabled: Link Layer configurations are not captured. + #1 + + + + + + + XCVR_STATUS + TRANSCEIVER STATUS + 0x4 + 32 + read-write + 0 + 0xFFFBC000 + + + TSM_COUNT + TSM_COUNT + 0 + 8 + read-only + + + PLL_SEQ_STATE + PLL Sequence State + 8 + 4 + read-only + + + 0000 + PLL OFF + #0000 + + + 0010 + CTUNE + #0010 + + + 0011 + CTUNE_SETTLE + #0011 + + + 0110 + HPMCAL1 + #0110 + + + 1000 + HPMCAL1_SETTLE + #1000 + + + 1010 + HPMCAL2 + #1010 + + + 1100 + HPMCAL2_SETTLE + #1100 + + + 1111 + PLLREADY + #1111 + + + + + RX_MODE + Receive Mode + 12 + 1 + read-only + + + TX_MODE + Transmit Mode + 13 + 1 + read-only + + + XTAL_READY + RF Osciallator Xtal Ready + 18 + 1 + read-only + + + 0 + Indicates that the RF Oscillator is disabled or has not completed its warmup. + #0 + + + 1 + Indicates that the RF Oscillator has completed its warmup count and is ready for use. + #1 + + + + + XCVR_BUSY + Transceiver Busy Status Bit + 20 + 1 + read-only + + + 0 + RF Channel in available (TSM is idle) + #0 + + + 1 + RF Channel in use (TSM is busy) + #1 + + + + + TSM_IRQ0 + TSM Interrupt #0 + 24 + 1 + read-write + + + 0 + TSM Interrupt #0 is not asserted. + #0 + + + 1 + TSM Interrupt #0 is asserted. Write '1' to this bit to clear it. + #1 + + + + + TSM_IRQ1 + TSM Interrupt #1 + 25 + 1 + read-write + + + 0 + TSM Interrupt #1 is not asserted. + #0 + + + 1 + TSM Interrupt #1 is asserted. Write '1' to this bit to clear it. + #1 + + + + + + + OVERWRITE_VER + OVERWRITE VERSION + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + OVERWRITE_VER + Overwrite Version Number. + 0 + 8 + read-write + + + + + RADIO_DFT + Radio DFT REGISTER + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + RADIO_DFT_MODE + Radio DFT modes + 0 + 4 + read-write + + + 0000 + Normal Radio Operation, DFT not engaged. + #0000 + + + 0001 + Carrier Only + #0001 + + + 0010 + Pattern Register GFSK + #0010 + + + 0011 + LFSR + #0011 + + + 0100 + RAM Modulation + #0100 + + + 1010 + PLL Coarse Tune BIST + #1010 + + + 1011 + PLL Frequency Synthesizer BIST + #1011 + + + 1100 + High Port DAC BIST + #1100 + + + 1101 + VCO Frequency Meter + #1101 + + + + + SOC_TEST_SEL + Radio Clock Selector for SoC RF Clock Tests + 4 + 2 + read-write + + + 00 + No Clock Selected + #00 + + + 01 + PLL Sigma Delta Clock, divided by 2 + #01 + + + 10 + Auxiliary PLL Clock, divided by 2 + #10 + + + 11 + RF Ref Osc clock, divided by 2 + #11 + + + + + + + DMA_CTRL + DMA CONTROL + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + DMA_PAGE + Transceiver DMA Page Selector + 0 + 4 + read-write + + + 0000 + DMA idle + #0000 + + + 0001 + RXDIG-IQ + #0001 + + + 0010 + RXDIG-IQ-ALT + #0010 + + + 0011 + ADC-IQ + #0011 + + + 0100 + DCEST-IQ + #0100 + + + 0101 + PHASE + #0101 + + + 0110 + RSSI-PHASE + #0110 + + + 0111 + MAG-PHASE + #0111 + + + 1000 + PHY + #1000 + + + 1001 + DETERMINISTIC + #1001 + + + + + DMA_START_TRG + DMA Start Trigger Selector + 4 + 4 + read-write + + + 0000 + no trigger + #0000 + + + 0001 + PHY: pd found + #0001 + + + 0010 + PHY: aa found + #0010 + + + 0101 + RXDIG: agc_dcoc_gain_chg + #0101 + + + 0110 + TSM: rx_dig_en + #0110 + + + 0111 + TSM: tsm_spare2_en + #0111 + + + 1000 + RBME: crc_pass + #1000 + + + 1001 + RBME: crc_vld + #1001 + + + 1010 + Localization control: dma_capt_trig + #1010 + + + 1011 + GenericLL: cte_present + #1011 + + + + + DMA_START_EDGE + DMA Start Trigger Edge Selector + 8 + 1 + read-write + + + 0 + Trigger fires on a rising edge of the selected trigger source + #0 + + + 1 + Trigger fires on a falling edge of the selected trigger source + #1 + + + + + DMA_DEC + DMA Decimation Rate + 10 + 2 + read-write + + + 00 + Data is captured on every data valid + #00 + + + 01 + Data is captured on every 2nd data valid + #01 + + + 10 + Data is captured on everey 4th data valid + #10 + + + 11 + Data is captured on every 8th data valid + #11 + + + + + DMA_START_DLY + DMA Start Trigger Delay + 12 + 11 + read-write + + + DMA_EN + DMA Enable + 23 + 1 + read-write + + + DMA_AA_TRIGGERED + DMA Access Address triggered + 24 + 1 + read-only + + + DMA_START_TRIGGERED + DMA Start Trigger Occurred + 25 + 1 + read-only + + + + + DBG_RAM_CTRL + DBG RAM CONTROL + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + DBG_PAGE + Packet RAM Debug DMA Page Selector + 0 + 4 + read-write + + + 0000 + DMA idle + #0000 + + + 0001 + RXDIG-IQ + #0001 + + + 0010 + RXDIG-IQ-ALT + #0010 + + + 0011 + ADC-IQ + #0011 + + + 0100 + DCEST-IQ + #0100 + + + 0101 + PHASE + #0101 + + + 0110 + RSSI-PHASE + #0110 + + + 0111 + MAG-PHASE + #0111 + + + 1000 + PHY + #1000 + + + + + DBG_START_TRG + Packet RAM Debug Start Trigger Selector + 4 + 4 + read-write + + + 0000 + no trigger + #0000 + + + 0001 + PHY: pd found + #0001 + + + 0010 + PHY: aa found + #0010 + + + 0101 + RXDIG: agc_dcoc_gain_chg + #0101 + + + 0110 + TSM: rx_dig_en + #0110 + + + 0111 + TSM: tsm_spare2_en + #0111 + + + 1000 + RBME: crc_pass + #1000 + + + 1001 + RBME: crc_vld + #1001 + + + 1010 + Localization control: dma_capt_trig + #1010 + + + 1011 + GenericLL: cte_present + #1011 + + + + + DBG_START_EDGE + Packet RAM Debug Start Trigger Edge Selector + 8 + 1 + read-write + + + 0 + Trigger fires on a rising edge of the selected trigger source + #0 + + + 1 + Trigger fires on a falling edge of the selected trigger source + #1 + + + + + DBG_STOP_EDGE + Packet RAM Debug Stop Trigger Edge Selector + 9 + 1 + read-write + + + 0 + Trigger fires on a rising edge of the selected trigger source + #0 + + + 1 + Trigger fires on a falling edge of the selected trigger source + #1 + + + + + DBG_DEC + DBG Decimation Rate + 10 + 2 + read-write + + + 00 + Data is captured on every data valid + #00 + + + 01 + Data is captured on every 2nd data valid + #01 + + + 10 + Data is captured on everey 4th data valid + #10 + + + 11 + Data is captured on every 8th data valid + #11 + + + + + DBG_START_DLY + DBG Start Trigger Delay + 12 + 11 + read-write + + + DBG_EN + Packet RAM Debug Mode Enable + 23 + 1 + read-write + + + DBG_AA_TRIGGERED + Packet Ram Debug Access Address triggered + 24 + 1 + read-only + + + DBG_START_TRIGGERED + Packet RAM Debug Start Triggered + 25 + 1 + read-only + + + DBG_STOP_TRIGGERED + Packet RAM Debug Stop Triggered + 26 + 1 + read-only + + + DBG_RAM_FULL + DBG_RAM_FULL + 27 + 1 + read-only + + + 0 + Packet RAM is not full + #0 + + + 1 + Packet RAM is full + #1 + + + + + DBG_STOP_TRG + Packet RAM Debug Stop Trigger Selector + 28 + 4 + read-write + + + 0000 + no trigger + #0000 + + + 0001 + PHY: pd found + #0001 + + + 0010 + PHY: aa found + #0010 + + + 0101 + RXDIG: agc_dcoc_gain_chg + #0101 + + + 0110 + TSM: rx_dig_en + #0110 + + + 0111 + TSM: tsm_spare3_en + #0111 + + + 1000 + RBME: crc_fail + #1000 + + + 1001 + RBME: crc_vld + #1001 + + + 1010 + RBME: error + #1010 + + + 1011 + Generic header fail + #1011 + + + 1100 + PLL unlock + #1100 + + + 1101 + Bluetooth LE crc_err_count_incr + #1101 + + + + + + + DBG_RAM_ADDR + DBG RAM ADDRESS + 0x1C + 32 + read-write + 0x7FFC0000 + 0xFFFFFFFF + + + DBG_RAM_FIRST + DBG RAM First Address + 0 + 15 + read-write + + + DBG_RAM_LAST + DBG RAM Last Address + 16 + 15 + read-write + + + + + DBG_RAM_STOP_ADDR + DBG RAM STOP ADDRESS + 0x20 + 32 + read-only + 0 + 0xFFFFFFFF + + + DBG_RAM_STOP + DBG RAM Stop Address + 0 + 15 + read-only + + + + + FAD_CTRL + FAD CONTROL + 0x24 + 32 + read-write + 0xF080 + 0xFFFFFFFF + + + ANTX + Antenna Selection State + 1 + 1 + read-only + + + ANTX_OVRD_EN + Antenna State Override Enable + 2 + 1 + read-write + + + ANTX_OVRD + Antenna State Override Value + 3 + 1 + read-write + + + ANTX_EN + FAD Antenna Controls Enable + 4 + 2 + read-write + + + 00 + all disabled (held low) + #00 + + + 01 + only RX/TX_SWITCH enabled + #01 + + + 10 + only ANT_A/B enabled + #10 + + + 11 + all enabled + #11 + + + + + ANTX_HZ + FAD PAD Tristate Control + 6 + 1 + read-write + + + 0 + ANT_A, ANT_B, RX_SWITCH and TX_SWITCH are actively driven outputs. + #0 + + + 1 + Antenna controls high impedance- Set ANT_A, ANT_B, RX_SWITCH and TX_SWITCH in high impedance. + #1 + + + + + ANTX_CTRLMODE + Antenna Diversity Control Mode + 7 + 1 + read-write + + + ANTX_POL + FAD Antenna Controls Polarity + 8 + 4 + read-write + + + FAD_NOT_GPIO + FAD versus GPIO Mode Selector + 12 + 4 + read-write + + + + + COEX_CTRL + COEXISTENCE CONTROL + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + RF_NOT_ALLOWED_EN + RF_NOT_ALLOWED PER-LINK-LAYER ENABLE + 0 + 4 + read-write + + + RF_NOT_ALLOWED_NO_TX + RF_NOT_ALLOWED_NO_TX + 4 + 1 + read-write + + + 0 + Assertion on RF_NOT_ALLOWED has no effect on TX + #0 + + + 1 + Assertion on RF_NOT_ALLOWED can abort TX + #1 + + + + + RF_NOT_ALLOWED_NO_RX + RF_NOT_ALLOWED_NO_RX + 5 + 1 + read-write + + + 0 + Assertion on RF_NOT_ALLOWED has no effect on RX + #0 + + + 1 + Assertion on RF_NOT_ALLOWED can abort RX + #1 + + + + + RF_NOT_ALLOWED_ASSERTED + RF_NOT_ALLOWED_ASSERTED + 6 + 1 + read-write + + + 0 + Assertion on RF_NOT_ALLOWED has not occurred + #0 + + + 1 + Assertion on RF_NOT_ALLOWED has occurred since the last time this bit was cleared + #1 + + + + + RF_NOT_ALLOWED_TX_ABORT + RF_NOT_ALLOWED_TX_ABORT + 7 + 1 + read-write + + + 0 + A TX abort due to assertion on RF_NOT_ALLOWED has not occurred + #0 + + + 1 + A TX abort due to assertion on RF_NOT_ALLOWED has occurred since the last time this bit was cleared + #1 + + + + + RF_NOT_ALLOWED_RX_ABORT + RF_NOT_ALLOWED_RX_ABORT + 8 + 1 + read-write + + + 0 + A RX abort due to assertion on RF_NOT_ALLOWED has not occurred + #0 + + + 1 + A RX abort due to assertion on RF_NOT_ALLOWED has occurred since the last time this bit was cleared + #1 + + + + + RF_NOT_ALLOWED + RF_NOT_ALLOWED + 9 + 1 + read-only + + + TSM_SPARE1_EXTEND + TSM_SPARE1_EX Extension Duration + 16 + 8 + read-write + + + + + LCL_CFG0 + LOCALIZATION CONTROL CONFIG0 + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + LCL_EN + Localization Control Module Enable + 0 + 1 + read-write + + + TX_LCL_EN + Enable Switching in TX + 1 + 1 + read-write + + + RX_LCL_EN + Enable Switching in RX + 2 + 1 + read-write + + + LANT_INV + Invert Antenna Switch Output + 3 + 1 + read-write + + + COMP_EN + Pattern Matching Enable + 4 + 1 + read-write + + + COMP_TX_EN + Pattern Matching Enable in TX + 5 + 1 + read-write + + + SW_TRIG + Software Trigger. Can be used with either RX or TX + 6 + 1 + read-write + + + LANT_SW_WIGGLE + LANT_SW Wiggle + 7 + 1 + read-write + + + PM_NUM_BYTES + Number of Bytes to Match + 8 + 2 + read-write + + + 00 + 4 bytes + #00 + + + 01 + 5 bytes + #01 + + + 10 + 6 bytes + #10 + + + 11 + 8 bytes + #11 + + + + + LANT_BLOCK_TX + Block LANT_SW for TX + 10 + 1 + read-write + + + LANT_BLOCK_RX + Block LANT_SW for RX + 11 + 1 + read-write + + + CTE_DUR + Total Switching Duration + 16 + 9 + read-write + + + + + LCL_CFG1 + LOCALIZATION CONTROL CONFIG1 + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + M_ON_DELAY + M on Delay + 0 + 10 + read-write + + + N_ON_DELAY + N on Delay + 12 + 4 + read-write + + + + + LCL_TX_CFG0 + LOCALIZATION CONTROL TX CONFIG0 + 0x38 + 32 + read-write + 0 + 0xFFFFFFFF + + + TX_DELAY + Interval delay before TX switching begins. + 0 + 11 + read-write + + + TX_DELAY_OFF + Fine sample delay after TX_DELAY. + 16 + 5 + read-write + + + + + LCL_TX_CFG1 + LOCALIZATION CONTROL TX CONFIG1 + 0x3C + 32 + read-write + 0 + 0xFFFFFFFF + + + TX_SPINT + Number of TX Samples that define the length of an Interval , where 0=1sample, 1=2sample, etc. + 0 + 5 + read-write + + + TX_ANT_TRIG_SEL + Selects Trigger for TX + 8 + 3 + read-write + + + 000 + Software Trigger + #000 + + + 001 + Localization control: pattern found + #001 + + + 010 + CRC Complete + #010 + + + 011 + PA Warmup Complete + #011 + + + 100 + RBME tx_done_pre + #100 + + + + + TX_HI_PER + Number of intervals for antenna HIGH + 16 + 5 + read-write + + + TX_LO_PER + Number of intervals for antenna LOW + 24 + 5 + read-write + + + + + LCL_RX_CFG0 + LOCALIZATION CONTROL RX CONFIG0 + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + RX_DELAY + Interval delay before RX switching begins. + 0 + 11 + read-write + + + RX_DELAY_OFF + Fine sample delay after RX_DELAY. + 16 + 5 + read-write + + + + + LCL_RX_CFG1 + LOCALIZATION CONTROL RX CONFIG1 + 0x44 + 32 + read-write + 0 + 0xFFFFFFFF + + + RX_SPINT + Number of RX Samples that define the length of an Interval , where 0=1sample, 1=2sample, etc. + 0 + 5 + read-write + + + RX_ANT_TRIG_SEL + Selects Trigger for RX + 8 + 3 + read-write + + + 000 + Software Trigger + #000 + + + 001 + Localization control: pattern found + #001 + + + 010 + CRC Complete + #010 + + + 011 + CRC Pass + #011 + + + 100 + GenericLL: cte_present + #100 + + + 101 + PHY: aa_fnd_to_ll + #101 + + + + + RX_HI_PER + Number of intervals for antenna HIGH + 16 + 5 + read-write + + + RX_LO_PER + Number of intervals for antenna LOW + 24 + 5 + read-write + + + + + LCL_PM_MSB + LOCALIZATION CONTROL PM MSB + 0x48 + 32 + read-write + 0 + 0xFFFFFFFF + + + COMP_PATTERN_MSB + Upper bytes of pattern to be matched, bits 63:32 + 0 + 32 + read-write + + + + + LCL_PM_LSB + LOCALIZATION CONTROL PM LSB + 0x4C + 32 + read-write + 0 + 0xFFFFFFFF + + + COMP_PATTERN_LSB + Lower bytes of pattern to be matched, bits 31:0 + 0 + 32 + read-write + + + + + IPS_FO_ADDR0 + IPS FAST OVERWRITE ADDRESS + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + IPS Address + 0 + 12 + read-write + + + ENTRY_RX + Enable Entry for RX + 12 + 1 + read-write + + + ENTRY_TX + Enable Entry for TX + 13 + 1 + read-write + + + + + IPS_FO_ADDR1 + IPS FAST OVERWRITE ADDRESS + 0x54 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + IPS Address + 0 + 12 + read-write + + + ENTRY_RX + Enable Entry for RX + 12 + 1 + read-write + + + ENTRY_TX + Enable Entry for TX + 13 + 1 + read-write + + + + + IPS_FO_ADDR2 + IPS FAST OVERWRITE ADDRESS + 0x58 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + IPS Address + 0 + 12 + read-write + + + ENTRY_RX + Enable Entry for RX + 12 + 1 + read-write + + + ENTRY_TX + Enable Entry for TX + 13 + 1 + read-write + + + + + IPS_FO_ADDR3 + IPS FAST OVERWRITE ADDRESS + 0x5C + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + IPS Address + 0 + 12 + read-write + + + ENTRY_RX + Enable Entry for RX + 12 + 1 + read-write + + + ENTRY_TX + Enable Entry for TX + 13 + 1 + read-write + + + + + IPS_FO_ADDR4 + IPS FAST OVERWRITE ADDRESS + 0x60 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + IPS Address + 0 + 12 + read-write + + + ENTRY_RX + Enable Entry for RX + 12 + 1 + read-write + + + ENTRY_TX + Enable Entry for TX + 13 + 1 + read-write + + + + + IPS_FO_ADDR5 + IPS FAST OVERWRITE ADDRESS + 0x64 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + IPS Address + 0 + 12 + read-write + + + ENTRY_RX + Enable Entry for RX + 12 + 1 + read-write + + + ENTRY_TX + Enable Entry for TX + 13 + 1 + read-write + + + + + IPS_FO_ADDR6 + IPS FAST OVERWRITE ADDRESS + 0x68 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + IPS Address + 0 + 12 + read-write + + + ENTRY_RX + Enable Entry for RX + 12 + 1 + read-write + + + ENTRY_TX + Enable Entry for TX + 13 + 1 + read-write + + + + + IPS_FO_ADDR7 + IPS FAST OVERWRITE ADDRESS + 0x6C + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + IPS Address + 0 + 12 + read-write + + + ENTRY_RX + Enable Entry for RX + 12 + 1 + read-write + + + ENTRY_TX + Enable Entry for TX + 13 + 1 + read-write + + + + + IPS_FO_DRS0_DATA0 + IPS FAST OVERWRITE DRS0 DATA + 0x70 + 32 + read-write + 0 + 0xFFFFFFFF + + + DRS0_DATA + Fast Overwrite DRS0 data + 0 + 32 + read-write + + + + + IPS_FO_DRS0_DATA1 + IPS FAST OVERWRITE DRS0 DATA + 0x74 + 32 + read-write + 0 + 0xFFFFFFFF + + + DRS0_DATA + Fast Overwrite DRS0 data + 0 + 32 + read-write + + + + + IPS_FO_DRS0_DATA2 + IPS FAST OVERWRITE DRS0 DATA + 0x78 + 32 + read-write + 0 + 0xFFFFFFFF + + + DRS0_DATA + Fast Overwrite DRS0 data + 0 + 32 + read-write + + + + + IPS_FO_DRS0_DATA3 + IPS FAST OVERWRITE DRS0 DATA + 0x7C + 32 + read-write + 0 + 0xFFFFFFFF + + + DRS0_DATA + Fast Overwrite DRS0 data + 0 + 32 + read-write + + + + + IPS_FO_DRS0_DATA4 + IPS FAST OVERWRITE DRS0 DATA + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + DRS0_DATA + Fast Overwrite DRS0 data + 0 + 32 + read-write + + + + + IPS_FO_DRS0_DATA5 + IPS FAST OVERWRITE DRS0 DATA + 0x84 + 32 + read-write + 0 + 0xFFFFFFFF + + + DRS0_DATA + Fast Overwrite DRS0 data + 0 + 32 + read-write + + + + + IPS_FO_DRS0_DATA6 + IPS FAST OVERWRITE DRS0 DATA + 0x88 + 32 + read-write + 0 + 0xFFFFFFFF + + + DRS0_DATA + Fast Overwrite DRS0 data + 0 + 32 + read-write + + + + + IPS_FO_DRS0_DATA7 + IPS FAST OVERWRITE DRS0 DATA + 0x8C + 32 + read-write + 0 + 0xFFFFFFFF + + + DRS0_DATA + Fast Overwrite DRS0 data + 0 + 32 + read-write + + + + + IPS_FO_DRS1_DATA0 + IPS FAST OVERWRITE DRS1 DATA + 0x90 + 32 + read-write + 0 + 0xFFFFFFFF + + + DRS1_DATA + Fast Overwrite DRS1 data + 0 + 32 + read-write + + + + + IPS_FO_DRS1_DATA1 + IPS FAST OVERWRITE DRS1 DATA + 0x94 + 32 + read-write + 0 + 0xFFFFFFFF + + + DRS1_DATA + Fast Overwrite DRS1 data + 0 + 32 + read-write + + + + + IPS_FO_DRS1_DATA2 + IPS FAST OVERWRITE DRS1 DATA + 0x98 + 32 + read-write + 0 + 0xFFFFFFFF + + + DRS1_DATA + Fast Overwrite DRS1 data + 0 + 32 + read-write + + + + + IPS_FO_DRS1_DATA3 + IPS FAST OVERWRITE DRS1 DATA + 0x9C + 32 + read-write + 0 + 0xFFFFFFFF + + + DRS1_DATA + Fast Overwrite DRS1 data + 0 + 32 + read-write + + + + + IPS_FO_DRS1_DATA4 + IPS FAST OVERWRITE DRS1 DATA + 0xA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DRS1_DATA + Fast Overwrite DRS1 data + 0 + 32 + read-write + + + + + IPS_FO_DRS1_DATA5 + IPS FAST OVERWRITE DRS1 DATA + 0xA4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DRS1_DATA + Fast Overwrite DRS1 data + 0 + 32 + read-write + + + + + IPS_FO_DRS1_DATA6 + IPS FAST OVERWRITE DRS1 DATA + 0xA8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DRS1_DATA + Fast Overwrite DRS1 data + 0 + 32 + read-write + + + + + IPS_FO_DRS1_DATA7 + IPS FAST OVERWRITE DRS1 DATA + 0xAC + 32 + read-write + 0 + 0xFFFFFFFF + + + DRS1_DATA + Fast Overwrite DRS1 data + 0 + 32 + read-write + + + + + + + XCVR_TSM + XCVR_TSM + 0x40087380 + + 0 + 0x12C + registers + + + + CTRL + TSM CONTROL + 0 + 32 + read-write + 0xFF000000 + 0xFFFFFFFF + + + TSM_SOFT_RESET + TSM Soft Reset + 1 + 1 + read-write + + + 0 + TSM Soft Reset removed. Normal operation. + #0 + + + 1 + TSM Soft Reset engaged. TSM forced to IDLE, and holds there until the bit is cleared. + #1 + + + + + FORCE_TX_EN + Force Transmit Enable + 2 + 1 + read-write + + + 0 + TSM Idle + #0 + + + 1 + TSM executes a TX sequence + #1 + + + + + FORCE_RX_EN + Force Receive Enable + 3 + 1 + read-write + + + 0 + TSM Idle + #0 + + + 1 + TSM executes a RX sequence + #1 + + + + + TSM_IRQ0_EN + TSM_IRQ0 Enable/Disable bit + 8 + 1 + read-write + + + 0 + TSM_IRQ0 is disabled + #0 + + + 1 + TSM_IRQ0 is enabled + #1 + + + + + TSM_IRQ1_EN + TSM_IRQ1 Enable/Disable bit + 9 + 1 + read-write + + + 0 + TSM_IRQ1 is disabled + #0 + + + 1 + TSM_IRQ1 is enabled + #1 + + + + + TX_ABORT_DIS + Transmit Abort Disable + 16 + 1 + read-write + + + RX_ABORT_DIS + Receive Abort Disable + 17 + 1 + read-write + + + ABORT_ON_CTUNE + Abort On Coarse Tune Lock Detect Failure + 18 + 1 + read-write + + + 0 + don't allow TSM abort on Coarse Tune Unlock Detect + #0 + + + 1 + allow TSM abort on Coarse Tune Unlock Detect + #1 + + + + + ABORT_ON_CYCLE_SLIP + Abort On Cycle Slip Lock Detect Failure + 19 + 1 + read-write + + + 0 + don't allow TSM abort on Cycle Slip Unlock Detect + #0 + + + 1 + allow TSM abort on Cycle Slip Unlock Detect + #1 + + + + + ABORT_ON_FREQ_TARG + Abort On Frequency Target Lock Detect Failure + 20 + 1 + read-write + + + 0 + don't allow TSM abort on Frequency Target Unlock Detect + #0 + + + 1 + allow TSM abort on Frequency Target Unlock Detect + #1 + + + + + BKPT + TSM Breakpoint + 24 + 8 + read-write + + + + + END_OF_SEQ + TSM END OF SEQUENCE + 0x4 + 32 + read-write + 0x67666A63 + 0xFFFFFFFF + + + END_OF_TX_WU + End of TX Warmup + 0 + 8 + read-write + + + END_OF_TX_WD + End of TX Warmdown + 8 + 8 + read-write + + + END_OF_RX_WU + End of RX Warmup + 16 + 8 + read-write + + + END_OF_RX_WD + End of RX Warmdown + 24 + 8 + read-write + + + + + WU_LATENCY + WARMUP LATENCY + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + TX_DATAPATH_LATENCY + TX Datapath Latency + 0 + 8 + read-write + + + RX_SETTLING_LATENCY + RX Settling Latency + 16 + 8 + read-write + + + + + RECYCLE_COUNT + TSM RECYCLE COUNT + 0x24 + 32 + read-write + 0x1A0464 + 0xFFFFFFFF + + + RECYCLE_COUNT0 + TSM RX Recycle Count 0 + 0 + 8 + read-write + + + RECYCLE_COUNT1 + TSM RX Recycle Count 1 + 8 + 8 + read-write + + + RECYCLE_COUNT2 + TSM RX Recycle Count 2 + 16 + 8 + read-write + + + + + FAST_CTRL1 + TSM FAST WARMUP CONTROL 1 + 0x28 + 32 + read-write + 0xFF00 + 0xFFFFFFFF + + + FAST_TX_WU_EN + Fast TSM TX Warmup Enable + 0 + 1 + read-write + + + 0 + Fast TSM TX Warmups are disabled + #0 + + + 1 + Fast TSM TX Warmup requests from the Generic link layer are enabled. + #1 + + + + + FAST_RX_WU_EN + Fast TSM RX Warmup Enable + 1 + 1 + read-write + + + 0 + Fast TSM RX Warmups are disabled + #0 + + + 1 + Fast TSM RX Warmup requests from the Generic link layer are enabled. + #1 + + + + + FAST_RX2TX_EN + Fast TSM RX-to-TX Transition Enable + 2 + 1 + read-write + + + 0 + Disable Fast RX-to-TX transitions + #0 + + + 1 + Enable Fast RX-to-TX transitions (if fast_rx2tx_wu is asserted by the link layer) + #1 + + + + + PWRSAVE_TX_WU_EN + Pwrsave TSM TX Warmup Enable + 4 + 1 + read-write + + + 0 + Pwrsave TSM TX Warmups are disabled + #0 + + + 1 + Pwrsave TSM TX Warmups are enabled, if the RF channel has not changed since the last TX warmup, and for Bluetooth LE mode, the RF channel is not an advertising channel. + #1 + + + + + PWRSAVE_RX_WU_EN + Pwrsave TSM RX Warmup Enable + 5 + 1 + read-write + + + 0 + Pwrsave TSM RX Warmups are disabled + #0 + + + 1 + Pwrsave TSM RX Warmups are enabled, if the RF channel has not changed since the last RX warmup, and for Bluetooth LE mode, the RF channel is not an advertising channel. + #1 + + + + + PWRSAVE_WU_CLEAR + Pwrsave TSM Warmup Clear State + 6 + 1 + read-write + + + FAST_RX2TX_START + TSM "Jump-to" point for a Fast TSM RX-to-TX Transition. + 8 + 8 + read-write + + + + + FAST_CTRL2 + TSM FAST WARMUP CONTROL 2 + 0x2C + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + FAST_START_TX + Fast TSM TX "Jump-from" Point + 0 + 8 + read-write + + + FAST_DEST_TX + Fast TSM TX "Jump-to" Point + 8 + 8 + read-write + + + FAST_START_RX + Fast TSM RX "Jump-from" Point + 16 + 8 + read-write + + + FAST_DEST_RX + Fast TSM RX "Jump-to" Point + 24 + 8 + read-write + + + + + TIMING00 + TSM_TIMING00 + 0x30 + 32 + read-write + 0x67006A00 + 0xFFFFFFFF + + + BB_LDO_HF_EN_TX_HI + Assertion time setting for BB_LDO_HF_EN (TX) + 0 + 8 + read-write + + + BB_LDO_HF_EN_TX_LO + De-assertion time setting for BB_LDO_HF_EN (TX) + 8 + 8 + read-write + + + BB_LDO_HF_EN_RX_HI + Assertion time setting for BB_LDO_HF_EN (RX) + 16 + 8 + read-write + + + BB_LDO_HF_EN_RX_LO + De-assertion time setting for BB_LDO_HF_EN (RX) + 24 + 8 + read-write + + + + + TIMING01 + TSM_TIMING01 + 0x34 + 32 + read-write + 0x67006A00 + 0xFFFFFFFF + + + BB_LDO_ADCDAC_EN_TX_HI + Assertion time setting for BB_LDO_ADCDAC_EN (TX) + 0 + 8 + read-write + + + BB_LDO_ADCDAC_EN_TX_LO + De-assertion time setting for BB_LDO_ADCDAC_EN (TX) + 8 + 8 + read-write + + + BB_LDO_ADCDAC_EN_RX_HI + Assertion time setting for BB_LDO_ADCDAC_EN (RX) + 16 + 8 + read-write + + + BB_LDO_ADCDAC_EN_RX_LO + De-assertion time setting for BB_LDO_ADCDAC_EN (RX) + 24 + 8 + read-write + + + + + TIMING02 + TSM_TIMING02 + 0x38 + 32 + read-write + 0x6700FFFF + 0xFFFFFFFF + + + BB_LDO_BBA_EN_RX_HI + Assertion time setting for BB_LDO_BBA_EN (RX) + 16 + 8 + read-write + + + BB_LDO_BBA_EN_RX_LO + De-assertion time setting for BB_LDO_BBA_EN (RX) + 24 + 8 + read-write + + + + + TIMING03 + TSM_TIMING03 + 0x3C + 32 + read-write + 0x67006A00 + 0xFFFFFFFF + + + BB_LDO_PD_EN_TX_HI + Assertion time setting for BB_LDO_PD_EN (TX) + 0 + 8 + read-write + + + BB_LDO_PD_EN_TX_LO + De-assertion time setting for BB_LDO_PD_EN (TX) + 8 + 8 + read-write + + + BB_LDO_PD_EN_RX_HI + Assertion time setting for BB_LDO_PD_EN (RX) + 16 + 8 + read-write + + + BB_LDO_PD_EN_RX_LO + De-assertion time setting for BB_LDO_PD_EN (RX) + 24 + 8 + read-write + + + + + TIMING04 + TSM_TIMING04 + 0x40 + 32 + read-write + 0x67006A00 + 0xFFFFFFFF + + + BB_LDO_FDBK_EN_TX_HI + Assertion time setting for BB_LDO_FDBK_EN (TX) + 0 + 8 + read-write + + + BB_LDO_FDBK_EN_TX_LO + De-assertion time setting for BB_LDO_FDBK_EN (TX) + 8 + 8 + read-write + + + BB_LDO_FDBK_EN_RX_HI + Assertion time setting for BB_LDO_FDBK_EN (RX) + 16 + 8 + read-write + + + BB_LDO_FDBK_EN_RX_LO + De-assertion time setting for BB_LDO_FDBK_EN (RX) + 24 + 8 + read-write + + + + + TIMING05 + TSM_TIMING05 + 0x44 + 32 + read-write + 0x67006A00 + 0xFFFFFFFF + + + BB_LDO_VCOLO_EN_TX_HI + Assertion time setting for BB_LDO_VCOLO_EN (TX) + 0 + 8 + read-write + + + BB_LDO_VCOLO_EN_TX_LO + De-assertion time setting for BB_LDO_VCOLO_EN (TX) + 8 + 8 + read-write + + + BB_LDO_VCOLO_EN_RX_HI + Assertion time setting for BB_LDO_VCOLO_EN (RX) + 16 + 8 + read-write + + + BB_LDO_VCOLO_EN_RX_LO + De-assertion time setting for BB_LDO_VCOLO_EN (RX) + 24 + 8 + read-write + + + + + TIMING06 + TSM_TIMING06 + 0x48 + 32 + read-write + 0x67006A00 + 0xFFFFFFFF + + + BB_LDO_VTREF_EN_TX_HI + Assertion time setting for BB_LDO_VTREF_EN (TX) + 0 + 8 + read-write + + + BB_LDO_VTREF_EN_TX_LO + De-assertion time setting for BB_LDO_VTREF_EN (TX) + 8 + 8 + read-write + + + BB_LDO_VTREF_EN_RX_HI + Assertion time setting for BB_LDO_VTREF_EN (RX) + 16 + 8 + read-write + + + BB_LDO_VTREF_EN_RX_LO + De-assertion time setting for BB_LDO_VTREF_EN (RX) + 24 + 8 + read-write + + + + + TIMING07 + TSM_TIMING07 + 0x4C + 32 + read-write + 0x5000500 + 0xFFFFFFFF + + + BB_LDO_FDBK_BLEED_EN_TX_HI + Assertion time setting for BB_LDO_FDBK_BLEED_EN (TX) + 0 + 8 + read-write + + + BB_LDO_FDBK_BLEED_EN_TX_LO + De-assertion time setting for BB_LDO_FDBK_BLEED_EN (TX) + 8 + 8 + read-write + + + BB_LDO_FDBK_BLEED_EN_RX_HI + Assertion time setting for BB_LDO_FDBK_BLEED_EN (RX) + 16 + 8 + read-write + + + BB_LDO_FDBK_BLEED_EN_RX_LO + De-assertion time setting for BB_LDO_FDBK_BLEED_EN (RX) + 24 + 8 + read-write + + + + + TIMING08 + TSM_TIMING08 + 0x50 + 32 + read-write + 0x3000300 + 0xFFFFFFFF + + + BB_LDO_VCOLO_BLEED_EN_TX_HI + Assertion time setting for BB_LDO_VCOLO_BLEED_EN (TX) + 0 + 8 + read-write + + + BB_LDO_VCOLO_BLEED_EN_TX_LO + De-assertion time setting for BB_LDO_VCOLO_BLEED_EN (TX) + 8 + 8 + read-write + + + BB_LDO_VCOLO_BLEED_EN_RX_HI + Assertion time setting for BB_LDO_VCOLO_BLEED_EN (RX) + 16 + 8 + read-write + + + BB_LDO_VCOLO_BLEED_EN_RX_LO + De-assertion time setting for BB_LDO_VCOLO_BLEED_EN (RX) + 24 + 8 + read-write + + + + + TIMING09 + TSM_TIMING09 + 0x54 + 32 + read-write + 0x3000300 + 0xFFFFFFFF + + + BB_LDO_VCOLO_FASTCHARGE_EN_TX_HI + Assertion time setting for BB_LDO_VCOLO_FASTCHARGE_EN (TX) + 0 + 8 + read-write + + + BB_LDO_VCOLO_FASTCHARGE_EN_TX_LO + De-assertion time setting for BB_LDO_VCOLO_FASTCHARGE_EN (TX) + 8 + 8 + read-write + + + BB_LDO_VCOLO_FASTCHARGE_EN_RX_HI + Assertion time setting for BB_LDO_VCOLO_FASTCHARGE_EN (RX) + 16 + 8 + read-write + + + BB_LDO_VCOLO_FASTCHARGE_EN_RX_LO + De-assertion time setting for BB_LDO_VCOLO_FASTCHARGE_EN (RX) + 24 + 8 + read-write + + + + + TIMING10 + TSM_TIMING10 + 0x58 + 32 + read-write + 0x67036A03 + 0xFFFFFFFF + + + BB_XTAL_PLL_REF_CLK_EN_TX_HI + Assertion time setting for BB_XTAL_PLL_REF_CLK_EN (TX) + 0 + 8 + read-write + + + BB_XTAL_PLL_REF_CLK_EN_TX_LO + De-assertion time setting for BB_XTAL_PLL_REF_CLK_EN (TX) + 8 + 8 + read-write + + + BB_XTAL_PLL_REF_CLK_EN_RX_HI + Assertion time setting for BB_XTAL_PLL_REF_CLK_EN (RX) + 16 + 8 + read-write + + + BB_XTAL_PLL_REF_CLK_EN_RX_LO + De-assertion time setting for BB_XTAL_PLL_REF_CLK_EN (RX) + 24 + 8 + read-write + + + + + TIMING11 + TSM_TIMING11 + 0x5C + 32 + read-write + 0xFFFF6A03 + 0xFFFFFFFF + + + BB_XTAL_DAC_REF_CLK_EN_TX_HI + Assertion time setting for BB_XTAL_DAC_REF_CLK_EN (TX) + 0 + 8 + read-write + + + BB_XTAL_DAC_REF_CLK_EN_TX_LO + De-assertion time setting for BB_XTAL_DAC_REF_CLK_EN (TX) + 8 + 8 + read-write + + + + + TIMING12 + TSM_TIMING12 + 0x60 + 32 + read-write + 0x6703FFFF + 0xFFFFFFFF + + + RXTX_AUXPLL_VCO_REF_CLK_EN_RX_HI + Assertion time setting for RXTX_AUXPLL_VCO_REF_CLK_EN (RX) + 16 + 8 + read-write + + + RXTX_AUXPLL_VCO_REF_CLK_EN_RX_LO + De-assertion time setting for RXTX_AUXPLL_VCO_REF_CLK_EN (RX) + 24 + 8 + read-write + + + + + TIMING13 + TSM_TIMING13 + 0x64 + 32 + read-write + 0x16004A00 + 0xFFFFFFFF + + + PLL_LOOP_IS_OPEN_TX_HI + Assertion time setting for PLL_LOOP_IS_OPEN (TX) + 0 + 8 + read-write + + + PLL_LOOP_IS_OPEN_TX_LO + De-assertion time setting for PLL_LOOP_IS_OPEN (TX) + 8 + 8 + read-write + + + PLL_LOOP_IS_OPEN_RX_HI + Assertion time setting for PLL_LOOP_IS_OPEN (RX) + 16 + 8 + read-write + + + PLL_LOOP_IS_OPEN_RX_LO + De-assertion time setting for PLL_LOOP_IS_OPEN (RX) + 24 + 8 + read-write + + + + + TIMING14 + TSM_TIMING14 + 0x68 + 32 + read-write + 0x672F645F + 0xFFFFFFFF + + + SY_PD_CYCLE_SLIP_LD_FT_EN_TX_HI + Assertion time setting for SY_PD_CYCLE_SLIP_LD_FT_EN (TX) + 0 + 8 + read-write + + + SY_PD_CYCLE_SLIP_LD_FT_EN_TX_LO + De-assertion time setting for SY_PD_CYCLE_SLIP_LD_FT_EN (TX) + 8 + 8 + read-write + + + SY_PD_CYCLE_SLIP_LD_FT_EN_RX_HI + Assertion time setting for SY_PD_CYCLE_SLIP_LD_FT_EN (RX) + 16 + 8 + read-write + + + SY_PD_CYCLE_SLIP_LD_FT_EN_RX_LO + De-assertion time setting for SY_PD_CYCLE_SLIP_LD_FT_EN (RX) + 24 + 8 + read-write + + + + + TIMING15 + TSM_TIMING15 + 0x6C + 32 + read-write + 0x67036A03 + 0xFFFFFFFF + + + SY_VCO_EN_TX_HI + Assertion time setting for SY_VCO_EN (TX) + 0 + 8 + read-write + + + SY_VCO_EN_TX_LO + De-assertion time setting for SY_VCO_EN (TX) + 8 + 8 + read-write + + + SY_VCO_EN_RX_HI + Assertion time setting for SY_VCO_EN (RX) + 16 + 8 + read-write + + + SY_VCO_EN_RX_LO + De-assertion time setting for SY_VCO_EN (RX) + 24 + 8 + read-write + + + + + TIMING16 + TSM_TIMING16 + 0x70 + 32 + read-write + 0x671AFFFF + 0xFFFFFFFF + + + SY_LO_RX_BUF_EN_RX_HI + Assertion time setting for SY_LO_RX_BUF_EN (RX) + 16 + 8 + read-write + + + SY_LO_RX_BUF_EN_RX_LO + De-assertion time setting for SY_LO_RX_BUF_EN (RX) + 24 + 8 + read-write + + + + + TIMING17 + TSM_TIMING17 + 0x74 + 32 + read-write + 0xFFFF6A5A + 0xFFFFFFFF + + + SY_LO_TX_BUF_EN_TX_HI + Assertion time setting for SY_LO_TX_BUF_EN (TX) + 0 + 8 + read-write + + + SY_LO_TX_BUF_EN_TX_LO + De-assertion time setting for SY_LO_TX_BUF_EN (TX) + 8 + 8 + read-write + + + + + TIMING18 + TSM_TIMING18 + 0x78 + 32 + read-write + 0x67056A05 + 0xFFFFFFFF + + + SY_DIVN_EN_TX_HI + Assertion time setting for SY_DIVN_EN (TX) + 0 + 8 + read-write + + + SY_DIVN_EN_TX_LO + De-assertion time setting for SY_DIVN_EN (TX) + 8 + 8 + read-write + + + SY_DIVN_EN_RX_HI + Assertion time setting for SY_DIVN_EN (RX) + 16 + 8 + read-write + + + SY_DIVN_EN_RX_LO + De-assertion time setting for SY_DIVN_EN (RX) + 24 + 8 + read-write + + + + + TIMING19 + TSM_TIMING19 + 0x7C + 32 + read-write + 0x16054A05 + 0xFFFFFFFF + + + SY_PD_FILTER_CHARGE_EN_TX_HI + Assertion time setting for SY_PD_FILTER_CHARGE_EN (TX) + 0 + 8 + read-write + + + SY_PD_FILTER_CHARGE_EN_TX_LO + De-assertion time setting for SY_PD_FILTER_CHARGE_EN (TX) + 8 + 8 + read-write + + + SY_PD_FILTER_CHARGE_EN_RX_HI + Assertion time setting for SY_PD_FILTER_CHARGE_EN (RX) + 16 + 8 + read-write + + + SY_PD_FILTER_CHARGE_EN_RX_LO + De-assertion time setting for SY_PD_FILTER_CHARGE_EN (RX) + 24 + 8 + read-write + + + + + TIMING20 + TSM_TIMING20 + 0x80 + 32 + read-write + 0x67056A05 + 0xFFFFFFFF + + + SY_PD_EN_TX_HI + Assertion time setting for SY_PD_EN (TX) + 0 + 8 + read-write + + + SY_PD_EN_TX_LO + De-assertion time setting for SY_PD_EN (TX) + 8 + 8 + read-write + + + SY_PD_EN_RX_HI + Assertion time setting for SY_PD_EN (RX) + 16 + 8 + read-write + + + SY_PD_EN_RX_LO + De-assertion time setting for SY_PD_EN (RX) + 24 + 8 + read-write + + + + + TIMING21 + TSM_TIMING21 + 0x84 + 32 + read-write + 0x67046A04 + 0xFFFFFFFF + + + SY_LO_DIVN_EN_TX_HI + Assertion time setting for SY_LO_DIVN_EN (TX) + 0 + 8 + read-write + + + SY_LO_DIVN_EN_TX_LO + De-assertion time setting for SY_LO_DIVN_EN (TX) + 8 + 8 + read-write + + + SY_LO_DIVN_EN_RX_HI + Assertion time setting for SY_LO_DIVN_EN (RX) + 16 + 8 + read-write + + + SY_LO_DIVN_EN_RX_LO + De-assertion time setting for SY_LO_DIVN_EN (RX) + 24 + 8 + read-write + + + + + TIMING22 + TSM_TIMING22 + 0x88 + 32 + read-write + 0x6704FFFF + 0xFFFFFFFF + + + SY_LO_RX_EN_RX_HI + Assertion time setting for SY_LO_RX_EN (RX) + 16 + 8 + read-write + + + SY_LO_RX_EN_RX_LO + De-assertion time setting for SY_LO_RX_EN (RX) + 24 + 8 + read-write + + + + + TIMING23 + TSM_TIMING23 + 0x8C + 32 + read-write + 0xFFFF6A04 + 0xFFFFFFFF + + + SY_LO_TX_EN_TX_HI + Assertion time setting for SY_LO_TX_EN (TX) + 0 + 8 + read-write + + + SY_LO_TX_EN_TX_LO + De-assertion time setting for SY_LO_TX_EN (TX) + 8 + 8 + read-write + + + + + TIMING24 + TSM_TIMING24 + 0x90 + 32 + read-write + 0x16004A00 + 0xFFFFFFFF + + + SY_DIVN_CAL_EN_TX_HI + Assertion time setting for SY_DIVN_CAL_EN (TX) + 0 + 8 + read-write + + + SY_DIVN_CAL_EN_TX_LO + De-assertion time setting for SY_DIVN_CAL_EN (TX) + 8 + 8 + read-write + + + SY_DIVN_CAL_EN_RX_HI + Assertion time setting for SY_DIVN_CAL_EN (RX) + 16 + 8 + read-write + + + SY_DIVN_CAL_EN_RX_LO + De-assertion time setting for SY_DIVN_CAL_EN (RX) + 24 + 8 + read-write + + + + + TIMING25 + TSM_TIMING25 + 0x94 + 32 + read-write + 0x671BFFFF + 0xFFFFFFFF + + + RX_LNA_MIXER_EN_RX_HI + Assertion time setting for RX_LNA_MIXER_EN (RX) + 16 + 8 + read-write + + + RX_LNA_MIXER_EN_RX_LO + De-assertion time setting for RX_LNA_MIXER_EN (RX) + 24 + 8 + read-write + + + + + TIMING27 + TSM_TIMING27 + 0x9C + 32 + read-write + 0x671EFFFF + 0xFFFFFFFF + + + RX_ADC_I_Q_EN_RX_HI + Assertion time setting for RX_ADC_I_Q_EN (RX) + 16 + 8 + read-write + + + RX_ADC_I_Q_EN_RX_LO + De-assertion time setting for RX_ADC_I_Q_EN (RX) + 24 + 8 + read-write + + + + + TIMING28 + TSM_TIMING28 + 0xA0 + 32 + read-write + 0x1F1EFFFF + 0xFFFFFFFF + + + RX_ADC_RESET_EN_RX_HI + Assertion time setting for RX_ADC_RESET_EN (RX) + 16 + 8 + read-write + + + RX_ADC_RESET_EN_RX_LO + De-assertion time setting for RX_ADC_RESET_EN (RX) + 24 + 8 + read-write + + + + + TIMING29 + TSM_TIMING29 + 0xA4 + 32 + read-write + 0x671CFFFF + 0xFFFFFFFF + + + RX_BBA_I_Q_EN_RX_HI + Assertion time setting for RX_BBA_I_Q_EN (RX) + 16 + 8 + read-write + + + RX_BBA_I_Q_EN_RX_LO + De-assertion time setting for RX_BBA_I_Q_EN (RX) + 24 + 8 + read-write + + + + + TIMING30 + TSM_TIMING30 + 0xA8 + 32 + read-write + 0x671EFFFF + 0xFFFFFFFF + + + RX_BBA_PDET_EN_RX_HI + Assertion time setting for RX_BBA_PDET_EN (RX) + 16 + 8 + read-write + + + RX_BBA_PDET_EN_RX_LO + De-assertion time setting for RX_BBA_PDET_EN (RX) + 24 + 8 + read-write + + + + + TIMING31 + TSM_TIMING31 + 0xAC + 32 + read-write + 0x671DFFFF + 0xFFFFFFFF + + + RX_BBA_TZA_DCOC_EN_RX_HI + Assertion time setting for RX_BBA_TZA_DCOC_EN (RX) + 16 + 8 + read-write + + + RX_BBA_TZA_DCOC_EN_RX_LO + De-assertion time setting for RX_BBA_TZA_DCOC_EN (RX) + 24 + 8 + read-write + + + + + TIMING32 + TSM_TIMING32 + 0xB0 + 32 + read-write + 0x671BFFFF + 0xFFFFFFFF + + + RX_TZA_I_Q_EN_RX_HI + Assertion time setting for RX_TZA_I_Q_EN (RX) + 16 + 8 + read-write + + + RX_TZA_I_Q_EN_RX_LO + De-assertion time setting for RX_TZA_I_Q_EN (RX) + 24 + 8 + read-write + + + + + TIMING33 + TSM_TIMING33 + 0xB4 + 32 + read-write + 0x671EFFFF + 0xFFFFFFFF + + + RX_TZA_PDET_EN_RX_HI + Assertion time setting for RX_TZA_PDET_EN (RX) + 16 + 8 + read-write + + + RX_TZA_PDET_EN_RX_LO + De-assertion time setting for RX_TZA_PDET_EN (RX) + 24 + 8 + read-write + + + + + TIMING34 + TSM_TIMING34 + 0xB8 + 32 + read-write + 0x67056A05 + 0xFFFFFFFF + + + PLL_DIG_EN_TX_HI + Assertion time setting for PLL_DIG_EN (TX) + 0 + 8 + read-write + + + PLL_DIG_EN_TX_LO + De-assertion time setting for PLL_DIG_EN (TX) + 8 + 8 + read-write + + + PLL_DIG_EN_RX_HI + Assertion time setting for PLL_DIG_EN (RX) + 16 + 8 + read-write + + + PLL_DIG_EN_RX_LO + De-assertion time setting for PLL_DIG_EN (RX) + 24 + 8 + read-write + + + + + TIMING35 + TSM_TIMING35 + 0xBC + 32 + read-write + 0xFFFF6A5D + 0xFFFFFFFF + + + TX_DIG_EN_TX_HI + Assertion time setting for TX_DIG_EN (TX) + 0 + 8 + read-write + + + TX_DIG_EN_TX_LO + De-assertion time setting for TX_DIG_EN (TX) + 8 + 8 + read-write + + + + + TIMING36 + TSM_TIMING36 + 0xC0 + 32 + read-write + 0x6764FFFF + 0xFFFFFFFF + + + RX_DIG_EN_RX_HI + Assertion time setting for RX_DIG_EN (RX) + 16 + 8 + read-write + + + RX_DIG_EN_RX_LO + De-assertion time setting for RX_DIG_EN (RX) + 24 + 8 + read-write + + + + + TIMING37 + TSM_TIMING37 + 0xC4 + 32 + read-write + 0x6564FFFF + 0xFFFFFFFF + + + RX_INIT_RX_HI + Assertion time setting for RX_INIT (RX) + 16 + 8 + read-write + + + RX_INIT_RX_LO + De-assertion time setting for RX_INIT (RX) + 24 + 8 + read-write + + + + + TIMING38 + TSM_TIMING38 + 0xC8 + 32 + read-write + 0x670C6A40 + 0xFFFFFFFF + + + SIGMA_DELTA_EN_TX_HI + Assertion time setting for SIGMA_DELTA_EN (TX) + 0 + 8 + read-write + + + SIGMA_DELTA_EN_TX_LO + De-assertion time setting for SIGMA_DELTA_EN (TX) + 8 + 8 + read-write + + + SIGMA_DELTA_EN_RX_HI + Assertion time setting for SIGMA_DELTA_EN (RX) + 16 + 8 + read-write + + + SIGMA_DELTA_EN_RX_LO + De-assertion time setting for SIGMA_DELTA_EN (RX) + 24 + 8 + read-write + + + + + TIMING39 + TSM_TIMING39 + 0xCC + 32 + read-write + 0x6764FFFF + 0xFFFFFFFF + + + RX_PHY_EN_RX_HI + Assertion time setting for RX_PHY_EN (RX) + 16 + 8 + read-write + + + RX_PHY_EN_RX_LO + De-assertion time setting for RX_PHY_EN (RX) + 24 + 8 + read-write + + + + + TIMING40 + TSM_TIMING40 + 0xD0 + 32 + read-write + 0x6724FFFF + 0xFFFFFFFF + + + DCOC_EN_RX_HI + Assertion time setting for DCOC_EN (RX) + 16 + 8 + read-write + + + DCOC_EN_RX_LO + De-assertion time setting for DCOC_EN (RX) + 24 + 8 + read-write + + + + + TIMING41 + TSM_TIMING41 + 0xD4 + 32 + read-write + 0x2524FFFF + 0xFFFFFFFF + + + DCOC_INIT_RX_HI + Assertion time setting for DCOC_INIT (RX) + 16 + 8 + read-write + + + DCOC_INIT_RX_LO + De-assertion time setting for DCOC_INIT (RX) + 24 + 8 + read-write + + + + + TIMING42 + TSM_TIMING42 + 0xD8 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + SAR_ADC_TRIG_EN_TX_HI + Assertion time setting for SAR_ADC_TRIG_EN (TX) + 0 + 8 + read-write + + + SAR_ADC_TRIG_EN_TX_LO + De-assertion time setting for SAR_ADC_TRIG_EN (TX) + 8 + 8 + read-write + + + SAR_ADC_TRIG_EN_RX_HI + Assertion time setting for SAR_ADC_TRIG_EN (RX) + 16 + 8 + read-write + + + SAR_ADC_TRIG_EN_RX_LO + De-assertion time setting for SAR_ADC_TRIG_EN (RX) + 24 + 8 + read-write + + + + + TIMING43 + TSM_TIMING43 + 0xDC + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + TSM_SPARE0_EN_TX_HI + Assertion time setting for TSM_SPARE0_EN (TX) + 0 + 8 + read-write + + + TSM_SPARE0_EN_TX_LO + De-assertion time setting for TSM_SPARE0_EN (TX) + 8 + 8 + read-write + + + TSM_SPARE0_EN_RX_HI + Assertion time setting for TSM_SPARE0_EN (RX) + 16 + 8 + read-write + + + TSM_SPARE0_EN_RX_LO + De-assertion time setting for TSM_SPARE0_EN (RX) + 24 + 8 + read-write + + + + + TIMING44 + TSM_TIMING44 + 0xE0 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + TSM_SPARE1_EN_TX_HI + Assertion time setting for TSM_SPARE1_EN (TX) + 0 + 8 + read-write + + + TSM_SPARE1_EN_TX_LO + De-assertion time setting for TSM_SPARE1_EN (TX) + 8 + 8 + read-write + + + TSM_SPARE1_EN_RX_HI + Assertion time setting for TSM_SPARE1_EN (RX) + 16 + 8 + read-write + + + TSM_SPARE1_EN_RX_LO + De-assertion time setting for TSM_SPARE1_EN (RX) + 24 + 8 + read-write + + + + + TIMING45 + TSM_TIMING45 + 0xE4 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + TSM_SPARE2_EN_TX_HI + Assertion time setting for TSM_SPARE2_EN (TX) + 0 + 8 + read-write + + + TSM_SPARE2_EN_TX_LO + De-assertion time setting for TSM_SPARE2_EN (TX) + 8 + 8 + read-write + + + TSM_SPARE2_EN_RX_HI + Assertion time setting for TSM_SPARE2_EN (RX) + 16 + 8 + read-write + + + TSM_SPARE2_EN_RX_LO + De-assertion time setting for TSM_SPARE2_EN (RX) + 24 + 8 + read-write + + + + + TIMING46 + TSM_TIMING46 + 0xE8 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + TSM_SPARE3_EN_TX_HI + Assertion time setting for TSM_SPARE3_EN (TX) + 0 + 8 + read-write + + + TSM_SPARE3_EN_TX_LO + De-assertion time setting for TSM_SPARE3_EN (TX) + 8 + 8 + read-write + + + TSM_SPARE3_EN_RX_HI + Assertion time setting for TSM_SPARE3_EN (RX) + 16 + 8 + read-write + + + TSM_SPARE3_EN_RX_LO + De-assertion time setting for TSM_SPARE3_EN (RX) + 24 + 8 + read-write + + + + + TIMING47 + TSM_TIMING47 + 0xEC + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + GPIO0_TRIG_EN_TX_HI + Assertion time setting for GPIO0_TRIG_EN (TX) + 0 + 8 + read-write + + + GPIO0_TRIG_EN_TX_LO + De-assertion time setting for GPIO0_TRIG_EN (TX) + 8 + 8 + read-write + + + GPIO0_TRIG_EN_RX_HI + Assertion time setting for GPIO0_TRIG_EN (RX) + 16 + 8 + read-write + + + GPIO0_TRIG_EN_RX_LO + De-assertion time setting for GPIO0_TRIG_EN (RX) + 24 + 8 + read-write + + + + + TIMING48 + TSM_TIMING48 + 0xF0 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + GPIO1_TRIG_EN_TX_HI + Assertion time setting for GPIO1_TRIG_EN (TX) + 0 + 8 + read-write + + + GPIO1_TRIG_EN_TX_LO + De-assertion time setting for GPIO1_TRIG_EN (TX) + 8 + 8 + read-write + + + GPIO1_TRIG_EN_RX_HI + Assertion time setting for GPIO1_TRIG_EN (RX) + 16 + 8 + read-write + + + GPIO1_TRIG_EN_RX_LO + De-assertion time setting for GPIO1_TRIG_EN (RX) + 24 + 8 + read-write + + + + + TIMING49 + TSM_TIMING49 + 0xF4 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + GPIO2_TRIG_EN_TX_HI + Assertion time setting for GPIO2_TRIG_EN (TX) + 0 + 8 + read-write + + + GPIO2_TRIG_EN_TX_LO + De-assertion time setting for GPIO2_TRIG_EN (TX) + 8 + 8 + read-write + + + GPIO2_TRIG_EN_RX_HI + Assertion time setting for GPIO2_TRIG_EN (RX) + 16 + 8 + read-write + + + GPIO2_TRIG_EN_RX_LO + De-assertion time setting for GPIO2_TRIG_EN (RX) + 24 + 8 + read-write + + + + + TIMING50 + TSM_TIMING50 + 0xF8 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + GPIO3_TRIG_EN_TX_HI + Assertion time setting for GPIO3_TRIG_EN (TX) + 0 + 8 + read-write + + + GPIO3_TRIG_EN_TX_LO + De-assertion time setting for GPIO3_TRIG_EN (TX) + 8 + 8 + read-write + + + GPIO3_TRIG_EN_RX_HI + Assertion time setting for GPIO3_TRIG_EN (RX) + 16 + 8 + read-write + + + GPIO3_TRIG_EN_RX_LO + De-assertion time setting for GPIO3_TRIG_EN (RX) + 24 + 8 + read-write + + + + + TIMING51 + TSM_TIMING51 + 0xFC + 32 + read-write + 0x6703FFFF + 0xFFFFFFFF + + + RXTX_AUXPLL_BIAS_EN_RX_HI + Assertion time setting for RXTX_AUXPLL_BIAS_EN (RX) + 16 + 8 + read-write + + + RXTX_AUXPLL_BIAS_EN_RX_LO + De-assertion time setting for RXTX_AUXPLL_BIAS_EN (RX) + 24 + 8 + read-write + + + + + TIMING52 + TSM_TIMING52 + 0x100 + 32 + read-write + 0x1504FFFF + 0xFFFFFFFF + + + RXTX_AUXPLL_FCAL_EN_RX_HI + Assertion time setting for RXTX_AUXPLL_FCAL_EN (RX) + 16 + 8 + read-write + + + RXTX_AUXPLL_FCAL_EN_RX_LO + De-assertion time setting for RXTX_AUXPLL_FCAL_EN (RX) + 24 + 8 + read-write + + + + + TIMING53 + TSM_TIMING53 + 0x104 + 32 + read-write + 0x6704FFFF + 0xFFFFFFFF + + + RXTX_AUXPLL_LF_PD_EN_RX_HI + Assertion time setting for RXTX_AUXPLL_LF_PD_EN (RX) + 16 + 8 + read-write + + + RXTX_AUXPLL_LF_PD_EN_RX_LO + De-assertion time setting for RXTX_AUXPLL_LF_PD_EN (RX) + 24 + 8 + read-write + + + + + TIMING54 + TSM_TIMING54 + 0x108 + 32 + read-write + 0x1504FFFF + 0xFFFFFFFF + + + RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_RX_HI + Assertion time setting for RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN (RX) + 16 + 8 + read-write + + + RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_RX_LO + De-assertion time setting for RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN (RX) + 24 + 8 + read-write + + + + + TIMING55 + TSM_TIMING55 + 0x10C + 32 + read-write + 0x671EFFFF + 0xFFFFFFFF + + + RXTX_AUXPLL_ADC_BUF_EN_RX_HI + Assertion time setting for RXTX_AUXPLL_ADC_BUF_EN (RX) + 16 + 8 + read-write + + + RXTX_AUXPLL_ADC_BUF_EN_RX_LO + De-assertion time setting for RXTX_AUXPLL_ADC_BUF_EN (RX) + 24 + 8 + read-write + + + + + TIMING56 + TSM_TIMING56 + 0x110 + 32 + read-write + 0x671EFFFF + 0xFFFFFFFF + + + RXTX_AUXPLL_DIG_BUF_EN_RX_HI + Assertion time setting for RXTX_AUXPLL_DIG_BUF_EN (RX) + 16 + 8 + read-write + + + RXTX_AUXPLL_DIG_BUF_EN_RX_LO + De-assertion time setting for RXTX_AUXPLL_DIG_BUF_EN (RX) + 24 + 8 + read-write + + + + + TIMING57 + TSM_TIMING57 + 0x114 + 32 + read-write + 0x1A03FFFF + 0xFFFFFFFF + + + RXTX_RCCAL_EN_RX_HI + Assertion time setting for RXTX_RCCAL_EN (RX) + 16 + 8 + read-write + + + RXTX_RCCAL_EN_RX_LO + De-assertion time setting for RXTX_RCCAL_EN (RX) + 24 + 8 + read-write + + + + + TIMING58 + TSM_TIMING58 + 0x118 + 32 + read-write + 0xFFFF6A03 + 0xFFFFFFFF + + + TX_HPM_DAC_EN_TX_HI + Assertion time setting for TX_HPM_DAC_EN (TX) + 0 + 8 + read-write + + + TX_HPM_DAC_EN_TX_LO + De-assertion time setting for TX_HPM_DAC_EN (TX) + 8 + 8 + read-write + + + + + OVRD0 + TSM OVERRIDE REGISTER 0 + 0x11C + 32 + read-write + 0 + 0xFFFFFFFF + + + BB_LDO_HF_EN_OVRD_EN + Override control for BB_LDO_HF_EN + 0 + 1 + read-write + + + 0 + Normal operation. + #0 + + + 1 + Use the state of BB_LDO_HF_EN_OVRD to override the signal "bb_ldo_hf_en". + #1 + + + + + BB_LDO_HF_EN_OVRD + Override value for BB_LDO_HF_EN + 1 + 1 + read-write + + + BB_LDO_ADCDAC_EN_OVRD_EN + Override control for BB_LDO_ADCDAC_EN + 2 + 1 + read-write + + + 0 + Normal operation. + #0 + + + 1 + Use the state of BB_LDO_ADCDAC_EN_OVRD to override the signal "bb_ldo_adcdac_en". + #1 + + + + + BB_LDO_ADCDAC_EN_OVRD + Override value for BB_LDO_ADCDAC_EN + 3 + 1 + read-write + + + BB_LDO_BBA_EN_OVRD_EN + Override control for BB_LDO_BBA_EN + 4 + 1 + read-write + + + 0 + Normal operation. + #0 + + + 1 + Use the state of BB_LDO_BBA_EN_OVRD to override the signal "bb_ldo_bba_en". + #1 + + + + + BB_LDO_BBA_EN_OVRD + Override value for BB_LDO_BBA_EN + 5 + 1 + read-write + + + BB_LDO_PD_EN_OVRD_EN + Override control for BB_LDO_PD_EN + 6 + 1 + read-write + + + 0 + Normal operation. + #0 + + + 1 + Use the state of BB_LDO_PD_EN_OVRD to override the signal "bb_ldo_pd_en". + #1 + + + + + BB_LDO_PD_EN_OVRD + Override value for BB_LDO_PD_EN + 7 + 1 + read-write + + + BB_LDO_FDBK_EN_OVRD_EN + Override control for BB_LDO_FDBK_EN + 8 + 1 + read-write + + + 0 + Normal operation. + #0 + + + 1 + Use the state of BB_LDO_FDBK_EN_OVRD to override the signal "bb_ldo_fdbk_en". + #1 + + + + + BB_LDO_FDBK_EN_OVRD + Override value for BB_LDO_FDBK_EN + 9 + 1 + read-write + + + BB_LDO_VCOLO_EN_OVRD_EN + Override control for BB_LDO_VCOLO_EN + 10 + 1 + read-write + + + 0 + Normal operation. + #0 + + + 1 + Use the state of BB_LDO_VCOLO_EN_OVRD to override the signal "bb_ldo_vcolo_en". + #1 + + + + + BB_LDO_VCOLO_EN_OVRD + Override value for BB_LDO_VCOLO_EN + 11 + 1 + read-write + + + BB_LDO_VTREF_EN_OVRD_EN + Override control for BB_LDO_VTREF_EN + 12 + 1 + read-write + + + 0 + Normal operation. + #0 + + + 1 + Use the state of BB_LDO_VTREF_EN_OVRD to override the signal "bb_ldo_vtref_en". + #1 + + + + + BB_LDO_VTREF_EN_OVRD + Override value for BB_LDO_VTREF_EN + 13 + 1 + read-write + + + BB_LDO_FDBK_BLEED_EN_OVRD_EN + Override control for BB_LDO_FDBK_BLEED_EN + 14 + 1 + read-write + + + 0 + Normal operation. + #0 + + + 1 + Use the state of BB_LDO_FDBK_BLEED_EN_OVRD to override the signal "bb_ldo_fdbk_bleed_en". + #1 + + + + + BB_LDO_FDBK_BLEED_EN_OVRD + Override value for BB_LDO_FDBK_BLEED_EN + 15 + 1 + read-write + + + BB_LDO_VCOLO_BLEED_EN_OVRD_EN + Override control for BB_LDO_VCOLO_BLEED_EN + 16 + 1 + read-write + + + 0 + Normal operation. + #0 + + + 1 + Use the state of BB_LDO_VCOLO_BLEED_EN_OVRD to override the signal "bb_ldo_vcolo_bleed_en". + #1 + + + + + BB_LDO_VCOLO_BLEED_EN_OVRD + Override value for BB_LDO_VCOLO_BLEED_EN + 17 + 1 + read-write + + + BB_LDO_VCOLO_FASTCHARGE_EN_OVRD_EN + Override control for BB_LDO_VCOLO_FASTCHARGE_EN + 18 + 1 + read-write + + + 0 + Normal operation. + #0 + + + 1 + Use the state of BB_LDO_VCOLO_FASTCHARGE_EN_OVRD to override the signal "bb_ldo_vcolo_fastcharge_en". + #1 + + + + + BB_LDO_VCOLO_FASTCHARGE_EN_OVRD + Override value for BB_LDO_VCOLO_FASTCHARGE_EN + 19 + 1 + read-write + + + BB_XTAL_PLL_REF_CLK_EN_OVRD_EN + Override control for BB_XTAL_PLL_REF_CLK_EN + 20 + 1 + read-write + + + 0 + Normal operation. + #0 + + + 1 + Use the state of BB_XTAL_PLL_REF_CLK_EN_OVRD to override the signal "bb_xtal_pll_ref_clk_en". + #1 + + + + + BB_XTAL_PLL_REF_CLK_EN_OVRD + Override value for BB_XTAL_PLL_REF_CLK_EN + 21 + 1 + read-write + + + BB_XTAL_DAC_REF_CLK_EN_OVRD_EN + Override control for BB_XTAL_DAC_REF_CLK_EN + 22 + 1 + read-write + + + 0 + Normal operation. + #0 + + + 1 + Use the state of BB_XTAL_DAC_REF_CLK_EN_OVRD to override the signal "bb_xtal_dac_ref_clk_en". + #1 + + + + + BB_XTAL_DAC_REF_CLK_EN_OVRD + Override value for BB_XTAL_DAC_REF_CLK_EN + 23 + 1 + read-write + + + BB_XTAL_AUXPLL_REF_CLK_EN_OVRD_EN + Override control for BB_XTAL_AUXPLL_REF_CLK_EN + 24 + 1 + read-write + + + 0 + Normal operation. + #0 + + + 1 + Use the state of BB_XTAL_AUXPLL_REF_CLK_EN_OVRD to override the signal "bb_xtal_auxpll_ref_clk_en". + #1 + + + + + BB_XTAL_AUXPLL_REF_CLK_EN_OVRD + Override value for BB_XTAL_AUXPLL_REF_CLK_EN + 25 + 1 + read-write + + + PLL_LOOP_IS_OPEN_OVRD_EN + Override control for PLL_LOOP_IS_OPEN + 26 + 1 + read-write + + + 0 + Normal operation. + #0 + + + 1 + Use the state of PLL_LOOP_IS_OPEN_OVRD to override the signal "pll_loop_is_open". + #1 + + + + + PLL_LOOP_IS_OPEN_OVRD + Override value for PLL_LOOP_IS_OPEN + 27 + 1 + read-write + + + SY_PD_CYCLE_SLIP_LD_EN_OVRD_EN + Override control for SY_PD_CYCLE_SLIP_LD_EN + 28 + 1 + read-write + + + 0 + Normal operation. + #0 + + + 1 + Use the state of SY_PD_CYCLE_SLIP_LD_EN_OVRD to override the signal "sy_pd_cycle_slip_ld_en". + #1 + + + + + SY_PD_CYCLE_SLIP_LD_EN_OVRD + Override value for SY_PD_CYCLE_SLIP_LD_EN + 29 + 1 + read-write + + + SY_VCO_EN_OVRD_EN + Override control for SY_VCO_EN + 30 + 1 + read-write + + + 0 + Normal operation. + #0 + + + 1 + Use the state of SY_VCO_EN_OVRD to override the signal "sy_vco_en". + #1 + + + + + SY_VCO_EN_OVRD + Override value for SY_VCO_EN + 31 + 1 + read-write + + + + + OVRD1 + TSM OVERRIDE REGISTER 1 + 0x120 + 32 + read-write + 0 + 0xFFFFFFFF + + + SY_LO_RX_BUF_EN_OVRD_EN + Override control for SY_LO_RX_BUF_EN + 0 + 1 + read-write + + + 0 + Normal operation. + #0 + + + 1 + Use the state of SY_LO_RX_BUF_EN_OVRD to override the signal "sy_lo_rx_buf_en". + #1 + + + + + SY_LO_RX_BUF_EN_OVRD + Override value for SY_LO_RX_BUF_EN + 1 + 1 + read-write + + + SY_LO_TX_BUF_EN_OVRD_EN + Override control for SY_LO_TX_BUF_EN + 2 + 1 + read-write + + + 0 + Normal operation. + #0 + + + 1 + Use the state of SY_LO_TX_BUF_EN_OVRD to override the signal "sy_lo_tx_buf_en". + #1 + + + + + SY_LO_TX_BUF_EN_OVRD + Override value for SY_LO_TX_BUF_EN + 3 + 1 + read-write + + + SY_DIVN_EN_OVRD_EN + Override control for SY_DIVN_EN + 4 + 1 + read-write + + + 0 + Normal operation. + #0 + + + 1 + Use the state of SY_DIVN_EN_OVRD to override the signal "sy_divn_en". + #1 + + + + + SY_DIVN_EN_OVRD + Override value for SY_DIVN_EN + 5 + 1 + read-write + + + SY_PD_FILTER_CHARGE_EN_OVRD_EN + Override control for SY_PD_FILTER_CHARGE_EN + 6 + 1 + read-write + + + 0 + Normal operation. + #0 + + + 1 + Use the state of SY_PD_FILTER_CHARGE_EN_OVRD to override the signal "sy_pd_filter_charge_en". + #1 + + + + + SY_PD_FILTER_CHARGE_EN_OVRD + Override value for SY_PD_FILTER_CHARGE_EN + 7 + 1 + read-write + + + SY_PD_EN_OVRD_EN + Override control for SY_PD_EN + 8 + 1 + read-write + + + 0 + Normal operation. + #0 + + + 1 + Use the state of SY_PD_EN_OVRD to override the signal "sy_pd_en". + #1 + + + + + SY_PD_EN_OVRD + Override value for SY_PD_EN + 9 + 1 + read-write + + + SY_LO_DIVN_EN_OVRD_EN + Override control for SY_LO_DIVN_EN + 10 + 1 + read-write + + + 0 + Normal operation. + #0 + + + 1 + Use the state of SY_LO_DIVN_EN_OVRD to override the signal "sy_lo_divn_en". + #1 + + + + + SY_LO_DIVN_EN_OVRD + Override value for SY_LO_DIVN_EN + 11 + 1 + read-write + + + SY_LO_RX_EN_OVRD_EN + Override control for SY_LO_RX_EN + 12 + 1 + read-write + + + 0 + Normal operation. + #0 + + + 1 + Use the state of SY_LO_RX_EN_OVRD to override the signal "sy_lo_rx_en". + #1 + + + + + SY_LO_RX_EN_OVRD + Override value for SY_LO_RX_EN + 13 + 1 + read-write + + + SY_LO_TX_EN_OVRD_EN + Override control for SY_LO_TX_EN + 14 + 1 + read-write + + + 0 + Normal operation. + #0 + + + 1 + Use the state of SY_LO_TX_EN_OVRD to override the signal "sy_lo_tx_en". + #1 + + + + + SY_LO_TX_EN_OVRD + Override value for SY_LO_TX_EN + 15 + 1 + read-write + + + SY_DIVN_CAL_EN_OVRD_EN + Override control for SY_DIVN_CAL_EN + 16 + 1 + read-write + + + 0 + Normal operation. + #0 + + + 1 + Use the state of SY_DIVN_CAL_EN_OVRD to override the signal "sy_divn_cal_en". + #1 + + + + + SY_DIVN_CAL_EN_OVRD + Override value for SY_DIVN_CAL_EN + 17 + 1 + read-write + + + RX_MIXER_EN_OVRD_EN + Override control for RX_MIXER_EN + 18 + 1 + read-write + + + 0 + Normal operation. + #0 + + + 1 + Use the state of RX_MIXER_EN_OVRD to override the signal "rx_mixer_en". + #1 + + + + + RX_MIXER_EN_OVRD + Override value for RX_MIXER_EN + 19 + 1 + read-write + + + RX_ADC_I_EN_OVRD_EN + Override control for RX_ADC_I_EN + 22 + 1 + read-write + + + 0 + Normal operation. + #0 + + + 1 + Use the state of RX_ADC_I_EN_OVRD to override the signal "rx_adc_i_en". + #1 + + + + + RX_ADC_I_EN_OVRD + Override value for RX_ADC_I_EN + 23 + 1 + read-write + + + RX_ADC_Q_EN_OVRD_EN + Override control for RX_ADC_Q_EN + 24 + 1 + read-write + + + 0 + Normal operation. + #0 + + + 1 + Use the state of RX_ADC_Q_EN_OVRD to override the signal "rx_adc_q_en". + #1 + + + + + RX_ADC_Q_EN_OVRD + Override value for RX_ADC_Q_EN + 25 + 1 + read-write + + + RX_ADC_RESET_EN_OVRD_EN + Override control for RX_ADC_RESET_EN + 26 + 1 + read-write + + + 0 + Normal operation. + #0 + + + 1 + Use the state of RX_ADC_RESET_EN_OVRD to override the signal "rx_adc_reset_en". + #1 + + + + + RX_ADC_RESET_EN_OVRD + Override value for RX_ADC_RESET_EN + 27 + 1 + read-write + + + RX_BBA_I_EN_OVRD_EN + Override control for RX_BBA_I_EN + 28 + 1 + read-write + + + 0 + Normal operation. + #0 + + + 1 + Use the state of RX_BBA_I_EN_OVRD to override the signal "rx_bba_i_en". + #1 + + + + + RX_BBA_I_EN_OVRD + Override value for RX_BBA_I_EN + 29 + 1 + read-write + + + RX_BBA_Q_EN_OVRD_EN + Override control for RX_BBA_Q_EN + 30 + 1 + read-write + + + 0 + Normal operation. + #0 + + + 1 + Use the state of RX_BBA_Q_EN_OVRD to override the signal "rx_bba_q_en". + #1 + + + + + RX_BBA_Q_EN_OVRD + Override value for RX_BBA_Q_EN + 31 + 1 + read-write + + + + + OVRD2 + TSM OVERRIDE REGISTER 2 + 0x124 + 32 + read-write + 0 + 0xFFFFFFFF + + + RX_BBA_PDET_EN_OVRD_EN + Override control for RX_BBA_PDET_EN + 0 + 1 + read-write + + + 0 + Normal operation. + #0 + + + 1 + Use the state of RX_BBA_PDET_EN_OVRD to override the signal "rx_bba_pdet_en". + #1 + + + + + RX_BBA_PDET_EN_OVRD + Override value for RX_BBA_PDET_EN + 1 + 1 + read-write + + + RX_BBA_DCOC_EN_OVRD_EN + Override control for RX_BBA_DCOC_EN + 2 + 1 + read-write + + + 0 + Normal operation. + #0 + + + 1 + Use the state of RX_BBA_DCOC_EN_OVRD to override the signal "rx_bba_dcoc_en". + #1 + + + + + RX_BBA_DCOC_EN_OVRD + Override value for RX_BBA_DCOC_EN + 3 + 1 + read-write + + + RX_LNA_EN_OVRD_EN + Override control for RX_LNA_EN + 4 + 1 + read-write + + + 0 + Normal operation. + #0 + + + 1 + Use the state of RX_LNA_EN_OVRD to override the signal "rx_lna_en". + #1 + + + + + RX_LNA_EN_OVRD + Override value for RX_LNA_EN + 5 + 1 + read-write + + + RX_TZA_I_EN_OVRD_EN + Override control for RX_TZA_I_EN + 6 + 1 + read-write + + + 0 + Normal operation. + #0 + + + 1 + Use the state of RX_TZA_I_EN_OVRD to override the signal "rx_tza_i_en". + #1 + + + + + RX_TZA_I_EN_OVRD + Override value for RX_TZA_I_EN + 7 + 1 + read-write + + + RX_TZA_Q_EN_OVRD_EN + Override control for RX_TZA_Q_EN + 8 + 1 + read-write + + + 0 + Normal operation. + #0 + + + 1 + Use the state of RX_TZA_Q_EN_OVRD to override the signal "rx_tza_q_en". + #1 + + + + + RX_TZA_Q_EN_OVRD + Override value for RX_TZA_Q_EN + 9 + 1 + read-write + + + RX_TZA_PDET_EN_OVRD_EN + Override control for RX_TZA_PDET_EN + 10 + 1 + read-write + + + 0 + Normal operation. + #0 + + + 1 + Use the state of RX_TZA_PDET_EN_OVRD to override the signal "rx_tza_pdet_en". + #1 + + + + + RX_TZA_PDET_EN_OVRD + Override value for RX_TZA_PDET_EN + 11 + 1 + read-write + + + RX_TZA_DCOC_EN_OVRD_EN + Override control for RX_TZA_DCOC_EN + 12 + 1 + read-write + + + 0 + Normal operation. + #0 + + + 1 + Use the state of RX_TZA_DCOC_EN_OVRD to override the signal "rx_tza_dcoc_en". + #1 + + + + + RX_TZA_DCOC_EN_OVRD + Override control for RX_TZA_DCOC_EN + 13 + 1 + read-write + + + 0 + Normal operation. + #0 + + + 1 + Use the state of RX_TZA_DCOC_EN_OVRD to override the signal "rx_tza_dcoc_en". + #1 + + + + + PLL_DIG_EN_OVRD_EN + Override control for PLL_DIG_EN + 14 + 1 + read-write + + + 0 + Normal operation. + #0 + + + 1 + Use the state of PLL_DIG_EN_OVRD to override the signal "pll_dig_en". + #1 + + + + + PLL_DIG_EN_OVRD + Override value for PLL_DIG_EN + 15 + 1 + read-write + + + TX_DIG_EN_OVRD_EN + Override control for TX_DIG_EN + 16 + 1 + read-write + + + 0 + Normal operation. + #0 + + + 1 + Use the state of TX_DIG_EN_OVRD to override the signal "tx_dig_en". + #1 + + + + + TX_DIG_EN_OVRD + Override value for TX_DIG_EN + 17 + 1 + read-write + + + RX_DIG_EN_OVRD_EN + Override control for RX_DIG_EN + 18 + 1 + read-write + + + 0 + Normal operation. + #0 + + + 1 + Use the state of RX_DIG_EN_OVRD to override the signal "rx_dig_en". + #1 + + + + + RX_DIG_EN_OVRD + Override value for RX_DIG_EN + 19 + 1 + read-write + + + RX_INIT_OVRD_EN + Override control for RX_INIT + 20 + 1 + read-write + + + 0 + Normal operation. + #0 + + + 1 + Use the state of RX_INIT_OVRD to override the signal "rx_init". + #1 + + + + + RX_INIT_OVRD + Override value for RX_INIT + 21 + 1 + read-write + + + SIGMA_DELTA_EN_OVRD_EN + Override control for SIGMA_DELTA_EN + 22 + 1 + read-write + + + 0 + Normal operation. + #0 + + + 1 + Use the state of SIGMA_DELTA_EN_OVRD to override the signal "sigma_delta_en". + #1 + + + + + SIGMA_DELTA_EN_OVRD + Override value for SIGMA_DELTA_EN + 23 + 1 + read-write + + + RX_PHY_EN_OVRD_EN + Override control for RX_PHY_EN + 24 + 1 + read-write + + + 0 + Normal operation. + #0 + + + 1 + Use the state of RX_PHY_EN_OVRD to override the signal "rx_phy_en". + #1 + + + + + RX_PHY_EN_OVRD + Override value for RX_PHY_EN + 25 + 1 + read-write + + + DCOC_EN_OVRD_EN + Override control for DCOC_EN + 26 + 1 + read-write + + + 0 + Normal operation. + #0 + + + 1 + Use the state of DCOC_EN_OVRD to override the signal "dcoc_en". + #1 + + + + + DCOC_EN_OVRD + Override value for DCOC_EN + 27 + 1 + read-write + + + DCOC_INIT_OVRD_EN + Override control for DCOC_INIT + 28 + 1 + read-write + + + 0 + Normal operation. + #0 + + + 1 + Use the state of DCOC_INIT_OVRD to override the signal "dcoc_init". + #1 + + + + + DCOC_INIT_OVRD + Override value for DCOC_INIT + 29 + 1 + read-write + + + FREQ_TARG_LD_EN_OVRD_EN + Override control for FREQ_TARG_LD_EN + 30 + 1 + read-write + + + 0 + Normal operation. + #0 + + + 1 + Use the state of FREQ_TARG_LD_EN_OVRD to override the signal "freq_targ_ld_en". + #1 + + + + + FREQ_TARG_LD_EN_OVRD + Override value for FREQ_TARG_LD_EN + 31 + 1 + read-write + + + + + OVRD3 + TSM OVERRIDE REGISTER 3 + 0x128 + 32 + read-write + 0 + 0xFFFFFFFF + + + TSM_SPARE0_EN_OVRD_EN + Override control for TSM_SPARE0_EN + 0 + 1 + read-write + + + 0 + Normal operation. + #0 + + + 1 + Use the state of TSM_SPARE0_EN_OVRD to override the signal "tsm_spare0_en". + #1 + + + + + TSM_SPARE0_EN_OVRD + Override value for TSM_SPARE0_EN + 1 + 1 + read-write + + + TSM_SPARE1_EN_OVRD_EN + Override control for TSM_SPARE1_EN + 2 + 1 + read-write + + + 0 + Normal operation. + #0 + + + 1 + Use the state of TSM_SPARE1_EN_OVRD to override the signal "tsm_spare1_en". + #1 + + + + + TSM_SPARE1_EN_OVRD + Override value for TSM_SPARE1_EN + 3 + 1 + read-write + + + TSM_SPARE2_EN_OVRD_EN + Override control for TSM_SPARE2_EN + 4 + 1 + read-write + + + 0 + Normal operation. + #0 + + + 1 + Use the state of TSM_SPARE2_EN_OVRD to override the signal "tsm_spare2_en". + #1 + + + + + TSM_SPARE2_EN_OVRD + Override value for TSM_SPARE2_EN + 5 + 1 + read-write + + + TSM_SPARE3_EN_OVRD_EN + Override control for TSM_SPARE3_EN + 6 + 1 + read-write + + + 0 + Normal operation. + #0 + + + 1 + Use the state of TSM_SPARE3_EN_OVRD to override the signal "tsm_spare3_en". + #1 + + + + + TSM_SPARE3_EN_OVRD + Override value for TSM_SPARE3_EN + 7 + 1 + read-write + + + RXTX_AUXPLL_BIAS_EN_OVRD_EN + Override control for RXTX_AUXPLL_BIAS_EN + 8 + 1 + read-write + + + 0 + Normal operation. + #0 + + + 1 + Use the state of RXTX_AUXPLL_BIAS_EN_OVRD to override the signal "rxtx_auxpll_bias_en". + #1 + + + + + RXTX_AUXPLL_BIAS_EN_OVRD + Override value for RXTX_AUXPLL_BIAS_EN + 9 + 1 + read-write + + + RXTX_AUXPLL_VCO_EN_OVRD_EN + Override control for RXTX_AUXPLL_VCO_EN + 10 + 1 + read-write + + + 0 + Normal operation. + #0 + + + 1 + Use the state of RXTX_AUXPLL_VCO_EN_OVRD to override the signal "rxtx_auxpll_vco_en". + #1 + + + + + RXTX_AUXPLL_VCO_EN_OVRD + Override value for RXTX_AUXPLL_VCO_EN + 11 + 1 + read-write + + + RXTX_AUXPLL_FCAL_EN_OVRD_EN + Override control for RXTX_AUXPLL_FCAL_EN + 12 + 1 + read-write + + + 0 + Normal operation. + #0 + + + 1 + Use the state of RXTX_AUXPLL_FCAL_EN_OVRD to override the signal "rxtx_auxpll_fcal_en". + #1 + + + + + RXTX_AUXPLL_FCAL_EN_OVRD + Override value for RXTX_AUXPLL_FCAL_EN + 13 + 1 + read-write + + + RXTX_AUXPLL_LF_EN_OVRD_EN + Override control for RXTX_AUXPLL_LF_EN + 14 + 1 + read-write + + + 0 + Normal operation. + #0 + + + 1 + Use the state of RXTX_AUXPLL_LF_EN_OVRD to override the signal "rxtx_auxpll_lf_en". + #1 + + + + + RXTX_AUXPLL_LF_EN_OVRD + Override value for RXTX_AUXPLL_LF_EN + 15 + 1 + read-write + + + RXTX_AUXPLL_PD_EN_OVRD_EN + Override control for RXTX_AUXPLL_PD_EN + 16 + 1 + read-write + + + 0 + Normal operation. + #0 + + + 1 + Use the state of RXTX_AUXPLL_PD_EN_OVRD to override the signal "rxtx_auxpll_pd_en". + #1 + + + + + RXTX_AUXPLL_PD_EN_OVRD + Override value for RXTX_AUXPLL_PD_EN + 17 + 1 + read-write + + + RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_OVRD_EN + Override control for RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN + 18 + 1 + read-write + + + 0 + Normal operation. + #0 + + + 1 + Use the state of RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_OVRD to override the signal "rxtx_auxpll_pd_lf_filter_charge_en". + #1 + + + + + RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_OVRD + Override value for RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN + 19 + 1 + read-write + + + RXTX_AUXPLL_ADC_BUF_EN_OVRD_EN + Override control for RXTX_AUXPLL_ADC_BUF_EN + 20 + 1 + read-write + + + 0 + Normal operation. + #0 + + + 1 + Use the state of RXTX_AUXPLL_ADC_BUF_EN_OVRD to override the signal "rxtx_auxpll_adc_buf_en". + #1 + + + + + RXTX_AUXPLL_ADC_BUF_EN_OVRD + Override value for RXTX_AUXPLL_ADC_BUF_EN + 21 + 1 + read-write + + + RXTX_AUXPLL_DIG_BUF_EN_OVRD_EN + Override control for RXTX_AUXPLL_DIG_BUF_EN + 22 + 1 + read-write + + + 0 + Normal operation. + #0 + + + 1 + Use the state of RXTX_AUXPLL_DIG_BUF_EN_OVRD to override the signal "rxtx_auxpll_dig_buf_en". + #1 + + + + + RXTX_AUXPLL_DIG_BUF_EN_OVRD + Override value for RXTX_AUXPLL_DIG_BUF_EN + 23 + 1 + read-write + + + RXTX_RCCAL_EN_OVRD_EN + Override control for RXTX_RCCAL_EN + 24 + 1 + read-write + + + 0 + Normal operation. + #0 + + + 1 + Use the state of RXTX_RCCAL_EN_OVRD to override the signal "rxtx_rccal_en". + #1 + + + + + RXTX_RCCAL_EN_OVRD + Override value for RXTX_RCCAL_EN + 25 + 1 + read-write + + + TX_HPM_DAC_EN_OVRD_EN + Override control for TX_HPM_DAC_EN + 26 + 1 + read-write + + + 0 + Normal operation. + #0 + + + 1 + Use the state of TX_HPM_DAC_EN_OVRD to override the signal "tx_hpm_dac_en". + #1 + + + + + TX_HPM_DAC_EN_OVRD + Override value for TX_HPM_DAC_EN + 27 + 1 + read-write + + + TX_MODE_OVRD_EN + Override control for TX_MODE + 28 + 1 + read-write + + + 0 + Normal operation. + #0 + + + 1 + Use the state of TX_MODE_OVRD to override the signal "tx_mode". + #1 + + + + + TX_MODE_OVRD + Override value for TX_MODE + 29 + 1 + read-write + + + RX_MODE_OVRD_EN + Override control for RX_MODE + 30 + 1 + read-write + + + 0 + Normal operation. + #0 + + + 1 + Use the state of RX_MODE_OVRD to override the signal "rx_mode". + #1 + + + + + RX_MODE_OVRD + Override value for RX_MODE + 31 + 1 + read-write + + + + + + + XCVR_ANALOG + XCVR_ANALOG + 0x40087500 + + 0 + 0x28 + registers + + + + BB_LDO_1 + RF Analog Baseband LDO Control 1 + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BB_LDO_ADCDAC_BYP + rmap_bb_ldo_adcdac_byp + 0 + 1 + read-write + + + 0 + Bypass disabled. + #0 + + + 1 + Bypass enabled + #1 + + + + + BB_LDO_ADCDAC_DIAGSEL + rmap_bb_ldo_adcdac_diagsel + 1 + 1 + read-write + + + 0 + Diag disable + #0 + + + 1 + Diag enable + #1 + + + + + BB_LDO_ADCDAC_SPARE + rmap_bb_ldo_adcdac_spare[1:0] + 2 + 2 + read-write + + + BB_LDO_ADCDAC_TRIM + rmap_bb_ldo_adcdac_trim[2:0] + 4 + 3 + read-write + + + 000 + 1.20 V ( Default ) + #000 + + + 001 + 1.25 V + #001 + + + 010 + 1.28 V + #010 + + + 011 + 1.33 V + #011 + + + 100 + 1.40 V + #100 + + + 101 + 1.44 V + #101 + + + 110 + 1.50 V + #110 + + + 111 + 1.66 V + #111 + + + + + BB_LDO_BBA_BYP + rmap_bb_ldo_bba_byp + 8 + 1 + read-write + + + 0 + Bypass disabled. + #0 + + + 1 + Bypass enabled + #1 + + + + + BB_LDO_BBA_DIAGSEL + rmap_bb_ldo_bba_diagsel + 9 + 1 + read-write + + + 0 + Diag disable + #0 + + + 1 + Diag enable + #1 + + + + + BB_LDO_BBA_SPARE + rmap_bb_ldo_bba_spare[1:0] + 10 + 2 + read-write + + + BB_LDO_BBA_TRIM + rmap_bb_ldo_bba_trim[2:0] + 12 + 3 + read-write + + + 000 + 1.20 V ( Default ) + #000 + + + 001 + 1.25 V + #001 + + + 010 + 1.28 V + #010 + + + 011 + 1.33 V + #011 + + + 100 + 1.40 V + #100 + + + 101 + 1.44 V + #101 + + + 110 + 1.50 V + #110 + + + 111 + 1.66 V + #111 + + + + + BB_LDO_FDBK_BYP + rmap_bb_ldo_fdbk_byp + 16 + 1 + read-write + + + 0 + Bypass disabled. + #0 + + + 1 + Bypass enabled + #1 + + + + + BB_LDO_FDBK_DIAGSEL + rmap_bb_ldo_fdbk_diagsel + 17 + 1 + read-write + + + 0 + Diag disable + #0 + + + 1 + Diag enable + #1 + + + + + BB_LDO_FDBK_SPARE + rmap_bb_ldo_fdbk_spare[1:0] + 18 + 2 + read-write + + + BB_LDO_FDBK_TRIM + rmap_bb_ldo_fdbk_trim[2:0] + 20 + 3 + read-write + + + 000 + 1.2/1.176 V ( Default ) + #000 + + + 001 + 1.138/1.115 V + #001 + + + 010 + 1.085/1.066 V + #010 + + + 011 + 1.04/1.025 V + #011 + + + 100 + 1.28/1.25 V + #100 + + + 101 + 1.4/1.35 V + #101 + + + 110 + 1.55/1.4 V + #110 + + + 111 + 1.78/1.4 V + #111 + + + + + BB_LDO_HF_BYP + rmap_bb_ldo_hf_byp + 24 + 1 + read-write + + + 0 + Bypass disabled. + #0 + + + 1 + Bypass enabled + #1 + + + + + BB_LDO_HF_DIAGSEL + rmap_bb_ldo_hf_diagsel + 25 + 1 + read-write + + + 0 + Diag disable + #0 + + + 1 + Diag enable + #1 + + + + + BB_LDO_HF_SPARE + rmap_bb_ldo_hf_spare[1:0] + 26 + 2 + read-write + + + BB_LDO_HF_TRIM_RX + rmap_bb_ldo_hf_trim[2:0] + 28 + 3 + read-write + + + 000 + 1.20 V ( Default ) + #000 + + + 001 + 1.25 V + #001 + + + 010 + 1.28 V + #010 + + + 011 + 1.33 V + #011 + + + 100 + 1.40 V + #100 + + + 101 + 1.44 V + #101 + + + 110 + 1.50 V + #110 + + + 111 + 1.66 V + #111 + + + + + + + BB_LDO_2 + RF Analog Baseband LDO Control 2 + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + BB_LDO_PD_BYP + rmap_bb_ldo_pd_byp + 0 + 1 + read-write + + + 0 + Bypass disabled. + #0 + + + 1 + Bypass enabled + #1 + + + + + BB_LDO_PD_DIAGSEL + rmap_bb_ldo_pd_diagsel + 1 + 1 + read-write + + + 0 + Diag disable + #0 + + + 1 + Diag enable + #1 + + + + + BB_LDO_PD_SPARE + rmap_bb_ldo_pd_spare[1:0] + 2 + 2 + read-write + + + BB_LDO_PD_TRIM + rmap_bb_ldo_pd_trim[2:0] + 4 + 3 + read-write + + + 000 + 1.20 V ( Default ) + #000 + + + 001 + 1.25 V + #001 + + + 010 + 1.28 V + #010 + + + 011 + 1.33 V + #011 + + + 100 + 1.40 V + #100 + + + 101 + 1.44 V + #101 + + + 110 + 1.50 V + #110 + + + 111 + 1.66 V + #111 + + + + + BB_LDO_VCO_SPARE + rmap_bb_ldo_vco_spare[1:0] + 8 + 2 + read-write + + + BB_LDO_VCOLO_BYP + rmap_bb_ldo_vcolo_byp + 10 + 1 + read-write + + + 0 + Bypass disabled. + #0 + + + 1 + Bypass enabled + #1 + + + + + BB_LDO_VCOLO_DIAGSEL + rmap_bb_ldo_vcolo_diagsel + 11 + 1 + read-write + + + 0 + Diag disable + #0 + + + 1 + Diag enable + #1 + + + + + BB_LDO_VCOLO_TRIM + rmap_bb_ldo_vcolo_trim[2:0] + 12 + 3 + read-write + + + 000 + 1.138/1.117 V ( Default ) + #000 + + + 001 + 1.076/1.058 V + #001 + + + 010 + 1.027/1.012 V + #010 + + + 011 + 0.98/0.97 V + #011 + + + 100 + 1.22/1.19 V + #100 + + + 101 + 1.33/1.3 V + #101 + + + 110 + 1.5/1.4 V + #110 + + + 111 + 1.82/1.4 V + #111 + + + + + BB_LDO_VTREF_DIAGSEL + rmap_bb_ldo_vtref_diagsel + 16 + 1 + read-write + + + 0 + Diag disable + #0 + + + 1 + Diag enable + #1 + + + + + BB_LDO_VTREF_TC + rmap_bb_ldo_vtref_tc[1:0] + 17 + 2 + read-write + + + 00 + 1.117/1.176 V + #00 + + + 01 + 1.134/1.188 V + #01 + + + 10 + 1.10/1.162 V + #10 + + + 11 + 1.09/1.152 V + #11 + + + + + BB_LDO_HF_TRIM_TX + rmap_bb_ldo_hf_trim[2:0] + 28 + 3 + read-write + + + 000 + 1.20 V ( Default ) + #000 + + + 001 + 1.25 V + #001 + + + 010 + 1.28 V + #010 + + + 011 + 1.33 V + #011 + + + 100 + 1.40 V + #100 + + + 101 + 1.44 V + #101 + + + 110 + 1.50 V + #110 + + + 111 + 1.66 V + #111 + + + + + + + RX_ADC + RF Analog ADC Control + 0x8 + 32 + read-write + 0x140 + 0xFFFFFFFF + + + RX_ADC_BUMP + rmap_rx_adc_bump[7:0] + 0 + 8 + read-write + + + RX_ADC_FS_SEL + rmap_rx_adc_fs_sel[1:0] + 8 + 2 + read-write + + + 00 + 52MHz (2x26MHz) + #00 + + + 01 + 64MHz (2x32MHz) + #01 + + + 10 + +13% of 64MHz + #10 + + + 11 + - 11% of 64MHz + #11 + + + + + RX_ADC_I_DIAGSEL + rmap_rx_adc_i_diagsel + 10 + 1 + read-write + + + RX_ADC_Q_DIAGSEL + rmap_rx_adc_q_diagsel + 11 + 1 + read-write + + + RX_ADC_SPARE + rmap_rx_adc_spare[3:0] + 12 + 4 + read-write + + + + + RX_BBA + RF Analog BBA Control + 0xC + 32 + read-write + 0x3003303 + 0xFFFFFFFF + + + RX_BBA_BW_SEL + rmap_rx_bba_bw_sel[2:0] + 0 + 3 + read-write + + + 000 + 1000K + #000 + + + 001 + 900K + #001 + + + 010 + 800K + #010 + + + 011 + 700K Default + #011 + + + 100 + 600K + #100 + + + 101 + 500K + #101 + + + + + RX_BBA_CUR_BUMP + rmap_rx_bba_cur_bump + 3 + 1 + read-write + + + RX_BBA_DIAGSEL1 + rmap_rx_bba_diagsel1 + 4 + 1 + read-write + + + 0 + Diag disable + #0 + + + 1 + Diag enable + #1 + + + + + RX_BBA_DIAGSEL2 + rmap_rx_bba_diagsel2 + 5 + 1 + read-write + + + 0 + Diag disable + #0 + + + 1 + Diag enable + #1 + + + + + RX_BBA_DIAGSEL3 + rmap_rx_bba_diagsel3 + 6 + 1 + read-write + + + 0 + Diag disable + #0 + + + 1 + Diag enable + #1 + + + + + RX_BBA_DIAGSEL4 + rmap_rx_bba_diagsel4 + 7 + 1 + read-write + + + 0 + Diag disable + #0 + + + 1 + Diag enable + #1 + + + + + RX_BBA_BW_SEL_DRS + rmap_rx_bba_bw_sel[2:0], for DataRate Switch + 8 + 3 + read-write + + + 000 + 1000K + #000 + + + 001 + 900K + #001 + + + 010 + 800K + #010 + + + 011 + 700K Default + #011 + + + 100 + 600K + #100 + + + 101 + 500K + #101 + + + + + RX_BBA2_BW_SEL_DRS + rmap_bba2_bw_sel[2:0], for DataRate Switch + 12 + 3 + read-write + + + 000 + 1000K + #000 + + + 001 + 900K + #001 + + + 010 + 800K + #010 + + + 011 + 700K Default + #011 + + + 100 + 600K + #100 + + + 101 + 500K + #101 + + + + + RX_BBA_SPARE + rmap_rx_bba_spare[5:0] + 16 + 6 + read-write + + + 00 + 600mV (Default) + #0 + + + 01 + 675mV + #1 + + + 10 + 450mV + #10 + + + 11 + 525mV + #11 + + + + + RX_BBA2_BW_SEL + rmap_bba2_bw_sel[2:0] + 24 + 3 + read-write + + + 000 + 1000K + #000 + + + 001 + 900K + #001 + + + 010 + 800K + #010 + + + 011 + 700K Default + #011 + + + 100 + 600K + #100 + + + 101 + 500K + #101 + + + + + RX_BBA2_SPARE + rmap_rx_bba2_spare[2:0] + 28 + 3 + read-write + + + + + RX_LNA + RF Analog LNA Control + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + RX_LNA_BUMP + rmap_rx_lna_bump[3:0] + 0 + 4 + read-write + + + 0000 + Default + #0000 + + + 0001 + -25% + #0001 + + + 0010 + +50% + #0010 + + + 0011 + +25% + #0011 + + + 0100 + CM 480mV + #0100 + + + 1000 + CM 600mV + #1000 + + + 1100 + CM 660mV + #1100 + + + + + RX_LNA_HG_DIAGSEL + rmap_rx_lna_hg_diagsel + 4 + 1 + read-write + + + RX_LNA_HIZ_ENABLE + rmap_rx_lna_hiZ_enable + 5 + 1 + read-write + + + RX_LNA_LG_DIAGSEL + rmap_rx_lna_lg_diagsel + 6 + 1 + read-write + + + RX_LNA_SPARE + rmap_rx_lna_spare[1:0] + 8 + 2 + read-write + + + RX_MIXER_BUMP + rmap_rx_mixer_bump[3:0] + 16 + 4 + read-write + + + 00 + 825mV (Default) + #0000 + + + 01 + 750mV + #0001 + + + 10 + 900mV + #0010 + + + 11 + 975mV + #0011 + + + + + RX_MIXER_SPARE + rmap_rx_mixer_spare + 20 + 1 + read-write + + + + + RX_TZA + RF Analog TZA Control + 0x14 + 32 + read-write + 0x303 + 0xFFFFFFFF + + + RX_TZA_BW_SEL + rmap_rx_tza_bw_sel[2:0] + 0 + 3 + read-write + + + 000 + 1000K + #000 + + + 001 + 900K + #001 + + + 010 + 800K + #010 + + + 011 + 700K Default + #011 + + + 100 + 600K + #100 + + + 101 + 500K + #101 + + + + + RX_TZA_CUR_BUMP + rmap_rx_tza_cur_bump + 3 + 1 + read-write + + + RX_TZA_GAIN_BUMP + rmap_rx_tza_gain_bump + 4 + 1 + read-write + + + RX_TZA_BW_SEL_DRS + rmap_rx_tza_bw_sel[2:0], for DataRate Switch + 8 + 3 + read-write + + + 000 + 1000K + #000 + + + 001 + 900K + #001 + + + 010 + 800K + #010 + + + 011 + 700K Default + #011 + + + 100 + 600K + #100 + + + 101 + 500K + #101 + + + + + RX_TZA_SPARE + rmap_rx_tza_spare[5:0] + 16 + 6 + read-write + + + 00 + 600mV (Default) + #0 + + + 01 + 675mV + #1 + + + 10 + 450mV + #10 + + + 11 + 525mV + #11 + + + + + RX_TZA1_DIAGSEL + rmap_rx_tza1_diagsel + 24 + 1 + read-write + + + 0 + Diag disable + #0 + + + 1 + Diag enable + #1 + + + + + RX_TZA2_DIAGSEL + rmap_rx_tza2_diagsel + 25 + 1 + read-write + + + 0 + Diag disable + #0 + + + 1 + Diag enable + #1 + + + + + RX_TZA3_DIAGSEL + rmap_rx_tza3_diagsel + 26 + 1 + read-write + + + 0 + Diag disable + #0 + + + 1 + Diag enable + #1 + + + + + RX_TZA4_DIAGSEL + rmap_rx_tza4_diagsel + 27 + 1 + read-write + + + 0 + Diag disable + #0 + + + 1 + Diag enable + #1 + + + + + + + RX_AUXPLL + RF Analog Aux PLL Control + 0x18 + 32 + read-write + 0x9002 + 0xFFFFFFFF + + + BIAS_TRIM + rmap_rxtx_auxpll_bias_trim[2:0] + 0 + 3 + read-write + + + DIAGSEL1 + rmap_rxtx_auxpll_diagsel1 + 3 + 1 + read-write + + + DIAGSEL2 + rmap_rxtx_auxpll_diagsel2 + 4 + 1 + read-write + + + LF_CNTL + rmap_rxtx_auxpll_lf_cntl[2:0] + 5 + 3 + read-write + + + SPARE + rmap_rxtx_auxpll_spare[3:0] + 8 + 4 + read-write + + + VCO_DAC_REF_ADJUST + rmap_rxtx_auxpll_vco_dac_ref_adjust[3:0] + 12 + 4 + read-write + + + VTUNE_TESTMODE + rmap_rxtx_auxpll_vtune_testmode + 16 + 1 + read-write + + + RXTX_BAL_BIAST + rmap_rxtx_bal_biast[1:0] + 20 + 2 + read-write + + + 00 + 0.6 + #00 + + + 01 + 0.4 + #01 + + + 10 + 0.9 + #10 + + + 11 + 1.2 + #11 + + + + + RXTX_BAL_SPARE + rmap_rxtx_bal_spare[2:0] + 24 + 3 + read-write + + + RXTX_RCCAL_DIAGSEL + rmap_rxtx_rccal_diagsel + 28 + 1 + read-write + + + + + SY_CTRL_1 + RF Analog Synthesizer Control 1 + 0x1C + 32 + read-write + 0x150 + 0xFFFFFFFF + + + SY_DIVN_SPARE + rmap_sy_divn_spare + 0 + 1 + read-write + + + SY_FCAL_SPARE + rmap_sy_fcal_spare + 1 + 1 + read-write + + + SY_LO_BUMP_RTLO_FDBK + rmap_sy_lo_bump_rtlo_fdbk[1:0] + 4 + 2 + read-write + + + 00 + 1.045 V + #00 + + + 01 + 1.084 V + #01 + + + 10 + 1.097 V + #10 + + + 11 + 1.10 V + #11 + + + + + SY_LO_BUMP_RTLO_RX + rmap_sy_lo_bump_rtlo_rx[1:0] + 6 + 2 + read-write + + + 00 + 1.051/1.037 V + #00 + + + 01 + 1.082/1.075 V + #01 + + + 10 + 1.092/1.088 V + #10 + + + 11 + 1.098/1.094 V + #11 + + + + + SY_LO_BUMP_RTLO_TX + rmap_sy_lo_bump_rtlo_tx[1:0] + 8 + 2 + read-write + + + 00 + 1.071/1.065 V + #00 + + + 01 + 1.092/1.090 V + #01 + + + 10 + 1.099/1.098 V + #10 + + + 11 + 1.10/1.1 V + #11 + + + + + SY_LO_DIAGSEL + rmap_sy_lo_diagsel + 10 + 1 + read-write + + + 0 + Diag disable + #0 + + + 1 + Diag enable + #1 + + + + + SY_LO_SPARE + rmap_sy_lo_spare[2:0] + 12 + 3 + read-write + + + SY_LPF_FILT_CTRL + rmap_sy_lpf_filt_ctrl[2:0] + 16 + 3 + read-write + + + SY_LPF_SPARE + rmap_sy_lpf_spare + 19 + 1 + read-write + + + SY_PD_DIAGSEL + rmap_sy_pd_diagsel + 20 + 1 + read-write + + + SY_PD_PCH_TUNE + rmap_sy_pd_pch_tune[1:0] + 21 + 2 + read-write + + + SY_PD_PCH_SEL + rmap_sy_pd_pch_sel + 23 + 1 + read-write + + + 0 + inverter based precharge + #0 + + + 1 + resistor divider based precharge + #1 + + + + + SY_PD_SPARE + rmap_sy_pd_spare[1:0] + 24 + 2 + read-write + + + 0 + Default ; + #00 + + + 1 + PD output is pulled down. + #01 + + + + + + + SY_CTRL_2 + RF Analog Synthesizer Control 2 + 0x20 + 32 + read-write + 0x14 + 0xFFFFFFFF + + + SY_VCO_BIAS + rmap_sy_vco_bias[2:0] + 0 + 3 + read-write + + + 000 + 0.97V + #000 + + + 001 + 1.033V + #001 + + + 010 + 1.06V + #010 + + + 011 + 1.07V + #011 + + + 100 + 1.08V + #100 + + + 101 + 1.085V + #101 + + + 110 + 1.090V + #110 + + + 111 + 1.095V + #111 + + + + + SY_VCO_DIAGSEL + rmap_sy_vco_diagsel + 3 + 1 + read-write + + + 1 + Diag enable + #1 + + + 0 + Diag disable + #0 + + + + + SY_VCO_KV + rmap_sy_vco_kv[2:0] + 4 + 3 + read-write + + + 000 + 50MHz/V + #000 + + + 001 + 60MHz/V + #001 + + + 010 + 70MHz/V + #010 + + + 011 + 80MHz/V + #011 + + + 100 + 80MHz/V + #100 + + + 101 + 80MHz/V + #101 + + + 110 + 80MHz/V + #110 + + + 111 + 80MHz/V + #111 + + + + + SY_VCO_KVM + rmap_sy_vco_kvm[2:0] + 8 + 3 + read-write + + + 000 + 10MHz/V + #000 + + + 001 + 20MHz/V + #001 + + + 010 + 30MHz/V + #010 + + + 011 + 40MHz/V + #011 + + + 100 + 40MHz/V + #100 + + + 101 + 40MHz/V + #101 + + + 110 + 40MHz/V + #110 + + + 111 + 40MHz/V + #111 + + + + + SY_VCO_PK_DET_ON + rmap_sy_vco_pk_det_on + 12 + 1 + read-write + + + 1 + Enable + #1 + + + 0 + Disable + #0 + + + + + SY_VCO_SPARE + rmap_sy_vco_spare[2:0] + 14 + 3 + read-write + + + SY_VCO_KVM_DRS + rmap_sy_vco_kvm[2:0], for DataRate Switch + 24 + 3 + read-write + + + 000 + 10MHz/V + #000 + + + 001 + 20MHz/V + #001 + + + 010 + 30MHz/V + #010 + + + 011 + 40MHz/V + #011 + + + 100 + 40MHz/V + #100 + + + 101 + 40MHz/V + #101 + + + 110 + 40MHz/V + #110 + + + 111 + 40MHz/V + #111 + + + + + + + TX_DAC_PA + RF Analog TX HPM DAC and PA Control + 0x24 + 32 + read-write + 0x20000 + 0xFFFFFFFF + + + TX_DAC_BUMP_CAP + rmap_tx_dac_bump_cap[1:0] + 0 + 2 + read-write + + + 00 + 1pF(default) + #00 + + + 01 + 1.5pF + #01 + + + 10 + 1.5pF + #10 + + + 11 + 2pF + #11 + + + + + TX_DAC_BUMP_IDAC + rmap_tx_dac_bump_idac[1:0] + 3 + 2 + read-write + + + 00 + 250nA(default) + #00 + + + 01 + 207nA + #01 + + + 10 + 312nA + #10 + + + 11 + 415nA + #11 + + + + + TX_DAC_BUMP_RLOAD + rmap_tx_dac_bump_rload[1:0] + 6 + 2 + read-write + + + 00 + 3.12 kohms(default) + #00 + + + 01 + 2.34 kohms + #01 + + + 10 + 3.9 kohms + #10 + + + 11 + 4.6 kohms + #11 + + + + + TX_DAC_DIAGSEL + rmap_tx_dac_diagsel + 9 + 1 + read-write + + + 0 + Disable Diag + #0 + + + 1 + Enable Diag + #1 + + + + + TX_DAC_INVERT_CLK + rmap_tx_dac_invert_clk + 10 + 1 + read-write + + + TX_DAC_OPAMP_DIAGSEL + rmap_tx_dac_opamp_diagsel + 11 + 1 + read-write + + + 0 + Disable Diag + #0 + + + 1 + Enable Diag + #1 + + + + + TX_DAC_SPARE + rmap_tx_dac_spare[2:0] + 13 + 3 + read-write + + + TX_PA_BUMP_VBIAS + rmap_tx_pa_bump_vbias[2:0] + 17 + 3 + read-write + + + 000 + 0.557 + #000 + + + 001 + 0.651 + #001 + + + 010 + 0.741 + #010 + + + 011 + 0.822 + #011 + + + 100 + 0.590 + #100 + + + 101 + 0.683 + #101 + + + 110 + 0.771 + #110 + + + 111 + 0.850 + #111 + + + + + TX_PA_DIAGSEL + rmap_tx_pa_diagsel + 21 + 1 + read-write + + + TX_PA_SPARE + rmap_tx_pa_spare[2:0] + 23 + 3 + read-write + + + + + + + XCVR_PLL_DIG + XCVR_PLL_DIG + 0x40087600 + + 0 + 0x88 + registers + + + + HPM_BUMP + PLL HPM Analog Bump Control + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + HPM_VCM_TX + rfctrl_tx_dac_bump_vcm[2:0] during Transmission + 0 + 3 + read-write + + + 000 + 0.158 + #000 + + + 001 + 0.193 + #001 + + + 010 + 0.225 + #010 + + + 011 + 0.255 + #011 + + + 100 + 0.283 + #100 + + + 101 + 0.309 + #101 + + + 110 + 0.334 + #110 + + + 111 + 0.357 + #111 + + + + + HPM_VCM_CAL + rfctrl_tx_dac_bump_vcm[2:0] during Calibration + 4 + 3 + read-write + + + 000 + 0.158 + #000 + + + 001 + 0.193 + #001 + + + 010 + 0.225 + #010 + + + 011 + 0.255 + #011 + + + 100 + 0.283 + #100 + + + 101 + 0.309 + #101 + + + 110 + 0.334 + #110 + + + 111 + 0.357 + #111 + + + + + HPM_FDB_RES_TX + rfctrl_tx_dac_bump_fdb_res[1:0] during Transmission + 8 + 2 + read-write + + + 00 + 1.0 + #00 + + + 01 + 0.5 (gain of 1/2) + #01 + + + 10 + 1.17 + #10 + + + 11 + 1.5 + #11 + + + + + HPM_FDB_RES_CAL + rfctrl_tx_dac_bump_fdb_res[1:0] during Calibration + 12 + 2 + read-write + + + 00 + 1.0 + #00 + + + 01 + 0.5 (gain of 1/2) + #01 + + + 10 + 1.17 + #10 + + + 11 + 1.5 + #11 + + + + + + + MOD_CTRL + PLL Modulation Control + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + MODULATION_WORD_MANUAL + Manual Modulation Word + 0 + 13 + read-write + + + MOD_DISABLE + Disable Modulation Word + 15 + 1 + read-write + + + HPM_MOD_MANUAL + Manual HPM Modulation + 16 + 8 + read-write + + + HPM_MOD_DISABLE + Disable HPM Modulation + 27 + 1 + read-write + + + HPM_SDM_OUT_MANUAL + Manual HPM SDM out + 28 + 2 + read-write + + + HPM_SDM_OUT_DISABLE + Disable HPM SDM out + 31 + 1 + read-write + + + + + CHAN_MAP + PLL Channel Mapping + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + CHANNEL_NUM_OVRD + Channel Selection Override + 0 + 16 + read-write + + + BAND_SELECT + Channel Mapping Band Select + 16 + 3 + read-write + + + 00 + Bluetooth Low Energy + #000 + + + 01 + Bluetooth Low Energy in MBAN + #001 + + + 10 + Bluetooth Low Energy overlap MBAN + #010 + + + + + BMR + Bluetooth Low Energy MBAN Channel Remap + 19 + 1 + read-write + + + 0 + Bluetooth Low Energy channel 39 is mapped to Bluetooth Low Energy channel 39, 2.480 GHz + #0 + + + 1 + Bluetooth Low Energy channel 39 is mapped to MBAN channel 39, 2.399 GHz + #1 + + + + + HOP_TBL_CFG_OVRD + Hop Table Configuration Override + 24 + 3 + read-write + + + 10 + CHANNEL_NUM_OVRD[15:7] is signed Numerator offset to CHANNEL_NUM_OVRD[6:0] mapped channel number + #010 + + + 11 + CHANNEL_NUM_OVRD[15:1] is selected as the signed Numerator, CHANNEL_NUM_OVRD[0] is integer selection + #011 + + + + + HOP_TBL_CFG_OVRD_EN + Hop Table Configuration Override Enable + 27 + 1 + read-write + + + + + CHAN_MAP_EXT + PLL Channel Mapping Extended + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + NUM_OFFSET + Numerator Offset + 0 + 28 + read-write + + + CTUNE_TGT_OFFSET + Coarse Tune Target Frequency Offset + 28 + 3 + read-write + + + + + LOCK_DETECT + PLL Lock Detect Control + 0x18 + 32 + read-write + 0x606800 + 0xFFFFFFFF + + + CT_FAIL + Real time status of Coarse Tune Fail signal + 0 + 1 + read-only + + + CTFF + CTUNE Failure Flag, held until cleared + 1 + 1 + read-write + + + CS_FAIL + Real time status of Cycle Slip circuit + 2 + 1 + read-only + + + CSFF + Cycle Slip Failure Flag, held until cleared + 3 + 1 + read-write + + + FT_FAIL + Real time status of Frequency Target Failure + 4 + 1 + read-only + + + FTFF + Frequency Target Failure Flag + 5 + 1 + read-write + + + CTUNE_LDF_LEV + CTUNE Lock Detect Fail Level + 8 + 4 + read-write + + + FTF_RX_THRSH + RX Frequency Target Fail Threshold + 12 + 6 + read-write + + + FTF_TX_THRSH + TX Frequency Target Fail Threshold + 18 + 6 + read-write + + + FCAL_HOLD_EN + Frequency Counter Hold Enable + 24 + 1 + read-write + + + 0 + The frequency counter is turned off after CTUNE (RX Mode) or HPM CAL (TX Mode) + #0 + + + 1 + The frequency counter is held on after CTUNE (RX Mode) or HPM CAL (TX Mode) for an optional lock detect sequence. + #1 + + + + + FTW_TXRX + TX and RX Frequency Target Window time select + 25 + 3 + read-write + + + 000 + FTW_TX = 4us ; FTW_RX = 4us + #000 + + + 001 + FTW_TX = 4us ; FTW_RX = 8us + #001 + + + 010 + FTW_TX = 8us ; FTW_RX = 4us + #010 + + + 011 + FTW_TX = 8us ; FTW_RX = 8us + #011 + + + 100 + FTW_TX = 16us ; FTW_RX = 16us + #100 + + + 101 + FTW_TX = 16us ; FTW_RX = 32us + #101 + + + 110 + FTW_TX = 32us ; FTW_RX = 16us + #110 + + + 111 + FTW_TX = 32us ; FTW_RX = 32us + #111 + + + + + FREQ_COUNT_GO + Start the Frequency Meter + 28 + 1 + read-write + + + FREQ_COUNT_FINISHED + Frequency Meter has finished the Count Time + 29 + 1 + read-only + + + FREQ_COUNT_TIME + Frequency Meter Count Time + 30 + 2 + read-write + + + 00 + 800 us + #00 + + + 01 + 25 us + #01 + + + 10 + 50 us + #10 + + + 11 + 100 us + #11 + + + + + + + HPM_CTRL + PLL High Port Modulator Control + 0x1C + 32 + read-write + 0x90840000 + 0xFFFFFFFF + + + HPM_SDM_IN_MANUAL + Manual High Port SDM Fractional value + 0 + 10 + read-write + + + HPFF + HPM SDM Invalid Flag + 13 + 1 + read-write + + + HPM_SDM_OUT_INVERT + Invert HPM SDM Output + 14 + 1 + read-write + + + HPM_SDM_IN_DISABLE + Disable HPM SDM Input + 15 + 1 + read-write + + + HPM_LFSR_SIZE + HPM LFSR Length + 16 + 3 + read-write + + + 000 + LFSR 9, tap mask 100010000 + #000 + + + 001 + LFSR 10, tap mask 1001000000 + #001 + + + 010 + LFSR 11, tap mask 11101000000 + #010 + + + 011 + LFSR 13, tap mask 1101100000000 + #011 + + + 100 + LFSR 15, tap mask 111010000000000 + #100 + + + 101 + LFSR 17, tap mask 11110000000000000 + #101 + + + + + HPM_DTH_SCL + HPM Dither Scale + 20 + 1 + read-write + + + HPM_DTH_EN + Dither Enable for HPM LFSR + 23 + 1 + read-write + + + HPM_SCALE + High Port Modulation Scale + 24 + 3 + read-write + + + 000 + No Scaling + #000 + + + 001 + Divide by 2 + #001 + + + 010 + Multiply by 2 + #010 + + + 011 + Multiply by 4 + #011 + + + 100 + Divide by 4 + #100 + + + + + HPM_INTEGER_INVERT + Invert High Port Modulation Integer + 27 + 1 + read-write + + + HPM_CAL_INVERT + Invert High Port Modulator Calibration + 28 + 1 + read-write + + + HPM_CAL_TIME + High Port Modulation Calibration Time + 29 + 2 + read-write + + + 00 + 25 us + #00 + + + 01 + 50 us + #01 + + + 10 + 100 us + #10 + + + 11 + N/A + #11 + + + + + HPM_MOD_IN_INVERT + Invert High Port Modulation + 31 + 1 + read-write + + + + + HPM_SDM_RES + PLL High Port Sigma Delta Results + 0x2C + 32 + read-write + 0x1000000 + 0xFFFFFFFF + + + HPM_NUM_SELECTED + High Port Modulator SDM Numerator + 0 + 10 + read-only + + + HPM_DENOM + High Port Modulator SDM Denominator + 16 + 10 + read-write + + + HPM_COUNT_ADJUST + HPM_COUNT_ADJUST + 28 + 4 + read-write + + + + + LPM_CTRL + PLL Low Port Modulator Control + 0x30 + 32 + read-write + 0x8000800 + 0xFFFFFFFF + + + PLL_LD_MANUAL + Manual PLL Loop Divider value + 0 + 5 + read-write + + + HPM_CAL_SCALE + High Port Calibration Word Scaling + 8 + 4 + read-write + + + 0011 + Divide by 32 + #0011 + + + 0100 + Divide by 16 + #0100 + + + 0101 + Divide by 8 + #0101 + + + 0110 + Divide by 4 + #0110 + + + 0111 + Divide by 2 + #0111 + + + 1000 + No Scaling + #1000 + + + 1001 + Multiply by 2 + #1001 + + + 1010 + Multiply by 4 + #1010 + + + 1011 + Multiply by 8 + #1011 + + + + + PLL_LD_DISABLE + Disable PLL Loop Divider + 12 + 1 + read-write + + + LPFF + LPM SDM Invalid Flag + 13 + 1 + read-write + + + LPM_SDM_INV + Invert LPM SDM + 14 + 1 + read-write + + + LPM_DISABLE + Disable LPM SDM + 15 + 1 + read-write + + + LPM_DTH_SCL + LPM Dither Scale + 16 + 4 + read-write + + + 0101 + -128 to 96 + #0101 + + + 0110 + -256 to 192 + #0110 + + + 0111 + -512 to 384 + #0111 + + + 1000 + -1024 to 768 + #1000 + + + 1001 + -2048 to 1536 + #1001 + + + 1010 + -4096 to 3072 + #1010 + + + 1011 + -8192 to 6144 + #1011 + + + + + LPM_D_CTRL + LPM Dither Control in Override Mode + 22 + 1 + read-write + + + LPM_D_OVRD + LPM Dither Override Mode Select + 23 + 1 + read-write + + + LPM_SCALE + LPM Scale Factor + 24 + 4 + read-write + + + 0000 + No Scaling + #0000 + + + 0001 + Multiply by 2 + #0001 + + + 0010 + Multiply by 4 + #0010 + + + 0011 + Multiply by 8 + #0011 + + + 0100 + Multiply by 16 + #0100 + + + 0101 + Multiply by 32 + #0101 + + + 0110 + Multiply by 64 + #0110 + + + 0111 + Multiply by 128 + #0111 + + + 1000 + Multiply by 256 + #1000 + + + 1001 + Multiply by 512 + #1001 + + + 1010 + Multiply by 1024 + #1010 + + + 1011 + Multiply by 2048 + #1011 + + + + + LPM_SDM_USE_NEG + Use the Negedge of the Sigma Delta clock + 31 + 1 + read-write + + + + + LPM_SDM_CTRL1 + PLL Low Port Sigma Delta Control 1 + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + LPM_INTG_SELECTED + Low Port Modulation Integer Value Selected + 0 + 7 + read-only + + + HPM_ARRAY_BIAS + Bias value for High Port DAC Array Midpoint + 8 + 7 + read-write + + + LPM_INTG + Manual Low Port Modulation Integer Value + 16 + 7 + read-write + + + SDM_MAP_DISABLE + Disable SDM Mapping + 31 + 1 + read-write + + + + + LPM_SDM_CTRL2 + PLL Low Port Sigma Delta Control 2 + 0x38 + 32 + read-write + 0x2000000 + 0xFFFFFFFF + + + LPM_NUM + Low Port Modulation Numerator + 0 + 28 + read-write + + + + + LPM_SDM_CTRL3 + PLL Low Port Sigma Delta Control 3 + 0x3C + 32 + read-write + 0x4000000 + 0xFFFFFFFF + + + LPM_DENOM + Low Port Modulation Denominator + 0 + 28 + read-write + + + + + LPM_SDM_RES1 + PLL Low Port Sigma Delta Result 1 + 0x40 + 32 + read-only + 0xE200000 + 0xFFFFFFFF + + + LPM_NUM_SELECTED + Low Port Modulation Numerator Applied + 0 + 28 + read-only + + + + + LPM_SDM_RES2 + PLL Low Port Sigma Delta Result 2 + 0x44 + 32 + read-only + 0x4000000 + 0xFFFFFFFF + + + LPM_DENOM_SELECTED + Low Port Modulation Denominator Selected + 0 + 28 + read-only + + + + + DELAY_MATCH + PLL Delay Matching + 0x48 + 32 + read-write + 0x204 + 0xFFFFFFFF + + + LPM_SDM_DELAY + Low Port SDM Delay Matching + 0 + 4 + read-write + + + HPM_SDM_DELAY + High Port SDM Delay Matching + 8 + 4 + read-write + + + HPM_INTEGER_DELAY + High Port Integer Delay Matching + 16 + 4 + read-write + + + + + BALUN_TX + Balun Tuning Cap Settings in Transmit Mode + 0x4C + 32 + read-write + 0 + 0xFFFFFFFF + + + TUNING_RANGE_0 + Tuning Range 0 + 0 + 3 + read-write + + + TUNING_RANGE_1 + Tuning Range 1 + 3 + 3 + read-write + + + TUNING_RANGE_2 + Tuning Range 2 + 6 + 3 + read-write + + + TUNING_RANGE_3 + Tuning Range 3 + 9 + 3 + read-write + + + TUNING_RANGE_4 + Tuning Range 4 + 12 + 3 + read-write + + + TUNING_RANGE_5 + Tuning Range 5 + 15 + 3 + read-write + + + TUNING_RANGE_6 + Tuning Range 6 + 18 + 3 + read-write + + + TUNING_RANGE_7 + Tuning Range 7 + 21 + 3 + read-write + + + + + BALUN_RX + Balun Tuning Cap Settings in Receive Mode + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + TUNING_RANGE_0 + Tuning Range 0 + 0 + 3 + read-write + + + TUNING_RANGE_1 + Tuning Range 1 + 3 + 3 + read-write + + + TUNING_RANGE_2 + Tuning Range 2 + 6 + 3 + read-write + + + TUNING_RANGE_3 + Tuning Range 3 + 9 + 3 + read-write + + + TUNING_RANGE_4 + Tuning Range 4 + 12 + 3 + read-write + + + TUNING_RANGE_5 + Tuning Range 5 + 15 + 3 + read-write + + + TUNING_RANGE_6 + Tuning Range 6 + 18 + 3 + read-write + + + TUNING_RANGE_7 + Tuning Range 7 + 21 + 3 + read-write + + + + + MAX_TX_CFG1_FREQ + Max Transmit Frequency For TX Configuration 1 + 0x58 + 32 + read-write + 0xFFF + 0xFFFFFFFF + + + MAX_TX_CFG1_FREQ + Maximum Transmit Frequency for Standard TX Settings + 0 + 12 + read-write + + + + + CTUNE_CTRL + PLL Coarse Tune Control + 0x5C + 32 + read-write + 0 + 0xFFFFFFFF + + + CTUNE_TARGET_MANUAL + Manual Coarse Tune Target + 0 + 12 + read-write + + + CTUNE_TARGET_DISABLE + Disable Coarse Tune Target + 15 + 1 + read-write + + + CTUNE_ADJUST + Coarse Tune Count Adjustment + 16 + 4 + read-write + + + CTUNE_MANUAL + Manual Coarse Tune Setting + 20 + 7 + read-write + + + CTUNE_DISABLE + Coarse Tune Disable + 31 + 1 + read-write + + + + + DATA_RATE_OVRD_CTRL1 + PLL Data Rate Override Control + 0x60 + 32 + read-write + 0 + 0xFFFFFFFF + + + HPM_CAL_SCALE_CFG1 + HPM Scale Configuration1 + 0 + 4 + read-write + + + LPM_SCALE_CFG1 + LPM Scale Configuration1 + 4 + 4 + read-write + + + HPM_FDB_RES_CAL_CFG1 + HPM FDB RES Calibration Configuration1 + 8 + 2 + read-write + + + HPM_FDB_RES_TX_CFG1 + HPM FDB RES Transmit Configuration1 + 10 + 2 + read-write + + + + + CTUNE_RES + PLL Coarse Tune Results + 0x84 + 32 + read-only + 0 + 0xFFFFFFFF + + + CTUNE_SELECTED + Coarse Tune Setting to VCO + 0 + 7 + read-only + + + CTUNE_BEST_DIFF + Coarse Tune Absolute Best Difference + 10 + 8 + read-only + + + CTUNE_FREQ_SELECTED + Coarse Tune Frequency Selected + 18 + 12 + read-only + + + + + + + XCVR_TX_DIG + XCVR_TX_DIG + 0x40087700 + + 0 + 0x60 + registers + + + + TXDIG_CTRL + TXDIG_CTRL + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + MODULATOR_SEL + MODULATOR_SEL + 0 + 1 + read-write + + + PFC_EN + PFC_EN + 1 + 1 + read-write + + + DATA_STREAM_SEL + DATA_STREAM_SEL + 2 + 1 + read-write + + + INV_DATA_OUT + INV_DATA_OUT + 4 + 1 + read-write + + + + + DATA_PADDING_CTRL + DATA_PADDING_CTRL + 0x4 + 32 + read-write + 0x10 + 0xFFFFFFFF + + + DATA_PADDING_SEL + DATA_PADDING_SEL + 0 + 2 + read-write + + + TX_CAPTURE_POL + TX_CAPTURE_POL + 2 + 1 + read-write + + + CTE_DATA + CTE_DATA + 4 + 1 + read-write + + + PAD_DLY + PAD_DLY + 8 + 4 + read-write + + + PAD_DLY_EN + PAD_DLY_EN + 12 + 1 + read-write + + + RAMP_DN_PAD_EN + RAMP_DN_PAD_EN + 16 + 1 + read-write + + + + + DATA_PADDING_CTRL_1 + DATA_PADDING_CTRL_1 + 0x8 + 32 + read-write + 0x1000 + 0xFFFFFFFF + + + RAMP_UP_DLY + RAMP_UP_DLY + 0 + 5 + read-write + + + TX_DATA_FLUSH_DLY + TX_DATA_FLUSH_DLY + 8 + 3 + read-write + + + PA_PUP_ADJ + PA_PUP_ADJ + 12 + 4 + read-write + + + + + DATA_PADDING_CTRL_2 + DATA_PADDING_CTRL_2 + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_PAD_MFDEV + DATA_PAD_MFDEV + 0 + 13 + read-write + + + DATA_PAD_PFDEV + DATA_PAD_PFDEV + 16 + 13 + read-write + + + + + FSK_CTRL + FSK_CTRL + 0x10 + 32 + read-write + 0x8001800 + 0xFFFFFFFF + + + FSK_FDEV_0 + FSK_FDEV_0 + 0 + 13 + read-write + + + FSK_FDEV_1 + FSK_FDEV_1 + 16 + 13 + read-write + + + + + GFSK_CTRL + GFSK_CTRL + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + GFSK_FDEV + GFSK_FDEV + 0 + 12 + read-write + + + GFSK_COEFF_MAN + GFSK_COEFF_MAN + 12 + 1 + read-write + + + BT_EQ_OR_GTR_ONE + BT_EQ_OR_GTR_ONE + 16 + 1 + read-write + + + + + GFSK_COEFF_0_1 + GFSK_COEFF_0_1 + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + GFSK_COEFF_0 + GFSK_COEFF_0 + 0 + 9 + read-write + + + GFSK_COEFF_1 + GFSK_COEFF_1 + 16 + 9 + read-write + + + + + GFSK_COEFF_2_3 + GFSK_COEFF_2_3 + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + GFSK_COEFF_2 + GFSK_COEFF_2 + 0 + 9 + read-write + + + GFSK_COEFF_3 + GFSK_COEFF_3 + 16 + 9 + read-write + + + + + GFSK_COEFF_4_5 + GFSK_COEFF_4_5 + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + GFSK_COEFF_4 + GFSK_COEFF_4 + 0 + 9 + read-write + + + GFSK_COEFF_5 + GFSK_COEFF_5 + 16 + 9 + read-write + + + + + GFSK_COEFF_6_7 + GFSK_COEFF_6_7 + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + GFSK_COEFF_6 + GFSK_COEFF_6 + 0 + 9 + read-write + + + GFSK_COEFF_7 + GFSK_COEFF_7 + 16 + 9 + read-write + + + + + IMAGE_FILTER_CTRL + IMAGE_FILTER_CTRL + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + IMAGE_FIR_FILTER_SEL + IMAGE_FIR_FILTER_SEL + 0 + 2 + read-write + + + IMAGE_FILTER_OVRD_EN + IMAGE_FILTER_OVRD_EN + 2 + 1 + read-write + + + IMAGE_FIR_FILTER_OVRD + IMAGE_FIR_FILTER_OVRD + 3 + 1 + read-write + + + IMAGE_SYNC1_FILTER_OVRD + IMAGE_SYNC1_FILTER_OVRD + 4 + 1 + read-write + + + IMAGE_SYNC0_FILTER_OVRD + IMAGE_SYNC0_FILTER_OVRD + 5 + 1 + read-write + + + FREQ_WORD_ADJ + FREQ_WORD_ADJ + 16 + 10 + read-write + + + + + PA_CTRL + PA_CTRL + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + PA_TGT_POWER + PA_TGT_POWER + 0 + 6 + read-write + + + TGT_PWR_SRC + TGT_PWR_SRC + 8 + 1 + read-write + + + EARLY_WU_COMPLETE + EARLY_WU_COMPLETE + 12 + 1 + read-write + + + PA_RAMP_SEL + PA_RAMP_SEL + 16 + 2 + read-write + + + TX_PA_PUP_OVRD + TX_PA_PUP_OVRD + 30 + 1 + read-write + + + TX_PA_PUP_OVRD_EN + TX_PA_PUP_OVRD_EN + 31 + 1 + read-write + + + + + PA_RAMP_TBL0 + PA_RAMP_TBL0 + 0x30 + 32 + read-write + 0x6040201 + 0xFFFFFFFF + + + PA_RAMP0 + PA_RAMP0 + 0 + 6 + read-write + + + PA_RAMP1 + PA_RAMP1 + 8 + 6 + read-write + + + PA_RAMP2 + PA_RAMP2 + 16 + 6 + read-write + + + PA_RAMP3 + PA_RAMP3 + 24 + 6 + read-write + + + + + PA_RAMP_TBL1 + PA_RAMP_TBL1 + 0x34 + 32 + read-write + 0x14100C08 + 0xFFFFFFFF + + + PA_RAMP4 + PA_RAMP4 + 0 + 6 + read-write + + + PA_RAMP5 + PA_RAMP5 + 8 + 6 + read-write + + + PA_RAMP6 + PA_RAMP6 + 16 + 6 + read-write + + + PA_RAMP7 + PA_RAMP7 + 24 + 6 + read-write + + + + + PA_RAMP_TBL2 + PA_RAMP_TBL2 + 0x38 + 32 + read-write + 0x28221C18 + 0xFFFFFFFF + + + PA_RAMP8 + PA_RAMP8 + 0 + 6 + read-write + + + PA_RAMP9 + PA_RAMP9 + 8 + 6 + read-write + + + PA_RAMP10 + PA_RAMP10 + 16 + 6 + read-write + + + PA_RAMP11 + PA_RAMP11 + 24 + 6 + read-write + + + + + PA_RAMP_TBL3 + PA_RAMP_TBL3 + 0x3C + 32 + read-write + 0x3C36302C + 0xFFFFFFFF + + + PA_RAMP12 + PA_RAMP12 + 0 + 6 + read-write + + + PA_RAMP13 + PA_RAMP13 + 8 + 6 + read-write + + + PA_RAMP14 + PA_RAMP14 + 16 + 6 + read-write + + + PA_RAMP15 + PA_RAMP15 + 24 + 6 + read-write + + + + + SWITCH_TX_CTRL + SWITCH_TX_CTRL + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + SWITCH_MOD + SWITCH_MOD + 0 + 1 + read-write + + + SWITCH_FIR_SEL + SWITCH_FIR_SEL + 1 + 2 + read-write + + + SWITCH_GFSK_COEFF + SWITCH_GFSK_COEFF + 3 + 1 + read-write + + + SWITCH_TGT_PWR + SWITCH_TGT_PWR + 8 + 6 + read-write + + + + + RF_DFT_TX_CTRL0 + RF_DFT_TX_CTRL0 + 0x44 + 32 + read-write + 0 + 0xFFFFFFFF + + + DFT_MAX_RAM_SIZE + DFT_MAX_RAM_SIZE + 0 + 15 + read-write + + + DFT_RAM_BASE_ADDR + DFT_RAM_BASE_ADDR + 16 + 15 + read-write + + + DFT_RAM_EN + DFT_RAM_EN + 31 + 1 + read-write + + + + + RF_DFT_TX_CTRL1 + RF_DFT_TX_CTRL1 + 0x48 + 32 + read-write + 0x2101FFFF + 0xFFFFFFFF + + + LFSR_OUT + LFSR_OUT + 0 + 17 + read-only + + + LFSR_CLK_SEL + LFSR_CLK_SEL + 24 + 3 + read-write + + + LFSR_LENGTH + LFSR_LENGTH + 27 + 3 + read-write + + + LRM + LRM + 30 + 1 + read-write + + + LFSR_EN + LFSR_EN + 31 + 1 + read-write + + + + + RF_DFT_TX_CTRL2 + RF_DFT_TX_CTRL2 + 0x4C + 32 + read-write + 0 + 0xFFFFFFFF + + + DFT_PA_AM_MOD_FREQ + DFT_PA_AM_MOD_FREQ + 0 + 4 + read-write + + + DFT_PA_AM_MOD_ENTRIES + DFT_PA_AM_MOD_ENTRIES + 4 + 4 + read-write + + + DFT_PA_AM_MOD_EN + DFT_PA_AM_MOD_EN + 8 + 1 + read-write + + + DFT_PATTERN_EN + DFT_PATTERN_EN + 31 + 1 + read-write + + + + + RF_DFT_PATTERN + RF_DFT_PATTERN + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + DFT_MOD_PATTERN + DFT_MOD_PATTERN + 0 + 32 + read-write + + + + + DATARATE_CONFIG_FSK_CTRL + DATARATE_CONFIG_FSK_CTRL + 0x54 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATARATE_CONFIG_FSK_FDEV0 + DATARATE_CONFIG_DATA_PAD_MFDEV + 0 + 13 + read-write + + + DATARATE_CONFIG_FSK_FDEV1 + DATARATE_CONFIG_DATA_PAD_PFDEV + 16 + 13 + read-write + + + + + DATARATE_CONFIG_GFSK_CTRL + DATARATE_CONFIG_GFSK_CTRL + 0x58 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATARATE_CONFIG_GFSK_FDEV + DATARATE_CONFIG_GFSK_FDEV + 0 + 12 + read-write + + + + + DATARATE_CONFIG_FILTER_CTRL + DATARATE_CONFIG_FILTER_CTRL + 0x5C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATARATE_CONFIG_IMAGE_FILTER_OVRD_EN + DATARATE_CONFIG_IMAGE_FILTER_OVRD_EN + 0 + 1 + read-write + + + DATARATE_CONFIG_FIR_FILTER_OVRD + DATARATE_CONFIG_FIR_FILTER_OVRD + 1 + 1 + read-write + + + DATARATE_CONFIG_SYNC0_FILTER_OVRD + DATARATE_CONFIG_SYNC0_FILTER_OVRD + 2 + 1 + read-write + + + DATARATE_CONFIG_SYNC1_FILTER_OVRD + DATARATE_CONFIG_SYNC1_FILTER_OVRD + 3 + 1 + read-write + + + DATARATE_CONFIG_GFSK_FILT_CLK_SEL + DATARATE_CONFIG_GFSK_FILT_CLK_SEL + 16 + 3 + read-write + + + DATARATE_CONFIG_SYNC0_CLK_SEL + DATARATE_CONFIG_IMAGE_SYNC0_CLK_SEL + 20 + 3 + read-write + + + DATARATE_CONFIG_SYNC1_CLK_SEL + DATARATE_CONFIG_IMAGE_SYNC1_CLK_SEL + 24 + 3 + read-write + + + DATARATE_CONFIG_IMAGE_FIR_CLK_SEL + DATARATE_CONFIG_IMAGE_FIR_CLK_SEL + 28 + 1 + read-write + + + + + + + XCVR_2P4GHZ_PHY + 2.4GHz PHY REGISTERS + 0x40087800 + + 0 + 0x118 + registers + + + + FSK_PD_CFG0 + PHY Uncoded Preamble Detect Config 0 + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + PREAMBLE_T_SCALE + Scaling factor used for fractional time estimation during preamble search. + 0 + 4 + read-write + + + PD_IIR_ALPHA + Forgetting factor used by the complex correlations smoothing leaky integrator. + 8 + 8 + read-write + + + + + FSK_PD_CFG1 + PHY Uncoded Preamble Detect Config 1 + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + PREAMBLE_PATTERN + 8-bit preamble pattern used in FM-domain preamble detector. + 0 + 8 + read-write + + + + + FSK_PD_CFG2 + PHY Uncoded Preamble Detect Config 2 + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + PD_THRESH_ACQ_1_3_1M + Preamble detect threshold for acq mode 1 and 3 at data rate 1Mbps + 0 + 8 + read-write + + + PD_THRESH_ACQ_1_3_2M + Preamble detect threshold for acq mode 1 and 3 at data rate 2Mbps + 16 + 8 + read-write + + + + + FSK_PD_PH0 + no description available + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + ref0 + Uncoded preamble reference waveform sample 0 (sfix6en5) + 0 + 6 + read-write + + + ref1 + Uncoded preamble reference waveform sample 1 (sfix6en5) + 8 + 6 + read-write + + + ref2 + Uncoded preamble reference waveform sample 2 (sfix6en5) + 16 + 6 + read-write + + + ref3 + Uncoded preamble reference waveform sample 3 (sfix6en5) + 24 + 6 + read-write + + + + + FSK_PD_PH1 + no description available + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + ref0 + Uncoded preamble reference waveform sample 4 (sfix6en5) + 0 + 6 + read-write + + + ref1 + Uncoded preamble reference waveform sample 5 (sfix6en5) + 8 + 6 + read-write + + + ref2 + Uncoded preamble reference waveform sample 6 (sfix6en5) + 16 + 6 + read-write + + + ref3 + Uncoded preamble reference waveform sample 7 (sfix6en5) + 24 + 6 + read-write + + + + + FSK_PD_RO_PH2 + no description available + 0x14 + 32 + read-only + 0 + 0xFFFFFFFF + + + ref0 + Uncoded preamble reference waveform sample 16 (sfix6en5) + 0 + 6 + read-only + + + ref1 + Uncoded preamble reference waveform sample 17 (sfix6en5) + 8 + 6 + read-only + + + ref2 + Uncoded preamble reference waveform sample 18 (sfix6en5) + 16 + 6 + read-only + + + ref3 + Uncoded preamble reference waveform sample 19 (sfix6en5) + 24 + 6 + read-only + + + + + FSK_PD_RO_PH3 + no description available + 0x18 + 32 + read-only + 0 + 0xFFFFFFFF + + + ref0 + Uncoded preamble reference waveform sample 20 (sfix6en5) + 0 + 6 + read-only + + + ref1 + Uncoded preamble reference waveform sample 21 (sfix6en5) + 8 + 6 + read-only + + + ref2 + Uncoded preamble reference waveform sample 22 (sfix6en5) + 16 + 6 + read-only + + + ref3 + Uncoded preamble reference waveform sample 23 (sfix6en5) + 24 + 6 + read-only + + + + + FSK_PD_RO_PH4 + no description available + 0x1C + 32 + read-only + 0 + 0xFFFFFFFF + + + ref0 + Uncoded preamble reference waveform sample 24 (sfix6en5) + 0 + 6 + read-only + + + ref1 + Uncoded preamble reference waveform sample 25 (sfix6en5) + 8 + 6 + read-only + + + ref2 + Uncoded preamble reference waveform sample 26 (sfix6en5) + 16 + 6 + read-only + + + ref3 + Uncoded preamble reference waveform sample 27 (sfix6en5) + 24 + 6 + read-only + + + + + FSK_PD_RO_PH5 + no description available + 0x20 + 32 + read-only + 0 + 0xFFFFFFFF + + + ref0 + Uncoded preamble reference waveform sample 28 (sfix6en5) + 0 + 6 + read-only + + + ref1 + Uncoded preamble reference waveform sample 29 (sfix6en5) + 8 + 6 + read-only + + + ref2 + Uncoded preamble reference waveform sample 30 (sfix6en5) + 16 + 6 + read-only + + + ref3 + Uncoded preamble reference waveform sample 31 (sfix6en5) + 24 + 6 + read-only + + + + + FSK_CFG0 + PHY Uncoded Config 0 + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + AA_OUT_SEL + Specifies which AA bits to be played-back to the LL: + 1 + 1 + read-write + + + 0 + output the received AA bits + #0 + + + 1 + output the programmed AA bits + #1 + + + + + FSK_BIT_INVERT + This applies at the demodulator, so it affects both AA and the data portions of the packet. + 2 + 1 + read-write + + + 0 + Normal demodulation + #0 + + + 1 + Invert demodulated bits + #1 + + + + + HAM_CHK_LOW_PWR + Indicates whether hamming-distance check is applied at signal levels below mag_thresh_high; + 4 + 1 + read-write + + + 0 + no + #0 + + + 1 + yes + #1 + + + + + MSK_EN + Configures PHY for MSK decoding. + 5 + 1 + read-write + + + MSK2FSK_SEED + Last bit of preamble. + 6 + 1 + read-write + + + AA_ACQ_1_2_3_THRESH_1M + For 1Mbps data rate, Correlation threshold applicable to AA detection; uses ufix5_En5 fixed-point format. + 8 + 5 + read-write + + + BLE_NTW_ADR_THR + Maximum hamming distance from the given AA pattern that may still be accepted as a match; valid range [0,7]. + 20 + 3 + read-write + + + AA_ACQ_1_2_3_THRESH_2M + For 2Mbps data rate, correlation threshold applicable to AA detection; uses ufix5_En5 fixed-point format. + 24 + 5 + read-write + + + + + FSK_CFG1 + PHY Uncoded Config 1 + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + OVERH + Modulation index; represented in ufix11_En7 format. + 0 + 11 + read-write + + + OVERH_INV + Reciprocal of modulation index; represented in ufix9_En7 format. + 11 + 9 + read-write + + + SYNCTSCALE + Scaling factor used for fractional time estimation during AA search; represented in ufix4_En3 format. + 24 + 4 + read-write + + + + + FSK_CFG2 + PHY Uncoded Config 2 + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + MAG_THRESH_1M + For 1Mbps data rate, the lowest signal level below which synchronization is considered unreliable and hence disallowed; uses ufix12_En24 fixed-point format. + 0 + 12 + read-write + + + MAG_THRESH_HI_1M + For 1Mbps data rate, the lowest signal level above which hamming-distance is always checked during AA detection; uses ufix12_En24 fixed-point format. + 16 + 12 + read-write + + + MAG_WIN + Indicates the forgetting factor used in received signal level measurement; + 28 + 4 + read-write + + + + + FSK_CFG3 + PHY Uncoded Config 3 + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + MAG_THRESH_2M + For 2Mbps data rate, the lowest signal level below which synchronization is considered unreliable and hence disallowed; uses ufix12_En24 fixed-point format. + 0 + 12 + read-write + + + MAG_THRESH_HI_2M + For 2Mbps data rate, the lowest signal level above which hamming-distance is always checked during AA detection; uses ufix12_En24 fixed-point format. + 16 + 12 + read-write + + + + + FSK_PT + PHY Uncoded Power Threshold Config + 0x34 + 32 + read-write + 0x80000 + 0xFFFFFFFF + + + AGC_TIMEOUT + Time-out, applicable to special conditioning of signal power detection in the Power threshold block, after each AGC gain adjustment. It is expressed in number of samples. + 0 + 16 + read-write + + + COND_SIG_PRST_EN + Enables special conditioning of signal detection; + 16 + 1 + read-write + + + 0 + disable. + #0 + + + 1 + enable. + #1 + + + + + COND_AA_BUFF_EN + Enables special condition for enabling AA detector buffer; + 17 + 1 + read-write + + + 0 + disable. + #0 + + + 1 + enable. + #1 + + + + + BYPASS_WITH_RSSI + Bypass signal power measurement with RSSI measurement; + 18 + 1 + read-write + + + 0 + no + #0 + + + 1 + yes + #1 + + + + + POW_TH_BYPASS + Bypass power threshold when AGC gain are not set max; + 19 + 1 + read-write + + + 0 + no bypass + #0 + + + 1 + yes bypass + #1 + + + + + + + FSK_FAD_CTRL + PHY Uncoded FAD Control + 0x38 + 32 + read-write + 0 + 0xFFFFFFFF + + + FAD_EN + Enables FAD; + 0 + 1 + read-write + + + 0 + disable. + #0 + + + 1 + enable. + #1 + + + + + + + FSK_FAD_CFG + PHY Uncoded FAD Config + 0x3C + 32 + read-write + 0 + 0xFFFFFFFF + + + WIN_FAD_WAIT_SYNCH + Time-window to wait for clean samples, before transitioning to AA search PHY state, if PD was found after antenna switch (refered to as T3 in the PHY state-machine section). + 0 + 7 + read-write + + + WIN_FAD_WAIT_PD + Time-window to wait for clean samples if PD was not found after antenna switch (refered to as T2 in the PHY state-machine section). + 8 + 7 + read-write + + + WIN_FAD_SEARCH_PD + Time-window to match preamble pattern on samples coming from the previously selected antenna (refered to as T1 in the PHY state-machine section). + 16 + 7 + read-write + + + WIN_SEARCH_PD + Time-window to match preamble pattern on samples coming from the currently selected antenna (refered to as T0 in the PHY state-machine section). + 24 + 7 + read-write + + + + + FSK_STAT + PHY Uncoded Status + 0x40 + 32 + read-only + 0 + 0xFFFFFFFF + + + EXT_TO_MODES_13 + Reserved + 1 + 1 + read-only + + + AA_FOUND + Indicates that a uncoded AA detect is active. + 2 + 1 + read-only + + + LAST_AA_BIT + reserved + 3 + 1 + read-only + + + AA_MATCH + Indicates which non-coded AA has matched. This will clear when the PHY is re-initialized. + 4 + 4 + read-only + + + HAMM_DIST + Indicates the hamming distance witnessed when AA match occurred. + 8 + 7 + read-only + + + CORR_MAX + Indicates the correlation witnessed when AA match occurred + 16 + 5 + read-only + + + TOF_OFF + Timing offset for use in time-of-flight calculation. + 28 + 4 + read-only + + + + + LR_PD_CFG + PHY Long Range Preamble Detect Config + 0x44 + 32 + read-write + 0 + 0xFFFFFFFF + + + CORR_TH + Correlation threshold applicable to preamble detection; uses (0,8,8) fixed-point format. + 0 + 8 + read-write + + + FREQ_TH + Threshold used to compare CFO estimates in the LR preamble detector; uses ufix5_En5 format. + 8 + 5 + read-write + + + NO_PEAKS + Number of consecutive correlation values that have to exceed the PD correlation threshold,for the same preamble phase, to assert preamble found; + 16 + 2 + read-write + + + 00 + 2 peaks; + #00 + + + 01 + 3 peaks; + #01 + + + 10 + 4 peaks; + #10 + + + 11 + 5 peaks; + #11 + + + + + + + LR_PD_PH0 + no description available + 0x48 + 32 + read-write + 0 + 0xFFFFFFFF + + + ref0 + Long range preamble reference waveform sample 0 (sfix6en5) + 0 + 6 + read-write + + + ref1 + Long range preamble reference waveform sample 1 (sfix6en5) + 8 + 6 + read-write + + + ref2 + Long range preamble reference waveform sample 2 (sfix6en5) + 16 + 6 + read-write + + + ref3 + Long range preamble reference waveform sample 3 (sfix6en5) + 24 + 6 + read-write + + + + + LR_PD_PH1 + no description available + 0x4C + 32 + read-write + 0 + 0xFFFFFFFF + + + ref0 + Long range preamble reference waveform sample 4 (sfix6en5) + 0 + 6 + read-write + + + ref1 + Long range preamble reference waveform sample 5 (sfix6en5) + 8 + 6 + read-write + + + ref2 + Long range preamble reference waveform sample 6 (sfix6en5) + 16 + 6 + read-write + + + ref3 + Long range preamble reference waveform sample 7 (sfix6en5) + 24 + 6 + read-write + + + + + LR_PD_PH2 + no description available + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + ref0 + Long range preamble reference waveform sample 8 (sfix6en5) + 0 + 6 + read-write + + + ref1 + Long range preamble reference waveform sample 9 (sfix6en5) + 8 + 6 + read-write + + + ref2 + Long range preamble reference waveform sample 10 (sfix6en5) + 16 + 6 + read-write + + + ref3 + Long range preamble reference waveform sample 11 (sfix6en5) + 24 + 6 + read-write + + + + + LR_PD_PH3 + no description available + 0x54 + 32 + read-write + 0 + 0xFFFFFFFF + + + ref0 + Long range preamble reference waveform sample 12 (sfix6en5) + 0 + 6 + read-write + + + ref1 + Long range preamble reference waveform sample 13 (sfix6en5) + 8 + 6 + read-write + + + ref2 + Long range preamble reference waveform sample 14 (sfix6en5) + 16 + 6 + read-write + + + ref3 + Long range preamble reference waveform sample 15 (sfix6en5) + 24 + 6 + read-write + + + + + LR_PD_RO_PH4 + no description available + 0x58 + 32 + read-only + 0 + 0xFFFFFFFF + + + ref0 + Long range preamble reference waveform sample 16 (sfix6en5) + 0 + 6 + read-only + + + ref1 + Long range preamble reference waveform sample 17 (sfix6en5) + 8 + 6 + read-only + + + ref2 + Long range preamble reference waveform sample 18 (sfix6en5) + 16 + 6 + read-only + + + ref3 + Long range preamble reference waveform sample 19 (sfix6en5) + 24 + 6 + read-only + + + + + LR_PD_RO_PH5 + no description available + 0x5C + 32 + read-only + 0 + 0xFFFFFFFF + + + ref0 + Long range preamble reference waveform sample 20 (sfix6en5) + 0 + 6 + read-only + + + ref1 + Long range preamble reference waveform sample 21 (sfix6en5) + 8 + 6 + read-only + + + ref2 + Long range preamble reference waveform sample 22 (sfix6en5) + 16 + 6 + read-only + + + ref3 + Long range preamble reference waveform sample 23 (sfix6en5) + 24 + 6 + read-only + + + + + LR_PD_RO_PH6 + no description available + 0x60 + 32 + read-only + 0 + 0xFFFFFFFF + + + ref0 + Long range preamble reference waveform sample 24 (sfix6en5) + 0 + 6 + read-only + + + ref1 + Long range preamble reference waveform sample 25 (sfix6en5) + 8 + 6 + read-only + + + ref2 + Long range preamble reference waveform sample 26 (sfix6en5) + 16 + 6 + read-only + + + ref3 + Long range preamble reference waveform sample 27 (sfix6en5) + 24 + 6 + read-only + + + + + LR_PD_RO_PH7 + no description available + 0x64 + 32 + read-only + 0 + 0xFFFFFFFF + + + ref0 + Long range preamble reference waveform sample 28 (sfix6en5) + 0 + 6 + read-only + + + ref1 + Long range preamble reference waveform sample 29 (sfix6en5) + 8 + 6 + read-only + + + ref2 + Long range preamble reference waveform sample 30 (sfix6en5) + 16 + 6 + read-only + + + ref3 + Long range preamble reference waveform sample 31 (sfix6en5) + 24 + 6 + read-only + + + + + LR_PD_RO_PH8 + no description available + 0x68 + 32 + read-only + 0 + 0xFFFFFFFF + + + ref0 + Long range preamble reference waveform sample 32 (sfix6en5) + 0 + 6 + read-only + + + ref1 + Long range preamble reference waveform sample 33 (sfix6en5) + 8 + 6 + read-only + + + ref2 + Long range preamble reference waveform sample 34 (sfix6en5) + 16 + 6 + read-only + + + ref3 + Long range preamble reference waveform sample 35 (sfix6en5) + 24 + 6 + read-only + + + + + LR_PD_RO_PH9 + no description available + 0x6C + 32 + read-only + 0 + 0xFFFFFFFF + + + ref0 + Long range preamble reference waveform sample 36 (sfix6en5) + 0 + 6 + read-only + + + ref1 + Long range preamble reference waveform sample 37 (sfix6en5) + 8 + 6 + read-only + + + ref2 + Long range preamble reference waveform sample 38 (sfix6en5) + 16 + 6 + read-only + + + ref3 + Long range preamble reference waveform sample 39 (sfix6en5) + 24 + 6 + read-only + + + + + LR_PD_RO_PH10 + no description available + 0x70 + 32 + read-only + 0 + 0xFFFFFFFF + + + ref0 + Long range preamble reference waveform sample 40 (sfix6en5) + 0 + 6 + read-only + + + ref1 + Long range preamble reference waveform sample 41 (sfix6en5) + 8 + 6 + read-only + + + ref2 + Long range preamble reference waveform sample 42 (sfix6en5) + 16 + 6 + read-only + + + ref3 + Long range preamble reference waveform sample 43 (sfix6en5) + 24 + 6 + read-only + + + + + LR_PD_RO_PH11 + no description available + 0x74 + 32 + read-only + 0 + 0xFFFFFFFF + + + ref0 + Long range preamble reference waveform sample 44 (sfix6en5) + 0 + 6 + read-only + + + ref1 + Long range preamble reference waveform sample 45 (sfix6en5) + 8 + 6 + read-only + + + ref2 + Long range preamble reference waveform sample 46 (sfix6en5) + 16 + 6 + read-only + + + ref3 + Long range preamble reference waveform sample 47 (sfix6en5) + 24 + 6 + read-only + + + + + LR_PD_RO_PH12 + no description available + 0x78 + 32 + read-only + 0 + 0xFFFFFFFF + + + ref0 + Long range preamble reference waveform sample 48 (sfix6en5) + 0 + 6 + read-only + + + ref1 + Long range preamble reference waveform sample 49 (sfix6en5) + 8 + 6 + read-only + + + ref2 + Long range preamble reference waveform sample 50 (sfix6en5) + 16 + 6 + read-only + + + ref3 + Long range preamble reference waveform sample 51 (sfix6en5) + 24 + 6 + read-only + + + + + LR_PD_RO_PH13 + no description available + 0x7C + 32 + read-only + 0 + 0xFFFFFFFF + + + ref0 + Long range preamble reference waveform sample 52 (sfix6en5) + 0 + 6 + read-only + + + ref1 + Long range preamble reference waveform sample 53 (sfix6en5) + 8 + 6 + read-only + + + ref2 + Long range preamble reference waveform sample 54 (sfix6en5) + 16 + 6 + read-only + + + ref3 + Long range preamble reference waveform sample 55 (sfix6en5) + 24 + 6 + read-only + + + + + LR_PD_RO_PH14 + no description available + 0x80 + 32 + read-only + 0 + 0xFFFFFFFF + + + ref0 + Long range preamble reference waveform sample 56 (sfix6en5) + 0 + 6 + read-only + + + ref1 + Long range preamble reference waveform sample 57 (sfix6en5) + 8 + 6 + read-only + + + ref2 + Long range preamble reference waveform sample 58 (sfix6en5) + 16 + 6 + read-only + + + ref3 + Long range preamble reference waveform sample 59 (sfix6en5) + 24 + 6 + read-only + + + + + LR_PD_RO_PH15 + no description available + 0x84 + 32 + read-only + 0 + 0xFFFFFFFF + + + ref0 + Long range preamble reference waveform sample 60 (sfix6en5) + 0 + 6 + read-only + + + ref1 + Long range preamble reference waveform sample 61 (sfix6en5) + 8 + 6 + read-only + + + ref2 + Long range preamble reference waveform sample 62 (sfix6en5) + 16 + 6 + read-only + + + ref3 + Long range preamble reference waveform sample 63 (sfix6en5) + 24 + 6 + read-only + + + + + LR_PD_RO_PH16 + no description available + 0x88 + 32 + read-only + 0 + 0xFFFFFFFF + + + ref0 + Long range preamble reference waveform sample 64 (sfix6en5) + 0 + 6 + read-only + + + ref1 + Long range preamble reference waveform sample 65 (sfix6en5) + 8 + 6 + read-only + + + ref2 + Long range preamble reference waveform sample 66 (sfix6en5) + 16 + 6 + read-only + + + ref3 + Long range preamble reference waveform sample 67 (sfix6en5) + 24 + 6 + read-only + + + + + LR_AA_CFG + PHY Long Range AA Config + 0x8C + 32 + read-write + 0 + 0xFFFFFFFF + + + AA_COR_THRESH + Threshold use to compare the correlation magnitude in the long-range AA correlator. + 0 + 8 + read-write + + + AA_HAM_THRESH + Threshold use to compare the Hamming distance, between reference coded sequence and received coded sequence, in the long-range AA correlator. + 8 + 6 + read-write + + + ACCESS_ADDR_HAM + Threshold use to compare the Hamming distance, between the reference AA sequence and the received Viterbi decoded AA sequence. + 16 + 5 + read-write + + + AA_LR_CORR_GAIN + AA correlator gain. Format ufix6en3. This gain is applied to soft bits from the demodulator before they are used for address search synchronization. + 24 + 6 + read-write + + + + + LR_STAT + PHY Long Range Status + 0x90 + 32 + read-only + 0 + 0xFFFFFFFF + + + DECODED_HAMM_DIST + Hamming distance between the reference sequence and the Viterbi decoded received sequence + 0 + 6 + read-only + + + AA_FOUND + Indicates that a AA detect is active for both LR and uncoded. + 6 + 1 + read-only + + + CI + CI received. + 7 + 1 + read-only + + + CODED_HAMM_DIST + Hamming distance between the coded reference sequence and the coded received sequence. + 8 + 7 + read-only + + + AA_CORR_MAX + Indicates the AA correlation magnitude witnessed when AA match occurred + 16 + 8 + read-only + + + CMAG_MAX + Indicates the maximum preamble correlation magnitude during preamble found + 24 + 8 + read-only + + + + + SM_CFG + PHY State Machine Config + 0x94 + 32 + read-write + 0 + 0xFFFFFFFF + + + ACQ_MODE + Acquisition mode for non-coded reception + 0 + 2 + read-write + + + 01 + Use preamble and verify a correlation peak, the synch at the symbol rate as symbol timing is established by the preamble acquisition + #01 + + + 10 + Use synch only (which may incorporate part of the preamble) + #10 + + + 11 + Use mainly the sync detection: Use a low threshold on the preamble detector and launch the synch detection only if the preamble has shown a recent peak + #11 + + + + + EN_PHY_SM_EXT_RST + Reserved, should keep 0. + 2 + 1 + read-write + + + AGC_FRZ_ON_PD_FOUND_ACQ1_LR + Specfies AGC freeze condition for non-coded acq.1 and Bluetooth LE long range. + 3 + 1 + read-write + + + 0 + AGC freeze on AA found. + #0 + + + 1 + AGC freeze asserted on PD found. + #1 + + + + + PH_BUFF_PTR_SYM + Phase buffer size to demodulator, long range only. + 4 + 2 + read-write + + + EARLY_PD_TIMEOUT + Time-out used to reset the AGC state-machine for the eventuality that an "PD found early" event occurs but it is not followed by an "PD found" event + 8 + 6 + read-write + + + AA_TIMEOUT_UNCODED + Time-out value for access address search for uncoded packets + 16 + 10 + read-write + + + + + MISC + PHY Misc Config + 0x98 + 32 + read-write + 0 + 0xFFFFFFFF + + + RSSI_CORR_TH + Threshold use to compare a correlation magnitude value, computed in the acquisition block, in order to determine the correlation flag value provided by the PHY to the LQI computation block. Format is ufix8_En8 + 0 + 8 + read-write + + + DMA_PAGE_SEL + Select which DMA page is send out + 8 + 3 + read-write + + + 000 + Select DMA PAGE 0 for M3C with cfo; + #000 + + + 001 + Select DMA PAGE 1 for M3C with magnitude; + #001 + + + 010 + Select DMA PAGE 2 for un-coded; + #010 + + + 011 + Select DMA PAGE 3 for Long Range Preampble Detect; + #011 + + + 100 + Select DMA PAGE 4 for Long Range AA Detect; + #100 + + + + + ECO1_RSVD + Reserved. Must be programed as reset value 0. + 11 + 5 + read-write + + + PHY_CLK_CTRL + Enables various clock gating features. Bits are individually decoded, so any combination is allowable. + 16 + 10 + read-write + + + ECO2_RSVD + Reserved + 26 + 4 + read-write + + + DTEST_MUX_EN + Reserved. Should be programed as reset value 0. + 30 + 1 + read-write + + + PHY_CLK_ON + Force PHY clock ON + 31 + 1 + read-write + + + + + STAT0 + PHY Status 0 + 0x9C + 32 + read-only + 0 + 0xFFFFFFFF + + + PD_FOUND + PD_FOUND for LR or uncoded + 0 + 1 + read-only + + + LR_DET_FLAG + Indicates Bluetooth LE long range was detected + 1 + 1 + read-only + + + AA_MATCHED + Indicates AA was matched for LR or uncoded + 2 + 1 + read-only + + + AA_FOUND_ID + Indicates which AA was matched for LR and uncode + 3 + 3 + read-only + + + 000 + uncoded address 0 matched + #000 + + + 001 + uncoded address 1 matched + #001 + + + 010 + uncoded address 2 matched + #010 + + + 011 + uncoded address 3 matched + #011 + + + 100 + long range address matched + #100 + + + + + DATA_RATE + Indicates the data rate of received bit + 6 + 2 + read-only + + + 00 + 1Mbps + #00 + + + 01 + 2Mbps + #01 + + + 10 + 125kbps + #10 + + + 11 + 500kbps + #11 + + + + + FRAC + Indicates the fractional timing estimate determined in the acquisition block. Format is sfix6_en5(sign extend from sfix3_En2). + 8 + 6 + read-only + + + CFO_EST + Indicates the currently estimated CFO. Format is sfix10_en9(sign extend form sfix8_en9) + 16 + 10 + read-only + + + + + STAT1 + PHY Status 1 + 0xA0 + 32 + read-only + 0 + 0xFFFFFFFF + + + AA_BITS + AA bits either received or programed + 0 + 32 + read-only + + + + + STAT2 + PHY Status 2 + 0xA4 + 32 + read-only + 0 + 0xFFFFFFFF + + + CNT_ANT_SW + Count of uncoded ANT switch event when FAD was enabled. + 0 + 2 + read-only + + + CNT_UNCAA_TIMEOUT + Count of uncoded AA search timeout event + 2 + 2 + read-only + + + CNT_LRAA_TIMEOUT + Count of lang range AA search timeout event + 4 + 2 + read-only + + + CNT_AACI_TIMEOUT + Count of long range AACI detect timeout event + 6 + 2 + read-only + + + CNT_AGC_RST + Count of AGC soft reset event + 8 + 2 + read-only + + + + + PREPHY_MISC + PHY PrePHY Misc Config + 0xA8 + 32 + read-write + 0 + 0xFFFFFFFF + + + BUFF_PTR_LR + Pointer to the PrePHY IQ buffer for the reception of the long-range packets. + 0 + 5 + read-write + + + BUFF_PTR_GFSK + Pointer to the PrePHY IQ buffer for the reception of the uncoded packets. + 8 + 5 + read-write + + + + + DMD_CTRL0 + PHY Demodulator Control 0 + 0xAC + 32 + read-write + 0 + 0xFFFFFFFF + + + TED_ACT_WIN + Active window size for the time tracking mechanism, expressed in symbols. + 0 + 2 + read-write + + + FED_ACT_WIN + Active window size for the frequency tracking mechanism, expressed in symbols. + 8 + 2 + read-write + + + DREP_SCALE_FREQ + Frequency domain signal scaling factor used by the de-repeater. + 16 + 4 + read-write + + + REPEAT_FACTOR + Repetition factor used by the de-repeater. + 20 + 3 + read-write + + + TERR_TRK_EN + Enables time tracking in the demodulator. + 26 + 1 + read-write + + + FERR_TRK_EN + Enables frequency tracking in the demodulator. + 27 + 1 + read-write + + + DREP_SINE_EN + Flag used to enable the non-linear operation in the de-repeater. + 28 + 1 + read-write + + + DEMOD_MOD + Determines the number of taps used by the demodulator correlators; + 29 + 2 + read-write + + + 00 + use 12 taps + #00 + + + 01 + use 4 taps + #01 + + + 10 + use 7 taps + #10 + + + 11 + use 13 taps + #11 + + + + + + + DMD_CTRL1 + PHY Dmodulator Control 1 + 0xB0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FED_IDLE_WIN + Idle window size for the frequency tracking mechanism, expressed in symbols. + 0 + 10 + read-write + + + TED_ERR_SCALE + Scaling factor used by the time tracking loop. + 10 + 4 + read-write + + + FED_IMM_MEAS_EN + Specifies whether the frequency tracking starts with an active window; + 15 + 1 + read-write + + + 0 + start with idle window + #0 + + + 1 + start with active window + #1 + + + + + TED_IDLE_WIN + Idle window size for the time tracking mechanism, expressed in symbols. + 16 + 10 + read-write + + + TTRK_INT_RANGE + Timing error correction interpolation range, expressed in samples. The value must equal or bigger than 1. + 26 + 4 + read-write + + + TED_IMM_MEAS_EN + Specifies whether the time tracking starts with an active window; + 31 + 1 + read-write + + + 0 + start with idle window + #0 + + + 1 + start with active window + #1 + + + + + + + DMD_CTRL2 + PHY Demodulator Control 2 + 0xB4 + 32 + read-write + 0x111 + 0xFFFFFFFF + + + WAIT_DMD_LR_ADJ + Reserved. Must be programed as reset value 1. + 0 + 4 + read-write + + + WAIT_VIA_AFTER_AA_ADJ + Reserved. Must be programed as reset value 1. + 4 + 4 + read-write + + + WAIT_DMD_CLKEN_ADJ + Reserved. Must be programed as reset value 1. + 8 + 4 + read-write + + + + + DMD_WAVE0_REG0 + no description available + 0xB8 + 32 + read-write + 0 + 0xFFFFFFFF + + + SMPL0 + Demodulator waveform 0 sample 0 (sfix6en5) + 0 + 6 + read-write + + + SMPL1 + Demodulator waveform 0 sample 1 (sfix6en5) + 6 + 6 + read-write + + + SMPL2 + Demodulator waveform 0 sample 2 (sfix6en5) + 12 + 6 + read-write + + + SMPL3 + Demodulator waveform 0 sample 3 (sfix6en5) + 18 + 6 + read-write + + + SMPL4 + Demodulator waveform 0 sample 4 (sfix6en5) + 24 + 6 + read-write + + + + + DMD_WAVE0_REG1 + no description available + 0xBC + 32 + read-write + 0 + 0xFFFFFFFF + + + SMPL5 + Demodulator waveform 0 sample 5 (sfix6en5) + 0 + 6 + read-write + + + SMPL6 + Demodulator waveform 0 sample 6 (sfix6en5) + 6 + 6 + read-write + + + SMPL7 + Demodulator waveform 0 sample 7 (sfix6en5) + 12 + 6 + read-write + + + SMPL8 + Demodulator waveform 0 sample 8 (sfix6en5) + 18 + 6 + read-write + + + SMPL9 + Demodulator waveform 0 sample 9 (sfix6en5) + 24 + 6 + read-write + + + + + DMD_WAVE0_REG2 + no description available + 0xC0 + 32 + read-write + 0 + 0xFFFFFFFF + + + SMPL10 + Demodulator waveform 0 sample 10 (sfix6en5) + 0 + 6 + read-write + + + SMPL11 + Demodulator waveform 0 sample 11 (sfix6en5) + 6 + 6 + read-write + + + SMPL12 + Demodulator waveform 0 sample 12 (sfix6en5) + 12 + 6 + read-write + + + + + DMD_WAVE1_REG0 + no description available + 0xC4 + 32 + read-write + 0 + 0xFFFFFFFF + + + SMPL0 + Demodulator waveform 1 sample 0 (sfix6en5) + 0 + 6 + read-write + + + SMPL1 + Demodulator waveform 1 sample 1 (sfix6en5) + 6 + 6 + read-write + + + SMPL2 + Demodulator waveform 1 sample 2 (sfix6en5) + 12 + 6 + read-write + + + SMPL3 + Demodulator waveform 1 sample 3 (sfix6en5) + 18 + 6 + read-write + + + SMPL4 + Demodulator waveform 1 sample 4 (sfix6en5) + 24 + 6 + read-write + + + + + DMD_WAVE1_REG1 + no description available + 0xC8 + 32 + read-write + 0 + 0xFFFFFFFF + + + SMPL5 + Demodulator waveform 1 sample 5 (sfix6en5) + 0 + 6 + read-write + + + SMPL6 + Demodulator waveform 1 sample 6 (sfix6en5) + 6 + 6 + read-write + + + SMPL7 + Demodulator waveform 1 sample 7 (sfix6en5) + 12 + 6 + read-write + + + SMPL8 + Demodulator waveform 1 sample 8 (sfix6en5) + 18 + 6 + read-write + + + SMPL9 + Demodulator waveform 1 sample 9 (sfix6en5) + 24 + 6 + read-write + + + + + DMD_WAVE1_REG2 + no description available + 0xCC + 32 + read-write + 0 + 0xFFFFFFFF + + + SMPL10 + Demodulator waveform 1 sample 10 (sfix6en5) + 0 + 6 + read-write + + + SMPL11 + Demodulator waveform 1 sample 11 (sfix6en5) + 6 + 6 + read-write + + + SMPL12 + Demodulator waveform 1 sample 12 (sfix6en5) + 12 + 6 + read-write + + + + + DMD_WAVE2_REG0 + no description available + 0xD0 + 32 + read-write + 0 + 0xFFFFFFFF + + + SMPL0 + Demodulator waveform 2 sample 0 (sfix6en5) + 0 + 6 + read-write + + + SMPL1 + Demodulator waveform 2 sample 1 (sfix6en5) + 6 + 6 + read-write + + + SMPL2 + Demodulator waveform 2 sample 2 (sfix6en5) + 12 + 6 + read-write + + + SMPL3 + Demodulator waveform 2 sample 3 (sfix6en5) + 18 + 6 + read-write + + + SMPL4 + Demodulator waveform 2 sample 4 (sfix6en5) + 24 + 6 + read-write + + + + + DMD_WAVE2_REG1 + no description available + 0xD4 + 32 + read-write + 0 + 0xFFFFFFFF + + + SMPL5 + Demodulator waveform 2 sample 5 (sfix6en5) + 0 + 6 + read-write + + + SMPL6 + Demodulator waveform 2 sample 6 (sfix6en5) + 6 + 6 + read-write + + + SMPL7 + Demodulator waveform 2 sample 7 (sfix6en5) + 12 + 6 + read-write + + + SMPL8 + Demodulator waveform 2 sample 8 (sfix6en5) + 18 + 6 + read-write + + + SMPL9 + Demodulator waveform 2 sample 9 (sfix6en5) + 24 + 6 + read-write + + + + + DMD_WAVE2_REG2 + no description available + 0xD8 + 32 + read-write + 0 + 0xFFFFFFFF + + + SMPL10 + Demodulator waveform 2 sample 10 (sfix6en5) + 0 + 6 + read-write + + + SMPL11 + Demodulator waveform 2 sample 11 (sfix6en5) + 6 + 6 + read-write + + + SMPL12 + Demodulator waveform 2 sample 12 (sfix6en5) + 12 + 6 + read-write + + + + + DMD_WAVE3_REG0 + no description available + 0xDC + 32 + read-write + 0 + 0xFFFFFFFF + + + SMPL0 + Demodulator waveform 3 sample 0 (sfix6en5) + 0 + 6 + read-write + + + SMPL1 + Demodulator waveform 3 sample 1 (sfix6en5) + 6 + 6 + read-write + + + SMPL2 + Demodulator waveform 3 sample 2 (sfix6en5) + 12 + 6 + read-write + + + SMPL3 + Demodulator waveform 3 sample 3 (sfix6en5) + 18 + 6 + read-write + + + SMPL4 + Demodulator waveform 3 sample 4 (sfix6en5) + 24 + 6 + read-write + + + + + DMD_WAVE3_REG1 + no description available + 0xE0 + 32 + read-write + 0 + 0xFFFFFFFF + + + SMPL5 + Demodulator waveform 3 sample 5 (sfix6en5) + 0 + 6 + read-write + + + SMPL6 + Demodulator waveform 3 sample 6 (sfix6en5) + 6 + 6 + read-write + + + SMPL7 + Demodulator waveform 3 sample 7 (sfix6en5) + 12 + 6 + read-write + + + SMPL8 + Demodulator waveform 3 sample 8 (sfix6en5) + 18 + 6 + read-write + + + SMPL9 + Demodulator waveform 3 sample 9 (sfix6en5) + 24 + 6 + read-write + + + + + DMD_WAVE3_REG2 + no description available + 0xE4 + 32 + read-write + 0 + 0xFFFFFFFF + + + SMPL10 + Demodulator waveform 3 sample 10 (sfix6en5) + 0 + 6 + read-write + + + SMPL11 + Demodulator waveform 3 sample 11 (sfix6en5) + 6 + 6 + read-write + + + SMPL12 + Demodulator waveform 3 sample 12 (sfix6en5) + 12 + 6 + read-write + + + + + DMD_WAVE4_REG0 + no description available + 0xE8 + 32 + read-write + 0 + 0xFFFFFFFF + + + SMPL0 + Demodulator waveform 4 sample 0 (sfix6en5) + 0 + 6 + read-write + + + SMPL1 + Demodulator waveform 4 sample 1 (sfix6en5) + 6 + 6 + read-write + + + SMPL2 + Demodulator waveform 4 sample 2 (sfix6en5) + 12 + 6 + read-write + + + SMPL3 + Demodulator waveform 4 sample 3 (sfix6en5) + 18 + 6 + read-write + + + SMPL4 + Demodulator waveform 4 sample 4 (sfix6en5) + 24 + 6 + read-write + + + + + DMD_WAVE4_REG1 + no description available + 0xEC + 32 + read-write + 0 + 0xFFFFFFFF + + + SMPL5 + Demodulator waveform 4 sample 5 (sfix6en5) + 0 + 6 + read-write + + + SMPL6 + Demodulator waveform 4 sample 6 (sfix6en5) + 6 + 6 + read-write + + + SMPL7 + Demodulator waveform 4 sample 7 (sfix6en5) + 12 + 6 + read-write + + + SMPL8 + Demodulator waveform 4 sample 8 (sfix6en5) + 18 + 6 + read-write + + + SMPL9 + Demodulator waveform 4 sample 9 (sfix6en5) + 24 + 6 + read-write + + + + + DMD_WAVE4_REG2 + no description available + 0xF0 + 32 + read-write + 0 + 0xFFFFFFFF + + + SMPL10 + Demodulator waveform 4 sample 10 (sfix6en5) + 0 + 6 + read-write + + + SMPL11 + Demodulator waveform 4 sample 11 (sfix6en5) + 6 + 6 + read-write + + + SMPL12 + Demodulator waveform 4 sample 12 (sfix6en5) + 12 + 6 + read-write + + + + + DMD_WAVE5_REG0 + no description available + 0xF4 + 32 + read-write + 0 + 0xFFFFFFFF + + + SMPL0 + Demodulator waveform 5 sample 0 (sfix6en5) + 0 + 6 + read-write + + + SMPL1 + Demodulator waveform 5 sample 1 (sfix6en5) + 6 + 6 + read-write + + + SMPL2 + Demodulator waveform 5 sample 2 (sfix6en5) + 12 + 6 + read-write + + + SMPL3 + Demodulator waveform 5 sample 3 (sfix6en5) + 18 + 6 + read-write + + + SMPL4 + Demodulator waveform 5 sample 4 (sfix6en5) + 24 + 6 + read-write + + + + + DMD_WAVE5_REG1 + no description available + 0xF8 + 32 + read-write + 0 + 0xFFFFFFFF + + + SMPL5 + Demodulator waveform 5 sample 5 (sfix6en5) + 0 + 6 + read-write + + + SMPL6 + Demodulator waveform 5 sample 6 (sfix6en5) + 6 + 6 + read-write + + + SMPL7 + Demodulator waveform 5 sample 7 (sfix6en5) + 12 + 6 + read-write + + + SMPL8 + Demodulator waveform 5 sample 8 (sfix6en5) + 18 + 6 + read-write + + + SMPL9 + Demodulator waveform 5 sample 9 (sfix6en5) + 24 + 6 + read-write + + + + + DMD_WAVE5_REG2 + no description available + 0xFC + 32 + read-write + 0 + 0xFFFFFFFF + + + SMPL10 + Demodulator waveform 5 sample 10 (sfix6en5) + 0 + 6 + read-write + + + SMPL11 + Demodulator waveform 5 sample 11 (sfix6en5) + 6 + 6 + read-write + + + SMPL12 + Demodulator waveform 5 sample 12 (sfix6en5) + 12 + 6 + read-write + + + + + DMD_WAVE6_REG0 + no description available + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + SMPL0 + Demodulator waveform 6 sample 0 (sfix6en5) + 0 + 6 + read-write + + + SMPL1 + Demodulator waveform 6 sample 1 (sfix6en5) + 6 + 6 + read-write + + + SMPL2 + Demodulator waveform 6 sample 2 (sfix6en5) + 12 + 6 + read-write + + + SMPL3 + Demodulator waveform 6 sample 3 (sfix6en5) + 18 + 6 + read-write + + + SMPL4 + Demodulator waveform 6 sample 4 (sfix6en5) + 24 + 6 + read-write + + + + + DMD_WAVE6_REG1 + no description available + 0x104 + 32 + read-write + 0 + 0xFFFFFFFF + + + SMPL5 + Demodulator waveform 6 sample 5 (sfix6en5) + 0 + 6 + read-write + + + SMPL6 + Demodulator waveform 6 sample 6 (sfix6en5) + 6 + 6 + read-write + + + SMPL7 + Demodulator waveform 6 sample 7 (sfix6en5) + 12 + 6 + read-write + + + SMPL8 + Demodulator waveform 6 sample 8 (sfix6en5) + 18 + 6 + read-write + + + SMPL9 + Demodulator waveform 6 sample 9 (sfix6en5) + 24 + 6 + read-write + + + + + DMD_WAVE6_REG2 + no description available + 0x108 + 32 + read-write + 0 + 0xFFFFFFFF + + + SMPL10 + Demodulator waveform 6 sample 10 (sfix6en5) + 0 + 6 + read-write + + + SMPL11 + Demodulator waveform 6 sample 11 (sfix6en5) + 6 + 6 + read-write + + + SMPL12 + Demodulator waveform 6 sample 12 (sfix6en5) + 12 + 6 + read-write + + + + + DMD_WAVE7_REG0 + no description available + 0x10C + 32 + read-write + 0 + 0xFFFFFFFF + + + SMPL0 + Demodulator waveform 7 sample 0 (sfix6en5) + 0 + 6 + read-write + + + SMPL1 + Demodulator waveform 7 sample 1 (sfix6en5) + 6 + 6 + read-write + + + SMPL2 + Demodulator waveform 7 sample 2 (sfix6en5) + 12 + 6 + read-write + + + SMPL3 + Demodulator waveform 7 sample 3 (sfix6en5) + 18 + 6 + read-write + + + SMPL4 + Demodulator waveform 7 sample 4 (sfix6en5) + 24 + 6 + read-write + + + + + DMD_WAVE7_REG1 + no description available + 0x110 + 32 + read-write + 0 + 0xFFFFFFFF + + + SMPL5 + Demodulator waveform 7 sample 5 (sfix6en5) + 0 + 6 + read-write + + + SMPL6 + Demodulator waveform 7 sample 6 (sfix6en5) + 6 + 6 + read-write + + + SMPL7 + Demodulator waveform 7 sample 7 (sfix6en5) + 12 + 6 + read-write + + + SMPL8 + Demodulator waveform 7 sample 8 (sfix6en5) + 18 + 6 + read-write + + + SMPL9 + Demodulator waveform 7 sample 9 (sfix6en5) + 24 + 6 + read-write + + + + + DMD_WAVE7_REG2 + no description available + 0x114 + 32 + read-write + 0 + 0xFFFFFFFF + + + SMPL10 + Demodulator waveform 7 sample 10 (sfix6en5) + 0 + 6 + read-write + + + SMPL11 + Demodulator waveform 7 sample 11 (sfix6en5) + 6 + 6 + read-write + + + SMPL12 + Demodulator waveform 7 sample 12 (sfix6en5) + 12 + 6 + read-write + + + + + + + TX_PACKET_RAM + RADIO_PACKET_RAM + RADIO_PACKET_RAM + 0x40088000 + + 0 + 0x2800 + registers + + + + PACKET_RAM_0 + Shared Packet RAM for multiple Link Layer usage. + 0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1 + Shared Packet RAM for multiple Link Layer usage. + 0x4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2 + Shared Packet RAM for multiple Link Layer usage. + 0x8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_3 + Shared Packet RAM for multiple Link Layer usage. + 0xC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_4 + Shared Packet RAM for multiple Link Layer usage. + 0x10 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_5 + Shared Packet RAM for multiple Link Layer usage. + 0x14 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_6 + Shared Packet RAM for multiple Link Layer usage. + 0x18 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_7 + Shared Packet RAM for multiple Link Layer usage. + 0x1C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_8 + Shared Packet RAM for multiple Link Layer usage. + 0x20 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_9 + Shared Packet RAM for multiple Link Layer usage. + 0x24 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_10 + Shared Packet RAM for multiple Link Layer usage. + 0x28 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_11 + Shared Packet RAM for multiple Link Layer usage. + 0x2C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_12 + Shared Packet RAM for multiple Link Layer usage. + 0x30 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_13 + Shared Packet RAM for multiple Link Layer usage. + 0x34 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_14 + Shared Packet RAM for multiple Link Layer usage. + 0x38 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_15 + Shared Packet RAM for multiple Link Layer usage. + 0x3C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_16 + Shared Packet RAM for multiple Link Layer usage. + 0x40 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_17 + Shared Packet RAM for multiple Link Layer usage. + 0x44 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_18 + Shared Packet RAM for multiple Link Layer usage. + 0x48 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_19 + Shared Packet RAM for multiple Link Layer usage. + 0x4C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_20 + Shared Packet RAM for multiple Link Layer usage. + 0x50 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_21 + Shared Packet RAM for multiple Link Layer usage. + 0x54 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_22 + Shared Packet RAM for multiple Link Layer usage. + 0x58 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_23 + Shared Packet RAM for multiple Link Layer usage. + 0x5C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_24 + Shared Packet RAM for multiple Link Layer usage. + 0x60 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_25 + Shared Packet RAM for multiple Link Layer usage. + 0x64 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_26 + Shared Packet RAM for multiple Link Layer usage. + 0x68 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_27 + Shared Packet RAM for multiple Link Layer usage. + 0x6C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_28 + Shared Packet RAM for multiple Link Layer usage. + 0x70 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_29 + Shared Packet RAM for multiple Link Layer usage. + 0x74 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_30 + Shared Packet RAM for multiple Link Layer usage. + 0x78 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_31 + Shared Packet RAM for multiple Link Layer usage. + 0x7C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_32 + Shared Packet RAM for multiple Link Layer usage. + 0x80 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_33 + Shared Packet RAM for multiple Link Layer usage. + 0x84 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_34 + Shared Packet RAM for multiple Link Layer usage. + 0x88 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_35 + Shared Packet RAM for multiple Link Layer usage. + 0x8C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_36 + Shared Packet RAM for multiple Link Layer usage. + 0x90 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_37 + Shared Packet RAM for multiple Link Layer usage. + 0x94 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_38 + Shared Packet RAM for multiple Link Layer usage. + 0x98 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_39 + Shared Packet RAM for multiple Link Layer usage. + 0x9C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_40 + Shared Packet RAM for multiple Link Layer usage. + 0xA0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_41 + Shared Packet RAM for multiple Link Layer usage. + 0xA4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_42 + Shared Packet RAM for multiple Link Layer usage. + 0xA8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_43 + Shared Packet RAM for multiple Link Layer usage. + 0xAC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_44 + Shared Packet RAM for multiple Link Layer usage. + 0xB0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_45 + Shared Packet RAM for multiple Link Layer usage. + 0xB4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_46 + Shared Packet RAM for multiple Link Layer usage. + 0xB8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_47 + Shared Packet RAM for multiple Link Layer usage. + 0xBC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_48 + Shared Packet RAM for multiple Link Layer usage. + 0xC0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_49 + Shared Packet RAM for multiple Link Layer usage. + 0xC4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_50 + Shared Packet RAM for multiple Link Layer usage. + 0xC8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_51 + Shared Packet RAM for multiple Link Layer usage. + 0xCC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_52 + Shared Packet RAM for multiple Link Layer usage. + 0xD0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_53 + Shared Packet RAM for multiple Link Layer usage. + 0xD4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_54 + Shared Packet RAM for multiple Link Layer usage. + 0xD8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_55 + Shared Packet RAM for multiple Link Layer usage. + 0xDC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_56 + Shared Packet RAM for multiple Link Layer usage. + 0xE0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_57 + Shared Packet RAM for multiple Link Layer usage. + 0xE4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_58 + Shared Packet RAM for multiple Link Layer usage. + 0xE8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_59 + Shared Packet RAM for multiple Link Layer usage. + 0xEC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_60 + Shared Packet RAM for multiple Link Layer usage. + 0xF0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_61 + Shared Packet RAM for multiple Link Layer usage. + 0xF4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_62 + Shared Packet RAM for multiple Link Layer usage. + 0xF8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_63 + Shared Packet RAM for multiple Link Layer usage. + 0xFC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_64 + Shared Packet RAM for multiple Link Layer usage. + 0x100 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_65 + Shared Packet RAM for multiple Link Layer usage. + 0x104 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_66 + Shared Packet RAM for multiple Link Layer usage. + 0x108 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_67 + Shared Packet RAM for multiple Link Layer usage. + 0x10C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_68 + Shared Packet RAM for multiple Link Layer usage. + 0x110 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_69 + Shared Packet RAM for multiple Link Layer usage. + 0x114 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_70 + Shared Packet RAM for multiple Link Layer usage. + 0x118 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_71 + Shared Packet RAM for multiple Link Layer usage. + 0x11C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_72 + Shared Packet RAM for multiple Link Layer usage. + 0x120 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_73 + Shared Packet RAM for multiple Link Layer usage. + 0x124 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_74 + Shared Packet RAM for multiple Link Layer usage. + 0x128 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_75 + Shared Packet RAM for multiple Link Layer usage. + 0x12C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_76 + Shared Packet RAM for multiple Link Layer usage. + 0x130 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_77 + Shared Packet RAM for multiple Link Layer usage. + 0x134 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_78 + Shared Packet RAM for multiple Link Layer usage. + 0x138 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_79 + Shared Packet RAM for multiple Link Layer usage. + 0x13C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_80 + Shared Packet RAM for multiple Link Layer usage. + 0x140 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_81 + Shared Packet RAM for multiple Link Layer usage. + 0x144 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_82 + Shared Packet RAM for multiple Link Layer usage. + 0x148 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_83 + Shared Packet RAM for multiple Link Layer usage. + 0x14C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_84 + Shared Packet RAM for multiple Link Layer usage. + 0x150 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_85 + Shared Packet RAM for multiple Link Layer usage. + 0x154 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_86 + Shared Packet RAM for multiple Link Layer usage. + 0x158 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_87 + Shared Packet RAM for multiple Link Layer usage. + 0x15C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_88 + Shared Packet RAM for multiple Link Layer usage. + 0x160 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_89 + Shared Packet RAM for multiple Link Layer usage. + 0x164 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_90 + Shared Packet RAM for multiple Link Layer usage. + 0x168 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_91 + Shared Packet RAM for multiple Link Layer usage. + 0x16C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_92 + Shared Packet RAM for multiple Link Layer usage. + 0x170 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_93 + Shared Packet RAM for multiple Link Layer usage. + 0x174 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_94 + Shared Packet RAM for multiple Link Layer usage. + 0x178 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_95 + Shared Packet RAM for multiple Link Layer usage. + 0x17C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_96 + Shared Packet RAM for multiple Link Layer usage. + 0x180 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_97 + Shared Packet RAM for multiple Link Layer usage. + 0x184 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_98 + Shared Packet RAM for multiple Link Layer usage. + 0x188 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_99 + Shared Packet RAM for multiple Link Layer usage. + 0x18C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_100 + Shared Packet RAM for multiple Link Layer usage. + 0x190 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_101 + Shared Packet RAM for multiple Link Layer usage. + 0x194 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_102 + Shared Packet RAM for multiple Link Layer usage. + 0x198 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_103 + Shared Packet RAM for multiple Link Layer usage. + 0x19C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_104 + Shared Packet RAM for multiple Link Layer usage. + 0x1A0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_105 + Shared Packet RAM for multiple Link Layer usage. + 0x1A4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_106 + Shared Packet RAM for multiple Link Layer usage. + 0x1A8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_107 + Shared Packet RAM for multiple Link Layer usage. + 0x1AC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_108 + Shared Packet RAM for multiple Link Layer usage. + 0x1B0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_109 + Shared Packet RAM for multiple Link Layer usage. + 0x1B4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_110 + Shared Packet RAM for multiple Link Layer usage. + 0x1B8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_111 + Shared Packet RAM for multiple Link Layer usage. + 0x1BC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_112 + Shared Packet RAM for multiple Link Layer usage. + 0x1C0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_113 + Shared Packet RAM for multiple Link Layer usage. + 0x1C4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_114 + Shared Packet RAM for multiple Link Layer usage. + 0x1C8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_115 + Shared Packet RAM for multiple Link Layer usage. + 0x1CC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_116 + Shared Packet RAM for multiple Link Layer usage. + 0x1D0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_117 + Shared Packet RAM for multiple Link Layer usage. + 0x1D4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_118 + Shared Packet RAM for multiple Link Layer usage. + 0x1D8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_119 + Shared Packet RAM for multiple Link Layer usage. + 0x1DC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_120 + Shared Packet RAM for multiple Link Layer usage. + 0x1E0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_121 + Shared Packet RAM for multiple Link Layer usage. + 0x1E4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_122 + Shared Packet RAM for multiple Link Layer usage. + 0x1E8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_123 + Shared Packet RAM for multiple Link Layer usage. + 0x1EC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_124 + Shared Packet RAM for multiple Link Layer usage. + 0x1F0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_125 + Shared Packet RAM for multiple Link Layer usage. + 0x1F4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_126 + Shared Packet RAM for multiple Link Layer usage. + 0x1F8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_127 + Shared Packet RAM for multiple Link Layer usage. + 0x1FC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_128 + Shared Packet RAM for multiple Link Layer usage. + 0x200 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_129 + Shared Packet RAM for multiple Link Layer usage. + 0x204 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_130 + Shared Packet RAM for multiple Link Layer usage. + 0x208 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_131 + Shared Packet RAM for multiple Link Layer usage. + 0x20C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_132 + Shared Packet RAM for multiple Link Layer usage. + 0x210 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_133 + Shared Packet RAM for multiple Link Layer usage. + 0x214 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_134 + Shared Packet RAM for multiple Link Layer usage. + 0x218 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_135 + Shared Packet RAM for multiple Link Layer usage. + 0x21C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_136 + Shared Packet RAM for multiple Link Layer usage. + 0x220 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_137 + Shared Packet RAM for multiple Link Layer usage. + 0x224 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_138 + Shared Packet RAM for multiple Link Layer usage. + 0x228 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_139 + Shared Packet RAM for multiple Link Layer usage. + 0x22C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_140 + Shared Packet RAM for multiple Link Layer usage. + 0x230 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_141 + Shared Packet RAM for multiple Link Layer usage. + 0x234 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_142 + Shared Packet RAM for multiple Link Layer usage. + 0x238 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_143 + Shared Packet RAM for multiple Link Layer usage. + 0x23C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_144 + Shared Packet RAM for multiple Link Layer usage. + 0x240 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_145 + Shared Packet RAM for multiple Link Layer usage. + 0x244 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_146 + Shared Packet RAM for multiple Link Layer usage. + 0x248 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_147 + Shared Packet RAM for multiple Link Layer usage. + 0x24C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_148 + Shared Packet RAM for multiple Link Layer usage. + 0x250 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_149 + Shared Packet RAM for multiple Link Layer usage. + 0x254 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_150 + Shared Packet RAM for multiple Link Layer usage. + 0x258 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_151 + Shared Packet RAM for multiple Link Layer usage. + 0x25C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_152 + Shared Packet RAM for multiple Link Layer usage. + 0x260 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_153 + Shared Packet RAM for multiple Link Layer usage. + 0x264 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_154 + Shared Packet RAM for multiple Link Layer usage. + 0x268 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_155 + Shared Packet RAM for multiple Link Layer usage. + 0x26C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_156 + Shared Packet RAM for multiple Link Layer usage. + 0x270 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_157 + Shared Packet RAM for multiple Link Layer usage. + 0x274 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_158 + Shared Packet RAM for multiple Link Layer usage. + 0x278 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_159 + Shared Packet RAM for multiple Link Layer usage. + 0x27C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_160 + Shared Packet RAM for multiple Link Layer usage. + 0x280 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_161 + Shared Packet RAM for multiple Link Layer usage. + 0x284 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_162 + Shared Packet RAM for multiple Link Layer usage. + 0x288 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_163 + Shared Packet RAM for multiple Link Layer usage. + 0x28C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_164 + Shared Packet RAM for multiple Link Layer usage. + 0x290 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_165 + Shared Packet RAM for multiple Link Layer usage. + 0x294 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_166 + Shared Packet RAM for multiple Link Layer usage. + 0x298 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_167 + Shared Packet RAM for multiple Link Layer usage. + 0x29C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_168 + Shared Packet RAM for multiple Link Layer usage. + 0x2A0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_169 + Shared Packet RAM for multiple Link Layer usage. + 0x2A4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_170 + Shared Packet RAM for multiple Link Layer usage. + 0x2A8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_171 + Shared Packet RAM for multiple Link Layer usage. + 0x2AC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_172 + Shared Packet RAM for multiple Link Layer usage. + 0x2B0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_173 + Shared Packet RAM for multiple Link Layer usage. + 0x2B4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_174 + Shared Packet RAM for multiple Link Layer usage. + 0x2B8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_175 + Shared Packet RAM for multiple Link Layer usage. + 0x2BC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_176 + Shared Packet RAM for multiple Link Layer usage. + 0x2C0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_177 + Shared Packet RAM for multiple Link Layer usage. + 0x2C4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_178 + Shared Packet RAM for multiple Link Layer usage. + 0x2C8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_179 + Shared Packet RAM for multiple Link Layer usage. + 0x2CC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_180 + Shared Packet RAM for multiple Link Layer usage. + 0x2D0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_181 + Shared Packet RAM for multiple Link Layer usage. + 0x2D4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_182 + Shared Packet RAM for multiple Link Layer usage. + 0x2D8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_183 + Shared Packet RAM for multiple Link Layer usage. + 0x2DC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_184 + Shared Packet RAM for multiple Link Layer usage. + 0x2E0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_185 + Shared Packet RAM for multiple Link Layer usage. + 0x2E4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_186 + Shared Packet RAM for multiple Link Layer usage. + 0x2E8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_187 + Shared Packet RAM for multiple Link Layer usage. + 0x2EC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_188 + Shared Packet RAM for multiple Link Layer usage. + 0x2F0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_189 + Shared Packet RAM for multiple Link Layer usage. + 0x2F4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_190 + Shared Packet RAM for multiple Link Layer usage. + 0x2F8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_191 + Shared Packet RAM for multiple Link Layer usage. + 0x2FC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_192 + Shared Packet RAM for multiple Link Layer usage. + 0x300 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_193 + Shared Packet RAM for multiple Link Layer usage. + 0x304 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_194 + Shared Packet RAM for multiple Link Layer usage. + 0x308 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_195 + Shared Packet RAM for multiple Link Layer usage. + 0x30C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_196 + Shared Packet RAM for multiple Link Layer usage. + 0x310 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_197 + Shared Packet RAM for multiple Link Layer usage. + 0x314 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_198 + Shared Packet RAM for multiple Link Layer usage. + 0x318 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_199 + Shared Packet RAM for multiple Link Layer usage. + 0x31C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_200 + Shared Packet RAM for multiple Link Layer usage. + 0x320 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_201 + Shared Packet RAM for multiple Link Layer usage. + 0x324 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_202 + Shared Packet RAM for multiple Link Layer usage. + 0x328 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_203 + Shared Packet RAM for multiple Link Layer usage. + 0x32C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_204 + Shared Packet RAM for multiple Link Layer usage. + 0x330 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_205 + Shared Packet RAM for multiple Link Layer usage. + 0x334 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_206 + Shared Packet RAM for multiple Link Layer usage. + 0x338 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_207 + Shared Packet RAM for multiple Link Layer usage. + 0x33C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_208 + Shared Packet RAM for multiple Link Layer usage. + 0x340 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_209 + Shared Packet RAM for multiple Link Layer usage. + 0x344 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_210 + Shared Packet RAM for multiple Link Layer usage. + 0x348 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_211 + Shared Packet RAM for multiple Link Layer usage. + 0x34C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_212 + Shared Packet RAM for multiple Link Layer usage. + 0x350 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_213 + Shared Packet RAM for multiple Link Layer usage. + 0x354 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_214 + Shared Packet RAM for multiple Link Layer usage. + 0x358 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_215 + Shared Packet RAM for multiple Link Layer usage. + 0x35C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_216 + Shared Packet RAM for multiple Link Layer usage. + 0x360 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_217 + Shared Packet RAM for multiple Link Layer usage. + 0x364 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_218 + Shared Packet RAM for multiple Link Layer usage. + 0x368 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_219 + Shared Packet RAM for multiple Link Layer usage. + 0x36C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_220 + Shared Packet RAM for multiple Link Layer usage. + 0x370 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_221 + Shared Packet RAM for multiple Link Layer usage. + 0x374 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_222 + Shared Packet RAM for multiple Link Layer usage. + 0x378 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_223 + Shared Packet RAM for multiple Link Layer usage. + 0x37C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_224 + Shared Packet RAM for multiple Link Layer usage. + 0x380 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_225 + Shared Packet RAM for multiple Link Layer usage. + 0x384 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_226 + Shared Packet RAM for multiple Link Layer usage. + 0x388 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_227 + Shared Packet RAM for multiple Link Layer usage. + 0x38C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_228 + Shared Packet RAM for multiple Link Layer usage. + 0x390 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_229 + Shared Packet RAM for multiple Link Layer usage. + 0x394 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_230 + Shared Packet RAM for multiple Link Layer usage. + 0x398 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_231 + Shared Packet RAM for multiple Link Layer usage. + 0x39C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_232 + Shared Packet RAM for multiple Link Layer usage. + 0x3A0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_233 + Shared Packet RAM for multiple Link Layer usage. + 0x3A4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_234 + Shared Packet RAM for multiple Link Layer usage. + 0x3A8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_235 + Shared Packet RAM for multiple Link Layer usage. + 0x3AC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_236 + Shared Packet RAM for multiple Link Layer usage. + 0x3B0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_237 + Shared Packet RAM for multiple Link Layer usage. + 0x3B4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_238 + Shared Packet RAM for multiple Link Layer usage. + 0x3B8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_239 + Shared Packet RAM for multiple Link Layer usage. + 0x3BC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_240 + Shared Packet RAM for multiple Link Layer usage. + 0x3C0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_241 + Shared Packet RAM for multiple Link Layer usage. + 0x3C4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_242 + Shared Packet RAM for multiple Link Layer usage. + 0x3C8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_243 + Shared Packet RAM for multiple Link Layer usage. + 0x3CC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_244 + Shared Packet RAM for multiple Link Layer usage. + 0x3D0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_245 + Shared Packet RAM for multiple Link Layer usage. + 0x3D4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_246 + Shared Packet RAM for multiple Link Layer usage. + 0x3D8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_247 + Shared Packet RAM for multiple Link Layer usage. + 0x3DC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_248 + Shared Packet RAM for multiple Link Layer usage. + 0x3E0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_249 + Shared Packet RAM for multiple Link Layer usage. + 0x3E4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_250 + Shared Packet RAM for multiple Link Layer usage. + 0x3E8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_251 + Shared Packet RAM for multiple Link Layer usage. + 0x3EC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_252 + Shared Packet RAM for multiple Link Layer usage. + 0x3F0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_253 + Shared Packet RAM for multiple Link Layer usage. + 0x3F4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_254 + Shared Packet RAM for multiple Link Layer usage. + 0x3F8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_255 + Shared Packet RAM for multiple Link Layer usage. + 0x3FC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_256 + Shared Packet RAM for multiple Link Layer usage. + 0x400 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_257 + Shared Packet RAM for multiple Link Layer usage. + 0x404 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_258 + Shared Packet RAM for multiple Link Layer usage. + 0x408 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_259 + Shared Packet RAM for multiple Link Layer usage. + 0x40C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_260 + Shared Packet RAM for multiple Link Layer usage. + 0x410 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_261 + Shared Packet RAM for multiple Link Layer usage. + 0x414 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_262 + Shared Packet RAM for multiple Link Layer usage. + 0x418 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_263 + Shared Packet RAM for multiple Link Layer usage. + 0x41C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_264 + Shared Packet RAM for multiple Link Layer usage. + 0x420 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_265 + Shared Packet RAM for multiple Link Layer usage. + 0x424 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_266 + Shared Packet RAM for multiple Link Layer usage. + 0x428 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_267 + Shared Packet RAM for multiple Link Layer usage. + 0x42C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_268 + Shared Packet RAM for multiple Link Layer usage. + 0x430 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_269 + Shared Packet RAM for multiple Link Layer usage. + 0x434 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_270 + Shared Packet RAM for multiple Link Layer usage. + 0x438 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_271 + Shared Packet RAM for multiple Link Layer usage. + 0x43C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_272 + Shared Packet RAM for multiple Link Layer usage. + 0x440 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_273 + Shared Packet RAM for multiple Link Layer usage. + 0x444 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_274 + Shared Packet RAM for multiple Link Layer usage. + 0x448 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_275 + Shared Packet RAM for multiple Link Layer usage. + 0x44C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_276 + Shared Packet RAM for multiple Link Layer usage. + 0x450 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_277 + Shared Packet RAM for multiple Link Layer usage. + 0x454 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_278 + Shared Packet RAM for multiple Link Layer usage. + 0x458 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_279 + Shared Packet RAM for multiple Link Layer usage. + 0x45C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_280 + Shared Packet RAM for multiple Link Layer usage. + 0x460 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_281 + Shared Packet RAM for multiple Link Layer usage. + 0x464 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_282 + Shared Packet RAM for multiple Link Layer usage. + 0x468 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_283 + Shared Packet RAM for multiple Link Layer usage. + 0x46C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_284 + Shared Packet RAM for multiple Link Layer usage. + 0x470 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_285 + Shared Packet RAM for multiple Link Layer usage. + 0x474 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_286 + Shared Packet RAM for multiple Link Layer usage. + 0x478 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_287 + Shared Packet RAM for multiple Link Layer usage. + 0x47C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_288 + Shared Packet RAM for multiple Link Layer usage. + 0x480 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_289 + Shared Packet RAM for multiple Link Layer usage. + 0x484 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_290 + Shared Packet RAM for multiple Link Layer usage. + 0x488 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_291 + Shared Packet RAM for multiple Link Layer usage. + 0x48C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_292 + Shared Packet RAM for multiple Link Layer usage. + 0x490 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_293 + Shared Packet RAM for multiple Link Layer usage. + 0x494 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_294 + Shared Packet RAM for multiple Link Layer usage. + 0x498 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_295 + Shared Packet RAM for multiple Link Layer usage. + 0x49C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_296 + Shared Packet RAM for multiple Link Layer usage. + 0x4A0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_297 + Shared Packet RAM for multiple Link Layer usage. + 0x4A4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_298 + Shared Packet RAM for multiple Link Layer usage. + 0x4A8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_299 + Shared Packet RAM for multiple Link Layer usage. + 0x4AC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_300 + Shared Packet RAM for multiple Link Layer usage. + 0x4B0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_301 + Shared Packet RAM for multiple Link Layer usage. + 0x4B4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_302 + Shared Packet RAM for multiple Link Layer usage. + 0x4B8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_303 + Shared Packet RAM for multiple Link Layer usage. + 0x4BC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_304 + Shared Packet RAM for multiple Link Layer usage. + 0x4C0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_305 + Shared Packet RAM for multiple Link Layer usage. + 0x4C4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_306 + Shared Packet RAM for multiple Link Layer usage. + 0x4C8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_307 + Shared Packet RAM for multiple Link Layer usage. + 0x4CC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_308 + Shared Packet RAM for multiple Link Layer usage. + 0x4D0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_309 + Shared Packet RAM for multiple Link Layer usage. + 0x4D4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_310 + Shared Packet RAM for multiple Link Layer usage. + 0x4D8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_311 + Shared Packet RAM for multiple Link Layer usage. + 0x4DC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_312 + Shared Packet RAM for multiple Link Layer usage. + 0x4E0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_313 + Shared Packet RAM for multiple Link Layer usage. + 0x4E4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_314 + Shared Packet RAM for multiple Link Layer usage. + 0x4E8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_315 + Shared Packet RAM for multiple Link Layer usage. + 0x4EC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_316 + Shared Packet RAM for multiple Link Layer usage. + 0x4F0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_317 + Shared Packet RAM for multiple Link Layer usage. + 0x4F4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_318 + Shared Packet RAM for multiple Link Layer usage. + 0x4F8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_319 + Shared Packet RAM for multiple Link Layer usage. + 0x4FC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_320 + Shared Packet RAM for multiple Link Layer usage. + 0x500 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_321 + Shared Packet RAM for multiple Link Layer usage. + 0x504 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_322 + Shared Packet RAM for multiple Link Layer usage. + 0x508 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_323 + Shared Packet RAM for multiple Link Layer usage. + 0x50C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_324 + Shared Packet RAM for multiple Link Layer usage. + 0x510 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_325 + Shared Packet RAM for multiple Link Layer usage. + 0x514 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_326 + Shared Packet RAM for multiple Link Layer usage. + 0x518 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_327 + Shared Packet RAM for multiple Link Layer usage. + 0x51C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_328 + Shared Packet RAM for multiple Link Layer usage. + 0x520 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_329 + Shared Packet RAM for multiple Link Layer usage. + 0x524 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_330 + Shared Packet RAM for multiple Link Layer usage. + 0x528 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_331 + Shared Packet RAM for multiple Link Layer usage. + 0x52C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_332 + Shared Packet RAM for multiple Link Layer usage. + 0x530 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_333 + Shared Packet RAM for multiple Link Layer usage. + 0x534 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_334 + Shared Packet RAM for multiple Link Layer usage. + 0x538 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_335 + Shared Packet RAM for multiple Link Layer usage. + 0x53C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_336 + Shared Packet RAM for multiple Link Layer usage. + 0x540 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_337 + Shared Packet RAM for multiple Link Layer usage. + 0x544 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_338 + Shared Packet RAM for multiple Link Layer usage. + 0x548 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_339 + Shared Packet RAM for multiple Link Layer usage. + 0x54C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_340 + Shared Packet RAM for multiple Link Layer usage. + 0x550 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_341 + Shared Packet RAM for multiple Link Layer usage. + 0x554 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_342 + Shared Packet RAM for multiple Link Layer usage. + 0x558 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_343 + Shared Packet RAM for multiple Link Layer usage. + 0x55C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_344 + Shared Packet RAM for multiple Link Layer usage. + 0x560 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_345 + Shared Packet RAM for multiple Link Layer usage. + 0x564 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_346 + Shared Packet RAM for multiple Link Layer usage. + 0x568 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_347 + Shared Packet RAM for multiple Link Layer usage. + 0x56C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_348 + Shared Packet RAM for multiple Link Layer usage. + 0x570 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_349 + Shared Packet RAM for multiple Link Layer usage. + 0x574 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_350 + Shared Packet RAM for multiple Link Layer usage. + 0x578 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_351 + Shared Packet RAM for multiple Link Layer usage. + 0x57C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_352 + Shared Packet RAM for multiple Link Layer usage. + 0x580 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_353 + Shared Packet RAM for multiple Link Layer usage. + 0x584 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_354 + Shared Packet RAM for multiple Link Layer usage. + 0x588 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_355 + Shared Packet RAM for multiple Link Layer usage. + 0x58C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_356 + Shared Packet RAM for multiple Link Layer usage. + 0x590 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_357 + Shared Packet RAM for multiple Link Layer usage. + 0x594 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_358 + Shared Packet RAM for multiple Link Layer usage. + 0x598 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_359 + Shared Packet RAM for multiple Link Layer usage. + 0x59C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_360 + Shared Packet RAM for multiple Link Layer usage. + 0x5A0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_361 + Shared Packet RAM for multiple Link Layer usage. + 0x5A4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_362 + Shared Packet RAM for multiple Link Layer usage. + 0x5A8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_363 + Shared Packet RAM for multiple Link Layer usage. + 0x5AC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_364 + Shared Packet RAM for multiple Link Layer usage. + 0x5B0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_365 + Shared Packet RAM for multiple Link Layer usage. + 0x5B4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_366 + Shared Packet RAM for multiple Link Layer usage. + 0x5B8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_367 + Shared Packet RAM for multiple Link Layer usage. + 0x5BC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_368 + Shared Packet RAM for multiple Link Layer usage. + 0x5C0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_369 + Shared Packet RAM for multiple Link Layer usage. + 0x5C4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_370 + Shared Packet RAM for multiple Link Layer usage. + 0x5C8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_371 + Shared Packet RAM for multiple Link Layer usage. + 0x5CC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_372 + Shared Packet RAM for multiple Link Layer usage. + 0x5D0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_373 + Shared Packet RAM for multiple Link Layer usage. + 0x5D4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_374 + Shared Packet RAM for multiple Link Layer usage. + 0x5D8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_375 + Shared Packet RAM for multiple Link Layer usage. + 0x5DC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_376 + Shared Packet RAM for multiple Link Layer usage. + 0x5E0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_377 + Shared Packet RAM for multiple Link Layer usage. + 0x5E4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_378 + Shared Packet RAM for multiple Link Layer usage. + 0x5E8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_379 + Shared Packet RAM for multiple Link Layer usage. + 0x5EC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_380 + Shared Packet RAM for multiple Link Layer usage. + 0x5F0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_381 + Shared Packet RAM for multiple Link Layer usage. + 0x5F4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_382 + Shared Packet RAM for multiple Link Layer usage. + 0x5F8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_383 + Shared Packet RAM for multiple Link Layer usage. + 0x5FC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_384 + Shared Packet RAM for multiple Link Layer usage. + 0x600 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_385 + Shared Packet RAM for multiple Link Layer usage. + 0x604 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_386 + Shared Packet RAM for multiple Link Layer usage. + 0x608 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_387 + Shared Packet RAM for multiple Link Layer usage. + 0x60C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_388 + Shared Packet RAM for multiple Link Layer usage. + 0x610 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_389 + Shared Packet RAM for multiple Link Layer usage. + 0x614 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_390 + Shared Packet RAM for multiple Link Layer usage. + 0x618 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_391 + Shared Packet RAM for multiple Link Layer usage. + 0x61C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_392 + Shared Packet RAM for multiple Link Layer usage. + 0x620 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_393 + Shared Packet RAM for multiple Link Layer usage. + 0x624 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_394 + Shared Packet RAM for multiple Link Layer usage. + 0x628 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_395 + Shared Packet RAM for multiple Link Layer usage. + 0x62C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_396 + Shared Packet RAM for multiple Link Layer usage. + 0x630 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_397 + Shared Packet RAM for multiple Link Layer usage. + 0x634 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_398 + Shared Packet RAM for multiple Link Layer usage. + 0x638 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_399 + Shared Packet RAM for multiple Link Layer usage. + 0x63C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_400 + Shared Packet RAM for multiple Link Layer usage. + 0x640 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_401 + Shared Packet RAM for multiple Link Layer usage. + 0x644 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_402 + Shared Packet RAM for multiple Link Layer usage. + 0x648 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_403 + Shared Packet RAM for multiple Link Layer usage. + 0x64C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_404 + Shared Packet RAM for multiple Link Layer usage. + 0x650 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_405 + Shared Packet RAM for multiple Link Layer usage. + 0x654 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_406 + Shared Packet RAM for multiple Link Layer usage. + 0x658 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_407 + Shared Packet RAM for multiple Link Layer usage. + 0x65C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_408 + Shared Packet RAM for multiple Link Layer usage. + 0x660 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_409 + Shared Packet RAM for multiple Link Layer usage. + 0x664 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_410 + Shared Packet RAM for multiple Link Layer usage. + 0x668 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_411 + Shared Packet RAM for multiple Link Layer usage. + 0x66C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_412 + Shared Packet RAM for multiple Link Layer usage. + 0x670 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_413 + Shared Packet RAM for multiple Link Layer usage. + 0x674 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_414 + Shared Packet RAM for multiple Link Layer usage. + 0x678 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_415 + Shared Packet RAM for multiple Link Layer usage. + 0x67C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_416 + Shared Packet RAM for multiple Link Layer usage. + 0x680 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_417 + Shared Packet RAM for multiple Link Layer usage. + 0x684 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_418 + Shared Packet RAM for multiple Link Layer usage. + 0x688 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_419 + Shared Packet RAM for multiple Link Layer usage. + 0x68C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_420 + Shared Packet RAM for multiple Link Layer usage. + 0x690 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_421 + Shared Packet RAM for multiple Link Layer usage. + 0x694 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_422 + Shared Packet RAM for multiple Link Layer usage. + 0x698 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_423 + Shared Packet RAM for multiple Link Layer usage. + 0x69C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_424 + Shared Packet RAM for multiple Link Layer usage. + 0x6A0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_425 + Shared Packet RAM for multiple Link Layer usage. + 0x6A4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_426 + Shared Packet RAM for multiple Link Layer usage. + 0x6A8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_427 + Shared Packet RAM for multiple Link Layer usage. + 0x6AC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_428 + Shared Packet RAM for multiple Link Layer usage. + 0x6B0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_429 + Shared Packet RAM for multiple Link Layer usage. + 0x6B4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_430 + Shared Packet RAM for multiple Link Layer usage. + 0x6B8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_431 + Shared Packet RAM for multiple Link Layer usage. + 0x6BC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_432 + Shared Packet RAM for multiple Link Layer usage. + 0x6C0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_433 + Shared Packet RAM for multiple Link Layer usage. + 0x6C4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_434 + Shared Packet RAM for multiple Link Layer usage. + 0x6C8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_435 + Shared Packet RAM for multiple Link Layer usage. + 0x6CC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_436 + Shared Packet RAM for multiple Link Layer usage. + 0x6D0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_437 + Shared Packet RAM for multiple Link Layer usage. + 0x6D4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_438 + Shared Packet RAM for multiple Link Layer usage. + 0x6D8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_439 + Shared Packet RAM for multiple Link Layer usage. + 0x6DC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_440 + Shared Packet RAM for multiple Link Layer usage. + 0x6E0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_441 + Shared Packet RAM for multiple Link Layer usage. + 0x6E4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_442 + Shared Packet RAM for multiple Link Layer usage. + 0x6E8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_443 + Shared Packet RAM for multiple Link Layer usage. + 0x6EC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_444 + Shared Packet RAM for multiple Link Layer usage. + 0x6F0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_445 + Shared Packet RAM for multiple Link Layer usage. + 0x6F4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_446 + Shared Packet RAM for multiple Link Layer usage. + 0x6F8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_447 + Shared Packet RAM for multiple Link Layer usage. + 0x6FC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_448 + Shared Packet RAM for multiple Link Layer usage. + 0x700 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_449 + Shared Packet RAM for multiple Link Layer usage. + 0x704 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_450 + Shared Packet RAM for multiple Link Layer usage. + 0x708 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_451 + Shared Packet RAM for multiple Link Layer usage. + 0x70C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_452 + Shared Packet RAM for multiple Link Layer usage. + 0x710 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_453 + Shared Packet RAM for multiple Link Layer usage. + 0x714 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_454 + Shared Packet RAM for multiple Link Layer usage. + 0x718 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_455 + Shared Packet RAM for multiple Link Layer usage. + 0x71C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_456 + Shared Packet RAM for multiple Link Layer usage. + 0x720 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_457 + Shared Packet RAM for multiple Link Layer usage. + 0x724 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_458 + Shared Packet RAM for multiple Link Layer usage. + 0x728 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_459 + Shared Packet RAM for multiple Link Layer usage. + 0x72C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_460 + Shared Packet RAM for multiple Link Layer usage. + 0x730 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_461 + Shared Packet RAM for multiple Link Layer usage. + 0x734 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_462 + Shared Packet RAM for multiple Link Layer usage. + 0x738 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_463 + Shared Packet RAM for multiple Link Layer usage. + 0x73C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_464 + Shared Packet RAM for multiple Link Layer usage. + 0x740 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_465 + Shared Packet RAM for multiple Link Layer usage. + 0x744 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_466 + Shared Packet RAM for multiple Link Layer usage. + 0x748 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_467 + Shared Packet RAM for multiple Link Layer usage. + 0x74C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_468 + Shared Packet RAM for multiple Link Layer usage. + 0x750 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_469 + Shared Packet RAM for multiple Link Layer usage. + 0x754 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_470 + Shared Packet RAM for multiple Link Layer usage. + 0x758 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_471 + Shared Packet RAM for multiple Link Layer usage. + 0x75C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_472 + Shared Packet RAM for multiple Link Layer usage. + 0x760 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_473 + Shared Packet RAM for multiple Link Layer usage. + 0x764 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_474 + Shared Packet RAM for multiple Link Layer usage. + 0x768 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_475 + Shared Packet RAM for multiple Link Layer usage. + 0x76C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_476 + Shared Packet RAM for multiple Link Layer usage. + 0x770 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_477 + Shared Packet RAM for multiple Link Layer usage. + 0x774 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_478 + Shared Packet RAM for multiple Link Layer usage. + 0x778 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_479 + Shared Packet RAM for multiple Link Layer usage. + 0x77C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_480 + Shared Packet RAM for multiple Link Layer usage. + 0x780 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_481 + Shared Packet RAM for multiple Link Layer usage. + 0x784 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_482 + Shared Packet RAM for multiple Link Layer usage. + 0x788 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_483 + Shared Packet RAM for multiple Link Layer usage. + 0x78C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_484 + Shared Packet RAM for multiple Link Layer usage. + 0x790 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_485 + Shared Packet RAM for multiple Link Layer usage. + 0x794 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_486 + Shared Packet RAM for multiple Link Layer usage. + 0x798 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_487 + Shared Packet RAM for multiple Link Layer usage. + 0x79C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_488 + Shared Packet RAM for multiple Link Layer usage. + 0x7A0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_489 + Shared Packet RAM for multiple Link Layer usage. + 0x7A4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_490 + Shared Packet RAM for multiple Link Layer usage. + 0x7A8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_491 + Shared Packet RAM for multiple Link Layer usage. + 0x7AC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_492 + Shared Packet RAM for multiple Link Layer usage. + 0x7B0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_493 + Shared Packet RAM for multiple Link Layer usage. + 0x7B4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_494 + Shared Packet RAM for multiple Link Layer usage. + 0x7B8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_495 + Shared Packet RAM for multiple Link Layer usage. + 0x7BC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_496 + Shared Packet RAM for multiple Link Layer usage. + 0x7C0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_497 + Shared Packet RAM for multiple Link Layer usage. + 0x7C4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_498 + Shared Packet RAM for multiple Link Layer usage. + 0x7C8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_499 + Shared Packet RAM for multiple Link Layer usage. + 0x7CC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_500 + Shared Packet RAM for multiple Link Layer usage. + 0x7D0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_501 + Shared Packet RAM for multiple Link Layer usage. + 0x7D4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_502 + Shared Packet RAM for multiple Link Layer usage. + 0x7D8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_503 + Shared Packet RAM for multiple Link Layer usage. + 0x7DC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_504 + Shared Packet RAM for multiple Link Layer usage. + 0x7E0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_505 + Shared Packet RAM for multiple Link Layer usage. + 0x7E4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_506 + Shared Packet RAM for multiple Link Layer usage. + 0x7E8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_507 + Shared Packet RAM for multiple Link Layer usage. + 0x7EC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_508 + Shared Packet RAM for multiple Link Layer usage. + 0x7F0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_509 + Shared Packet RAM for multiple Link Layer usage. + 0x7F4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_510 + Shared Packet RAM for multiple Link Layer usage. + 0x7F8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_511 + Shared Packet RAM for multiple Link Layer usage. + 0x7FC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_512 + Shared Packet RAM for multiple Link Layer usage. + 0x800 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_513 + Shared Packet RAM for multiple Link Layer usage. + 0x804 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_514 + Shared Packet RAM for multiple Link Layer usage. + 0x808 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_515 + Shared Packet RAM for multiple Link Layer usage. + 0x80C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_516 + Shared Packet RAM for multiple Link Layer usage. + 0x810 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_517 + Shared Packet RAM for multiple Link Layer usage. + 0x814 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_518 + Shared Packet RAM for multiple Link Layer usage. + 0x818 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_519 + Shared Packet RAM for multiple Link Layer usage. + 0x81C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_520 + Shared Packet RAM for multiple Link Layer usage. + 0x820 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_521 + Shared Packet RAM for multiple Link Layer usage. + 0x824 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_522 + Shared Packet RAM for multiple Link Layer usage. + 0x828 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_523 + Shared Packet RAM for multiple Link Layer usage. + 0x82C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_524 + Shared Packet RAM for multiple Link Layer usage. + 0x830 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_525 + Shared Packet RAM for multiple Link Layer usage. + 0x834 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_526 + Shared Packet RAM for multiple Link Layer usage. + 0x838 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_527 + Shared Packet RAM for multiple Link Layer usage. + 0x83C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_528 + Shared Packet RAM for multiple Link Layer usage. + 0x840 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_529 + Shared Packet RAM for multiple Link Layer usage. + 0x844 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_530 + Shared Packet RAM for multiple Link Layer usage. + 0x848 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_531 + Shared Packet RAM for multiple Link Layer usage. + 0x84C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_532 + Shared Packet RAM for multiple Link Layer usage. + 0x850 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_533 + Shared Packet RAM for multiple Link Layer usage. + 0x854 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_534 + Shared Packet RAM for multiple Link Layer usage. + 0x858 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_535 + Shared Packet RAM for multiple Link Layer usage. + 0x85C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_536 + Shared Packet RAM for multiple Link Layer usage. + 0x860 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_537 + Shared Packet RAM for multiple Link Layer usage. + 0x864 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_538 + Shared Packet RAM for multiple Link Layer usage. + 0x868 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_539 + Shared Packet RAM for multiple Link Layer usage. + 0x86C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_540 + Shared Packet RAM for multiple Link Layer usage. + 0x870 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_541 + Shared Packet RAM for multiple Link Layer usage. + 0x874 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_542 + Shared Packet RAM for multiple Link Layer usage. + 0x878 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_543 + Shared Packet RAM for multiple Link Layer usage. + 0x87C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_544 + Shared Packet RAM for multiple Link Layer usage. + 0x880 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_545 + Shared Packet RAM for multiple Link Layer usage. + 0x884 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_546 + Shared Packet RAM for multiple Link Layer usage. + 0x888 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_547 + Shared Packet RAM for multiple Link Layer usage. + 0x88C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_548 + Shared Packet RAM for multiple Link Layer usage. + 0x890 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_549 + Shared Packet RAM for multiple Link Layer usage. + 0x894 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_550 + Shared Packet RAM for multiple Link Layer usage. + 0x898 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_551 + Shared Packet RAM for multiple Link Layer usage. + 0x89C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_552 + Shared Packet RAM for multiple Link Layer usage. + 0x8A0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_553 + Shared Packet RAM for multiple Link Layer usage. + 0x8A4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_554 + Shared Packet RAM for multiple Link Layer usage. + 0x8A8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_555 + Shared Packet RAM for multiple Link Layer usage. + 0x8AC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_556 + Shared Packet RAM for multiple Link Layer usage. + 0x8B0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_557 + Shared Packet RAM for multiple Link Layer usage. + 0x8B4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_558 + Shared Packet RAM for multiple Link Layer usage. + 0x8B8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_559 + Shared Packet RAM for multiple Link Layer usage. + 0x8BC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_560 + Shared Packet RAM for multiple Link Layer usage. + 0x8C0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_561 + Shared Packet RAM for multiple Link Layer usage. + 0x8C4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_562 + Shared Packet RAM for multiple Link Layer usage. + 0x8C8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_563 + Shared Packet RAM for multiple Link Layer usage. + 0x8CC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_564 + Shared Packet RAM for multiple Link Layer usage. + 0x8D0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_565 + Shared Packet RAM for multiple Link Layer usage. + 0x8D4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_566 + Shared Packet RAM for multiple Link Layer usage. + 0x8D8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_567 + Shared Packet RAM for multiple Link Layer usage. + 0x8DC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_568 + Shared Packet RAM for multiple Link Layer usage. + 0x8E0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_569 + Shared Packet RAM for multiple Link Layer usage. + 0x8E4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_570 + Shared Packet RAM for multiple Link Layer usage. + 0x8E8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_571 + Shared Packet RAM for multiple Link Layer usage. + 0x8EC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_572 + Shared Packet RAM for multiple Link Layer usage. + 0x8F0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_573 + Shared Packet RAM for multiple Link Layer usage. + 0x8F4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_574 + Shared Packet RAM for multiple Link Layer usage. + 0x8F8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_575 + Shared Packet RAM for multiple Link Layer usage. + 0x8FC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_576 + Shared Packet RAM for multiple Link Layer usage. + 0x900 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_577 + Shared Packet RAM for multiple Link Layer usage. + 0x904 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_578 + Shared Packet RAM for multiple Link Layer usage. + 0x908 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_579 + Shared Packet RAM for multiple Link Layer usage. + 0x90C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_580 + Shared Packet RAM for multiple Link Layer usage. + 0x910 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_581 + Shared Packet RAM for multiple Link Layer usage. + 0x914 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_582 + Shared Packet RAM for multiple Link Layer usage. + 0x918 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_583 + Shared Packet RAM for multiple Link Layer usage. + 0x91C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_584 + Shared Packet RAM for multiple Link Layer usage. + 0x920 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_585 + Shared Packet RAM for multiple Link Layer usage. + 0x924 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_586 + Shared Packet RAM for multiple Link Layer usage. + 0x928 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_587 + Shared Packet RAM for multiple Link Layer usage. + 0x92C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_588 + Shared Packet RAM for multiple Link Layer usage. + 0x930 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_589 + Shared Packet RAM for multiple Link Layer usage. + 0x934 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_590 + Shared Packet RAM for multiple Link Layer usage. + 0x938 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_591 + Shared Packet RAM for multiple Link Layer usage. + 0x93C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_592 + Shared Packet RAM for multiple Link Layer usage. + 0x940 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_593 + Shared Packet RAM for multiple Link Layer usage. + 0x944 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_594 + Shared Packet RAM for multiple Link Layer usage. + 0x948 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_595 + Shared Packet RAM for multiple Link Layer usage. + 0x94C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_596 + Shared Packet RAM for multiple Link Layer usage. + 0x950 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_597 + Shared Packet RAM for multiple Link Layer usage. + 0x954 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_598 + Shared Packet RAM for multiple Link Layer usage. + 0x958 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_599 + Shared Packet RAM for multiple Link Layer usage. + 0x95C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_600 + Shared Packet RAM for multiple Link Layer usage. + 0x960 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_601 + Shared Packet RAM for multiple Link Layer usage. + 0x964 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_602 + Shared Packet RAM for multiple Link Layer usage. + 0x968 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_603 + Shared Packet RAM for multiple Link Layer usage. + 0x96C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_604 + Shared Packet RAM for multiple Link Layer usage. + 0x970 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_605 + Shared Packet RAM for multiple Link Layer usage. + 0x974 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_606 + Shared Packet RAM for multiple Link Layer usage. + 0x978 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_607 + Shared Packet RAM for multiple Link Layer usage. + 0x97C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_608 + Shared Packet RAM for multiple Link Layer usage. + 0x980 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_609 + Shared Packet RAM for multiple Link Layer usage. + 0x984 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_610 + Shared Packet RAM for multiple Link Layer usage. + 0x988 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_611 + Shared Packet RAM for multiple Link Layer usage. + 0x98C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_612 + Shared Packet RAM for multiple Link Layer usage. + 0x990 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_613 + Shared Packet RAM for multiple Link Layer usage. + 0x994 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_614 + Shared Packet RAM for multiple Link Layer usage. + 0x998 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_615 + Shared Packet RAM for multiple Link Layer usage. + 0x99C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_616 + Shared Packet RAM for multiple Link Layer usage. + 0x9A0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_617 + Shared Packet RAM for multiple Link Layer usage. + 0x9A4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_618 + Shared Packet RAM for multiple Link Layer usage. + 0x9A8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_619 + Shared Packet RAM for multiple Link Layer usage. + 0x9AC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_620 + Shared Packet RAM for multiple Link Layer usage. + 0x9B0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_621 + Shared Packet RAM for multiple Link Layer usage. + 0x9B4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_622 + Shared Packet RAM for multiple Link Layer usage. + 0x9B8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_623 + Shared Packet RAM for multiple Link Layer usage. + 0x9BC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_624 + Shared Packet RAM for multiple Link Layer usage. + 0x9C0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_625 + Shared Packet RAM for multiple Link Layer usage. + 0x9C4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_626 + Shared Packet RAM for multiple Link Layer usage. + 0x9C8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_627 + Shared Packet RAM for multiple Link Layer usage. + 0x9CC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_628 + Shared Packet RAM for multiple Link Layer usage. + 0x9D0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_629 + Shared Packet RAM for multiple Link Layer usage. + 0x9D4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_630 + Shared Packet RAM for multiple Link Layer usage. + 0x9D8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_631 + Shared Packet RAM for multiple Link Layer usage. + 0x9DC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_632 + Shared Packet RAM for multiple Link Layer usage. + 0x9E0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_633 + Shared Packet RAM for multiple Link Layer usage. + 0x9E4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_634 + Shared Packet RAM for multiple Link Layer usage. + 0x9E8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_635 + Shared Packet RAM for multiple Link Layer usage. + 0x9EC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_636 + Shared Packet RAM for multiple Link Layer usage. + 0x9F0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_637 + Shared Packet RAM for multiple Link Layer usage. + 0x9F4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_638 + Shared Packet RAM for multiple Link Layer usage. + 0x9F8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_639 + Shared Packet RAM for multiple Link Layer usage. + 0x9FC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_640 + Shared Packet RAM for multiple Link Layer usage. + 0xA00 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_641 + Shared Packet RAM for multiple Link Layer usage. + 0xA04 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_642 + Shared Packet RAM for multiple Link Layer usage. + 0xA08 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_643 + Shared Packet RAM for multiple Link Layer usage. + 0xA0C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_644 + Shared Packet RAM for multiple Link Layer usage. + 0xA10 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_645 + Shared Packet RAM for multiple Link Layer usage. + 0xA14 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_646 + Shared Packet RAM for multiple Link Layer usage. + 0xA18 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_647 + Shared Packet RAM for multiple Link Layer usage. + 0xA1C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_648 + Shared Packet RAM for multiple Link Layer usage. + 0xA20 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_649 + Shared Packet RAM for multiple Link Layer usage. + 0xA24 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_650 + Shared Packet RAM for multiple Link Layer usage. + 0xA28 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_651 + Shared Packet RAM for multiple Link Layer usage. + 0xA2C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_652 + Shared Packet RAM for multiple Link Layer usage. + 0xA30 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_653 + Shared Packet RAM for multiple Link Layer usage. + 0xA34 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_654 + Shared Packet RAM for multiple Link Layer usage. + 0xA38 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_655 + Shared Packet RAM for multiple Link Layer usage. + 0xA3C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_656 + Shared Packet RAM for multiple Link Layer usage. + 0xA40 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_657 + Shared Packet RAM for multiple Link Layer usage. + 0xA44 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_658 + Shared Packet RAM for multiple Link Layer usage. + 0xA48 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_659 + Shared Packet RAM for multiple Link Layer usage. + 0xA4C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_660 + Shared Packet RAM for multiple Link Layer usage. + 0xA50 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_661 + Shared Packet RAM for multiple Link Layer usage. + 0xA54 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_662 + Shared Packet RAM for multiple Link Layer usage. + 0xA58 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_663 + Shared Packet RAM for multiple Link Layer usage. + 0xA5C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_664 + Shared Packet RAM for multiple Link Layer usage. + 0xA60 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_665 + Shared Packet RAM for multiple Link Layer usage. + 0xA64 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_666 + Shared Packet RAM for multiple Link Layer usage. + 0xA68 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_667 + Shared Packet RAM for multiple Link Layer usage. + 0xA6C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_668 + Shared Packet RAM for multiple Link Layer usage. + 0xA70 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_669 + Shared Packet RAM for multiple Link Layer usage. + 0xA74 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_670 + Shared Packet RAM for multiple Link Layer usage. + 0xA78 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_671 + Shared Packet RAM for multiple Link Layer usage. + 0xA7C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_672 + Shared Packet RAM for multiple Link Layer usage. + 0xA80 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_673 + Shared Packet RAM for multiple Link Layer usage. + 0xA84 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_674 + Shared Packet RAM for multiple Link Layer usage. + 0xA88 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_675 + Shared Packet RAM for multiple Link Layer usage. + 0xA8C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_676 + Shared Packet RAM for multiple Link Layer usage. + 0xA90 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_677 + Shared Packet RAM for multiple Link Layer usage. + 0xA94 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_678 + Shared Packet RAM for multiple Link Layer usage. + 0xA98 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_679 + Shared Packet RAM for multiple Link Layer usage. + 0xA9C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_680 + Shared Packet RAM for multiple Link Layer usage. + 0xAA0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_681 + Shared Packet RAM for multiple Link Layer usage. + 0xAA4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_682 + Shared Packet RAM for multiple Link Layer usage. + 0xAA8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_683 + Shared Packet RAM for multiple Link Layer usage. + 0xAAC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_684 + Shared Packet RAM for multiple Link Layer usage. + 0xAB0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_685 + Shared Packet RAM for multiple Link Layer usage. + 0xAB4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_686 + Shared Packet RAM for multiple Link Layer usage. + 0xAB8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_687 + Shared Packet RAM for multiple Link Layer usage. + 0xABC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_688 + Shared Packet RAM for multiple Link Layer usage. + 0xAC0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_689 + Shared Packet RAM for multiple Link Layer usage. + 0xAC4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_690 + Shared Packet RAM for multiple Link Layer usage. + 0xAC8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_691 + Shared Packet RAM for multiple Link Layer usage. + 0xACC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_692 + Shared Packet RAM for multiple Link Layer usage. + 0xAD0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_693 + Shared Packet RAM for multiple Link Layer usage. + 0xAD4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_694 + Shared Packet RAM for multiple Link Layer usage. + 0xAD8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_695 + Shared Packet RAM for multiple Link Layer usage. + 0xADC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_696 + Shared Packet RAM for multiple Link Layer usage. + 0xAE0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_697 + Shared Packet RAM for multiple Link Layer usage. + 0xAE4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_698 + Shared Packet RAM for multiple Link Layer usage. + 0xAE8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_699 + Shared Packet RAM for multiple Link Layer usage. + 0xAEC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_700 + Shared Packet RAM for multiple Link Layer usage. + 0xAF0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_701 + Shared Packet RAM for multiple Link Layer usage. + 0xAF4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_702 + Shared Packet RAM for multiple Link Layer usage. + 0xAF8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_703 + Shared Packet RAM for multiple Link Layer usage. + 0xAFC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_704 + Shared Packet RAM for multiple Link Layer usage. + 0xB00 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_705 + Shared Packet RAM for multiple Link Layer usage. + 0xB04 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_706 + Shared Packet RAM for multiple Link Layer usage. + 0xB08 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_707 + Shared Packet RAM for multiple Link Layer usage. + 0xB0C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_708 + Shared Packet RAM for multiple Link Layer usage. + 0xB10 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_709 + Shared Packet RAM for multiple Link Layer usage. + 0xB14 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_710 + Shared Packet RAM for multiple Link Layer usage. + 0xB18 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_711 + Shared Packet RAM for multiple Link Layer usage. + 0xB1C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_712 + Shared Packet RAM for multiple Link Layer usage. + 0xB20 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_713 + Shared Packet RAM for multiple Link Layer usage. + 0xB24 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_714 + Shared Packet RAM for multiple Link Layer usage. + 0xB28 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_715 + Shared Packet RAM for multiple Link Layer usage. + 0xB2C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_716 + Shared Packet RAM for multiple Link Layer usage. + 0xB30 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_717 + Shared Packet RAM for multiple Link Layer usage. + 0xB34 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_718 + Shared Packet RAM for multiple Link Layer usage. + 0xB38 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_719 + Shared Packet RAM for multiple Link Layer usage. + 0xB3C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_720 + Shared Packet RAM for multiple Link Layer usage. + 0xB40 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_721 + Shared Packet RAM for multiple Link Layer usage. + 0xB44 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_722 + Shared Packet RAM for multiple Link Layer usage. + 0xB48 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_723 + Shared Packet RAM for multiple Link Layer usage. + 0xB4C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_724 + Shared Packet RAM for multiple Link Layer usage. + 0xB50 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_725 + Shared Packet RAM for multiple Link Layer usage. + 0xB54 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_726 + Shared Packet RAM for multiple Link Layer usage. + 0xB58 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_727 + Shared Packet RAM for multiple Link Layer usage. + 0xB5C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_728 + Shared Packet RAM for multiple Link Layer usage. + 0xB60 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_729 + Shared Packet RAM for multiple Link Layer usage. + 0xB64 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_730 + Shared Packet RAM for multiple Link Layer usage. + 0xB68 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_731 + Shared Packet RAM for multiple Link Layer usage. + 0xB6C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_732 + Shared Packet RAM for multiple Link Layer usage. + 0xB70 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_733 + Shared Packet RAM for multiple Link Layer usage. + 0xB74 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_734 + Shared Packet RAM for multiple Link Layer usage. + 0xB78 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_735 + Shared Packet RAM for multiple Link Layer usage. + 0xB7C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_736 + Shared Packet RAM for multiple Link Layer usage. + 0xB80 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_737 + Shared Packet RAM for multiple Link Layer usage. + 0xB84 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_738 + Shared Packet RAM for multiple Link Layer usage. + 0xB88 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_739 + Shared Packet RAM for multiple Link Layer usage. + 0xB8C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_740 + Shared Packet RAM for multiple Link Layer usage. + 0xB90 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_741 + Shared Packet RAM for multiple Link Layer usage. + 0xB94 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_742 + Shared Packet RAM for multiple Link Layer usage. + 0xB98 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_743 + Shared Packet RAM for multiple Link Layer usage. + 0xB9C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_744 + Shared Packet RAM for multiple Link Layer usage. + 0xBA0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_745 + Shared Packet RAM for multiple Link Layer usage. + 0xBA4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_746 + Shared Packet RAM for multiple Link Layer usage. + 0xBA8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_747 + Shared Packet RAM for multiple Link Layer usage. + 0xBAC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_748 + Shared Packet RAM for multiple Link Layer usage. + 0xBB0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_749 + Shared Packet RAM for multiple Link Layer usage. + 0xBB4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_750 + Shared Packet RAM for multiple Link Layer usage. + 0xBB8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_751 + Shared Packet RAM for multiple Link Layer usage. + 0xBBC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_752 + Shared Packet RAM for multiple Link Layer usage. + 0xBC0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_753 + Shared Packet RAM for multiple Link Layer usage. + 0xBC4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_754 + Shared Packet RAM for multiple Link Layer usage. + 0xBC8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_755 + Shared Packet RAM for multiple Link Layer usage. + 0xBCC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_756 + Shared Packet RAM for multiple Link Layer usage. + 0xBD0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_757 + Shared Packet RAM for multiple Link Layer usage. + 0xBD4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_758 + Shared Packet RAM for multiple Link Layer usage. + 0xBD8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_759 + Shared Packet RAM for multiple Link Layer usage. + 0xBDC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_760 + Shared Packet RAM for multiple Link Layer usage. + 0xBE0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_761 + Shared Packet RAM for multiple Link Layer usage. + 0xBE4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_762 + Shared Packet RAM for multiple Link Layer usage. + 0xBE8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_763 + Shared Packet RAM for multiple Link Layer usage. + 0xBEC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_764 + Shared Packet RAM for multiple Link Layer usage. + 0xBF0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_765 + Shared Packet RAM for multiple Link Layer usage. + 0xBF4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_766 + Shared Packet RAM for multiple Link Layer usage. + 0xBF8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_767 + Shared Packet RAM for multiple Link Layer usage. + 0xBFC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_768 + Shared Packet RAM for multiple Link Layer usage. + 0xC00 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_769 + Shared Packet RAM for multiple Link Layer usage. + 0xC04 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_770 + Shared Packet RAM for multiple Link Layer usage. + 0xC08 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_771 + Shared Packet RAM for multiple Link Layer usage. + 0xC0C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_772 + Shared Packet RAM for multiple Link Layer usage. + 0xC10 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_773 + Shared Packet RAM for multiple Link Layer usage. + 0xC14 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_774 + Shared Packet RAM for multiple Link Layer usage. + 0xC18 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_775 + Shared Packet RAM for multiple Link Layer usage. + 0xC1C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_776 + Shared Packet RAM for multiple Link Layer usage. + 0xC20 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_777 + Shared Packet RAM for multiple Link Layer usage. + 0xC24 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_778 + Shared Packet RAM for multiple Link Layer usage. + 0xC28 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_779 + Shared Packet RAM for multiple Link Layer usage. + 0xC2C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_780 + Shared Packet RAM for multiple Link Layer usage. + 0xC30 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_781 + Shared Packet RAM for multiple Link Layer usage. + 0xC34 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_782 + Shared Packet RAM for multiple Link Layer usage. + 0xC38 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_783 + Shared Packet RAM for multiple Link Layer usage. + 0xC3C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_784 + Shared Packet RAM for multiple Link Layer usage. + 0xC40 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_785 + Shared Packet RAM for multiple Link Layer usage. + 0xC44 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_786 + Shared Packet RAM for multiple Link Layer usage. + 0xC48 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_787 + Shared Packet RAM for multiple Link Layer usage. + 0xC4C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_788 + Shared Packet RAM for multiple Link Layer usage. + 0xC50 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_789 + Shared Packet RAM for multiple Link Layer usage. + 0xC54 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_790 + Shared Packet RAM for multiple Link Layer usage. + 0xC58 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_791 + Shared Packet RAM for multiple Link Layer usage. + 0xC5C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_792 + Shared Packet RAM for multiple Link Layer usage. + 0xC60 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_793 + Shared Packet RAM for multiple Link Layer usage. + 0xC64 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_794 + Shared Packet RAM for multiple Link Layer usage. + 0xC68 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_795 + Shared Packet RAM for multiple Link Layer usage. + 0xC6C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_796 + Shared Packet RAM for multiple Link Layer usage. + 0xC70 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_797 + Shared Packet RAM for multiple Link Layer usage. + 0xC74 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_798 + Shared Packet RAM for multiple Link Layer usage. + 0xC78 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_799 + Shared Packet RAM for multiple Link Layer usage. + 0xC7C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_800 + Shared Packet RAM for multiple Link Layer usage. + 0xC80 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_801 + Shared Packet RAM for multiple Link Layer usage. + 0xC84 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_802 + Shared Packet RAM for multiple Link Layer usage. + 0xC88 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_803 + Shared Packet RAM for multiple Link Layer usage. + 0xC8C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_804 + Shared Packet RAM for multiple Link Layer usage. + 0xC90 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_805 + Shared Packet RAM for multiple Link Layer usage. + 0xC94 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_806 + Shared Packet RAM for multiple Link Layer usage. + 0xC98 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_807 + Shared Packet RAM for multiple Link Layer usage. + 0xC9C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_808 + Shared Packet RAM for multiple Link Layer usage. + 0xCA0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_809 + Shared Packet RAM for multiple Link Layer usage. + 0xCA4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_810 + Shared Packet RAM for multiple Link Layer usage. + 0xCA8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_811 + Shared Packet RAM for multiple Link Layer usage. + 0xCAC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_812 + Shared Packet RAM for multiple Link Layer usage. + 0xCB0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_813 + Shared Packet RAM for multiple Link Layer usage. + 0xCB4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_814 + Shared Packet RAM for multiple Link Layer usage. + 0xCB8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_815 + Shared Packet RAM for multiple Link Layer usage. + 0xCBC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_816 + Shared Packet RAM for multiple Link Layer usage. + 0xCC0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_817 + Shared Packet RAM for multiple Link Layer usage. + 0xCC4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_818 + Shared Packet RAM for multiple Link Layer usage. + 0xCC8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_819 + Shared Packet RAM for multiple Link Layer usage. + 0xCCC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_820 + Shared Packet RAM for multiple Link Layer usage. + 0xCD0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_821 + Shared Packet RAM for multiple Link Layer usage. + 0xCD4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_822 + Shared Packet RAM for multiple Link Layer usage. + 0xCD8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_823 + Shared Packet RAM for multiple Link Layer usage. + 0xCDC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_824 + Shared Packet RAM for multiple Link Layer usage. + 0xCE0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_825 + Shared Packet RAM for multiple Link Layer usage. + 0xCE4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_826 + Shared Packet RAM for multiple Link Layer usage. + 0xCE8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_827 + Shared Packet RAM for multiple Link Layer usage. + 0xCEC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_828 + Shared Packet RAM for multiple Link Layer usage. + 0xCF0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_829 + Shared Packet RAM for multiple Link Layer usage. + 0xCF4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_830 + Shared Packet RAM for multiple Link Layer usage. + 0xCF8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_831 + Shared Packet RAM for multiple Link Layer usage. + 0xCFC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_832 + Shared Packet RAM for multiple Link Layer usage. + 0xD00 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_833 + Shared Packet RAM for multiple Link Layer usage. + 0xD04 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_834 + Shared Packet RAM for multiple Link Layer usage. + 0xD08 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_835 + Shared Packet RAM for multiple Link Layer usage. + 0xD0C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_836 + Shared Packet RAM for multiple Link Layer usage. + 0xD10 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_837 + Shared Packet RAM for multiple Link Layer usage. + 0xD14 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_838 + Shared Packet RAM for multiple Link Layer usage. + 0xD18 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_839 + Shared Packet RAM for multiple Link Layer usage. + 0xD1C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_840 + Shared Packet RAM for multiple Link Layer usage. + 0xD20 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_841 + Shared Packet RAM for multiple Link Layer usage. + 0xD24 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_842 + Shared Packet RAM for multiple Link Layer usage. + 0xD28 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_843 + Shared Packet RAM for multiple Link Layer usage. + 0xD2C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_844 + Shared Packet RAM for multiple Link Layer usage. + 0xD30 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_845 + Shared Packet RAM for multiple Link Layer usage. + 0xD34 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_846 + Shared Packet RAM for multiple Link Layer usage. + 0xD38 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_847 + Shared Packet RAM for multiple Link Layer usage. + 0xD3C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_848 + Shared Packet RAM for multiple Link Layer usage. + 0xD40 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_849 + Shared Packet RAM for multiple Link Layer usage. + 0xD44 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_850 + Shared Packet RAM for multiple Link Layer usage. + 0xD48 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_851 + Shared Packet RAM for multiple Link Layer usage. + 0xD4C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_852 + Shared Packet RAM for multiple Link Layer usage. + 0xD50 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_853 + Shared Packet RAM for multiple Link Layer usage. + 0xD54 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_854 + Shared Packet RAM for multiple Link Layer usage. + 0xD58 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_855 + Shared Packet RAM for multiple Link Layer usage. + 0xD5C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_856 + Shared Packet RAM for multiple Link Layer usage. + 0xD60 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_857 + Shared Packet RAM for multiple Link Layer usage. + 0xD64 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_858 + Shared Packet RAM for multiple Link Layer usage. + 0xD68 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_859 + Shared Packet RAM for multiple Link Layer usage. + 0xD6C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_860 + Shared Packet RAM for multiple Link Layer usage. + 0xD70 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_861 + Shared Packet RAM for multiple Link Layer usage. + 0xD74 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_862 + Shared Packet RAM for multiple Link Layer usage. + 0xD78 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_863 + Shared Packet RAM for multiple Link Layer usage. + 0xD7C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_864 + Shared Packet RAM for multiple Link Layer usage. + 0xD80 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_865 + Shared Packet RAM for multiple Link Layer usage. + 0xD84 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_866 + Shared Packet RAM for multiple Link Layer usage. + 0xD88 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_867 + Shared Packet RAM for multiple Link Layer usage. + 0xD8C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_868 + Shared Packet RAM for multiple Link Layer usage. + 0xD90 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_869 + Shared Packet RAM for multiple Link Layer usage. + 0xD94 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_870 + Shared Packet RAM for multiple Link Layer usage. + 0xD98 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_871 + Shared Packet RAM for multiple Link Layer usage. + 0xD9C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_872 + Shared Packet RAM for multiple Link Layer usage. + 0xDA0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_873 + Shared Packet RAM for multiple Link Layer usage. + 0xDA4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_874 + Shared Packet RAM for multiple Link Layer usage. + 0xDA8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_875 + Shared Packet RAM for multiple Link Layer usage. + 0xDAC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_876 + Shared Packet RAM for multiple Link Layer usage. + 0xDB0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_877 + Shared Packet RAM for multiple Link Layer usage. + 0xDB4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_878 + Shared Packet RAM for multiple Link Layer usage. + 0xDB8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_879 + Shared Packet RAM for multiple Link Layer usage. + 0xDBC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_880 + Shared Packet RAM for multiple Link Layer usage. + 0xDC0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_881 + Shared Packet RAM for multiple Link Layer usage. + 0xDC4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_882 + Shared Packet RAM for multiple Link Layer usage. + 0xDC8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_883 + Shared Packet RAM for multiple Link Layer usage. + 0xDCC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_884 + Shared Packet RAM for multiple Link Layer usage. + 0xDD0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_885 + Shared Packet RAM for multiple Link Layer usage. + 0xDD4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_886 + Shared Packet RAM for multiple Link Layer usage. + 0xDD8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_887 + Shared Packet RAM for multiple Link Layer usage. + 0xDDC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_888 + Shared Packet RAM for multiple Link Layer usage. + 0xDE0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_889 + Shared Packet RAM for multiple Link Layer usage. + 0xDE4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_890 + Shared Packet RAM for multiple Link Layer usage. + 0xDE8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_891 + Shared Packet RAM for multiple Link Layer usage. + 0xDEC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_892 + Shared Packet RAM for multiple Link Layer usage. + 0xDF0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_893 + Shared Packet RAM for multiple Link Layer usage. + 0xDF4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_894 + Shared Packet RAM for multiple Link Layer usage. + 0xDF8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_895 + Shared Packet RAM for multiple Link Layer usage. + 0xDFC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_896 + Shared Packet RAM for multiple Link Layer usage. + 0xE00 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_897 + Shared Packet RAM for multiple Link Layer usage. + 0xE04 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_898 + Shared Packet RAM for multiple Link Layer usage. + 0xE08 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_899 + Shared Packet RAM for multiple Link Layer usage. + 0xE0C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_900 + Shared Packet RAM for multiple Link Layer usage. + 0xE10 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_901 + Shared Packet RAM for multiple Link Layer usage. + 0xE14 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_902 + Shared Packet RAM for multiple Link Layer usage. + 0xE18 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_903 + Shared Packet RAM for multiple Link Layer usage. + 0xE1C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_904 + Shared Packet RAM for multiple Link Layer usage. + 0xE20 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_905 + Shared Packet RAM for multiple Link Layer usage. + 0xE24 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_906 + Shared Packet RAM for multiple Link Layer usage. + 0xE28 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_907 + Shared Packet RAM for multiple Link Layer usage. + 0xE2C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_908 + Shared Packet RAM for multiple Link Layer usage. + 0xE30 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_909 + Shared Packet RAM for multiple Link Layer usage. + 0xE34 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_910 + Shared Packet RAM for multiple Link Layer usage. + 0xE38 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_911 + Shared Packet RAM for multiple Link Layer usage. + 0xE3C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_912 + Shared Packet RAM for multiple Link Layer usage. + 0xE40 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_913 + Shared Packet RAM for multiple Link Layer usage. + 0xE44 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_914 + Shared Packet RAM for multiple Link Layer usage. + 0xE48 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_915 + Shared Packet RAM for multiple Link Layer usage. + 0xE4C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_916 + Shared Packet RAM for multiple Link Layer usage. + 0xE50 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_917 + Shared Packet RAM for multiple Link Layer usage. + 0xE54 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_918 + Shared Packet RAM for multiple Link Layer usage. + 0xE58 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_919 + Shared Packet RAM for multiple Link Layer usage. + 0xE5C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_920 + Shared Packet RAM for multiple Link Layer usage. + 0xE60 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_921 + Shared Packet RAM for multiple Link Layer usage. + 0xE64 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_922 + Shared Packet RAM for multiple Link Layer usage. + 0xE68 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_923 + Shared Packet RAM for multiple Link Layer usage. + 0xE6C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_924 + Shared Packet RAM for multiple Link Layer usage. + 0xE70 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_925 + Shared Packet RAM for multiple Link Layer usage. + 0xE74 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_926 + Shared Packet RAM for multiple Link Layer usage. + 0xE78 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_927 + Shared Packet RAM for multiple Link Layer usage. + 0xE7C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_928 + Shared Packet RAM for multiple Link Layer usage. + 0xE80 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_929 + Shared Packet RAM for multiple Link Layer usage. + 0xE84 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_930 + Shared Packet RAM for multiple Link Layer usage. + 0xE88 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_931 + Shared Packet RAM for multiple Link Layer usage. + 0xE8C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_932 + Shared Packet RAM for multiple Link Layer usage. + 0xE90 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_933 + Shared Packet RAM for multiple Link Layer usage. + 0xE94 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_934 + Shared Packet RAM for multiple Link Layer usage. + 0xE98 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_935 + Shared Packet RAM for multiple Link Layer usage. + 0xE9C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_936 + Shared Packet RAM for multiple Link Layer usage. + 0xEA0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_937 + Shared Packet RAM for multiple Link Layer usage. + 0xEA4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_938 + Shared Packet RAM for multiple Link Layer usage. + 0xEA8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_939 + Shared Packet RAM for multiple Link Layer usage. + 0xEAC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_940 + Shared Packet RAM for multiple Link Layer usage. + 0xEB0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_941 + Shared Packet RAM for multiple Link Layer usage. + 0xEB4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_942 + Shared Packet RAM for multiple Link Layer usage. + 0xEB8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_943 + Shared Packet RAM for multiple Link Layer usage. + 0xEBC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_944 + Shared Packet RAM for multiple Link Layer usage. + 0xEC0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_945 + Shared Packet RAM for multiple Link Layer usage. + 0xEC4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_946 + Shared Packet RAM for multiple Link Layer usage. + 0xEC8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_947 + Shared Packet RAM for multiple Link Layer usage. + 0xECC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_948 + Shared Packet RAM for multiple Link Layer usage. + 0xED0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_949 + Shared Packet RAM for multiple Link Layer usage. + 0xED4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_950 + Shared Packet RAM for multiple Link Layer usage. + 0xED8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_951 + Shared Packet RAM for multiple Link Layer usage. + 0xEDC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_952 + Shared Packet RAM for multiple Link Layer usage. + 0xEE0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_953 + Shared Packet RAM for multiple Link Layer usage. + 0xEE4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_954 + Shared Packet RAM for multiple Link Layer usage. + 0xEE8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_955 + Shared Packet RAM for multiple Link Layer usage. + 0xEEC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_956 + Shared Packet RAM for multiple Link Layer usage. + 0xEF0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_957 + Shared Packet RAM for multiple Link Layer usage. + 0xEF4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_958 + Shared Packet RAM for multiple Link Layer usage. + 0xEF8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_959 + Shared Packet RAM for multiple Link Layer usage. + 0xEFC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_960 + Shared Packet RAM for multiple Link Layer usage. + 0xF00 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_961 + Shared Packet RAM for multiple Link Layer usage. + 0xF04 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_962 + Shared Packet RAM for multiple Link Layer usage. + 0xF08 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_963 + Shared Packet RAM for multiple Link Layer usage. + 0xF0C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_964 + Shared Packet RAM for multiple Link Layer usage. + 0xF10 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_965 + Shared Packet RAM for multiple Link Layer usage. + 0xF14 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_966 + Shared Packet RAM for multiple Link Layer usage. + 0xF18 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_967 + Shared Packet RAM for multiple Link Layer usage. + 0xF1C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_968 + Shared Packet RAM for multiple Link Layer usage. + 0xF20 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_969 + Shared Packet RAM for multiple Link Layer usage. + 0xF24 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_970 + Shared Packet RAM for multiple Link Layer usage. + 0xF28 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_971 + Shared Packet RAM for multiple Link Layer usage. + 0xF2C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_972 + Shared Packet RAM for multiple Link Layer usage. + 0xF30 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_973 + Shared Packet RAM for multiple Link Layer usage. + 0xF34 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_974 + Shared Packet RAM for multiple Link Layer usage. + 0xF38 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_975 + Shared Packet RAM for multiple Link Layer usage. + 0xF3C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_976 + Shared Packet RAM for multiple Link Layer usage. + 0xF40 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_977 + Shared Packet RAM for multiple Link Layer usage. + 0xF44 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_978 + Shared Packet RAM for multiple Link Layer usage. + 0xF48 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_979 + Shared Packet RAM for multiple Link Layer usage. + 0xF4C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_980 + Shared Packet RAM for multiple Link Layer usage. + 0xF50 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_981 + Shared Packet RAM for multiple Link Layer usage. + 0xF54 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_982 + Shared Packet RAM for multiple Link Layer usage. + 0xF58 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_983 + Shared Packet RAM for multiple Link Layer usage. + 0xF5C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_984 + Shared Packet RAM for multiple Link Layer usage. + 0xF60 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_985 + Shared Packet RAM for multiple Link Layer usage. + 0xF64 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_986 + Shared Packet RAM for multiple Link Layer usage. + 0xF68 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_987 + Shared Packet RAM for multiple Link Layer usage. + 0xF6C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_988 + Shared Packet RAM for multiple Link Layer usage. + 0xF70 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_989 + Shared Packet RAM for multiple Link Layer usage. + 0xF74 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_990 + Shared Packet RAM for multiple Link Layer usage. + 0xF78 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_991 + Shared Packet RAM for multiple Link Layer usage. + 0xF7C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_992 + Shared Packet RAM for multiple Link Layer usage. + 0xF80 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_993 + Shared Packet RAM for multiple Link Layer usage. + 0xF84 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_994 + Shared Packet RAM for multiple Link Layer usage. + 0xF88 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_995 + Shared Packet RAM for multiple Link Layer usage. + 0xF8C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_996 + Shared Packet RAM for multiple Link Layer usage. + 0xF90 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_997 + Shared Packet RAM for multiple Link Layer usage. + 0xF94 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_998 + Shared Packet RAM for multiple Link Layer usage. + 0xF98 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_999 + Shared Packet RAM for multiple Link Layer usage. + 0xF9C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1000 + Shared Packet RAM for multiple Link Layer usage. + 0xFA0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1001 + Shared Packet RAM for multiple Link Layer usage. + 0xFA4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1002 + Shared Packet RAM for multiple Link Layer usage. + 0xFA8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1003 + Shared Packet RAM for multiple Link Layer usage. + 0xFAC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1004 + Shared Packet RAM for multiple Link Layer usage. + 0xFB0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1005 + Shared Packet RAM for multiple Link Layer usage. + 0xFB4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1006 + Shared Packet RAM for multiple Link Layer usage. + 0xFB8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1007 + Shared Packet RAM for multiple Link Layer usage. + 0xFBC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1008 + Shared Packet RAM for multiple Link Layer usage. + 0xFC0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1009 + Shared Packet RAM for multiple Link Layer usage. + 0xFC4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1010 + Shared Packet RAM for multiple Link Layer usage. + 0xFC8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1011 + Shared Packet RAM for multiple Link Layer usage. + 0xFCC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1012 + Shared Packet RAM for multiple Link Layer usage. + 0xFD0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1013 + Shared Packet RAM for multiple Link Layer usage. + 0xFD4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1014 + Shared Packet RAM for multiple Link Layer usage. + 0xFD8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1015 + Shared Packet RAM for multiple Link Layer usage. + 0xFDC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1016 + Shared Packet RAM for multiple Link Layer usage. + 0xFE0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1017 + Shared Packet RAM for multiple Link Layer usage. + 0xFE4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1018 + Shared Packet RAM for multiple Link Layer usage. + 0xFE8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1019 + Shared Packet RAM for multiple Link Layer usage. + 0xFEC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1020 + Shared Packet RAM for multiple Link Layer usage. + 0xFF0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1021 + Shared Packet RAM for multiple Link Layer usage. + 0xFF4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1022 + Shared Packet RAM for multiple Link Layer usage. + 0xFF8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1023 + Shared Packet RAM for multiple Link Layer usage. + 0xFFC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1024 + Shared Packet RAM for multiple Link Layer usage. + 0x1000 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1025 + Shared Packet RAM for multiple Link Layer usage. + 0x1004 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1026 + Shared Packet RAM for multiple Link Layer usage. + 0x1008 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1027 + Shared Packet RAM for multiple Link Layer usage. + 0x100C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1028 + Shared Packet RAM for multiple Link Layer usage. + 0x1010 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1029 + Shared Packet RAM for multiple Link Layer usage. + 0x1014 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1030 + Shared Packet RAM for multiple Link Layer usage. + 0x1018 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1031 + Shared Packet RAM for multiple Link Layer usage. + 0x101C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1032 + Shared Packet RAM for multiple Link Layer usage. + 0x1020 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1033 + Shared Packet RAM for multiple Link Layer usage. + 0x1024 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1034 + Shared Packet RAM for multiple Link Layer usage. + 0x1028 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1035 + Shared Packet RAM for multiple Link Layer usage. + 0x102C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1036 + Shared Packet RAM for multiple Link Layer usage. + 0x1030 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1037 + Shared Packet RAM for multiple Link Layer usage. + 0x1034 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1038 + Shared Packet RAM for multiple Link Layer usage. + 0x1038 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1039 + Shared Packet RAM for multiple Link Layer usage. + 0x103C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1040 + Shared Packet RAM for multiple Link Layer usage. + 0x1040 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1041 + Shared Packet RAM for multiple Link Layer usage. + 0x1044 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1042 + Shared Packet RAM for multiple Link Layer usage. + 0x1048 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1043 + Shared Packet RAM for multiple Link Layer usage. + 0x104C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1044 + Shared Packet RAM for multiple Link Layer usage. + 0x1050 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1045 + Shared Packet RAM for multiple Link Layer usage. + 0x1054 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1046 + Shared Packet RAM for multiple Link Layer usage. + 0x1058 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1047 + Shared Packet RAM for multiple Link Layer usage. + 0x105C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1048 + Shared Packet RAM for multiple Link Layer usage. + 0x1060 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1049 + Shared Packet RAM for multiple Link Layer usage. + 0x1064 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1050 + Shared Packet RAM for multiple Link Layer usage. + 0x1068 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1051 + Shared Packet RAM for multiple Link Layer usage. + 0x106C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1052 + Shared Packet RAM for multiple Link Layer usage. + 0x1070 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1053 + Shared Packet RAM for multiple Link Layer usage. + 0x1074 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1054 + Shared Packet RAM for multiple Link Layer usage. + 0x1078 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1055 + Shared Packet RAM for multiple Link Layer usage. + 0x107C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1056 + Shared Packet RAM for multiple Link Layer usage. + 0x1080 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1057 + Shared Packet RAM for multiple Link Layer usage. + 0x1084 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1058 + Shared Packet RAM for multiple Link Layer usage. + 0x1088 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1059 + Shared Packet RAM for multiple Link Layer usage. + 0x108C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1060 + Shared Packet RAM for multiple Link Layer usage. + 0x1090 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1061 + Shared Packet RAM for multiple Link Layer usage. + 0x1094 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1062 + Shared Packet RAM for multiple Link Layer usage. + 0x1098 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1063 + Shared Packet RAM for multiple Link Layer usage. + 0x109C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1064 + Shared Packet RAM for multiple Link Layer usage. + 0x10A0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1065 + Shared Packet RAM for multiple Link Layer usage. + 0x10A4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1066 + Shared Packet RAM for multiple Link Layer usage. + 0x10A8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1067 + Shared Packet RAM for multiple Link Layer usage. + 0x10AC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1068 + Shared Packet RAM for multiple Link Layer usage. + 0x10B0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1069 + Shared Packet RAM for multiple Link Layer usage. + 0x10B4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1070 + Shared Packet RAM for multiple Link Layer usage. + 0x10B8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1071 + Shared Packet RAM for multiple Link Layer usage. + 0x10BC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1072 + Shared Packet RAM for multiple Link Layer usage. + 0x10C0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1073 + Shared Packet RAM for multiple Link Layer usage. + 0x10C4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1074 + Shared Packet RAM for multiple Link Layer usage. + 0x10C8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1075 + Shared Packet RAM for multiple Link Layer usage. + 0x10CC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1076 + Shared Packet RAM for multiple Link Layer usage. + 0x10D0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1077 + Shared Packet RAM for multiple Link Layer usage. + 0x10D4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1078 + Shared Packet RAM for multiple Link Layer usage. + 0x10D8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1079 + Shared Packet RAM for multiple Link Layer usage. + 0x10DC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1080 + Shared Packet RAM for multiple Link Layer usage. + 0x10E0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1081 + Shared Packet RAM for multiple Link Layer usage. + 0x10E4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1082 + Shared Packet RAM for multiple Link Layer usage. + 0x10E8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1083 + Shared Packet RAM for multiple Link Layer usage. + 0x10EC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1084 + Shared Packet RAM for multiple Link Layer usage. + 0x10F0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1085 + Shared Packet RAM for multiple Link Layer usage. + 0x10F4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1086 + Shared Packet RAM for multiple Link Layer usage. + 0x10F8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1087 + Shared Packet RAM for multiple Link Layer usage. + 0x10FC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1088 + Shared Packet RAM for multiple Link Layer usage. + 0x1100 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1089 + Shared Packet RAM for multiple Link Layer usage. + 0x1104 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1090 + Shared Packet RAM for multiple Link Layer usage. + 0x1108 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1091 + Shared Packet RAM for multiple Link Layer usage. + 0x110C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1092 + Shared Packet RAM for multiple Link Layer usage. + 0x1110 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1093 + Shared Packet RAM for multiple Link Layer usage. + 0x1114 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1094 + Shared Packet RAM for multiple Link Layer usage. + 0x1118 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1095 + Shared Packet RAM for multiple Link Layer usage. + 0x111C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1096 + Shared Packet RAM for multiple Link Layer usage. + 0x1120 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1097 + Shared Packet RAM for multiple Link Layer usage. + 0x1124 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1098 + Shared Packet RAM for multiple Link Layer usage. + 0x1128 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1099 + Shared Packet RAM for multiple Link Layer usage. + 0x112C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1100 + Shared Packet RAM for multiple Link Layer usage. + 0x1130 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1101 + Shared Packet RAM for multiple Link Layer usage. + 0x1134 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1102 + Shared Packet RAM for multiple Link Layer usage. + 0x1138 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1103 + Shared Packet RAM for multiple Link Layer usage. + 0x113C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1104 + Shared Packet RAM for multiple Link Layer usage. + 0x1140 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1105 + Shared Packet RAM for multiple Link Layer usage. + 0x1144 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1106 + Shared Packet RAM for multiple Link Layer usage. + 0x1148 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1107 + Shared Packet RAM for multiple Link Layer usage. + 0x114C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1108 + Shared Packet RAM for multiple Link Layer usage. + 0x1150 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1109 + Shared Packet RAM for multiple Link Layer usage. + 0x1154 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1110 + Shared Packet RAM for multiple Link Layer usage. + 0x1158 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1111 + Shared Packet RAM for multiple Link Layer usage. + 0x115C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1112 + Shared Packet RAM for multiple Link Layer usage. + 0x1160 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1113 + Shared Packet RAM for multiple Link Layer usage. + 0x1164 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1114 + Shared Packet RAM for multiple Link Layer usage. + 0x1168 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1115 + Shared Packet RAM for multiple Link Layer usage. + 0x116C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1116 + Shared Packet RAM for multiple Link Layer usage. + 0x1170 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1117 + Shared Packet RAM for multiple Link Layer usage. + 0x1174 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1118 + Shared Packet RAM for multiple Link Layer usage. + 0x1178 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1119 + Shared Packet RAM for multiple Link Layer usage. + 0x117C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1120 + Shared Packet RAM for multiple Link Layer usage. + 0x1180 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1121 + Shared Packet RAM for multiple Link Layer usage. + 0x1184 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1122 + Shared Packet RAM for multiple Link Layer usage. + 0x1188 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1123 + Shared Packet RAM for multiple Link Layer usage. + 0x118C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1124 + Shared Packet RAM for multiple Link Layer usage. + 0x1190 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1125 + Shared Packet RAM for multiple Link Layer usage. + 0x1194 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1126 + Shared Packet RAM for multiple Link Layer usage. + 0x1198 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1127 + Shared Packet RAM for multiple Link Layer usage. + 0x119C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1128 + Shared Packet RAM for multiple Link Layer usage. + 0x11A0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1129 + Shared Packet RAM for multiple Link Layer usage. + 0x11A4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1130 + Shared Packet RAM for multiple Link Layer usage. + 0x11A8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1131 + Shared Packet RAM for multiple Link Layer usage. + 0x11AC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1132 + Shared Packet RAM for multiple Link Layer usage. + 0x11B0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1133 + Shared Packet RAM for multiple Link Layer usage. + 0x11B4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1134 + Shared Packet RAM for multiple Link Layer usage. + 0x11B8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1135 + Shared Packet RAM for multiple Link Layer usage. + 0x11BC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1136 + Shared Packet RAM for multiple Link Layer usage. + 0x11C0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1137 + Shared Packet RAM for multiple Link Layer usage. + 0x11C4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1138 + Shared Packet RAM for multiple Link Layer usage. + 0x11C8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1139 + Shared Packet RAM for multiple Link Layer usage. + 0x11CC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1140 + Shared Packet RAM for multiple Link Layer usage. + 0x11D0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1141 + Shared Packet RAM for multiple Link Layer usage. + 0x11D4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1142 + Shared Packet RAM for multiple Link Layer usage. + 0x11D8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1143 + Shared Packet RAM for multiple Link Layer usage. + 0x11DC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1144 + Shared Packet RAM for multiple Link Layer usage. + 0x11E0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1145 + Shared Packet RAM for multiple Link Layer usage. + 0x11E4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1146 + Shared Packet RAM for multiple Link Layer usage. + 0x11E8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1147 + Shared Packet RAM for multiple Link Layer usage. + 0x11EC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1148 + Shared Packet RAM for multiple Link Layer usage. + 0x11F0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1149 + Shared Packet RAM for multiple Link Layer usage. + 0x11F4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1150 + Shared Packet RAM for multiple Link Layer usage. + 0x11F8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1151 + Shared Packet RAM for multiple Link Layer usage. + 0x11FC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1152 + Shared Packet RAM for multiple Link Layer usage. + 0x1200 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1153 + Shared Packet RAM for multiple Link Layer usage. + 0x1204 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1154 + Shared Packet RAM for multiple Link Layer usage. + 0x1208 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1155 + Shared Packet RAM for multiple Link Layer usage. + 0x120C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1156 + Shared Packet RAM for multiple Link Layer usage. + 0x1210 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1157 + Shared Packet RAM for multiple Link Layer usage. + 0x1214 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1158 + Shared Packet RAM for multiple Link Layer usage. + 0x1218 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1159 + Shared Packet RAM for multiple Link Layer usage. + 0x121C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1160 + Shared Packet RAM for multiple Link Layer usage. + 0x1220 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1161 + Shared Packet RAM for multiple Link Layer usage. + 0x1224 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1162 + Shared Packet RAM for multiple Link Layer usage. + 0x1228 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1163 + Shared Packet RAM for multiple Link Layer usage. + 0x122C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1164 + Shared Packet RAM for multiple Link Layer usage. + 0x1230 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1165 + Shared Packet RAM for multiple Link Layer usage. + 0x1234 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1166 + Shared Packet RAM for multiple Link Layer usage. + 0x1238 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1167 + Shared Packet RAM for multiple Link Layer usage. + 0x123C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1168 + Shared Packet RAM for multiple Link Layer usage. + 0x1240 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1169 + Shared Packet RAM for multiple Link Layer usage. + 0x1244 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1170 + Shared Packet RAM for multiple Link Layer usage. + 0x1248 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1171 + Shared Packet RAM for multiple Link Layer usage. + 0x124C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1172 + Shared Packet RAM for multiple Link Layer usage. + 0x1250 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1173 + Shared Packet RAM for multiple Link Layer usage. + 0x1254 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1174 + Shared Packet RAM for multiple Link Layer usage. + 0x1258 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1175 + Shared Packet RAM for multiple Link Layer usage. + 0x125C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1176 + Shared Packet RAM for multiple Link Layer usage. + 0x1260 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1177 + Shared Packet RAM for multiple Link Layer usage. + 0x1264 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1178 + Shared Packet RAM for multiple Link Layer usage. + 0x1268 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1179 + Shared Packet RAM for multiple Link Layer usage. + 0x126C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1180 + Shared Packet RAM for multiple Link Layer usage. + 0x1270 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1181 + Shared Packet RAM for multiple Link Layer usage. + 0x1274 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1182 + Shared Packet RAM for multiple Link Layer usage. + 0x1278 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1183 + Shared Packet RAM for multiple Link Layer usage. + 0x127C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1184 + Shared Packet RAM for multiple Link Layer usage. + 0x1280 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1185 + Shared Packet RAM for multiple Link Layer usage. + 0x1284 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1186 + Shared Packet RAM for multiple Link Layer usage. + 0x1288 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1187 + Shared Packet RAM for multiple Link Layer usage. + 0x128C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1188 + Shared Packet RAM for multiple Link Layer usage. + 0x1290 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1189 + Shared Packet RAM for multiple Link Layer usage. + 0x1294 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1190 + Shared Packet RAM for multiple Link Layer usage. + 0x1298 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1191 + Shared Packet RAM for multiple Link Layer usage. + 0x129C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1192 + Shared Packet RAM for multiple Link Layer usage. + 0x12A0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1193 + Shared Packet RAM for multiple Link Layer usage. + 0x12A4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1194 + Shared Packet RAM for multiple Link Layer usage. + 0x12A8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1195 + Shared Packet RAM for multiple Link Layer usage. + 0x12AC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1196 + Shared Packet RAM for multiple Link Layer usage. + 0x12B0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1197 + Shared Packet RAM for multiple Link Layer usage. + 0x12B4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1198 + Shared Packet RAM for multiple Link Layer usage. + 0x12B8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1199 + Shared Packet RAM for multiple Link Layer usage. + 0x12BC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1200 + Shared Packet RAM for multiple Link Layer usage. + 0x12C0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1201 + Shared Packet RAM for multiple Link Layer usage. + 0x12C4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1202 + Shared Packet RAM for multiple Link Layer usage. + 0x12C8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1203 + Shared Packet RAM for multiple Link Layer usage. + 0x12CC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1204 + Shared Packet RAM for multiple Link Layer usage. + 0x12D0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1205 + Shared Packet RAM for multiple Link Layer usage. + 0x12D4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1206 + Shared Packet RAM for multiple Link Layer usage. + 0x12D8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1207 + Shared Packet RAM for multiple Link Layer usage. + 0x12DC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1208 + Shared Packet RAM for multiple Link Layer usage. + 0x12E0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1209 + Shared Packet RAM for multiple Link Layer usage. + 0x12E4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1210 + Shared Packet RAM for multiple Link Layer usage. + 0x12E8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1211 + Shared Packet RAM for multiple Link Layer usage. + 0x12EC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1212 + Shared Packet RAM for multiple Link Layer usage. + 0x12F0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1213 + Shared Packet RAM for multiple Link Layer usage. + 0x12F4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1214 + Shared Packet RAM for multiple Link Layer usage. + 0x12F8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1215 + Shared Packet RAM for multiple Link Layer usage. + 0x12FC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1216 + Shared Packet RAM for multiple Link Layer usage. + 0x1300 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1217 + Shared Packet RAM for multiple Link Layer usage. + 0x1304 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1218 + Shared Packet RAM for multiple Link Layer usage. + 0x1308 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1219 + Shared Packet RAM for multiple Link Layer usage. + 0x130C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1220 + Shared Packet RAM for multiple Link Layer usage. + 0x1310 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1221 + Shared Packet RAM for multiple Link Layer usage. + 0x1314 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1222 + Shared Packet RAM for multiple Link Layer usage. + 0x1318 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1223 + Shared Packet RAM for multiple Link Layer usage. + 0x131C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1224 + Shared Packet RAM for multiple Link Layer usage. + 0x1320 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1225 + Shared Packet RAM for multiple Link Layer usage. + 0x1324 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1226 + Shared Packet RAM for multiple Link Layer usage. + 0x1328 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1227 + Shared Packet RAM for multiple Link Layer usage. + 0x132C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1228 + Shared Packet RAM for multiple Link Layer usage. + 0x1330 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1229 + Shared Packet RAM for multiple Link Layer usage. + 0x1334 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1230 + Shared Packet RAM for multiple Link Layer usage. + 0x1338 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1231 + Shared Packet RAM for multiple Link Layer usage. + 0x133C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1232 + Shared Packet RAM for multiple Link Layer usage. + 0x1340 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1233 + Shared Packet RAM for multiple Link Layer usage. + 0x1344 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1234 + Shared Packet RAM for multiple Link Layer usage. + 0x1348 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1235 + Shared Packet RAM for multiple Link Layer usage. + 0x134C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1236 + Shared Packet RAM for multiple Link Layer usage. + 0x1350 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1237 + Shared Packet RAM for multiple Link Layer usage. + 0x1354 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1238 + Shared Packet RAM for multiple Link Layer usage. + 0x1358 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1239 + Shared Packet RAM for multiple Link Layer usage. + 0x135C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1240 + Shared Packet RAM for multiple Link Layer usage. + 0x1360 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1241 + Shared Packet RAM for multiple Link Layer usage. + 0x1364 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1242 + Shared Packet RAM for multiple Link Layer usage. + 0x1368 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1243 + Shared Packet RAM for multiple Link Layer usage. + 0x136C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1244 + Shared Packet RAM for multiple Link Layer usage. + 0x1370 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1245 + Shared Packet RAM for multiple Link Layer usage. + 0x1374 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1246 + Shared Packet RAM for multiple Link Layer usage. + 0x1378 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1247 + Shared Packet RAM for multiple Link Layer usage. + 0x137C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1248 + Shared Packet RAM for multiple Link Layer usage. + 0x1380 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1249 + Shared Packet RAM for multiple Link Layer usage. + 0x1384 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1250 + Shared Packet RAM for multiple Link Layer usage. + 0x1388 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1251 + Shared Packet RAM for multiple Link Layer usage. + 0x138C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1252 + Shared Packet RAM for multiple Link Layer usage. + 0x1390 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1253 + Shared Packet RAM for multiple Link Layer usage. + 0x1394 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1254 + Shared Packet RAM for multiple Link Layer usage. + 0x1398 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1255 + Shared Packet RAM for multiple Link Layer usage. + 0x139C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1256 + Shared Packet RAM for multiple Link Layer usage. + 0x13A0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1257 + Shared Packet RAM for multiple Link Layer usage. + 0x13A4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1258 + Shared Packet RAM for multiple Link Layer usage. + 0x13A8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1259 + Shared Packet RAM for multiple Link Layer usage. + 0x13AC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1260 + Shared Packet RAM for multiple Link Layer usage. + 0x13B0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1261 + Shared Packet RAM for multiple Link Layer usage. + 0x13B4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1262 + Shared Packet RAM for multiple Link Layer usage. + 0x13B8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1263 + Shared Packet RAM for multiple Link Layer usage. + 0x13BC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1264 + Shared Packet RAM for multiple Link Layer usage. + 0x13C0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1265 + Shared Packet RAM for multiple Link Layer usage. + 0x13C4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1266 + Shared Packet RAM for multiple Link Layer usage. + 0x13C8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1267 + Shared Packet RAM for multiple Link Layer usage. + 0x13CC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1268 + Shared Packet RAM for multiple Link Layer usage. + 0x13D0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1269 + Shared Packet RAM for multiple Link Layer usage. + 0x13D4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1270 + Shared Packet RAM for multiple Link Layer usage. + 0x13D8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1271 + Shared Packet RAM for multiple Link Layer usage. + 0x13DC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1272 + Shared Packet RAM for multiple Link Layer usage. + 0x13E0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1273 + Shared Packet RAM for multiple Link Layer usage. + 0x13E4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1274 + Shared Packet RAM for multiple Link Layer usage. + 0x13E8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1275 + Shared Packet RAM for multiple Link Layer usage. + 0x13EC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1276 + Shared Packet RAM for multiple Link Layer usage. + 0x13F0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1277 + Shared Packet RAM for multiple Link Layer usage. + 0x13F4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1278 + Shared Packet RAM for multiple Link Layer usage. + 0x13F8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1279 + Shared Packet RAM for multiple Link Layer usage. + 0x13FC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1280 + Shared Packet RAM for multiple Link Layer usage. + 0x1400 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1281 + Shared Packet RAM for multiple Link Layer usage. + 0x1404 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1282 + Shared Packet RAM for multiple Link Layer usage. + 0x1408 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1283 + Shared Packet RAM for multiple Link Layer usage. + 0x140C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1284 + Shared Packet RAM for multiple Link Layer usage. + 0x1410 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1285 + Shared Packet RAM for multiple Link Layer usage. + 0x1414 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1286 + Shared Packet RAM for multiple Link Layer usage. + 0x1418 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1287 + Shared Packet RAM for multiple Link Layer usage. + 0x141C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1288 + Shared Packet RAM for multiple Link Layer usage. + 0x1420 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1289 + Shared Packet RAM for multiple Link Layer usage. + 0x1424 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1290 + Shared Packet RAM for multiple Link Layer usage. + 0x1428 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1291 + Shared Packet RAM for multiple Link Layer usage. + 0x142C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1292 + Shared Packet RAM for multiple Link Layer usage. + 0x1430 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1293 + Shared Packet RAM for multiple Link Layer usage. + 0x1434 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1294 + Shared Packet RAM for multiple Link Layer usage. + 0x1438 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1295 + Shared Packet RAM for multiple Link Layer usage. + 0x143C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1296 + Shared Packet RAM for multiple Link Layer usage. + 0x1440 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1297 + Shared Packet RAM for multiple Link Layer usage. + 0x1444 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1298 + Shared Packet RAM for multiple Link Layer usage. + 0x1448 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1299 + Shared Packet RAM for multiple Link Layer usage. + 0x144C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1300 + Shared Packet RAM for multiple Link Layer usage. + 0x1450 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1301 + Shared Packet RAM for multiple Link Layer usage. + 0x1454 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1302 + Shared Packet RAM for multiple Link Layer usage. + 0x1458 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1303 + Shared Packet RAM for multiple Link Layer usage. + 0x145C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1304 + Shared Packet RAM for multiple Link Layer usage. + 0x1460 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1305 + Shared Packet RAM for multiple Link Layer usage. + 0x1464 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1306 + Shared Packet RAM for multiple Link Layer usage. + 0x1468 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1307 + Shared Packet RAM for multiple Link Layer usage. + 0x146C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1308 + Shared Packet RAM for multiple Link Layer usage. + 0x1470 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1309 + Shared Packet RAM for multiple Link Layer usage. + 0x1474 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1310 + Shared Packet RAM for multiple Link Layer usage. + 0x1478 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1311 + Shared Packet RAM for multiple Link Layer usage. + 0x147C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1312 + Shared Packet RAM for multiple Link Layer usage. + 0x1480 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1313 + Shared Packet RAM for multiple Link Layer usage. + 0x1484 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1314 + Shared Packet RAM for multiple Link Layer usage. + 0x1488 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1315 + Shared Packet RAM for multiple Link Layer usage. + 0x148C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1316 + Shared Packet RAM for multiple Link Layer usage. + 0x1490 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1317 + Shared Packet RAM for multiple Link Layer usage. + 0x1494 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1318 + Shared Packet RAM for multiple Link Layer usage. + 0x1498 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1319 + Shared Packet RAM for multiple Link Layer usage. + 0x149C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1320 + Shared Packet RAM for multiple Link Layer usage. + 0x14A0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1321 + Shared Packet RAM for multiple Link Layer usage. + 0x14A4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1322 + Shared Packet RAM for multiple Link Layer usage. + 0x14A8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1323 + Shared Packet RAM for multiple Link Layer usage. + 0x14AC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1324 + Shared Packet RAM for multiple Link Layer usage. + 0x14B0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1325 + Shared Packet RAM for multiple Link Layer usage. + 0x14B4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1326 + Shared Packet RAM for multiple Link Layer usage. + 0x14B8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1327 + Shared Packet RAM for multiple Link Layer usage. + 0x14BC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1328 + Shared Packet RAM for multiple Link Layer usage. + 0x14C0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1329 + Shared Packet RAM for multiple Link Layer usage. + 0x14C4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1330 + Shared Packet RAM for multiple Link Layer usage. + 0x14C8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1331 + Shared Packet RAM for multiple Link Layer usage. + 0x14CC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1332 + Shared Packet RAM for multiple Link Layer usage. + 0x14D0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1333 + Shared Packet RAM for multiple Link Layer usage. + 0x14D4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1334 + Shared Packet RAM for multiple Link Layer usage. + 0x14D8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1335 + Shared Packet RAM for multiple Link Layer usage. + 0x14DC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1336 + Shared Packet RAM for multiple Link Layer usage. + 0x14E0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1337 + Shared Packet RAM for multiple Link Layer usage. + 0x14E4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1338 + Shared Packet RAM for multiple Link Layer usage. + 0x14E8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1339 + Shared Packet RAM for multiple Link Layer usage. + 0x14EC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1340 + Shared Packet RAM for multiple Link Layer usage. + 0x14F0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1341 + Shared Packet RAM for multiple Link Layer usage. + 0x14F4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1342 + Shared Packet RAM for multiple Link Layer usage. + 0x14F8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1343 + Shared Packet RAM for multiple Link Layer usage. + 0x14FC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1344 + Shared Packet RAM for multiple Link Layer usage. + 0x1500 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1345 + Shared Packet RAM for multiple Link Layer usage. + 0x1504 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1346 + Shared Packet RAM for multiple Link Layer usage. + 0x1508 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1347 + Shared Packet RAM for multiple Link Layer usage. + 0x150C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1348 + Shared Packet RAM for multiple Link Layer usage. + 0x1510 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1349 + Shared Packet RAM for multiple Link Layer usage. + 0x1514 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1350 + Shared Packet RAM for multiple Link Layer usage. + 0x1518 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1351 + Shared Packet RAM for multiple Link Layer usage. + 0x151C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1352 + Shared Packet RAM for multiple Link Layer usage. + 0x1520 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1353 + Shared Packet RAM for multiple Link Layer usage. + 0x1524 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1354 + Shared Packet RAM for multiple Link Layer usage. + 0x1528 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1355 + Shared Packet RAM for multiple Link Layer usage. + 0x152C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1356 + Shared Packet RAM for multiple Link Layer usage. + 0x1530 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1357 + Shared Packet RAM for multiple Link Layer usage. + 0x1534 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1358 + Shared Packet RAM for multiple Link Layer usage. + 0x1538 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1359 + Shared Packet RAM for multiple Link Layer usage. + 0x153C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1360 + Shared Packet RAM for multiple Link Layer usage. + 0x1540 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1361 + Shared Packet RAM for multiple Link Layer usage. + 0x1544 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1362 + Shared Packet RAM for multiple Link Layer usage. + 0x1548 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1363 + Shared Packet RAM for multiple Link Layer usage. + 0x154C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1364 + Shared Packet RAM for multiple Link Layer usage. + 0x1550 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1365 + Shared Packet RAM for multiple Link Layer usage. + 0x1554 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1366 + Shared Packet RAM for multiple Link Layer usage. + 0x1558 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1367 + Shared Packet RAM for multiple Link Layer usage. + 0x155C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1368 + Shared Packet RAM for multiple Link Layer usage. + 0x1560 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1369 + Shared Packet RAM for multiple Link Layer usage. + 0x1564 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1370 + Shared Packet RAM for multiple Link Layer usage. + 0x1568 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1371 + Shared Packet RAM for multiple Link Layer usage. + 0x156C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1372 + Shared Packet RAM for multiple Link Layer usage. + 0x1570 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1373 + Shared Packet RAM for multiple Link Layer usage. + 0x1574 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1374 + Shared Packet RAM for multiple Link Layer usage. + 0x1578 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1375 + Shared Packet RAM for multiple Link Layer usage. + 0x157C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1376 + Shared Packet RAM for multiple Link Layer usage. + 0x1580 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1377 + Shared Packet RAM for multiple Link Layer usage. + 0x1584 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1378 + Shared Packet RAM for multiple Link Layer usage. + 0x1588 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1379 + Shared Packet RAM for multiple Link Layer usage. + 0x158C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1380 + Shared Packet RAM for multiple Link Layer usage. + 0x1590 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1381 + Shared Packet RAM for multiple Link Layer usage. + 0x1594 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1382 + Shared Packet RAM for multiple Link Layer usage. + 0x1598 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1383 + Shared Packet RAM for multiple Link Layer usage. + 0x159C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1384 + Shared Packet RAM for multiple Link Layer usage. + 0x15A0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1385 + Shared Packet RAM for multiple Link Layer usage. + 0x15A4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1386 + Shared Packet RAM for multiple Link Layer usage. + 0x15A8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1387 + Shared Packet RAM for multiple Link Layer usage. + 0x15AC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1388 + Shared Packet RAM for multiple Link Layer usage. + 0x15B0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1389 + Shared Packet RAM for multiple Link Layer usage. + 0x15B4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1390 + Shared Packet RAM for multiple Link Layer usage. + 0x15B8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1391 + Shared Packet RAM for multiple Link Layer usage. + 0x15BC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1392 + Shared Packet RAM for multiple Link Layer usage. + 0x15C0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1393 + Shared Packet RAM for multiple Link Layer usage. + 0x15C4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1394 + Shared Packet RAM for multiple Link Layer usage. + 0x15C8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1395 + Shared Packet RAM for multiple Link Layer usage. + 0x15CC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1396 + Shared Packet RAM for multiple Link Layer usage. + 0x15D0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1397 + Shared Packet RAM for multiple Link Layer usage. + 0x15D4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1398 + Shared Packet RAM for multiple Link Layer usage. + 0x15D8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1399 + Shared Packet RAM for multiple Link Layer usage. + 0x15DC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1400 + Shared Packet RAM for multiple Link Layer usage. + 0x15E0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1401 + Shared Packet RAM for multiple Link Layer usage. + 0x15E4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1402 + Shared Packet RAM for multiple Link Layer usage. + 0x15E8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1403 + Shared Packet RAM for multiple Link Layer usage. + 0x15EC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1404 + Shared Packet RAM for multiple Link Layer usage. + 0x15F0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1405 + Shared Packet RAM for multiple Link Layer usage. + 0x15F4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1406 + Shared Packet RAM for multiple Link Layer usage. + 0x15F8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1407 + Shared Packet RAM for multiple Link Layer usage. + 0x15FC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1408 + Shared Packet RAM for multiple Link Layer usage. + 0x1600 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1409 + Shared Packet RAM for multiple Link Layer usage. + 0x1604 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1410 + Shared Packet RAM for multiple Link Layer usage. + 0x1608 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1411 + Shared Packet RAM for multiple Link Layer usage. + 0x160C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1412 + Shared Packet RAM for multiple Link Layer usage. + 0x1610 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1413 + Shared Packet RAM for multiple Link Layer usage. + 0x1614 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1414 + Shared Packet RAM for multiple Link Layer usage. + 0x1618 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1415 + Shared Packet RAM for multiple Link Layer usage. + 0x161C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1416 + Shared Packet RAM for multiple Link Layer usage. + 0x1620 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1417 + Shared Packet RAM for multiple Link Layer usage. + 0x1624 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1418 + Shared Packet RAM for multiple Link Layer usage. + 0x1628 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1419 + Shared Packet RAM for multiple Link Layer usage. + 0x162C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1420 + Shared Packet RAM for multiple Link Layer usage. + 0x1630 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1421 + Shared Packet RAM for multiple Link Layer usage. + 0x1634 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1422 + Shared Packet RAM for multiple Link Layer usage. + 0x1638 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1423 + Shared Packet RAM for multiple Link Layer usage. + 0x163C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1424 + Shared Packet RAM for multiple Link Layer usage. + 0x1640 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1425 + Shared Packet RAM for multiple Link Layer usage. + 0x1644 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1426 + Shared Packet RAM for multiple Link Layer usage. + 0x1648 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1427 + Shared Packet RAM for multiple Link Layer usage. + 0x164C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1428 + Shared Packet RAM for multiple Link Layer usage. + 0x1650 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1429 + Shared Packet RAM for multiple Link Layer usage. + 0x1654 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1430 + Shared Packet RAM for multiple Link Layer usage. + 0x1658 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1431 + Shared Packet RAM for multiple Link Layer usage. + 0x165C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1432 + Shared Packet RAM for multiple Link Layer usage. + 0x1660 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1433 + Shared Packet RAM for multiple Link Layer usage. + 0x1664 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1434 + Shared Packet RAM for multiple Link Layer usage. + 0x1668 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1435 + Shared Packet RAM for multiple Link Layer usage. + 0x166C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1436 + Shared Packet RAM for multiple Link Layer usage. + 0x1670 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1437 + Shared Packet RAM for multiple Link Layer usage. + 0x1674 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1438 + Shared Packet RAM for multiple Link Layer usage. + 0x1678 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1439 + Shared Packet RAM for multiple Link Layer usage. + 0x167C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1440 + Shared Packet RAM for multiple Link Layer usage. + 0x1680 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1441 + Shared Packet RAM for multiple Link Layer usage. + 0x1684 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1442 + Shared Packet RAM for multiple Link Layer usage. + 0x1688 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1443 + Shared Packet RAM for multiple Link Layer usage. + 0x168C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1444 + Shared Packet RAM for multiple Link Layer usage. + 0x1690 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1445 + Shared Packet RAM for multiple Link Layer usage. + 0x1694 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1446 + Shared Packet RAM for multiple Link Layer usage. + 0x1698 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1447 + Shared Packet RAM for multiple Link Layer usage. + 0x169C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1448 + Shared Packet RAM for multiple Link Layer usage. + 0x16A0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1449 + Shared Packet RAM for multiple Link Layer usage. + 0x16A4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1450 + Shared Packet RAM for multiple Link Layer usage. + 0x16A8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1451 + Shared Packet RAM for multiple Link Layer usage. + 0x16AC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1452 + Shared Packet RAM for multiple Link Layer usage. + 0x16B0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1453 + Shared Packet RAM for multiple Link Layer usage. + 0x16B4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1454 + Shared Packet RAM for multiple Link Layer usage. + 0x16B8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1455 + Shared Packet RAM for multiple Link Layer usage. + 0x16BC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1456 + Shared Packet RAM for multiple Link Layer usage. + 0x16C0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1457 + Shared Packet RAM for multiple Link Layer usage. + 0x16C4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1458 + Shared Packet RAM for multiple Link Layer usage. + 0x16C8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1459 + Shared Packet RAM for multiple Link Layer usage. + 0x16CC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1460 + Shared Packet RAM for multiple Link Layer usage. + 0x16D0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1461 + Shared Packet RAM for multiple Link Layer usage. + 0x16D4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1462 + Shared Packet RAM for multiple Link Layer usage. + 0x16D8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1463 + Shared Packet RAM for multiple Link Layer usage. + 0x16DC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1464 + Shared Packet RAM for multiple Link Layer usage. + 0x16E0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1465 + Shared Packet RAM for multiple Link Layer usage. + 0x16E4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1466 + Shared Packet RAM for multiple Link Layer usage. + 0x16E8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1467 + Shared Packet RAM for multiple Link Layer usage. + 0x16EC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1468 + Shared Packet RAM for multiple Link Layer usage. + 0x16F0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1469 + Shared Packet RAM for multiple Link Layer usage. + 0x16F4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1470 + Shared Packet RAM for multiple Link Layer usage. + 0x16F8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1471 + Shared Packet RAM for multiple Link Layer usage. + 0x16FC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1472 + Shared Packet RAM for multiple Link Layer usage. + 0x1700 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1473 + Shared Packet RAM for multiple Link Layer usage. + 0x1704 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1474 + Shared Packet RAM for multiple Link Layer usage. + 0x1708 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1475 + Shared Packet RAM for multiple Link Layer usage. + 0x170C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1476 + Shared Packet RAM for multiple Link Layer usage. + 0x1710 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1477 + Shared Packet RAM for multiple Link Layer usage. + 0x1714 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1478 + Shared Packet RAM for multiple Link Layer usage. + 0x1718 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1479 + Shared Packet RAM for multiple Link Layer usage. + 0x171C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1480 + Shared Packet RAM for multiple Link Layer usage. + 0x1720 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1481 + Shared Packet RAM for multiple Link Layer usage. + 0x1724 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1482 + Shared Packet RAM for multiple Link Layer usage. + 0x1728 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1483 + Shared Packet RAM for multiple Link Layer usage. + 0x172C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1484 + Shared Packet RAM for multiple Link Layer usage. + 0x1730 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1485 + Shared Packet RAM for multiple Link Layer usage. + 0x1734 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1486 + Shared Packet RAM for multiple Link Layer usage. + 0x1738 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1487 + Shared Packet RAM for multiple Link Layer usage. + 0x173C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1488 + Shared Packet RAM for multiple Link Layer usage. + 0x1740 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1489 + Shared Packet RAM for multiple Link Layer usage. + 0x1744 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1490 + Shared Packet RAM for multiple Link Layer usage. + 0x1748 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1491 + Shared Packet RAM for multiple Link Layer usage. + 0x174C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1492 + Shared Packet RAM for multiple Link Layer usage. + 0x1750 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1493 + Shared Packet RAM for multiple Link Layer usage. + 0x1754 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1494 + Shared Packet RAM for multiple Link Layer usage. + 0x1758 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1495 + Shared Packet RAM for multiple Link Layer usage. + 0x175C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1496 + Shared Packet RAM for multiple Link Layer usage. + 0x1760 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1497 + Shared Packet RAM for multiple Link Layer usage. + 0x1764 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1498 + Shared Packet RAM for multiple Link Layer usage. + 0x1768 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1499 + Shared Packet RAM for multiple Link Layer usage. + 0x176C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1500 + Shared Packet RAM for multiple Link Layer usage. + 0x1770 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1501 + Shared Packet RAM for multiple Link Layer usage. + 0x1774 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1502 + Shared Packet RAM for multiple Link Layer usage. + 0x1778 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1503 + Shared Packet RAM for multiple Link Layer usage. + 0x177C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1504 + Shared Packet RAM for multiple Link Layer usage. + 0x1780 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1505 + Shared Packet RAM for multiple Link Layer usage. + 0x1784 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1506 + Shared Packet RAM for multiple Link Layer usage. + 0x1788 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1507 + Shared Packet RAM for multiple Link Layer usage. + 0x178C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1508 + Shared Packet RAM for multiple Link Layer usage. + 0x1790 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1509 + Shared Packet RAM for multiple Link Layer usage. + 0x1794 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1510 + Shared Packet RAM for multiple Link Layer usage. + 0x1798 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1511 + Shared Packet RAM for multiple Link Layer usage. + 0x179C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1512 + Shared Packet RAM for multiple Link Layer usage. + 0x17A0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1513 + Shared Packet RAM for multiple Link Layer usage. + 0x17A4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1514 + Shared Packet RAM for multiple Link Layer usage. + 0x17A8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1515 + Shared Packet RAM for multiple Link Layer usage. + 0x17AC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1516 + Shared Packet RAM for multiple Link Layer usage. + 0x17B0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1517 + Shared Packet RAM for multiple Link Layer usage. + 0x17B4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1518 + Shared Packet RAM for multiple Link Layer usage. + 0x17B8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1519 + Shared Packet RAM for multiple Link Layer usage. + 0x17BC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1520 + Shared Packet RAM for multiple Link Layer usage. + 0x17C0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1521 + Shared Packet RAM for multiple Link Layer usage. + 0x17C4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1522 + Shared Packet RAM for multiple Link Layer usage. + 0x17C8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1523 + Shared Packet RAM for multiple Link Layer usage. + 0x17CC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1524 + Shared Packet RAM for multiple Link Layer usage. + 0x17D0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1525 + Shared Packet RAM for multiple Link Layer usage. + 0x17D4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1526 + Shared Packet RAM for multiple Link Layer usage. + 0x17D8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1527 + Shared Packet RAM for multiple Link Layer usage. + 0x17DC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1528 + Shared Packet RAM for multiple Link Layer usage. + 0x17E0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1529 + Shared Packet RAM for multiple Link Layer usage. + 0x17E4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1530 + Shared Packet RAM for multiple Link Layer usage. + 0x17E8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1531 + Shared Packet RAM for multiple Link Layer usage. + 0x17EC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1532 + Shared Packet RAM for multiple Link Layer usage. + 0x17F0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1533 + Shared Packet RAM for multiple Link Layer usage. + 0x17F4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1534 + Shared Packet RAM for multiple Link Layer usage. + 0x17F8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1535 + Shared Packet RAM for multiple Link Layer usage. + 0x17FC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1536 + Shared Packet RAM for multiple Link Layer usage. + 0x1800 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1537 + Shared Packet RAM for multiple Link Layer usage. + 0x1804 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1538 + Shared Packet RAM for multiple Link Layer usage. + 0x1808 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1539 + Shared Packet RAM for multiple Link Layer usage. + 0x180C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1540 + Shared Packet RAM for multiple Link Layer usage. + 0x1810 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1541 + Shared Packet RAM for multiple Link Layer usage. + 0x1814 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1542 + Shared Packet RAM for multiple Link Layer usage. + 0x1818 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1543 + Shared Packet RAM for multiple Link Layer usage. + 0x181C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1544 + Shared Packet RAM for multiple Link Layer usage. + 0x1820 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1545 + Shared Packet RAM for multiple Link Layer usage. + 0x1824 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1546 + Shared Packet RAM for multiple Link Layer usage. + 0x1828 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1547 + Shared Packet RAM for multiple Link Layer usage. + 0x182C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1548 + Shared Packet RAM for multiple Link Layer usage. + 0x1830 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1549 + Shared Packet RAM for multiple Link Layer usage. + 0x1834 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1550 + Shared Packet RAM for multiple Link Layer usage. + 0x1838 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1551 + Shared Packet RAM for multiple Link Layer usage. + 0x183C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1552 + Shared Packet RAM for multiple Link Layer usage. + 0x1840 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1553 + Shared Packet RAM for multiple Link Layer usage. + 0x1844 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1554 + Shared Packet RAM for multiple Link Layer usage. + 0x1848 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1555 + Shared Packet RAM for multiple Link Layer usage. + 0x184C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1556 + Shared Packet RAM for multiple Link Layer usage. + 0x1850 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1557 + Shared Packet RAM for multiple Link Layer usage. + 0x1854 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1558 + Shared Packet RAM for multiple Link Layer usage. + 0x1858 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1559 + Shared Packet RAM for multiple Link Layer usage. + 0x185C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1560 + Shared Packet RAM for multiple Link Layer usage. + 0x1860 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1561 + Shared Packet RAM for multiple Link Layer usage. + 0x1864 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1562 + Shared Packet RAM for multiple Link Layer usage. + 0x1868 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1563 + Shared Packet RAM for multiple Link Layer usage. + 0x186C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1564 + Shared Packet RAM for multiple Link Layer usage. + 0x1870 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1565 + Shared Packet RAM for multiple Link Layer usage. + 0x1874 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1566 + Shared Packet RAM for multiple Link Layer usage. + 0x1878 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1567 + Shared Packet RAM for multiple Link Layer usage. + 0x187C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1568 + Shared Packet RAM for multiple Link Layer usage. + 0x1880 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1569 + Shared Packet RAM for multiple Link Layer usage. + 0x1884 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1570 + Shared Packet RAM for multiple Link Layer usage. + 0x1888 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1571 + Shared Packet RAM for multiple Link Layer usage. + 0x188C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1572 + Shared Packet RAM for multiple Link Layer usage. + 0x1890 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1573 + Shared Packet RAM for multiple Link Layer usage. + 0x1894 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1574 + Shared Packet RAM for multiple Link Layer usage. + 0x1898 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1575 + Shared Packet RAM for multiple Link Layer usage. + 0x189C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1576 + Shared Packet RAM for multiple Link Layer usage. + 0x18A0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1577 + Shared Packet RAM for multiple Link Layer usage. + 0x18A4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1578 + Shared Packet RAM for multiple Link Layer usage. + 0x18A8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1579 + Shared Packet RAM for multiple Link Layer usage. + 0x18AC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1580 + Shared Packet RAM for multiple Link Layer usage. + 0x18B0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1581 + Shared Packet RAM for multiple Link Layer usage. + 0x18B4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1582 + Shared Packet RAM for multiple Link Layer usage. + 0x18B8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1583 + Shared Packet RAM for multiple Link Layer usage. + 0x18BC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1584 + Shared Packet RAM for multiple Link Layer usage. + 0x18C0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1585 + Shared Packet RAM for multiple Link Layer usage. + 0x18C4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1586 + Shared Packet RAM for multiple Link Layer usage. + 0x18C8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1587 + Shared Packet RAM for multiple Link Layer usage. + 0x18CC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1588 + Shared Packet RAM for multiple Link Layer usage. + 0x18D0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1589 + Shared Packet RAM for multiple Link Layer usage. + 0x18D4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1590 + Shared Packet RAM for multiple Link Layer usage. + 0x18D8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1591 + Shared Packet RAM for multiple Link Layer usage. + 0x18DC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1592 + Shared Packet RAM for multiple Link Layer usage. + 0x18E0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1593 + Shared Packet RAM for multiple Link Layer usage. + 0x18E4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1594 + Shared Packet RAM for multiple Link Layer usage. + 0x18E8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1595 + Shared Packet RAM for multiple Link Layer usage. + 0x18EC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1596 + Shared Packet RAM for multiple Link Layer usage. + 0x18F0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1597 + Shared Packet RAM for multiple Link Layer usage. + 0x18F4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1598 + Shared Packet RAM for multiple Link Layer usage. + 0x18F8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1599 + Shared Packet RAM for multiple Link Layer usage. + 0x18FC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1600 + Shared Packet RAM for multiple Link Layer usage. + 0x1900 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1601 + Shared Packet RAM for multiple Link Layer usage. + 0x1904 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1602 + Shared Packet RAM for multiple Link Layer usage. + 0x1908 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1603 + Shared Packet RAM for multiple Link Layer usage. + 0x190C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1604 + Shared Packet RAM for multiple Link Layer usage. + 0x1910 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1605 + Shared Packet RAM for multiple Link Layer usage. + 0x1914 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1606 + Shared Packet RAM for multiple Link Layer usage. + 0x1918 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1607 + Shared Packet RAM for multiple Link Layer usage. + 0x191C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1608 + Shared Packet RAM for multiple Link Layer usage. + 0x1920 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1609 + Shared Packet RAM for multiple Link Layer usage. + 0x1924 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1610 + Shared Packet RAM for multiple Link Layer usage. + 0x1928 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1611 + Shared Packet RAM for multiple Link Layer usage. + 0x192C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1612 + Shared Packet RAM for multiple Link Layer usage. + 0x1930 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1613 + Shared Packet RAM for multiple Link Layer usage. + 0x1934 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1614 + Shared Packet RAM for multiple Link Layer usage. + 0x1938 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1615 + Shared Packet RAM for multiple Link Layer usage. + 0x193C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1616 + Shared Packet RAM for multiple Link Layer usage. + 0x1940 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1617 + Shared Packet RAM for multiple Link Layer usage. + 0x1944 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1618 + Shared Packet RAM for multiple Link Layer usage. + 0x1948 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1619 + Shared Packet RAM for multiple Link Layer usage. + 0x194C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1620 + Shared Packet RAM for multiple Link Layer usage. + 0x1950 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1621 + Shared Packet RAM for multiple Link Layer usage. + 0x1954 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1622 + Shared Packet RAM for multiple Link Layer usage. + 0x1958 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1623 + Shared Packet RAM for multiple Link Layer usage. + 0x195C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1624 + Shared Packet RAM for multiple Link Layer usage. + 0x1960 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1625 + Shared Packet RAM for multiple Link Layer usage. + 0x1964 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1626 + Shared Packet RAM for multiple Link Layer usage. + 0x1968 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1627 + Shared Packet RAM for multiple Link Layer usage. + 0x196C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1628 + Shared Packet RAM for multiple Link Layer usage. + 0x1970 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1629 + Shared Packet RAM for multiple Link Layer usage. + 0x1974 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1630 + Shared Packet RAM for multiple Link Layer usage. + 0x1978 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1631 + Shared Packet RAM for multiple Link Layer usage. + 0x197C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1632 + Shared Packet RAM for multiple Link Layer usage. + 0x1980 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1633 + Shared Packet RAM for multiple Link Layer usage. + 0x1984 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1634 + Shared Packet RAM for multiple Link Layer usage. + 0x1988 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1635 + Shared Packet RAM for multiple Link Layer usage. + 0x198C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1636 + Shared Packet RAM for multiple Link Layer usage. + 0x1990 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1637 + Shared Packet RAM for multiple Link Layer usage. + 0x1994 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1638 + Shared Packet RAM for multiple Link Layer usage. + 0x1998 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1639 + Shared Packet RAM for multiple Link Layer usage. + 0x199C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1640 + Shared Packet RAM for multiple Link Layer usage. + 0x19A0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1641 + Shared Packet RAM for multiple Link Layer usage. + 0x19A4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1642 + Shared Packet RAM for multiple Link Layer usage. + 0x19A8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1643 + Shared Packet RAM for multiple Link Layer usage. + 0x19AC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1644 + Shared Packet RAM for multiple Link Layer usage. + 0x19B0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1645 + Shared Packet RAM for multiple Link Layer usage. + 0x19B4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1646 + Shared Packet RAM for multiple Link Layer usage. + 0x19B8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1647 + Shared Packet RAM for multiple Link Layer usage. + 0x19BC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1648 + Shared Packet RAM for multiple Link Layer usage. + 0x19C0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1649 + Shared Packet RAM for multiple Link Layer usage. + 0x19C4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1650 + Shared Packet RAM for multiple Link Layer usage. + 0x19C8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1651 + Shared Packet RAM for multiple Link Layer usage. + 0x19CC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1652 + Shared Packet RAM for multiple Link Layer usage. + 0x19D0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1653 + Shared Packet RAM for multiple Link Layer usage. + 0x19D4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1654 + Shared Packet RAM for multiple Link Layer usage. + 0x19D8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1655 + Shared Packet RAM for multiple Link Layer usage. + 0x19DC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1656 + Shared Packet RAM for multiple Link Layer usage. + 0x19E0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1657 + Shared Packet RAM for multiple Link Layer usage. + 0x19E4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1658 + Shared Packet RAM for multiple Link Layer usage. + 0x19E8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1659 + Shared Packet RAM for multiple Link Layer usage. + 0x19EC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1660 + Shared Packet RAM for multiple Link Layer usage. + 0x19F0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1661 + Shared Packet RAM for multiple Link Layer usage. + 0x19F4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1662 + Shared Packet RAM for multiple Link Layer usage. + 0x19F8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1663 + Shared Packet RAM for multiple Link Layer usage. + 0x19FC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1664 + Shared Packet RAM for multiple Link Layer usage. + 0x1A00 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1665 + Shared Packet RAM for multiple Link Layer usage. + 0x1A04 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1666 + Shared Packet RAM for multiple Link Layer usage. + 0x1A08 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1667 + Shared Packet RAM for multiple Link Layer usage. + 0x1A0C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1668 + Shared Packet RAM for multiple Link Layer usage. + 0x1A10 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1669 + Shared Packet RAM for multiple Link Layer usage. + 0x1A14 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1670 + Shared Packet RAM for multiple Link Layer usage. + 0x1A18 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1671 + Shared Packet RAM for multiple Link Layer usage. + 0x1A1C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1672 + Shared Packet RAM for multiple Link Layer usage. + 0x1A20 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1673 + Shared Packet RAM for multiple Link Layer usage. + 0x1A24 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1674 + Shared Packet RAM for multiple Link Layer usage. + 0x1A28 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1675 + Shared Packet RAM for multiple Link Layer usage. + 0x1A2C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1676 + Shared Packet RAM for multiple Link Layer usage. + 0x1A30 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1677 + Shared Packet RAM for multiple Link Layer usage. + 0x1A34 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1678 + Shared Packet RAM for multiple Link Layer usage. + 0x1A38 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1679 + Shared Packet RAM for multiple Link Layer usage. + 0x1A3C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1680 + Shared Packet RAM for multiple Link Layer usage. + 0x1A40 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1681 + Shared Packet RAM for multiple Link Layer usage. + 0x1A44 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1682 + Shared Packet RAM for multiple Link Layer usage. + 0x1A48 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1683 + Shared Packet RAM for multiple Link Layer usage. + 0x1A4C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1684 + Shared Packet RAM for multiple Link Layer usage. + 0x1A50 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1685 + Shared Packet RAM for multiple Link Layer usage. + 0x1A54 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1686 + Shared Packet RAM for multiple Link Layer usage. + 0x1A58 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1687 + Shared Packet RAM for multiple Link Layer usage. + 0x1A5C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1688 + Shared Packet RAM for multiple Link Layer usage. + 0x1A60 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1689 + Shared Packet RAM for multiple Link Layer usage. + 0x1A64 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1690 + Shared Packet RAM for multiple Link Layer usage. + 0x1A68 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1691 + Shared Packet RAM for multiple Link Layer usage. + 0x1A6C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1692 + Shared Packet RAM for multiple Link Layer usage. + 0x1A70 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1693 + Shared Packet RAM for multiple Link Layer usage. + 0x1A74 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1694 + Shared Packet RAM for multiple Link Layer usage. + 0x1A78 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1695 + Shared Packet RAM for multiple Link Layer usage. + 0x1A7C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1696 + Shared Packet RAM for multiple Link Layer usage. + 0x1A80 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1697 + Shared Packet RAM for multiple Link Layer usage. + 0x1A84 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1698 + Shared Packet RAM for multiple Link Layer usage. + 0x1A88 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1699 + Shared Packet RAM for multiple Link Layer usage. + 0x1A8C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1700 + Shared Packet RAM for multiple Link Layer usage. + 0x1A90 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1701 + Shared Packet RAM for multiple Link Layer usage. + 0x1A94 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1702 + Shared Packet RAM for multiple Link Layer usage. + 0x1A98 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1703 + Shared Packet RAM for multiple Link Layer usage. + 0x1A9C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1704 + Shared Packet RAM for multiple Link Layer usage. + 0x1AA0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1705 + Shared Packet RAM for multiple Link Layer usage. + 0x1AA4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1706 + Shared Packet RAM for multiple Link Layer usage. + 0x1AA8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1707 + Shared Packet RAM for multiple Link Layer usage. + 0x1AAC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1708 + Shared Packet RAM for multiple Link Layer usage. + 0x1AB0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1709 + Shared Packet RAM for multiple Link Layer usage. + 0x1AB4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1710 + Shared Packet RAM for multiple Link Layer usage. + 0x1AB8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1711 + Shared Packet RAM for multiple Link Layer usage. + 0x1ABC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1712 + Shared Packet RAM for multiple Link Layer usage. + 0x1AC0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1713 + Shared Packet RAM for multiple Link Layer usage. + 0x1AC4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1714 + Shared Packet RAM for multiple Link Layer usage. + 0x1AC8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1715 + Shared Packet RAM for multiple Link Layer usage. + 0x1ACC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1716 + Shared Packet RAM for multiple Link Layer usage. + 0x1AD0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1717 + Shared Packet RAM for multiple Link Layer usage. + 0x1AD4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1718 + Shared Packet RAM for multiple Link Layer usage. + 0x1AD8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1719 + Shared Packet RAM for multiple Link Layer usage. + 0x1ADC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1720 + Shared Packet RAM for multiple Link Layer usage. + 0x1AE0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1721 + Shared Packet RAM for multiple Link Layer usage. + 0x1AE4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1722 + Shared Packet RAM for multiple Link Layer usage. + 0x1AE8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1723 + Shared Packet RAM for multiple Link Layer usage. + 0x1AEC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1724 + Shared Packet RAM for multiple Link Layer usage. + 0x1AF0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1725 + Shared Packet RAM for multiple Link Layer usage. + 0x1AF4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1726 + Shared Packet RAM for multiple Link Layer usage. + 0x1AF8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1727 + Shared Packet RAM for multiple Link Layer usage. + 0x1AFC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1728 + Shared Packet RAM for multiple Link Layer usage. + 0x1B00 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1729 + Shared Packet RAM for multiple Link Layer usage. + 0x1B04 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1730 + Shared Packet RAM for multiple Link Layer usage. + 0x1B08 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1731 + Shared Packet RAM for multiple Link Layer usage. + 0x1B0C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1732 + Shared Packet RAM for multiple Link Layer usage. + 0x1B10 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1733 + Shared Packet RAM for multiple Link Layer usage. + 0x1B14 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1734 + Shared Packet RAM for multiple Link Layer usage. + 0x1B18 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1735 + Shared Packet RAM for multiple Link Layer usage. + 0x1B1C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1736 + Shared Packet RAM for multiple Link Layer usage. + 0x1B20 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1737 + Shared Packet RAM for multiple Link Layer usage. + 0x1B24 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1738 + Shared Packet RAM for multiple Link Layer usage. + 0x1B28 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1739 + Shared Packet RAM for multiple Link Layer usage. + 0x1B2C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1740 + Shared Packet RAM for multiple Link Layer usage. + 0x1B30 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1741 + Shared Packet RAM for multiple Link Layer usage. + 0x1B34 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1742 + Shared Packet RAM for multiple Link Layer usage. + 0x1B38 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1743 + Shared Packet RAM for multiple Link Layer usage. + 0x1B3C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1744 + Shared Packet RAM for multiple Link Layer usage. + 0x1B40 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1745 + Shared Packet RAM for multiple Link Layer usage. + 0x1B44 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1746 + Shared Packet RAM for multiple Link Layer usage. + 0x1B48 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1747 + Shared Packet RAM for multiple Link Layer usage. + 0x1B4C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1748 + Shared Packet RAM for multiple Link Layer usage. + 0x1B50 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1749 + Shared Packet RAM for multiple Link Layer usage. + 0x1B54 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1750 + Shared Packet RAM for multiple Link Layer usage. + 0x1B58 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1751 + Shared Packet RAM for multiple Link Layer usage. + 0x1B5C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1752 + Shared Packet RAM for multiple Link Layer usage. + 0x1B60 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1753 + Shared Packet RAM for multiple Link Layer usage. + 0x1B64 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1754 + Shared Packet RAM for multiple Link Layer usage. + 0x1B68 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1755 + Shared Packet RAM for multiple Link Layer usage. + 0x1B6C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1756 + Shared Packet RAM for multiple Link Layer usage. + 0x1B70 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1757 + Shared Packet RAM for multiple Link Layer usage. + 0x1B74 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1758 + Shared Packet RAM for multiple Link Layer usage. + 0x1B78 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1759 + Shared Packet RAM for multiple Link Layer usage. + 0x1B7C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1760 + Shared Packet RAM for multiple Link Layer usage. + 0x1B80 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1761 + Shared Packet RAM for multiple Link Layer usage. + 0x1B84 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1762 + Shared Packet RAM for multiple Link Layer usage. + 0x1B88 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1763 + Shared Packet RAM for multiple Link Layer usage. + 0x1B8C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1764 + Shared Packet RAM for multiple Link Layer usage. + 0x1B90 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1765 + Shared Packet RAM for multiple Link Layer usage. + 0x1B94 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1766 + Shared Packet RAM for multiple Link Layer usage. + 0x1B98 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1767 + Shared Packet RAM for multiple Link Layer usage. + 0x1B9C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1768 + Shared Packet RAM for multiple Link Layer usage. + 0x1BA0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1769 + Shared Packet RAM for multiple Link Layer usage. + 0x1BA4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1770 + Shared Packet RAM for multiple Link Layer usage. + 0x1BA8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1771 + Shared Packet RAM for multiple Link Layer usage. + 0x1BAC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1772 + Shared Packet RAM for multiple Link Layer usage. + 0x1BB0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1773 + Shared Packet RAM for multiple Link Layer usage. + 0x1BB4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1774 + Shared Packet RAM for multiple Link Layer usage. + 0x1BB8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1775 + Shared Packet RAM for multiple Link Layer usage. + 0x1BBC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1776 + Shared Packet RAM for multiple Link Layer usage. + 0x1BC0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1777 + Shared Packet RAM for multiple Link Layer usage. + 0x1BC4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1778 + Shared Packet RAM for multiple Link Layer usage. + 0x1BC8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1779 + Shared Packet RAM for multiple Link Layer usage. + 0x1BCC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1780 + Shared Packet RAM for multiple Link Layer usage. + 0x1BD0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1781 + Shared Packet RAM for multiple Link Layer usage. + 0x1BD4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1782 + Shared Packet RAM for multiple Link Layer usage. + 0x1BD8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1783 + Shared Packet RAM for multiple Link Layer usage. + 0x1BDC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1784 + Shared Packet RAM for multiple Link Layer usage. + 0x1BE0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1785 + Shared Packet RAM for multiple Link Layer usage. + 0x1BE4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1786 + Shared Packet RAM for multiple Link Layer usage. + 0x1BE8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1787 + Shared Packet RAM for multiple Link Layer usage. + 0x1BEC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1788 + Shared Packet RAM for multiple Link Layer usage. + 0x1BF0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1789 + Shared Packet RAM for multiple Link Layer usage. + 0x1BF4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1790 + Shared Packet RAM for multiple Link Layer usage. + 0x1BF8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1791 + Shared Packet RAM for multiple Link Layer usage. + 0x1BFC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1792 + Shared Packet RAM for multiple Link Layer usage. + 0x1C00 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1793 + Shared Packet RAM for multiple Link Layer usage. + 0x1C04 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1794 + Shared Packet RAM for multiple Link Layer usage. + 0x1C08 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1795 + Shared Packet RAM for multiple Link Layer usage. + 0x1C0C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1796 + Shared Packet RAM for multiple Link Layer usage. + 0x1C10 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1797 + Shared Packet RAM for multiple Link Layer usage. + 0x1C14 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1798 + Shared Packet RAM for multiple Link Layer usage. + 0x1C18 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1799 + Shared Packet RAM for multiple Link Layer usage. + 0x1C1C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1800 + Shared Packet RAM for multiple Link Layer usage. + 0x1C20 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1801 + Shared Packet RAM for multiple Link Layer usage. + 0x1C24 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1802 + Shared Packet RAM for multiple Link Layer usage. + 0x1C28 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1803 + Shared Packet RAM for multiple Link Layer usage. + 0x1C2C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1804 + Shared Packet RAM for multiple Link Layer usage. + 0x1C30 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1805 + Shared Packet RAM for multiple Link Layer usage. + 0x1C34 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1806 + Shared Packet RAM for multiple Link Layer usage. + 0x1C38 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1807 + Shared Packet RAM for multiple Link Layer usage. + 0x1C3C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1808 + Shared Packet RAM for multiple Link Layer usage. + 0x1C40 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1809 + Shared Packet RAM for multiple Link Layer usage. + 0x1C44 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1810 + Shared Packet RAM for multiple Link Layer usage. + 0x1C48 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1811 + Shared Packet RAM for multiple Link Layer usage. + 0x1C4C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1812 + Shared Packet RAM for multiple Link Layer usage. + 0x1C50 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1813 + Shared Packet RAM for multiple Link Layer usage. + 0x1C54 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1814 + Shared Packet RAM for multiple Link Layer usage. + 0x1C58 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1815 + Shared Packet RAM for multiple Link Layer usage. + 0x1C5C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1816 + Shared Packet RAM for multiple Link Layer usage. + 0x1C60 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1817 + Shared Packet RAM for multiple Link Layer usage. + 0x1C64 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1818 + Shared Packet RAM for multiple Link Layer usage. + 0x1C68 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1819 + Shared Packet RAM for multiple Link Layer usage. + 0x1C6C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1820 + Shared Packet RAM for multiple Link Layer usage. + 0x1C70 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1821 + Shared Packet RAM for multiple Link Layer usage. + 0x1C74 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1822 + Shared Packet RAM for multiple Link Layer usage. + 0x1C78 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1823 + Shared Packet RAM for multiple Link Layer usage. + 0x1C7C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1824 + Shared Packet RAM for multiple Link Layer usage. + 0x1C80 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1825 + Shared Packet RAM for multiple Link Layer usage. + 0x1C84 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1826 + Shared Packet RAM for multiple Link Layer usage. + 0x1C88 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1827 + Shared Packet RAM for multiple Link Layer usage. + 0x1C8C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1828 + Shared Packet RAM for multiple Link Layer usage. + 0x1C90 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1829 + Shared Packet RAM for multiple Link Layer usage. + 0x1C94 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1830 + Shared Packet RAM for multiple Link Layer usage. + 0x1C98 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1831 + Shared Packet RAM for multiple Link Layer usage. + 0x1C9C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1832 + Shared Packet RAM for multiple Link Layer usage. + 0x1CA0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1833 + Shared Packet RAM for multiple Link Layer usage. + 0x1CA4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1834 + Shared Packet RAM for multiple Link Layer usage. + 0x1CA8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1835 + Shared Packet RAM for multiple Link Layer usage. + 0x1CAC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1836 + Shared Packet RAM for multiple Link Layer usage. + 0x1CB0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1837 + Shared Packet RAM for multiple Link Layer usage. + 0x1CB4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1838 + Shared Packet RAM for multiple Link Layer usage. + 0x1CB8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1839 + Shared Packet RAM for multiple Link Layer usage. + 0x1CBC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1840 + Shared Packet RAM for multiple Link Layer usage. + 0x1CC0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1841 + Shared Packet RAM for multiple Link Layer usage. + 0x1CC4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1842 + Shared Packet RAM for multiple Link Layer usage. + 0x1CC8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1843 + Shared Packet RAM for multiple Link Layer usage. + 0x1CCC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1844 + Shared Packet RAM for multiple Link Layer usage. + 0x1CD0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1845 + Shared Packet RAM for multiple Link Layer usage. + 0x1CD4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1846 + Shared Packet RAM for multiple Link Layer usage. + 0x1CD8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1847 + Shared Packet RAM for multiple Link Layer usage. + 0x1CDC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1848 + Shared Packet RAM for multiple Link Layer usage. + 0x1CE0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1849 + Shared Packet RAM for multiple Link Layer usage. + 0x1CE4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1850 + Shared Packet RAM for multiple Link Layer usage. + 0x1CE8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1851 + Shared Packet RAM for multiple Link Layer usage. + 0x1CEC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1852 + Shared Packet RAM for multiple Link Layer usage. + 0x1CF0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1853 + Shared Packet RAM for multiple Link Layer usage. + 0x1CF4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1854 + Shared Packet RAM for multiple Link Layer usage. + 0x1CF8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1855 + Shared Packet RAM for multiple Link Layer usage. + 0x1CFC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1856 + Shared Packet RAM for multiple Link Layer usage. + 0x1D00 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1857 + Shared Packet RAM for multiple Link Layer usage. + 0x1D04 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1858 + Shared Packet RAM for multiple Link Layer usage. + 0x1D08 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1859 + Shared Packet RAM for multiple Link Layer usage. + 0x1D0C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1860 + Shared Packet RAM for multiple Link Layer usage. + 0x1D10 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1861 + Shared Packet RAM for multiple Link Layer usage. + 0x1D14 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1862 + Shared Packet RAM for multiple Link Layer usage. + 0x1D18 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1863 + Shared Packet RAM for multiple Link Layer usage. + 0x1D1C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1864 + Shared Packet RAM for multiple Link Layer usage. + 0x1D20 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1865 + Shared Packet RAM for multiple Link Layer usage. + 0x1D24 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1866 + Shared Packet RAM for multiple Link Layer usage. + 0x1D28 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1867 + Shared Packet RAM for multiple Link Layer usage. + 0x1D2C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1868 + Shared Packet RAM for multiple Link Layer usage. + 0x1D30 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1869 + Shared Packet RAM for multiple Link Layer usage. + 0x1D34 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1870 + Shared Packet RAM for multiple Link Layer usage. + 0x1D38 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1871 + Shared Packet RAM for multiple Link Layer usage. + 0x1D3C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1872 + Shared Packet RAM for multiple Link Layer usage. + 0x1D40 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1873 + Shared Packet RAM for multiple Link Layer usage. + 0x1D44 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1874 + Shared Packet RAM for multiple Link Layer usage. + 0x1D48 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1875 + Shared Packet RAM for multiple Link Layer usage. + 0x1D4C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1876 + Shared Packet RAM for multiple Link Layer usage. + 0x1D50 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1877 + Shared Packet RAM for multiple Link Layer usage. + 0x1D54 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1878 + Shared Packet RAM for multiple Link Layer usage. + 0x1D58 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1879 + Shared Packet RAM for multiple Link Layer usage. + 0x1D5C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1880 + Shared Packet RAM for multiple Link Layer usage. + 0x1D60 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1881 + Shared Packet RAM for multiple Link Layer usage. + 0x1D64 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1882 + Shared Packet RAM for multiple Link Layer usage. + 0x1D68 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1883 + Shared Packet RAM for multiple Link Layer usage. + 0x1D6C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1884 + Shared Packet RAM for multiple Link Layer usage. + 0x1D70 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1885 + Shared Packet RAM for multiple Link Layer usage. + 0x1D74 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1886 + Shared Packet RAM for multiple Link Layer usage. + 0x1D78 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1887 + Shared Packet RAM for multiple Link Layer usage. + 0x1D7C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1888 + Shared Packet RAM for multiple Link Layer usage. + 0x1D80 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1889 + Shared Packet RAM for multiple Link Layer usage. + 0x1D84 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1890 + Shared Packet RAM for multiple Link Layer usage. + 0x1D88 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1891 + Shared Packet RAM for multiple Link Layer usage. + 0x1D8C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1892 + Shared Packet RAM for multiple Link Layer usage. + 0x1D90 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1893 + Shared Packet RAM for multiple Link Layer usage. + 0x1D94 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1894 + Shared Packet RAM for multiple Link Layer usage. + 0x1D98 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1895 + Shared Packet RAM for multiple Link Layer usage. + 0x1D9C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1896 + Shared Packet RAM for multiple Link Layer usage. + 0x1DA0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1897 + Shared Packet RAM for multiple Link Layer usage. + 0x1DA4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1898 + Shared Packet RAM for multiple Link Layer usage. + 0x1DA8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1899 + Shared Packet RAM for multiple Link Layer usage. + 0x1DAC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1900 + Shared Packet RAM for multiple Link Layer usage. + 0x1DB0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1901 + Shared Packet RAM for multiple Link Layer usage. + 0x1DB4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1902 + Shared Packet RAM for multiple Link Layer usage. + 0x1DB8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1903 + Shared Packet RAM for multiple Link Layer usage. + 0x1DBC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1904 + Shared Packet RAM for multiple Link Layer usage. + 0x1DC0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1905 + Shared Packet RAM for multiple Link Layer usage. + 0x1DC4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1906 + Shared Packet RAM for multiple Link Layer usage. + 0x1DC8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1907 + Shared Packet RAM for multiple Link Layer usage. + 0x1DCC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1908 + Shared Packet RAM for multiple Link Layer usage. + 0x1DD0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1909 + Shared Packet RAM for multiple Link Layer usage. + 0x1DD4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1910 + Shared Packet RAM for multiple Link Layer usage. + 0x1DD8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1911 + Shared Packet RAM for multiple Link Layer usage. + 0x1DDC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1912 + Shared Packet RAM for multiple Link Layer usage. + 0x1DE0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1913 + Shared Packet RAM for multiple Link Layer usage. + 0x1DE4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1914 + Shared Packet RAM for multiple Link Layer usage. + 0x1DE8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1915 + Shared Packet RAM for multiple Link Layer usage. + 0x1DEC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1916 + Shared Packet RAM for multiple Link Layer usage. + 0x1DF0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1917 + Shared Packet RAM for multiple Link Layer usage. + 0x1DF4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1918 + Shared Packet RAM for multiple Link Layer usage. + 0x1DF8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1919 + Shared Packet RAM for multiple Link Layer usage. + 0x1DFC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1920 + Shared Packet RAM for multiple Link Layer usage. + 0x1E00 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1921 + Shared Packet RAM for multiple Link Layer usage. + 0x1E04 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1922 + Shared Packet RAM for multiple Link Layer usage. + 0x1E08 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1923 + Shared Packet RAM for multiple Link Layer usage. + 0x1E0C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1924 + Shared Packet RAM for multiple Link Layer usage. + 0x1E10 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1925 + Shared Packet RAM for multiple Link Layer usage. + 0x1E14 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1926 + Shared Packet RAM for multiple Link Layer usage. + 0x1E18 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1927 + Shared Packet RAM for multiple Link Layer usage. + 0x1E1C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1928 + Shared Packet RAM for multiple Link Layer usage. + 0x1E20 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1929 + Shared Packet RAM for multiple Link Layer usage. + 0x1E24 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1930 + Shared Packet RAM for multiple Link Layer usage. + 0x1E28 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1931 + Shared Packet RAM for multiple Link Layer usage. + 0x1E2C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1932 + Shared Packet RAM for multiple Link Layer usage. + 0x1E30 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1933 + Shared Packet RAM for multiple Link Layer usage. + 0x1E34 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1934 + Shared Packet RAM for multiple Link Layer usage. + 0x1E38 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1935 + Shared Packet RAM for multiple Link Layer usage. + 0x1E3C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1936 + Shared Packet RAM for multiple Link Layer usage. + 0x1E40 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1937 + Shared Packet RAM for multiple Link Layer usage. + 0x1E44 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1938 + Shared Packet RAM for multiple Link Layer usage. + 0x1E48 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1939 + Shared Packet RAM for multiple Link Layer usage. + 0x1E4C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1940 + Shared Packet RAM for multiple Link Layer usage. + 0x1E50 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1941 + Shared Packet RAM for multiple Link Layer usage. + 0x1E54 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1942 + Shared Packet RAM for multiple Link Layer usage. + 0x1E58 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1943 + Shared Packet RAM for multiple Link Layer usage. + 0x1E5C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1944 + Shared Packet RAM for multiple Link Layer usage. + 0x1E60 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1945 + Shared Packet RAM for multiple Link Layer usage. + 0x1E64 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1946 + Shared Packet RAM for multiple Link Layer usage. + 0x1E68 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1947 + Shared Packet RAM for multiple Link Layer usage. + 0x1E6C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1948 + Shared Packet RAM for multiple Link Layer usage. + 0x1E70 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1949 + Shared Packet RAM for multiple Link Layer usage. + 0x1E74 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1950 + Shared Packet RAM for multiple Link Layer usage. + 0x1E78 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1951 + Shared Packet RAM for multiple Link Layer usage. + 0x1E7C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1952 + Shared Packet RAM for multiple Link Layer usage. + 0x1E80 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1953 + Shared Packet RAM for multiple Link Layer usage. + 0x1E84 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1954 + Shared Packet RAM for multiple Link Layer usage. + 0x1E88 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1955 + Shared Packet RAM for multiple Link Layer usage. + 0x1E8C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1956 + Shared Packet RAM for multiple Link Layer usage. + 0x1E90 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1957 + Shared Packet RAM for multiple Link Layer usage. + 0x1E94 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1958 + Shared Packet RAM for multiple Link Layer usage. + 0x1E98 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1959 + Shared Packet RAM for multiple Link Layer usage. + 0x1E9C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1960 + Shared Packet RAM for multiple Link Layer usage. + 0x1EA0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1961 + Shared Packet RAM for multiple Link Layer usage. + 0x1EA4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1962 + Shared Packet RAM for multiple Link Layer usage. + 0x1EA8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1963 + Shared Packet RAM for multiple Link Layer usage. + 0x1EAC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1964 + Shared Packet RAM for multiple Link Layer usage. + 0x1EB0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1965 + Shared Packet RAM for multiple Link Layer usage. + 0x1EB4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1966 + Shared Packet RAM for multiple Link Layer usage. + 0x1EB8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1967 + Shared Packet RAM for multiple Link Layer usage. + 0x1EBC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1968 + Shared Packet RAM for multiple Link Layer usage. + 0x1EC0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1969 + Shared Packet RAM for multiple Link Layer usage. + 0x1EC4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1970 + Shared Packet RAM for multiple Link Layer usage. + 0x1EC8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1971 + Shared Packet RAM for multiple Link Layer usage. + 0x1ECC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1972 + Shared Packet RAM for multiple Link Layer usage. + 0x1ED0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1973 + Shared Packet RAM for multiple Link Layer usage. + 0x1ED4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1974 + Shared Packet RAM for multiple Link Layer usage. + 0x1ED8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1975 + Shared Packet RAM for multiple Link Layer usage. + 0x1EDC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1976 + Shared Packet RAM for multiple Link Layer usage. + 0x1EE0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1977 + Shared Packet RAM for multiple Link Layer usage. + 0x1EE4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1978 + Shared Packet RAM for multiple Link Layer usage. + 0x1EE8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1979 + Shared Packet RAM for multiple Link Layer usage. + 0x1EEC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1980 + Shared Packet RAM for multiple Link Layer usage. + 0x1EF0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1981 + Shared Packet RAM for multiple Link Layer usage. + 0x1EF4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1982 + Shared Packet RAM for multiple Link Layer usage. + 0x1EF8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1983 + Shared Packet RAM for multiple Link Layer usage. + 0x1EFC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1984 + Shared Packet RAM for multiple Link Layer usage. + 0x1F00 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1985 + Shared Packet RAM for multiple Link Layer usage. + 0x1F04 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1986 + Shared Packet RAM for multiple Link Layer usage. + 0x1F08 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1987 + Shared Packet RAM for multiple Link Layer usage. + 0x1F0C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1988 + Shared Packet RAM for multiple Link Layer usage. + 0x1F10 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1989 + Shared Packet RAM for multiple Link Layer usage. + 0x1F14 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1990 + Shared Packet RAM for multiple Link Layer usage. + 0x1F18 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1991 + Shared Packet RAM for multiple Link Layer usage. + 0x1F1C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1992 + Shared Packet RAM for multiple Link Layer usage. + 0x1F20 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1993 + Shared Packet RAM for multiple Link Layer usage. + 0x1F24 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1994 + Shared Packet RAM for multiple Link Layer usage. + 0x1F28 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1995 + Shared Packet RAM for multiple Link Layer usage. + 0x1F2C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1996 + Shared Packet RAM for multiple Link Layer usage. + 0x1F30 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1997 + Shared Packet RAM for multiple Link Layer usage. + 0x1F34 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1998 + Shared Packet RAM for multiple Link Layer usage. + 0x1F38 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1999 + Shared Packet RAM for multiple Link Layer usage. + 0x1F3C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2000 + Shared Packet RAM for multiple Link Layer usage. + 0x1F40 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2001 + Shared Packet RAM for multiple Link Layer usage. + 0x1F44 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2002 + Shared Packet RAM for multiple Link Layer usage. + 0x1F48 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2003 + Shared Packet RAM for multiple Link Layer usage. + 0x1F4C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2004 + Shared Packet RAM for multiple Link Layer usage. + 0x1F50 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2005 + Shared Packet RAM for multiple Link Layer usage. + 0x1F54 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2006 + Shared Packet RAM for multiple Link Layer usage. + 0x1F58 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2007 + Shared Packet RAM for multiple Link Layer usage. + 0x1F5C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2008 + Shared Packet RAM for multiple Link Layer usage. + 0x1F60 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2009 + Shared Packet RAM for multiple Link Layer usage. + 0x1F64 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2010 + Shared Packet RAM for multiple Link Layer usage. + 0x1F68 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2011 + Shared Packet RAM for multiple Link Layer usage. + 0x1F6C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2012 + Shared Packet RAM for multiple Link Layer usage. + 0x1F70 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2013 + Shared Packet RAM for multiple Link Layer usage. + 0x1F74 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2014 + Shared Packet RAM for multiple Link Layer usage. + 0x1F78 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2015 + Shared Packet RAM for multiple Link Layer usage. + 0x1F7C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2016 + Shared Packet RAM for multiple Link Layer usage. + 0x1F80 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2017 + Shared Packet RAM for multiple Link Layer usage. + 0x1F84 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2018 + Shared Packet RAM for multiple Link Layer usage. + 0x1F88 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2019 + Shared Packet RAM for multiple Link Layer usage. + 0x1F8C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2020 + Shared Packet RAM for multiple Link Layer usage. + 0x1F90 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2021 + Shared Packet RAM for multiple Link Layer usage. + 0x1F94 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2022 + Shared Packet RAM for multiple Link Layer usage. + 0x1F98 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2023 + Shared Packet RAM for multiple Link Layer usage. + 0x1F9C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2024 + Shared Packet RAM for multiple Link Layer usage. + 0x1FA0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2025 + Shared Packet RAM for multiple Link Layer usage. + 0x1FA4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2026 + Shared Packet RAM for multiple Link Layer usage. + 0x1FA8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2027 + Shared Packet RAM for multiple Link Layer usage. + 0x1FAC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2028 + Shared Packet RAM for multiple Link Layer usage. + 0x1FB0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2029 + Shared Packet RAM for multiple Link Layer usage. + 0x1FB4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2030 + Shared Packet RAM for multiple Link Layer usage. + 0x1FB8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2031 + Shared Packet RAM for multiple Link Layer usage. + 0x1FBC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2032 + Shared Packet RAM for multiple Link Layer usage. + 0x1FC0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2033 + Shared Packet RAM for multiple Link Layer usage. + 0x1FC4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2034 + Shared Packet RAM for multiple Link Layer usage. + 0x1FC8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2035 + Shared Packet RAM for multiple Link Layer usage. + 0x1FCC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2036 + Shared Packet RAM for multiple Link Layer usage. + 0x1FD0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2037 + Shared Packet RAM for multiple Link Layer usage. + 0x1FD4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2038 + Shared Packet RAM for multiple Link Layer usage. + 0x1FD8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2039 + Shared Packet RAM for multiple Link Layer usage. + 0x1FDC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2040 + Shared Packet RAM for multiple Link Layer usage. + 0x1FE0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2041 + Shared Packet RAM for multiple Link Layer usage. + 0x1FE4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2042 + Shared Packet RAM for multiple Link Layer usage. + 0x1FE8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2043 + Shared Packet RAM for multiple Link Layer usage. + 0x1FEC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2044 + Shared Packet RAM for multiple Link Layer usage. + 0x1FF0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2045 + Shared Packet RAM for multiple Link Layer usage. + 0x1FF4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2046 + Shared Packet RAM for multiple Link Layer usage. + 0x1FF8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2047 + Shared Packet RAM for multiple Link Layer usage. + 0x1FFC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2048 + Shared Packet RAM for multiple Link Layer usage. + 0x2000 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2049 + Shared Packet RAM for multiple Link Layer usage. + 0x2004 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2050 + Shared Packet RAM for multiple Link Layer usage. + 0x2008 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2051 + Shared Packet RAM for multiple Link Layer usage. + 0x200C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2052 + Shared Packet RAM for multiple Link Layer usage. + 0x2010 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2053 + Shared Packet RAM for multiple Link Layer usage. + 0x2014 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2054 + Shared Packet RAM for multiple Link Layer usage. + 0x2018 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2055 + Shared Packet RAM for multiple Link Layer usage. + 0x201C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2056 + Shared Packet RAM for multiple Link Layer usage. + 0x2020 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2057 + Shared Packet RAM for multiple Link Layer usage. + 0x2024 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2058 + Shared Packet RAM for multiple Link Layer usage. + 0x2028 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2059 + Shared Packet RAM for multiple Link Layer usage. + 0x202C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2060 + Shared Packet RAM for multiple Link Layer usage. + 0x2030 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2061 + Shared Packet RAM for multiple Link Layer usage. + 0x2034 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2062 + Shared Packet RAM for multiple Link Layer usage. + 0x2038 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2063 + Shared Packet RAM for multiple Link Layer usage. + 0x203C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2064 + Shared Packet RAM for multiple Link Layer usage. + 0x2040 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2065 + Shared Packet RAM for multiple Link Layer usage. + 0x2044 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2066 + Shared Packet RAM for multiple Link Layer usage. + 0x2048 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2067 + Shared Packet RAM for multiple Link Layer usage. + 0x204C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2068 + Shared Packet RAM for multiple Link Layer usage. + 0x2050 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2069 + Shared Packet RAM for multiple Link Layer usage. + 0x2054 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2070 + Shared Packet RAM for multiple Link Layer usage. + 0x2058 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2071 + Shared Packet RAM for multiple Link Layer usage. + 0x205C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2072 + Shared Packet RAM for multiple Link Layer usage. + 0x2060 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2073 + Shared Packet RAM for multiple Link Layer usage. + 0x2064 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2074 + Shared Packet RAM for multiple Link Layer usage. + 0x2068 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2075 + Shared Packet RAM for multiple Link Layer usage. + 0x206C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2076 + Shared Packet RAM for multiple Link Layer usage. + 0x2070 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2077 + Shared Packet RAM for multiple Link Layer usage. + 0x2074 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2078 + Shared Packet RAM for multiple Link Layer usage. + 0x2078 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2079 + Shared Packet RAM for multiple Link Layer usage. + 0x207C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2080 + Shared Packet RAM for multiple Link Layer usage. + 0x2080 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2081 + Shared Packet RAM for multiple Link Layer usage. + 0x2084 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2082 + Shared Packet RAM for multiple Link Layer usage. + 0x2088 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2083 + Shared Packet RAM for multiple Link Layer usage. + 0x208C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2084 + Shared Packet RAM for multiple Link Layer usage. + 0x2090 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2085 + Shared Packet RAM for multiple Link Layer usage. + 0x2094 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2086 + Shared Packet RAM for multiple Link Layer usage. + 0x2098 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2087 + Shared Packet RAM for multiple Link Layer usage. + 0x209C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2088 + Shared Packet RAM for multiple Link Layer usage. + 0x20A0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2089 + Shared Packet RAM for multiple Link Layer usage. + 0x20A4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2090 + Shared Packet RAM for multiple Link Layer usage. + 0x20A8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2091 + Shared Packet RAM for multiple Link Layer usage. + 0x20AC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2092 + Shared Packet RAM for multiple Link Layer usage. + 0x20B0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2093 + Shared Packet RAM for multiple Link Layer usage. + 0x20B4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2094 + Shared Packet RAM for multiple Link Layer usage. + 0x20B8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2095 + Shared Packet RAM for multiple Link Layer usage. + 0x20BC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2096 + Shared Packet RAM for multiple Link Layer usage. + 0x20C0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2097 + Shared Packet RAM for multiple Link Layer usage. + 0x20C4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2098 + Shared Packet RAM for multiple Link Layer usage. + 0x20C8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2099 + Shared Packet RAM for multiple Link Layer usage. + 0x20CC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2100 + Shared Packet RAM for multiple Link Layer usage. + 0x20D0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2101 + Shared Packet RAM for multiple Link Layer usage. + 0x20D4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2102 + Shared Packet RAM for multiple Link Layer usage. + 0x20D8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2103 + Shared Packet RAM for multiple Link Layer usage. + 0x20DC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2104 + Shared Packet RAM for multiple Link Layer usage. + 0x20E0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2105 + Shared Packet RAM for multiple Link Layer usage. + 0x20E4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2106 + Shared Packet RAM for multiple Link Layer usage. + 0x20E8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2107 + Shared Packet RAM for multiple Link Layer usage. + 0x20EC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2108 + Shared Packet RAM for multiple Link Layer usage. + 0x20F0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2109 + Shared Packet RAM for multiple Link Layer usage. + 0x20F4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2110 + Shared Packet RAM for multiple Link Layer usage. + 0x20F8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2111 + Shared Packet RAM for multiple Link Layer usage. + 0x20FC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2112 + Shared Packet RAM for multiple Link Layer usage. + 0x2100 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2113 + Shared Packet RAM for multiple Link Layer usage. + 0x2104 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2114 + Shared Packet RAM for multiple Link Layer usage. + 0x2108 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2115 + Shared Packet RAM for multiple Link Layer usage. + 0x210C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2116 + Shared Packet RAM for multiple Link Layer usage. + 0x2110 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2117 + Shared Packet RAM for multiple Link Layer usage. + 0x2114 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2118 + Shared Packet RAM for multiple Link Layer usage. + 0x2118 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2119 + Shared Packet RAM for multiple Link Layer usage. + 0x211C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2120 + Shared Packet RAM for multiple Link Layer usage. + 0x2120 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2121 + Shared Packet RAM for multiple Link Layer usage. + 0x2124 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2122 + Shared Packet RAM for multiple Link Layer usage. + 0x2128 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2123 + Shared Packet RAM for multiple Link Layer usage. + 0x212C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2124 + Shared Packet RAM for multiple Link Layer usage. + 0x2130 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2125 + Shared Packet RAM for multiple Link Layer usage. + 0x2134 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2126 + Shared Packet RAM for multiple Link Layer usage. + 0x2138 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2127 + Shared Packet RAM for multiple Link Layer usage. + 0x213C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2128 + Shared Packet RAM for multiple Link Layer usage. + 0x2140 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2129 + Shared Packet RAM for multiple Link Layer usage. + 0x2144 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2130 + Shared Packet RAM for multiple Link Layer usage. + 0x2148 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2131 + Shared Packet RAM for multiple Link Layer usage. + 0x214C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2132 + Shared Packet RAM for multiple Link Layer usage. + 0x2150 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2133 + Shared Packet RAM for multiple Link Layer usage. + 0x2154 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2134 + Shared Packet RAM for multiple Link Layer usage. + 0x2158 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2135 + Shared Packet RAM for multiple Link Layer usage. + 0x215C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2136 + Shared Packet RAM for multiple Link Layer usage. + 0x2160 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2137 + Shared Packet RAM for multiple Link Layer usage. + 0x2164 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2138 + Shared Packet RAM for multiple Link Layer usage. + 0x2168 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2139 + Shared Packet RAM for multiple Link Layer usage. + 0x216C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2140 + Shared Packet RAM for multiple Link Layer usage. + 0x2170 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2141 + Shared Packet RAM for multiple Link Layer usage. + 0x2174 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2142 + Shared Packet RAM for multiple Link Layer usage. + 0x2178 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2143 + Shared Packet RAM for multiple Link Layer usage. + 0x217C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2144 + Shared Packet RAM for multiple Link Layer usage. + 0x2180 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2145 + Shared Packet RAM for multiple Link Layer usage. + 0x2184 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2146 + Shared Packet RAM for multiple Link Layer usage. + 0x2188 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2147 + Shared Packet RAM for multiple Link Layer usage. + 0x218C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2148 + Shared Packet RAM for multiple Link Layer usage. + 0x2190 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2149 + Shared Packet RAM for multiple Link Layer usage. + 0x2194 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2150 + Shared Packet RAM for multiple Link Layer usage. + 0x2198 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2151 + Shared Packet RAM for multiple Link Layer usage. + 0x219C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2152 + Shared Packet RAM for multiple Link Layer usage. + 0x21A0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2153 + Shared Packet RAM for multiple Link Layer usage. + 0x21A4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2154 + Shared Packet RAM for multiple Link Layer usage. + 0x21A8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2155 + Shared Packet RAM for multiple Link Layer usage. + 0x21AC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2156 + Shared Packet RAM for multiple Link Layer usage. + 0x21B0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2157 + Shared Packet RAM for multiple Link Layer usage. + 0x21B4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2158 + Shared Packet RAM for multiple Link Layer usage. + 0x21B8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2159 + Shared Packet RAM for multiple Link Layer usage. + 0x21BC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2160 + Shared Packet RAM for multiple Link Layer usage. + 0x21C0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2161 + Shared Packet RAM for multiple Link Layer usage. + 0x21C4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2162 + Shared Packet RAM for multiple Link Layer usage. + 0x21C8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2163 + Shared Packet RAM for multiple Link Layer usage. + 0x21CC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2164 + Shared Packet RAM for multiple Link Layer usage. + 0x21D0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2165 + Shared Packet RAM for multiple Link Layer usage. + 0x21D4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2166 + Shared Packet RAM for multiple Link Layer usage. + 0x21D8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2167 + Shared Packet RAM for multiple Link Layer usage. + 0x21DC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2168 + Shared Packet RAM for multiple Link Layer usage. + 0x21E0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2169 + Shared Packet RAM for multiple Link Layer usage. + 0x21E4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2170 + Shared Packet RAM for multiple Link Layer usage. + 0x21E8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2171 + Shared Packet RAM for multiple Link Layer usage. + 0x21EC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2172 + Shared Packet RAM for multiple Link Layer usage. + 0x21F0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2173 + Shared Packet RAM for multiple Link Layer usage. + 0x21F4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2174 + Shared Packet RAM for multiple Link Layer usage. + 0x21F8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2175 + Shared Packet RAM for multiple Link Layer usage. + 0x21FC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2176 + Shared Packet RAM for multiple Link Layer usage. + 0x2200 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2177 + Shared Packet RAM for multiple Link Layer usage. + 0x2204 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2178 + Shared Packet RAM for multiple Link Layer usage. + 0x2208 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2179 + Shared Packet RAM for multiple Link Layer usage. + 0x220C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2180 + Shared Packet RAM for multiple Link Layer usage. + 0x2210 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2181 + Shared Packet RAM for multiple Link Layer usage. + 0x2214 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2182 + Shared Packet RAM for multiple Link Layer usage. + 0x2218 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2183 + Shared Packet RAM for multiple Link Layer usage. + 0x221C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2184 + Shared Packet RAM for multiple Link Layer usage. + 0x2220 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2185 + Shared Packet RAM for multiple Link Layer usage. + 0x2224 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2186 + Shared Packet RAM for multiple Link Layer usage. + 0x2228 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2187 + Shared Packet RAM for multiple Link Layer usage. + 0x222C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2188 + Shared Packet RAM for multiple Link Layer usage. + 0x2230 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2189 + Shared Packet RAM for multiple Link Layer usage. + 0x2234 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2190 + Shared Packet RAM for multiple Link Layer usage. + 0x2238 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2191 + Shared Packet RAM for multiple Link Layer usage. + 0x223C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2192 + Shared Packet RAM for multiple Link Layer usage. + 0x2240 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2193 + Shared Packet RAM for multiple Link Layer usage. + 0x2244 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2194 + Shared Packet RAM for multiple Link Layer usage. + 0x2248 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2195 + Shared Packet RAM for multiple Link Layer usage. + 0x224C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2196 + Shared Packet RAM for multiple Link Layer usage. + 0x2250 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2197 + Shared Packet RAM for multiple Link Layer usage. + 0x2254 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2198 + Shared Packet RAM for multiple Link Layer usage. + 0x2258 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2199 + Shared Packet RAM for multiple Link Layer usage. + 0x225C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2200 + Shared Packet RAM for multiple Link Layer usage. + 0x2260 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2201 + Shared Packet RAM for multiple Link Layer usage. + 0x2264 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2202 + Shared Packet RAM for multiple Link Layer usage. + 0x2268 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2203 + Shared Packet RAM for multiple Link Layer usage. + 0x226C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2204 + Shared Packet RAM for multiple Link Layer usage. + 0x2270 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2205 + Shared Packet RAM for multiple Link Layer usage. + 0x2274 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2206 + Shared Packet RAM for multiple Link Layer usage. + 0x2278 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2207 + Shared Packet RAM for multiple Link Layer usage. + 0x227C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2208 + Shared Packet RAM for multiple Link Layer usage. + 0x2280 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2209 + Shared Packet RAM for multiple Link Layer usage. + 0x2284 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2210 + Shared Packet RAM for multiple Link Layer usage. + 0x2288 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2211 + Shared Packet RAM for multiple Link Layer usage. + 0x228C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2212 + Shared Packet RAM for multiple Link Layer usage. + 0x2290 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2213 + Shared Packet RAM for multiple Link Layer usage. + 0x2294 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2214 + Shared Packet RAM for multiple Link Layer usage. + 0x2298 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2215 + Shared Packet RAM for multiple Link Layer usage. + 0x229C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2216 + Shared Packet RAM for multiple Link Layer usage. + 0x22A0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2217 + Shared Packet RAM for multiple Link Layer usage. + 0x22A4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2218 + Shared Packet RAM for multiple Link Layer usage. + 0x22A8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2219 + Shared Packet RAM for multiple Link Layer usage. + 0x22AC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2220 + Shared Packet RAM for multiple Link Layer usage. + 0x22B0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2221 + Shared Packet RAM for multiple Link Layer usage. + 0x22B4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2222 + Shared Packet RAM for multiple Link Layer usage. + 0x22B8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2223 + Shared Packet RAM for multiple Link Layer usage. + 0x22BC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2224 + Shared Packet RAM for multiple Link Layer usage. + 0x22C0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2225 + Shared Packet RAM for multiple Link Layer usage. + 0x22C4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2226 + Shared Packet RAM for multiple Link Layer usage. + 0x22C8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2227 + Shared Packet RAM for multiple Link Layer usage. + 0x22CC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2228 + Shared Packet RAM for multiple Link Layer usage. + 0x22D0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2229 + Shared Packet RAM for multiple Link Layer usage. + 0x22D4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2230 + Shared Packet RAM for multiple Link Layer usage. + 0x22D8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2231 + Shared Packet RAM for multiple Link Layer usage. + 0x22DC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2232 + Shared Packet RAM for multiple Link Layer usage. + 0x22E0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2233 + Shared Packet RAM for multiple Link Layer usage. + 0x22E4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2234 + Shared Packet RAM for multiple Link Layer usage. + 0x22E8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2235 + Shared Packet RAM for multiple Link Layer usage. + 0x22EC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2236 + Shared Packet RAM for multiple Link Layer usage. + 0x22F0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2237 + Shared Packet RAM for multiple Link Layer usage. + 0x22F4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2238 + Shared Packet RAM for multiple Link Layer usage. + 0x22F8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2239 + Shared Packet RAM for multiple Link Layer usage. + 0x22FC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2240 + Shared Packet RAM for multiple Link Layer usage. + 0x2300 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2241 + Shared Packet RAM for multiple Link Layer usage. + 0x2304 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2242 + Shared Packet RAM for multiple Link Layer usage. + 0x2308 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2243 + Shared Packet RAM for multiple Link Layer usage. + 0x230C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2244 + Shared Packet RAM for multiple Link Layer usage. + 0x2310 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2245 + Shared Packet RAM for multiple Link Layer usage. + 0x2314 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2246 + Shared Packet RAM for multiple Link Layer usage. + 0x2318 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2247 + Shared Packet RAM for multiple Link Layer usage. + 0x231C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2248 + Shared Packet RAM for multiple Link Layer usage. + 0x2320 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2249 + Shared Packet RAM for multiple Link Layer usage. + 0x2324 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2250 + Shared Packet RAM for multiple Link Layer usage. + 0x2328 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2251 + Shared Packet RAM for multiple Link Layer usage. + 0x232C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2252 + Shared Packet RAM for multiple Link Layer usage. + 0x2330 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2253 + Shared Packet RAM for multiple Link Layer usage. + 0x2334 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2254 + Shared Packet RAM for multiple Link Layer usage. + 0x2338 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2255 + Shared Packet RAM for multiple Link Layer usage. + 0x233C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2256 + Shared Packet RAM for multiple Link Layer usage. + 0x2340 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2257 + Shared Packet RAM for multiple Link Layer usage. + 0x2344 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2258 + Shared Packet RAM for multiple Link Layer usage. + 0x2348 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2259 + Shared Packet RAM for multiple Link Layer usage. + 0x234C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2260 + Shared Packet RAM for multiple Link Layer usage. + 0x2350 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2261 + Shared Packet RAM for multiple Link Layer usage. + 0x2354 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2262 + Shared Packet RAM for multiple Link Layer usage. + 0x2358 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2263 + Shared Packet RAM for multiple Link Layer usage. + 0x235C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2264 + Shared Packet RAM for multiple Link Layer usage. + 0x2360 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2265 + Shared Packet RAM for multiple Link Layer usage. + 0x2364 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2266 + Shared Packet RAM for multiple Link Layer usage. + 0x2368 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2267 + Shared Packet RAM for multiple Link Layer usage. + 0x236C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2268 + Shared Packet RAM for multiple Link Layer usage. + 0x2370 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2269 + Shared Packet RAM for multiple Link Layer usage. + 0x2374 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2270 + Shared Packet RAM for multiple Link Layer usage. + 0x2378 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2271 + Shared Packet RAM for multiple Link Layer usage. + 0x237C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2272 + Shared Packet RAM for multiple Link Layer usage. + 0x2380 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2273 + Shared Packet RAM for multiple Link Layer usage. + 0x2384 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2274 + Shared Packet RAM for multiple Link Layer usage. + 0x2388 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2275 + Shared Packet RAM for multiple Link Layer usage. + 0x238C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2276 + Shared Packet RAM for multiple Link Layer usage. + 0x2390 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2277 + Shared Packet RAM for multiple Link Layer usage. + 0x2394 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2278 + Shared Packet RAM for multiple Link Layer usage. + 0x2398 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2279 + Shared Packet RAM for multiple Link Layer usage. + 0x239C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2280 + Shared Packet RAM for multiple Link Layer usage. + 0x23A0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2281 + Shared Packet RAM for multiple Link Layer usage. + 0x23A4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2282 + Shared Packet RAM for multiple Link Layer usage. + 0x23A8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2283 + Shared Packet RAM for multiple Link Layer usage. + 0x23AC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2284 + Shared Packet RAM for multiple Link Layer usage. + 0x23B0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2285 + Shared Packet RAM for multiple Link Layer usage. + 0x23B4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2286 + Shared Packet RAM for multiple Link Layer usage. + 0x23B8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2287 + Shared Packet RAM for multiple Link Layer usage. + 0x23BC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2288 + Shared Packet RAM for multiple Link Layer usage. + 0x23C0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2289 + Shared Packet RAM for multiple Link Layer usage. + 0x23C4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2290 + Shared Packet RAM for multiple Link Layer usage. + 0x23C8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2291 + Shared Packet RAM for multiple Link Layer usage. + 0x23CC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2292 + Shared Packet RAM for multiple Link Layer usage. + 0x23D0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2293 + Shared Packet RAM for multiple Link Layer usage. + 0x23D4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2294 + Shared Packet RAM for multiple Link Layer usage. + 0x23D8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2295 + Shared Packet RAM for multiple Link Layer usage. + 0x23DC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2296 + Shared Packet RAM for multiple Link Layer usage. + 0x23E0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2297 + Shared Packet RAM for multiple Link Layer usage. + 0x23E4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2298 + Shared Packet RAM for multiple Link Layer usage. + 0x23E8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2299 + Shared Packet RAM for multiple Link Layer usage. + 0x23EC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2300 + Shared Packet RAM for multiple Link Layer usage. + 0x23F0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2301 + Shared Packet RAM for multiple Link Layer usage. + 0x23F4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2302 + Shared Packet RAM for multiple Link Layer usage. + 0x23F8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2303 + Shared Packet RAM for multiple Link Layer usage. + 0x23FC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2304 + Shared Packet RAM for multiple Link Layer usage. + 0x2400 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2305 + Shared Packet RAM for multiple Link Layer usage. + 0x2404 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2306 + Shared Packet RAM for multiple Link Layer usage. + 0x2408 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2307 + Shared Packet RAM for multiple Link Layer usage. + 0x240C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2308 + Shared Packet RAM for multiple Link Layer usage. + 0x2410 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2309 + Shared Packet RAM for multiple Link Layer usage. + 0x2414 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2310 + Shared Packet RAM for multiple Link Layer usage. + 0x2418 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2311 + Shared Packet RAM for multiple Link Layer usage. + 0x241C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2312 + Shared Packet RAM for multiple Link Layer usage. + 0x2420 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2313 + Shared Packet RAM for multiple Link Layer usage. + 0x2424 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2314 + Shared Packet RAM for multiple Link Layer usage. + 0x2428 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2315 + Shared Packet RAM for multiple Link Layer usage. + 0x242C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2316 + Shared Packet RAM for multiple Link Layer usage. + 0x2430 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2317 + Shared Packet RAM for multiple Link Layer usage. + 0x2434 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2318 + Shared Packet RAM for multiple Link Layer usage. + 0x2438 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2319 + Shared Packet RAM for multiple Link Layer usage. + 0x243C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2320 + Shared Packet RAM for multiple Link Layer usage. + 0x2440 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2321 + Shared Packet RAM for multiple Link Layer usage. + 0x2444 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2322 + Shared Packet RAM for multiple Link Layer usage. + 0x2448 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2323 + Shared Packet RAM for multiple Link Layer usage. + 0x244C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2324 + Shared Packet RAM for multiple Link Layer usage. + 0x2450 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2325 + Shared Packet RAM for multiple Link Layer usage. + 0x2454 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2326 + Shared Packet RAM for multiple Link Layer usage. + 0x2458 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2327 + Shared Packet RAM for multiple Link Layer usage. + 0x245C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2328 + Shared Packet RAM for multiple Link Layer usage. + 0x2460 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2329 + Shared Packet RAM for multiple Link Layer usage. + 0x2464 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2330 + Shared Packet RAM for multiple Link Layer usage. + 0x2468 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2331 + Shared Packet RAM for multiple Link Layer usage. + 0x246C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2332 + Shared Packet RAM for multiple Link Layer usage. + 0x2470 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2333 + Shared Packet RAM for multiple Link Layer usage. + 0x2474 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2334 + Shared Packet RAM for multiple Link Layer usage. + 0x2478 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2335 + Shared Packet RAM for multiple Link Layer usage. + 0x247C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2336 + Shared Packet RAM for multiple Link Layer usage. + 0x2480 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2337 + Shared Packet RAM for multiple Link Layer usage. + 0x2484 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2338 + Shared Packet RAM for multiple Link Layer usage. + 0x2488 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2339 + Shared Packet RAM for multiple Link Layer usage. + 0x248C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2340 + Shared Packet RAM for multiple Link Layer usage. + 0x2490 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2341 + Shared Packet RAM for multiple Link Layer usage. + 0x2494 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2342 + Shared Packet RAM for multiple Link Layer usage. + 0x2498 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2343 + Shared Packet RAM for multiple Link Layer usage. + 0x249C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2344 + Shared Packet RAM for multiple Link Layer usage. + 0x24A0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2345 + Shared Packet RAM for multiple Link Layer usage. + 0x24A4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2346 + Shared Packet RAM for multiple Link Layer usage. + 0x24A8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2347 + Shared Packet RAM for multiple Link Layer usage. + 0x24AC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2348 + Shared Packet RAM for multiple Link Layer usage. + 0x24B0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2349 + Shared Packet RAM for multiple Link Layer usage. + 0x24B4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2350 + Shared Packet RAM for multiple Link Layer usage. + 0x24B8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2351 + Shared Packet RAM for multiple Link Layer usage. + 0x24BC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2352 + Shared Packet RAM for multiple Link Layer usage. + 0x24C0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2353 + Shared Packet RAM for multiple Link Layer usage. + 0x24C4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2354 + Shared Packet RAM for multiple Link Layer usage. + 0x24C8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2355 + Shared Packet RAM for multiple Link Layer usage. + 0x24CC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2356 + Shared Packet RAM for multiple Link Layer usage. + 0x24D0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2357 + Shared Packet RAM for multiple Link Layer usage. + 0x24D4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2358 + Shared Packet RAM for multiple Link Layer usage. + 0x24D8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2359 + Shared Packet RAM for multiple Link Layer usage. + 0x24DC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2360 + Shared Packet RAM for multiple Link Layer usage. + 0x24E0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2361 + Shared Packet RAM for multiple Link Layer usage. + 0x24E4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2362 + Shared Packet RAM for multiple Link Layer usage. + 0x24E8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2363 + Shared Packet RAM for multiple Link Layer usage. + 0x24EC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2364 + Shared Packet RAM for multiple Link Layer usage. + 0x24F0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2365 + Shared Packet RAM for multiple Link Layer usage. + 0x24F4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2366 + Shared Packet RAM for multiple Link Layer usage. + 0x24F8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2367 + Shared Packet RAM for multiple Link Layer usage. + 0x24FC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2368 + Shared Packet RAM for multiple Link Layer usage. + 0x2500 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2369 + Shared Packet RAM for multiple Link Layer usage. + 0x2504 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2370 + Shared Packet RAM for multiple Link Layer usage. + 0x2508 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2371 + Shared Packet RAM for multiple Link Layer usage. + 0x250C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2372 + Shared Packet RAM for multiple Link Layer usage. + 0x2510 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2373 + Shared Packet RAM for multiple Link Layer usage. + 0x2514 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2374 + Shared Packet RAM for multiple Link Layer usage. + 0x2518 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2375 + Shared Packet RAM for multiple Link Layer usage. + 0x251C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2376 + Shared Packet RAM for multiple Link Layer usage. + 0x2520 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2377 + Shared Packet RAM for multiple Link Layer usage. + 0x2524 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2378 + Shared Packet RAM for multiple Link Layer usage. + 0x2528 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2379 + Shared Packet RAM for multiple Link Layer usage. + 0x252C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2380 + Shared Packet RAM for multiple Link Layer usage. + 0x2530 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2381 + Shared Packet RAM for multiple Link Layer usage. + 0x2534 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2382 + Shared Packet RAM for multiple Link Layer usage. + 0x2538 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2383 + Shared Packet RAM for multiple Link Layer usage. + 0x253C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2384 + Shared Packet RAM for multiple Link Layer usage. + 0x2540 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2385 + Shared Packet RAM for multiple Link Layer usage. + 0x2544 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2386 + Shared Packet RAM for multiple Link Layer usage. + 0x2548 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2387 + Shared Packet RAM for multiple Link Layer usage. + 0x254C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2388 + Shared Packet RAM for multiple Link Layer usage. + 0x2550 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2389 + Shared Packet RAM for multiple Link Layer usage. + 0x2554 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2390 + Shared Packet RAM for multiple Link Layer usage. + 0x2558 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2391 + Shared Packet RAM for multiple Link Layer usage. + 0x255C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2392 + Shared Packet RAM for multiple Link Layer usage. + 0x2560 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2393 + Shared Packet RAM for multiple Link Layer usage. + 0x2564 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2394 + Shared Packet RAM for multiple Link Layer usage. + 0x2568 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2395 + Shared Packet RAM for multiple Link Layer usage. + 0x256C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2396 + Shared Packet RAM for multiple Link Layer usage. + 0x2570 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2397 + Shared Packet RAM for multiple Link Layer usage. + 0x2574 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2398 + Shared Packet RAM for multiple Link Layer usage. + 0x2578 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2399 + Shared Packet RAM for multiple Link Layer usage. + 0x257C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2400 + Shared Packet RAM for multiple Link Layer usage. + 0x2580 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2401 + Shared Packet RAM for multiple Link Layer usage. + 0x2584 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2402 + Shared Packet RAM for multiple Link Layer usage. + 0x2588 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2403 + Shared Packet RAM for multiple Link Layer usage. + 0x258C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2404 + Shared Packet RAM for multiple Link Layer usage. + 0x2590 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2405 + Shared Packet RAM for multiple Link Layer usage. + 0x2594 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2406 + Shared Packet RAM for multiple Link Layer usage. + 0x2598 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2407 + Shared Packet RAM for multiple Link Layer usage. + 0x259C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2408 + Shared Packet RAM for multiple Link Layer usage. + 0x25A0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2409 + Shared Packet RAM for multiple Link Layer usage. + 0x25A4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2410 + Shared Packet RAM for multiple Link Layer usage. + 0x25A8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2411 + Shared Packet RAM for multiple Link Layer usage. + 0x25AC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2412 + Shared Packet RAM for multiple Link Layer usage. + 0x25B0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2413 + Shared Packet RAM for multiple Link Layer usage. + 0x25B4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2414 + Shared Packet RAM for multiple Link Layer usage. + 0x25B8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2415 + Shared Packet RAM for multiple Link Layer usage. + 0x25BC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2416 + Shared Packet RAM for multiple Link Layer usage. + 0x25C0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2417 + Shared Packet RAM for multiple Link Layer usage. + 0x25C4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2418 + Shared Packet RAM for multiple Link Layer usage. + 0x25C8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2419 + Shared Packet RAM for multiple Link Layer usage. + 0x25CC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2420 + Shared Packet RAM for multiple Link Layer usage. + 0x25D0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2421 + Shared Packet RAM for multiple Link Layer usage. + 0x25D4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2422 + Shared Packet RAM for multiple Link Layer usage. + 0x25D8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2423 + Shared Packet RAM for multiple Link Layer usage. + 0x25DC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2424 + Shared Packet RAM for multiple Link Layer usage. + 0x25E0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2425 + Shared Packet RAM for multiple Link Layer usage. + 0x25E4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2426 + Shared Packet RAM for multiple Link Layer usage. + 0x25E8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2427 + Shared Packet RAM for multiple Link Layer usage. + 0x25EC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2428 + Shared Packet RAM for multiple Link Layer usage. + 0x25F0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2429 + Shared Packet RAM for multiple Link Layer usage. + 0x25F4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2430 + Shared Packet RAM for multiple Link Layer usage. + 0x25F8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2431 + Shared Packet RAM for multiple Link Layer usage. + 0x25FC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2432 + Shared Packet RAM for multiple Link Layer usage. + 0x2600 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2433 + Shared Packet RAM for multiple Link Layer usage. + 0x2604 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2434 + Shared Packet RAM for multiple Link Layer usage. + 0x2608 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2435 + Shared Packet RAM for multiple Link Layer usage. + 0x260C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2436 + Shared Packet RAM for multiple Link Layer usage. + 0x2610 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2437 + Shared Packet RAM for multiple Link Layer usage. + 0x2614 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2438 + Shared Packet RAM for multiple Link Layer usage. + 0x2618 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2439 + Shared Packet RAM for multiple Link Layer usage. + 0x261C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2440 + Shared Packet RAM for multiple Link Layer usage. + 0x2620 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2441 + Shared Packet RAM for multiple Link Layer usage. + 0x2624 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2442 + Shared Packet RAM for multiple Link Layer usage. + 0x2628 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2443 + Shared Packet RAM for multiple Link Layer usage. + 0x262C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2444 + Shared Packet RAM for multiple Link Layer usage. + 0x2630 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2445 + Shared Packet RAM for multiple Link Layer usage. + 0x2634 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2446 + Shared Packet RAM for multiple Link Layer usage. + 0x2638 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2447 + Shared Packet RAM for multiple Link Layer usage. + 0x263C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2448 + Shared Packet RAM for multiple Link Layer usage. + 0x2640 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2449 + Shared Packet RAM for multiple Link Layer usage. + 0x2644 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2450 + Shared Packet RAM for multiple Link Layer usage. + 0x2648 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2451 + Shared Packet RAM for multiple Link Layer usage. + 0x264C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2452 + Shared Packet RAM for multiple Link Layer usage. + 0x2650 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2453 + Shared Packet RAM for multiple Link Layer usage. + 0x2654 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2454 + Shared Packet RAM for multiple Link Layer usage. + 0x2658 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2455 + Shared Packet RAM for multiple Link Layer usage. + 0x265C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2456 + Shared Packet RAM for multiple Link Layer usage. + 0x2660 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2457 + Shared Packet RAM for multiple Link Layer usage. + 0x2664 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2458 + Shared Packet RAM for multiple Link Layer usage. + 0x2668 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2459 + Shared Packet RAM for multiple Link Layer usage. + 0x266C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2460 + Shared Packet RAM for multiple Link Layer usage. + 0x2670 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2461 + Shared Packet RAM for multiple Link Layer usage. + 0x2674 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2462 + Shared Packet RAM for multiple Link Layer usage. + 0x2678 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2463 + Shared Packet RAM for multiple Link Layer usage. + 0x267C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2464 + Shared Packet RAM for multiple Link Layer usage. + 0x2680 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2465 + Shared Packet RAM for multiple Link Layer usage. + 0x2684 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2466 + Shared Packet RAM for multiple Link Layer usage. + 0x2688 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2467 + Shared Packet RAM for multiple Link Layer usage. + 0x268C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2468 + Shared Packet RAM for multiple Link Layer usage. + 0x2690 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2469 + Shared Packet RAM for multiple Link Layer usage. + 0x2694 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2470 + Shared Packet RAM for multiple Link Layer usage. + 0x2698 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2471 + Shared Packet RAM for multiple Link Layer usage. + 0x269C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2472 + Shared Packet RAM for multiple Link Layer usage. + 0x26A0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2473 + Shared Packet RAM for multiple Link Layer usage. + 0x26A4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2474 + Shared Packet RAM for multiple Link Layer usage. + 0x26A8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2475 + Shared Packet RAM for multiple Link Layer usage. + 0x26AC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2476 + Shared Packet RAM for multiple Link Layer usage. + 0x26B0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2477 + Shared Packet RAM for multiple Link Layer usage. + 0x26B4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2478 + Shared Packet RAM for multiple Link Layer usage. + 0x26B8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2479 + Shared Packet RAM for multiple Link Layer usage. + 0x26BC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2480 + Shared Packet RAM for multiple Link Layer usage. + 0x26C0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2481 + Shared Packet RAM for multiple Link Layer usage. + 0x26C4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2482 + Shared Packet RAM for multiple Link Layer usage. + 0x26C8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2483 + Shared Packet RAM for multiple Link Layer usage. + 0x26CC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2484 + Shared Packet RAM for multiple Link Layer usage. + 0x26D0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2485 + Shared Packet RAM for multiple Link Layer usage. + 0x26D4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2486 + Shared Packet RAM for multiple Link Layer usage. + 0x26D8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2487 + Shared Packet RAM for multiple Link Layer usage. + 0x26DC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2488 + Shared Packet RAM for multiple Link Layer usage. + 0x26E0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2489 + Shared Packet RAM for multiple Link Layer usage. + 0x26E4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2490 + Shared Packet RAM for multiple Link Layer usage. + 0x26E8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2491 + Shared Packet RAM for multiple Link Layer usage. + 0x26EC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2492 + Shared Packet RAM for multiple Link Layer usage. + 0x26F0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2493 + Shared Packet RAM for multiple Link Layer usage. + 0x26F4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2494 + Shared Packet RAM for multiple Link Layer usage. + 0x26F8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2495 + Shared Packet RAM for multiple Link Layer usage. + 0x26FC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2496 + Shared Packet RAM for multiple Link Layer usage. + 0x2700 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2497 + Shared Packet RAM for multiple Link Layer usage. + 0x2704 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2498 + Shared Packet RAM for multiple Link Layer usage. + 0x2708 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2499 + Shared Packet RAM for multiple Link Layer usage. + 0x270C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2500 + Shared Packet RAM for multiple Link Layer usage. + 0x2710 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2501 + Shared Packet RAM for multiple Link Layer usage. + 0x2714 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2502 + Shared Packet RAM for multiple Link Layer usage. + 0x2718 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2503 + Shared Packet RAM for multiple Link Layer usage. + 0x271C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2504 + Shared Packet RAM for multiple Link Layer usage. + 0x2720 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2505 + Shared Packet RAM for multiple Link Layer usage. + 0x2724 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2506 + Shared Packet RAM for multiple Link Layer usage. + 0x2728 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2507 + Shared Packet RAM for multiple Link Layer usage. + 0x272C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2508 + Shared Packet RAM for multiple Link Layer usage. + 0x2730 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2509 + Shared Packet RAM for multiple Link Layer usage. + 0x2734 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2510 + Shared Packet RAM for multiple Link Layer usage. + 0x2738 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2511 + Shared Packet RAM for multiple Link Layer usage. + 0x273C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2512 + Shared Packet RAM for multiple Link Layer usage. + 0x2740 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2513 + Shared Packet RAM for multiple Link Layer usage. + 0x2744 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2514 + Shared Packet RAM for multiple Link Layer usage. + 0x2748 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2515 + Shared Packet RAM for multiple Link Layer usage. + 0x274C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2516 + Shared Packet RAM for multiple Link Layer usage. + 0x2750 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2517 + Shared Packet RAM for multiple Link Layer usage. + 0x2754 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2518 + Shared Packet RAM for multiple Link Layer usage. + 0x2758 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2519 + Shared Packet RAM for multiple Link Layer usage. + 0x275C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2520 + Shared Packet RAM for multiple Link Layer usage. + 0x2760 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2521 + Shared Packet RAM for multiple Link Layer usage. + 0x2764 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2522 + Shared Packet RAM for multiple Link Layer usage. + 0x2768 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2523 + Shared Packet RAM for multiple Link Layer usage. + 0x276C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2524 + Shared Packet RAM for multiple Link Layer usage. + 0x2770 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2525 + Shared Packet RAM for multiple Link Layer usage. + 0x2774 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2526 + Shared Packet RAM for multiple Link Layer usage. + 0x2778 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2527 + Shared Packet RAM for multiple Link Layer usage. + 0x277C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2528 + Shared Packet RAM for multiple Link Layer usage. + 0x2780 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2529 + Shared Packet RAM for multiple Link Layer usage. + 0x2784 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2530 + Shared Packet RAM for multiple Link Layer usage. + 0x2788 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2531 + Shared Packet RAM for multiple Link Layer usage. + 0x278C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2532 + Shared Packet RAM for multiple Link Layer usage. + 0x2790 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2533 + Shared Packet RAM for multiple Link Layer usage. + 0x2794 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2534 + Shared Packet RAM for multiple Link Layer usage. + 0x2798 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2535 + Shared Packet RAM for multiple Link Layer usage. + 0x279C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2536 + Shared Packet RAM for multiple Link Layer usage. + 0x27A0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2537 + Shared Packet RAM for multiple Link Layer usage. + 0x27A4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2538 + Shared Packet RAM for multiple Link Layer usage. + 0x27A8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2539 + Shared Packet RAM for multiple Link Layer usage. + 0x27AC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2540 + Shared Packet RAM for multiple Link Layer usage. + 0x27B0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2541 + Shared Packet RAM for multiple Link Layer usage. + 0x27B4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2542 + Shared Packet RAM for multiple Link Layer usage. + 0x27B8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2543 + Shared Packet RAM for multiple Link Layer usage. + 0x27BC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2544 + Shared Packet RAM for multiple Link Layer usage. + 0x27C0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2545 + Shared Packet RAM for multiple Link Layer usage. + 0x27C4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2546 + Shared Packet RAM for multiple Link Layer usage. + 0x27C8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2547 + Shared Packet RAM for multiple Link Layer usage. + 0x27CC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2548 + Shared Packet RAM for multiple Link Layer usage. + 0x27D0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2549 + Shared Packet RAM for multiple Link Layer usage. + 0x27D4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2550 + Shared Packet RAM for multiple Link Layer usage. + 0x27D8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2551 + Shared Packet RAM for multiple Link Layer usage. + 0x27DC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2552 + Shared Packet RAM for multiple Link Layer usage. + 0x27E0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2553 + Shared Packet RAM for multiple Link Layer usage. + 0x27E4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2554 + Shared Packet RAM for multiple Link Layer usage. + 0x27E8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2555 + Shared Packet RAM for multiple Link Layer usage. + 0x27EC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2556 + Shared Packet RAM for multiple Link Layer usage. + 0x27F0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2557 + Shared Packet RAM for multiple Link Layer usage. + 0x27F4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2558 + Shared Packet RAM for multiple Link Layer usage. + 0x27F8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2559 + Shared Packet RAM for multiple Link Layer usage. + 0x27FC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + + + RX_PACKET_RAM + RADIO_PACKET_RAM + RADIO_PACKET_RAM + 0x4008B000 + + 0 + 0x1D80 + registers + + + + PACKET_RAM_0 + Shared Packet RAM for multiple Link Layer usage. + 0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1 + Shared Packet RAM for multiple Link Layer usage. + 0x4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_2 + Shared Packet RAM for multiple Link Layer usage. + 0x8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_3 + Shared Packet RAM for multiple Link Layer usage. + 0xC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_4 + Shared Packet RAM for multiple Link Layer usage. + 0x10 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_5 + Shared Packet RAM for multiple Link Layer usage. + 0x14 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_6 + Shared Packet RAM for multiple Link Layer usage. + 0x18 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_7 + Shared Packet RAM for multiple Link Layer usage. + 0x1C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_8 + Shared Packet RAM for multiple Link Layer usage. + 0x20 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_9 + Shared Packet RAM for multiple Link Layer usage. + 0x24 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_10 + Shared Packet RAM for multiple Link Layer usage. + 0x28 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_11 + Shared Packet RAM for multiple Link Layer usage. + 0x2C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_12 + Shared Packet RAM for multiple Link Layer usage. + 0x30 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_13 + Shared Packet RAM for multiple Link Layer usage. + 0x34 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_14 + Shared Packet RAM for multiple Link Layer usage. + 0x38 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_15 + Shared Packet RAM for multiple Link Layer usage. + 0x3C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_16 + Shared Packet RAM for multiple Link Layer usage. + 0x40 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_17 + Shared Packet RAM for multiple Link Layer usage. + 0x44 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_18 + Shared Packet RAM for multiple Link Layer usage. + 0x48 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_19 + Shared Packet RAM for multiple Link Layer usage. + 0x4C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_20 + Shared Packet RAM for multiple Link Layer usage. + 0x50 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_21 + Shared Packet RAM for multiple Link Layer usage. + 0x54 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_22 + Shared Packet RAM for multiple Link Layer usage. + 0x58 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_23 + Shared Packet RAM for multiple Link Layer usage. + 0x5C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_24 + Shared Packet RAM for multiple Link Layer usage. + 0x60 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_25 + Shared Packet RAM for multiple Link Layer usage. + 0x64 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_26 + Shared Packet RAM for multiple Link Layer usage. + 0x68 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_27 + Shared Packet RAM for multiple Link Layer usage. + 0x6C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_28 + Shared Packet RAM for multiple Link Layer usage. + 0x70 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_29 + Shared Packet RAM for multiple Link Layer usage. + 0x74 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_30 + Shared Packet RAM for multiple Link Layer usage. + 0x78 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_31 + Shared Packet RAM for multiple Link Layer usage. + 0x7C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_32 + Shared Packet RAM for multiple Link Layer usage. + 0x80 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_33 + Shared Packet RAM for multiple Link Layer usage. + 0x84 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_34 + Shared Packet RAM for multiple Link Layer usage. + 0x88 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_35 + Shared Packet RAM for multiple Link Layer usage. + 0x8C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_36 + Shared Packet RAM for multiple Link Layer usage. + 0x90 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_37 + Shared Packet RAM for multiple Link Layer usage. + 0x94 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_38 + Shared Packet RAM for multiple Link Layer usage. + 0x98 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_39 + Shared Packet RAM for multiple Link Layer usage. + 0x9C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_40 + Shared Packet RAM for multiple Link Layer usage. + 0xA0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_41 + Shared Packet RAM for multiple Link Layer usage. + 0xA4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_42 + Shared Packet RAM for multiple Link Layer usage. + 0xA8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_43 + Shared Packet RAM for multiple Link Layer usage. + 0xAC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_44 + Shared Packet RAM for multiple Link Layer usage. + 0xB0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_45 + Shared Packet RAM for multiple Link Layer usage. + 0xB4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_46 + Shared Packet RAM for multiple Link Layer usage. + 0xB8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_47 + Shared Packet RAM for multiple Link Layer usage. + 0xBC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_48 + Shared Packet RAM for multiple Link Layer usage. + 0xC0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_49 + Shared Packet RAM for multiple Link Layer usage. + 0xC4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_50 + Shared Packet RAM for multiple Link Layer usage. + 0xC8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_51 + Shared Packet RAM for multiple Link Layer usage. + 0xCC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_52 + Shared Packet RAM for multiple Link Layer usage. + 0xD0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_53 + Shared Packet RAM for multiple Link Layer usage. + 0xD4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_54 + Shared Packet RAM for multiple Link Layer usage. + 0xD8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_55 + Shared Packet RAM for multiple Link Layer usage. + 0xDC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_56 + Shared Packet RAM for multiple Link Layer usage. + 0xE0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_57 + Shared Packet RAM for multiple Link Layer usage. + 0xE4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_58 + Shared Packet RAM for multiple Link Layer usage. + 0xE8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_59 + Shared Packet RAM for multiple Link Layer usage. + 0xEC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_60 + Shared Packet RAM for multiple Link Layer usage. + 0xF0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_61 + Shared Packet RAM for multiple Link Layer usage. + 0xF4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_62 + Shared Packet RAM for multiple Link Layer usage. + 0xF8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_63 + Shared Packet RAM for multiple Link Layer usage. + 0xFC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_64 + Shared Packet RAM for multiple Link Layer usage. + 0x100 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_65 + Shared Packet RAM for multiple Link Layer usage. + 0x104 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_66 + Shared Packet RAM for multiple Link Layer usage. + 0x108 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_67 + Shared Packet RAM for multiple Link Layer usage. + 0x10C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_68 + Shared Packet RAM for multiple Link Layer usage. + 0x110 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_69 + Shared Packet RAM for multiple Link Layer usage. + 0x114 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_70 + Shared Packet RAM for multiple Link Layer usage. + 0x118 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_71 + Shared Packet RAM for multiple Link Layer usage. + 0x11C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_72 + Shared Packet RAM for multiple Link Layer usage. + 0x120 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_73 + Shared Packet RAM for multiple Link Layer usage. + 0x124 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_74 + Shared Packet RAM for multiple Link Layer usage. + 0x128 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_75 + Shared Packet RAM for multiple Link Layer usage. + 0x12C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_76 + Shared Packet RAM for multiple Link Layer usage. + 0x130 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_77 + Shared Packet RAM for multiple Link Layer usage. + 0x134 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_78 + Shared Packet RAM for multiple Link Layer usage. + 0x138 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_79 + Shared Packet RAM for multiple Link Layer usage. + 0x13C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_80 + Shared Packet RAM for multiple Link Layer usage. + 0x140 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_81 + Shared Packet RAM for multiple Link Layer usage. + 0x144 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_82 + Shared Packet RAM for multiple Link Layer usage. + 0x148 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_83 + Shared Packet RAM for multiple Link Layer usage. + 0x14C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_84 + Shared Packet RAM for multiple Link Layer usage. + 0x150 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_85 + Shared Packet RAM for multiple Link Layer usage. + 0x154 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_86 + Shared Packet RAM for multiple Link Layer usage. + 0x158 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_87 + Shared Packet RAM for multiple Link Layer usage. + 0x15C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_88 + Shared Packet RAM for multiple Link Layer usage. + 0x160 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_89 + Shared Packet RAM for multiple Link Layer usage. + 0x164 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_90 + Shared Packet RAM for multiple Link Layer usage. + 0x168 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_91 + Shared Packet RAM for multiple Link Layer usage. + 0x16C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_92 + Shared Packet RAM for multiple Link Layer usage. + 0x170 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_93 + Shared Packet RAM for multiple Link Layer usage. + 0x174 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_94 + Shared Packet RAM for multiple Link Layer usage. + 0x178 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_95 + Shared Packet RAM for multiple Link Layer usage. + 0x17C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_96 + Shared Packet RAM for multiple Link Layer usage. + 0x180 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_97 + Shared Packet RAM for multiple Link Layer usage. + 0x184 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_98 + Shared Packet RAM for multiple Link Layer usage. + 0x188 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_99 + Shared Packet RAM for multiple Link Layer usage. + 0x18C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_100 + Shared Packet RAM for multiple Link Layer usage. + 0x190 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_101 + Shared Packet RAM for multiple Link Layer usage. + 0x194 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_102 + Shared Packet RAM for multiple Link Layer usage. + 0x198 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_103 + Shared Packet RAM for multiple Link Layer usage. + 0x19C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_104 + Shared Packet RAM for multiple Link Layer usage. + 0x1A0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_105 + Shared Packet RAM for multiple Link Layer usage. + 0x1A4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_106 + Shared Packet RAM for multiple Link Layer usage. + 0x1A8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_107 + Shared Packet RAM for multiple Link Layer usage. + 0x1AC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_108 + Shared Packet RAM for multiple Link Layer usage. + 0x1B0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_109 + Shared Packet RAM for multiple Link Layer usage. + 0x1B4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_110 + Shared Packet RAM for multiple Link Layer usage. + 0x1B8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_111 + Shared Packet RAM for multiple Link Layer usage. + 0x1BC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_112 + Shared Packet RAM for multiple Link Layer usage. + 0x1C0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_113 + Shared Packet RAM for multiple Link Layer usage. + 0x1C4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_114 + Shared Packet RAM for multiple Link Layer usage. + 0x1C8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_115 + Shared Packet RAM for multiple Link Layer usage. + 0x1CC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_116 + Shared Packet RAM for multiple Link Layer usage. + 0x1D0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_117 + Shared Packet RAM for multiple Link Layer usage. + 0x1D4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_118 + Shared Packet RAM for multiple Link Layer usage. + 0x1D8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_119 + Shared Packet RAM for multiple Link Layer usage. + 0x1DC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_120 + Shared Packet RAM for multiple Link Layer usage. + 0x1E0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_121 + Shared Packet RAM for multiple Link Layer usage. + 0x1E4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_122 + Shared Packet RAM for multiple Link Layer usage. + 0x1E8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_123 + Shared Packet RAM for multiple Link Layer usage. + 0x1EC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_124 + Shared Packet RAM for multiple Link Layer usage. + 0x1F0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_125 + Shared Packet RAM for multiple Link Layer usage. + 0x1F4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_126 + Shared Packet RAM for multiple Link Layer usage. + 0x1F8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_127 + Shared Packet RAM for multiple Link Layer usage. + 0x1FC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_128 + Shared Packet RAM for multiple Link Layer usage. + 0x200 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_129 + Shared Packet RAM for multiple Link Layer usage. + 0x204 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_130 + Shared Packet RAM for multiple Link Layer usage. + 0x208 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_131 + Shared Packet RAM for multiple Link Layer usage. + 0x20C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_132 + Shared Packet RAM for multiple Link Layer usage. + 0x210 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_133 + Shared Packet RAM for multiple Link Layer usage. + 0x214 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_134 + Shared Packet RAM for multiple Link Layer usage. + 0x218 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_135 + Shared Packet RAM for multiple Link Layer usage. + 0x21C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_136 + Shared Packet RAM for multiple Link Layer usage. + 0x220 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_137 + Shared Packet RAM for multiple Link Layer usage. + 0x224 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_138 + Shared Packet RAM for multiple Link Layer usage. + 0x228 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_139 + Shared Packet RAM for multiple Link Layer usage. + 0x22C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_140 + Shared Packet RAM for multiple Link Layer usage. + 0x230 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_141 + Shared Packet RAM for multiple Link Layer usage. + 0x234 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_142 + Shared Packet RAM for multiple Link Layer usage. + 0x238 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_143 + Shared Packet RAM for multiple Link Layer usage. + 0x23C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_144 + Shared Packet RAM for multiple Link Layer usage. + 0x240 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_145 + Shared Packet RAM for multiple Link Layer usage. + 0x244 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_146 + Shared Packet RAM for multiple Link Layer usage. + 0x248 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_147 + Shared Packet RAM for multiple Link Layer usage. + 0x24C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_148 + Shared Packet RAM for multiple Link Layer usage. + 0x250 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_149 + Shared Packet RAM for multiple Link Layer usage. + 0x254 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_150 + Shared Packet RAM for multiple Link Layer usage. + 0x258 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_151 + Shared Packet RAM for multiple Link Layer usage. + 0x25C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_152 + Shared Packet RAM for multiple Link Layer usage. + 0x260 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_153 + Shared Packet RAM for multiple Link Layer usage. + 0x264 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_154 + Shared Packet RAM for multiple Link Layer usage. + 0x268 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_155 + Shared Packet RAM for multiple Link Layer usage. + 0x26C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_156 + Shared Packet RAM for multiple Link Layer usage. + 0x270 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_157 + Shared Packet RAM for multiple Link Layer usage. + 0x274 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_158 + Shared Packet RAM for multiple Link Layer usage. + 0x278 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_159 + Shared Packet RAM for multiple Link Layer usage. + 0x27C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_160 + Shared Packet RAM for multiple Link Layer usage. + 0x280 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_161 + Shared Packet RAM for multiple Link Layer usage. + 0x284 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_162 + Shared Packet RAM for multiple Link Layer usage. + 0x288 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_163 + Shared Packet RAM for multiple Link Layer usage. + 0x28C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_164 + Shared Packet RAM for multiple Link Layer usage. + 0x290 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_165 + Shared Packet RAM for multiple Link Layer usage. + 0x294 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_166 + Shared Packet RAM for multiple Link Layer usage. + 0x298 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_167 + Shared Packet RAM for multiple Link Layer usage. + 0x29C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_168 + Shared Packet RAM for multiple Link Layer usage. + 0x2A0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_169 + Shared Packet RAM for multiple Link Layer usage. + 0x2A4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_170 + Shared Packet RAM for multiple Link Layer usage. + 0x2A8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_171 + Shared Packet RAM for multiple Link Layer usage. + 0x2AC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_172 + Shared Packet RAM for multiple Link Layer usage. + 0x2B0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_173 + Shared Packet RAM for multiple Link Layer usage. + 0x2B4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_174 + Shared Packet RAM for multiple Link Layer usage. + 0x2B8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_175 + Shared Packet RAM for multiple Link Layer usage. + 0x2BC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_176 + Shared Packet RAM for multiple Link Layer usage. + 0x2C0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_177 + Shared Packet RAM for multiple Link Layer usage. + 0x2C4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_178 + Shared Packet RAM for multiple Link Layer usage. + 0x2C8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_179 + Shared Packet RAM for multiple Link Layer usage. + 0x2CC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_180 + Shared Packet RAM for multiple Link Layer usage. + 0x2D0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_181 + Shared Packet RAM for multiple Link Layer usage. + 0x2D4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_182 + Shared Packet RAM for multiple Link Layer usage. + 0x2D8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_183 + Shared Packet RAM for multiple Link Layer usage. + 0x2DC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_184 + Shared Packet RAM for multiple Link Layer usage. + 0x2E0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_185 + Shared Packet RAM for multiple Link Layer usage. + 0x2E4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_186 + Shared Packet RAM for multiple Link Layer usage. + 0x2E8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_187 + Shared Packet RAM for multiple Link Layer usage. + 0x2EC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_188 + Shared Packet RAM for multiple Link Layer usage. + 0x2F0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_189 + Shared Packet RAM for multiple Link Layer usage. + 0x2F4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_190 + Shared Packet RAM for multiple Link Layer usage. + 0x2F8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_191 + Shared Packet RAM for multiple Link Layer usage. + 0x2FC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_192 + Shared Packet RAM for multiple Link Layer usage. + 0x300 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_193 + Shared Packet RAM for multiple Link Layer usage. + 0x304 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_194 + Shared Packet RAM for multiple Link Layer usage. + 0x308 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_195 + Shared Packet RAM for multiple Link Layer usage. + 0x30C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_196 + Shared Packet RAM for multiple Link Layer usage. + 0x310 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_197 + Shared Packet RAM for multiple Link Layer usage. + 0x314 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_198 + Shared Packet RAM for multiple Link Layer usage. + 0x318 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_199 + Shared Packet RAM for multiple Link Layer usage. + 0x31C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_200 + Shared Packet RAM for multiple Link Layer usage. + 0x320 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_201 + Shared Packet RAM for multiple Link Layer usage. + 0x324 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_202 + Shared Packet RAM for multiple Link Layer usage. + 0x328 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_203 + Shared Packet RAM for multiple Link Layer usage. + 0x32C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_204 + Shared Packet RAM for multiple Link Layer usage. + 0x330 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_205 + Shared Packet RAM for multiple Link Layer usage. + 0x334 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_206 + Shared Packet RAM for multiple Link Layer usage. + 0x338 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_207 + Shared Packet RAM for multiple Link Layer usage. + 0x33C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_208 + Shared Packet RAM for multiple Link Layer usage. + 0x340 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_209 + Shared Packet RAM for multiple Link Layer usage. + 0x344 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_210 + Shared Packet RAM for multiple Link Layer usage. + 0x348 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_211 + Shared Packet RAM for multiple Link Layer usage. + 0x34C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_212 + Shared Packet RAM for multiple Link Layer usage. + 0x350 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_213 + Shared Packet RAM for multiple Link Layer usage. + 0x354 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_214 + Shared Packet RAM for multiple Link Layer usage. + 0x358 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_215 + Shared Packet RAM for multiple Link Layer usage. + 0x35C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_216 + Shared Packet RAM for multiple Link Layer usage. + 0x360 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_217 + Shared Packet RAM for multiple Link Layer usage. + 0x364 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_218 + Shared Packet RAM for multiple Link Layer usage. + 0x368 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_219 + Shared Packet RAM for multiple Link Layer usage. + 0x36C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_220 + Shared Packet RAM for multiple Link Layer usage. + 0x370 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_221 + Shared Packet RAM for multiple Link Layer usage. + 0x374 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_222 + Shared Packet RAM for multiple Link Layer usage. + 0x378 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_223 + Shared Packet RAM for multiple Link Layer usage. + 0x37C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_224 + Shared Packet RAM for multiple Link Layer usage. + 0x380 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_225 + Shared Packet RAM for multiple Link Layer usage. + 0x384 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_226 + Shared Packet RAM for multiple Link Layer usage. + 0x388 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_227 + Shared Packet RAM for multiple Link Layer usage. + 0x38C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_228 + Shared Packet RAM for multiple Link Layer usage. + 0x390 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_229 + Shared Packet RAM for multiple Link Layer usage. + 0x394 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_230 + Shared Packet RAM for multiple Link Layer usage. + 0x398 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_231 + Shared Packet RAM for multiple Link Layer usage. + 0x39C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_232 + Shared Packet RAM for multiple Link Layer usage. + 0x3A0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_233 + Shared Packet RAM for multiple Link Layer usage. + 0x3A4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_234 + Shared Packet RAM for multiple Link Layer usage. + 0x3A8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_235 + Shared Packet RAM for multiple Link Layer usage. + 0x3AC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_236 + Shared Packet RAM for multiple Link Layer usage. + 0x3B0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_237 + Shared Packet RAM for multiple Link Layer usage. + 0x3B4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_238 + Shared Packet RAM for multiple Link Layer usage. + 0x3B8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_239 + Shared Packet RAM for multiple Link Layer usage. + 0x3BC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_240 + Shared Packet RAM for multiple Link Layer usage. + 0x3C0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_241 + Shared Packet RAM for multiple Link Layer usage. + 0x3C4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_242 + Shared Packet RAM for multiple Link Layer usage. + 0x3C8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_243 + Shared Packet RAM for multiple Link Layer usage. + 0x3CC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_244 + Shared Packet RAM for multiple Link Layer usage. + 0x3D0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_245 + Shared Packet RAM for multiple Link Layer usage. + 0x3D4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_246 + Shared Packet RAM for multiple Link Layer usage. + 0x3D8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_247 + Shared Packet RAM for multiple Link Layer usage. + 0x3DC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_248 + Shared Packet RAM for multiple Link Layer usage. + 0x3E0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_249 + Shared Packet RAM for multiple Link Layer usage. + 0x3E4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_250 + Shared Packet RAM for multiple Link Layer usage. + 0x3E8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_251 + Shared Packet RAM for multiple Link Layer usage. + 0x3EC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_252 + Shared Packet RAM for multiple Link Layer usage. + 0x3F0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_253 + Shared Packet RAM for multiple Link Layer usage. + 0x3F4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_254 + Shared Packet RAM for multiple Link Layer usage. + 0x3F8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_255 + Shared Packet RAM for multiple Link Layer usage. + 0x3FC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_256 + Shared Packet RAM for multiple Link Layer usage. + 0x400 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_257 + Shared Packet RAM for multiple Link Layer usage. + 0x404 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_258 + Shared Packet RAM for multiple Link Layer usage. + 0x408 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_259 + Shared Packet RAM for multiple Link Layer usage. + 0x40C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_260 + Shared Packet RAM for multiple Link Layer usage. + 0x410 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_261 + Shared Packet RAM for multiple Link Layer usage. + 0x414 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_262 + Shared Packet RAM for multiple Link Layer usage. + 0x418 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_263 + Shared Packet RAM for multiple Link Layer usage. + 0x41C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_264 + Shared Packet RAM for multiple Link Layer usage. + 0x420 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_265 + Shared Packet RAM for multiple Link Layer usage. + 0x424 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_266 + Shared Packet RAM for multiple Link Layer usage. + 0x428 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_267 + Shared Packet RAM for multiple Link Layer usage. + 0x42C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_268 + Shared Packet RAM for multiple Link Layer usage. + 0x430 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_269 + Shared Packet RAM for multiple Link Layer usage. + 0x434 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_270 + Shared Packet RAM for multiple Link Layer usage. + 0x438 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_271 + Shared Packet RAM for multiple Link Layer usage. + 0x43C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_272 + Shared Packet RAM for multiple Link Layer usage. + 0x440 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_273 + Shared Packet RAM for multiple Link Layer usage. + 0x444 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_274 + Shared Packet RAM for multiple Link Layer usage. + 0x448 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_275 + Shared Packet RAM for multiple Link Layer usage. + 0x44C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_276 + Shared Packet RAM for multiple Link Layer usage. + 0x450 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_277 + Shared Packet RAM for multiple Link Layer usage. + 0x454 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_278 + Shared Packet RAM for multiple Link Layer usage. + 0x458 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_279 + Shared Packet RAM for multiple Link Layer usage. + 0x45C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_280 + Shared Packet RAM for multiple Link Layer usage. + 0x460 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_281 + Shared Packet RAM for multiple Link Layer usage. + 0x464 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_282 + Shared Packet RAM for multiple Link Layer usage. + 0x468 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_283 + Shared Packet RAM for multiple Link Layer usage. + 0x46C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_284 + Shared Packet RAM for multiple Link Layer usage. + 0x470 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_285 + Shared Packet RAM for multiple Link Layer usage. + 0x474 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_286 + Shared Packet RAM for multiple Link Layer usage. + 0x478 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_287 + Shared Packet RAM for multiple Link Layer usage. + 0x47C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_288 + Shared Packet RAM for multiple Link Layer usage. + 0x480 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_289 + Shared Packet RAM for multiple Link Layer usage. + 0x484 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_290 + Shared Packet RAM for multiple Link Layer usage. + 0x488 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_291 + Shared Packet RAM for multiple Link Layer usage. + 0x48C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_292 + Shared Packet RAM for multiple Link Layer usage. + 0x490 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_293 + Shared Packet RAM for multiple Link Layer usage. + 0x494 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_294 + Shared Packet RAM for multiple Link Layer usage. + 0x498 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_295 + Shared Packet RAM for multiple Link Layer usage. + 0x49C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_296 + Shared Packet RAM for multiple Link Layer usage. + 0x4A0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_297 + Shared Packet RAM for multiple Link Layer usage. + 0x4A4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_298 + Shared Packet RAM for multiple Link Layer usage. + 0x4A8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_299 + Shared Packet RAM for multiple Link Layer usage. + 0x4AC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_300 + Shared Packet RAM for multiple Link Layer usage. + 0x4B0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_301 + Shared Packet RAM for multiple Link Layer usage. + 0x4B4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_302 + Shared Packet RAM for multiple Link Layer usage. + 0x4B8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_303 + Shared Packet RAM for multiple Link Layer usage. + 0x4BC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_304 + Shared Packet RAM for multiple Link Layer usage. + 0x4C0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_305 + Shared Packet RAM for multiple Link Layer usage. + 0x4C4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_306 + Shared Packet RAM for multiple Link Layer usage. + 0x4C8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_307 + Shared Packet RAM for multiple Link Layer usage. + 0x4CC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_308 + Shared Packet RAM for multiple Link Layer usage. + 0x4D0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_309 + Shared Packet RAM for multiple Link Layer usage. + 0x4D4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_310 + Shared Packet RAM for multiple Link Layer usage. + 0x4D8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_311 + Shared Packet RAM for multiple Link Layer usage. + 0x4DC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_312 + Shared Packet RAM for multiple Link Layer usage. + 0x4E0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_313 + Shared Packet RAM for multiple Link Layer usage. + 0x4E4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_314 + Shared Packet RAM for multiple Link Layer usage. + 0x4E8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_315 + Shared Packet RAM for multiple Link Layer usage. + 0x4EC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_316 + Shared Packet RAM for multiple Link Layer usage. + 0x4F0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_317 + Shared Packet RAM for multiple Link Layer usage. + 0x4F4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_318 + Shared Packet RAM for multiple Link Layer usage. + 0x4F8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_319 + Shared Packet RAM for multiple Link Layer usage. + 0x4FC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_320 + Shared Packet RAM for multiple Link Layer usage. + 0x500 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_321 + Shared Packet RAM for multiple Link Layer usage. + 0x504 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_322 + Shared Packet RAM for multiple Link Layer usage. + 0x508 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_323 + Shared Packet RAM for multiple Link Layer usage. + 0x50C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_324 + Shared Packet RAM for multiple Link Layer usage. + 0x510 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_325 + Shared Packet RAM for multiple Link Layer usage. + 0x514 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_326 + Shared Packet RAM for multiple Link Layer usage. + 0x518 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_327 + Shared Packet RAM for multiple Link Layer usage. + 0x51C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_328 + Shared Packet RAM for multiple Link Layer usage. + 0x520 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_329 + Shared Packet RAM for multiple Link Layer usage. + 0x524 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_330 + Shared Packet RAM for multiple Link Layer usage. + 0x528 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_331 + Shared Packet RAM for multiple Link Layer usage. + 0x52C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_332 + Shared Packet RAM for multiple Link Layer usage. + 0x530 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_333 + Shared Packet RAM for multiple Link Layer usage. + 0x534 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_334 + Shared Packet RAM for multiple Link Layer usage. + 0x538 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_335 + Shared Packet RAM for multiple Link Layer usage. + 0x53C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_336 + Shared Packet RAM for multiple Link Layer usage. + 0x540 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_337 + Shared Packet RAM for multiple Link Layer usage. + 0x544 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_338 + Shared Packet RAM for multiple Link Layer usage. + 0x548 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_339 + Shared Packet RAM for multiple Link Layer usage. + 0x54C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_340 + Shared Packet RAM for multiple Link Layer usage. + 0x550 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_341 + Shared Packet RAM for multiple Link Layer usage. + 0x554 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_342 + Shared Packet RAM for multiple Link Layer usage. + 0x558 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_343 + Shared Packet RAM for multiple Link Layer usage. + 0x55C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_344 + Shared Packet RAM for multiple Link Layer usage. + 0x560 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_345 + Shared Packet RAM for multiple Link Layer usage. + 0x564 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_346 + Shared Packet RAM for multiple Link Layer usage. + 0x568 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_347 + Shared Packet RAM for multiple Link Layer usage. + 0x56C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_348 + Shared Packet RAM for multiple Link Layer usage. + 0x570 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_349 + Shared Packet RAM for multiple Link Layer usage. + 0x574 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_350 + Shared Packet RAM for multiple Link Layer usage. + 0x578 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_351 + Shared Packet RAM for multiple Link Layer usage. + 0x57C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_352 + Shared Packet RAM for multiple Link Layer usage. + 0x580 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_353 + Shared Packet RAM for multiple Link Layer usage. + 0x584 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_354 + Shared Packet RAM for multiple Link Layer usage. + 0x588 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_355 + Shared Packet RAM for multiple Link Layer usage. + 0x58C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_356 + Shared Packet RAM for multiple Link Layer usage. + 0x590 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_357 + Shared Packet RAM for multiple Link Layer usage. + 0x594 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_358 + Shared Packet RAM for multiple Link Layer usage. + 0x598 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_359 + Shared Packet RAM for multiple Link Layer usage. + 0x59C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_360 + Shared Packet RAM for multiple Link Layer usage. + 0x5A0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_361 + Shared Packet RAM for multiple Link Layer usage. + 0x5A4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_362 + Shared Packet RAM for multiple Link Layer usage. + 0x5A8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_363 + Shared Packet RAM for multiple Link Layer usage. + 0x5AC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_364 + Shared Packet RAM for multiple Link Layer usage. + 0x5B0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_365 + Shared Packet RAM for multiple Link Layer usage. + 0x5B4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_366 + Shared Packet RAM for multiple Link Layer usage. + 0x5B8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_367 + Shared Packet RAM for multiple Link Layer usage. + 0x5BC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_368 + Shared Packet RAM for multiple Link Layer usage. + 0x5C0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_369 + Shared Packet RAM for multiple Link Layer usage. + 0x5C4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_370 + Shared Packet RAM for multiple Link Layer usage. + 0x5C8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_371 + Shared Packet RAM for multiple Link Layer usage. + 0x5CC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_372 + Shared Packet RAM for multiple Link Layer usage. + 0x5D0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_373 + Shared Packet RAM for multiple Link Layer usage. + 0x5D4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_374 + Shared Packet RAM for multiple Link Layer usage. + 0x5D8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_375 + Shared Packet RAM for multiple Link Layer usage. + 0x5DC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_376 + Shared Packet RAM for multiple Link Layer usage. + 0x5E0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_377 + Shared Packet RAM for multiple Link Layer usage. + 0x5E4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_378 + Shared Packet RAM for multiple Link Layer usage. + 0x5E8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_379 + Shared Packet RAM for multiple Link Layer usage. + 0x5EC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_380 + Shared Packet RAM for multiple Link Layer usage. + 0x5F0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_381 + Shared Packet RAM for multiple Link Layer usage. + 0x5F4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_382 + Shared Packet RAM for multiple Link Layer usage. + 0x5F8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_383 + Shared Packet RAM for multiple Link Layer usage. + 0x5FC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_384 + Shared Packet RAM for multiple Link Layer usage. + 0x600 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_385 + Shared Packet RAM for multiple Link Layer usage. + 0x604 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_386 + Shared Packet RAM for multiple Link Layer usage. + 0x608 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_387 + Shared Packet RAM for multiple Link Layer usage. + 0x60C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_388 + Shared Packet RAM for multiple Link Layer usage. + 0x610 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_389 + Shared Packet RAM for multiple Link Layer usage. + 0x614 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_390 + Shared Packet RAM for multiple Link Layer usage. + 0x618 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_391 + Shared Packet RAM for multiple Link Layer usage. + 0x61C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_392 + Shared Packet RAM for multiple Link Layer usage. + 0x620 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_393 + Shared Packet RAM for multiple Link Layer usage. + 0x624 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_394 + Shared Packet RAM for multiple Link Layer usage. + 0x628 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_395 + Shared Packet RAM for multiple Link Layer usage. + 0x62C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_396 + Shared Packet RAM for multiple Link Layer usage. + 0x630 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_397 + Shared Packet RAM for multiple Link Layer usage. + 0x634 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_398 + Shared Packet RAM for multiple Link Layer usage. + 0x638 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_399 + Shared Packet RAM for multiple Link Layer usage. + 0x63C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_400 + Shared Packet RAM for multiple Link Layer usage. + 0x640 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_401 + Shared Packet RAM for multiple Link Layer usage. + 0x644 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_402 + Shared Packet RAM for multiple Link Layer usage. + 0x648 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_403 + Shared Packet RAM for multiple Link Layer usage. + 0x64C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_404 + Shared Packet RAM for multiple Link Layer usage. + 0x650 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_405 + Shared Packet RAM for multiple Link Layer usage. + 0x654 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_406 + Shared Packet RAM for multiple Link Layer usage. + 0x658 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_407 + Shared Packet RAM for multiple Link Layer usage. + 0x65C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_408 + Shared Packet RAM for multiple Link Layer usage. + 0x660 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_409 + Shared Packet RAM for multiple Link Layer usage. + 0x664 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_410 + Shared Packet RAM for multiple Link Layer usage. + 0x668 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_411 + Shared Packet RAM for multiple Link Layer usage. + 0x66C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_412 + Shared Packet RAM for multiple Link Layer usage. + 0x670 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_413 + Shared Packet RAM for multiple Link Layer usage. + 0x674 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_414 + Shared Packet RAM for multiple Link Layer usage. + 0x678 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_415 + Shared Packet RAM for multiple Link Layer usage. + 0x67C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_416 + Shared Packet RAM for multiple Link Layer usage. + 0x680 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_417 + Shared Packet RAM for multiple Link Layer usage. + 0x684 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_418 + Shared Packet RAM for multiple Link Layer usage. + 0x688 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_419 + Shared Packet RAM for multiple Link Layer usage. + 0x68C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_420 + Shared Packet RAM for multiple Link Layer usage. + 0x690 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_421 + Shared Packet RAM for multiple Link Layer usage. + 0x694 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_422 + Shared Packet RAM for multiple Link Layer usage. + 0x698 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_423 + Shared Packet RAM for multiple Link Layer usage. + 0x69C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_424 + Shared Packet RAM for multiple Link Layer usage. + 0x6A0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_425 + Shared Packet RAM for multiple Link Layer usage. + 0x6A4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_426 + Shared Packet RAM for multiple Link Layer usage. + 0x6A8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_427 + Shared Packet RAM for multiple Link Layer usage. + 0x6AC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_428 + Shared Packet RAM for multiple Link Layer usage. + 0x6B0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_429 + Shared Packet RAM for multiple Link Layer usage. + 0x6B4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_430 + Shared Packet RAM for multiple Link Layer usage. + 0x6B8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_431 + Shared Packet RAM for multiple Link Layer usage. + 0x6BC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_432 + Shared Packet RAM for multiple Link Layer usage. + 0x6C0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_433 + Shared Packet RAM for multiple Link Layer usage. + 0x6C4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_434 + Shared Packet RAM for multiple Link Layer usage. + 0x6C8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_435 + Shared Packet RAM for multiple Link Layer usage. + 0x6CC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_436 + Shared Packet RAM for multiple Link Layer usage. + 0x6D0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_437 + Shared Packet RAM for multiple Link Layer usage. + 0x6D4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_438 + Shared Packet RAM for multiple Link Layer usage. + 0x6D8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_439 + Shared Packet RAM for multiple Link Layer usage. + 0x6DC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_440 + Shared Packet RAM for multiple Link Layer usage. + 0x6E0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_441 + Shared Packet RAM for multiple Link Layer usage. + 0x6E4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_442 + Shared Packet RAM for multiple Link Layer usage. + 0x6E8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_443 + Shared Packet RAM for multiple Link Layer usage. + 0x6EC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_444 + Shared Packet RAM for multiple Link Layer usage. + 0x6F0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_445 + Shared Packet RAM for multiple Link Layer usage. + 0x6F4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_446 + Shared Packet RAM for multiple Link Layer usage. + 0x6F8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_447 + Shared Packet RAM for multiple Link Layer usage. + 0x6FC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_448 + Shared Packet RAM for multiple Link Layer usage. + 0x700 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_449 + Shared Packet RAM for multiple Link Layer usage. + 0x704 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_450 + Shared Packet RAM for multiple Link Layer usage. + 0x708 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_451 + Shared Packet RAM for multiple Link Layer usage. + 0x70C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_452 + Shared Packet RAM for multiple Link Layer usage. + 0x710 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_453 + Shared Packet RAM for multiple Link Layer usage. + 0x714 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_454 + Shared Packet RAM for multiple Link Layer usage. + 0x718 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_455 + Shared Packet RAM for multiple Link Layer usage. + 0x71C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_456 + Shared Packet RAM for multiple Link Layer usage. + 0x720 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_457 + Shared Packet RAM for multiple Link Layer usage. + 0x724 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_458 + Shared Packet RAM for multiple Link Layer usage. + 0x728 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_459 + Shared Packet RAM for multiple Link Layer usage. + 0x72C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_460 + Shared Packet RAM for multiple Link Layer usage. + 0x730 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_461 + Shared Packet RAM for multiple Link Layer usage. + 0x734 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_462 + Shared Packet RAM for multiple Link Layer usage. + 0x738 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_463 + Shared Packet RAM for multiple Link Layer usage. + 0x73C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_464 + Shared Packet RAM for multiple Link Layer usage. + 0x740 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_465 + Shared Packet RAM for multiple Link Layer usage. + 0x744 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_466 + Shared Packet RAM for multiple Link Layer usage. + 0x748 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_467 + Shared Packet RAM for multiple Link Layer usage. + 0x74C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_468 + Shared Packet RAM for multiple Link Layer usage. + 0x750 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_469 + Shared Packet RAM for multiple Link Layer usage. + 0x754 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_470 + Shared Packet RAM for multiple Link Layer usage. + 0x758 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_471 + Shared Packet RAM for multiple Link Layer usage. + 0x75C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_472 + Shared Packet RAM for multiple Link Layer usage. + 0x760 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_473 + Shared Packet RAM for multiple Link Layer usage. + 0x764 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_474 + Shared Packet RAM for multiple Link Layer usage. + 0x768 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_475 + Shared Packet RAM for multiple Link Layer usage. + 0x76C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_476 + Shared Packet RAM for multiple Link Layer usage. + 0x770 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_477 + Shared Packet RAM for multiple Link Layer usage. + 0x774 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_478 + Shared Packet RAM for multiple Link Layer usage. + 0x778 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_479 + Shared Packet RAM for multiple Link Layer usage. + 0x77C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_480 + Shared Packet RAM for multiple Link Layer usage. + 0x780 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_481 + Shared Packet RAM for multiple Link Layer usage. + 0x784 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_482 + Shared Packet RAM for multiple Link Layer usage. + 0x788 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_483 + Shared Packet RAM for multiple Link Layer usage. + 0x78C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_484 + Shared Packet RAM for multiple Link Layer usage. + 0x790 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_485 + Shared Packet RAM for multiple Link Layer usage. + 0x794 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_486 + Shared Packet RAM for multiple Link Layer usage. + 0x798 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_487 + Shared Packet RAM for multiple Link Layer usage. + 0x79C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_488 + Shared Packet RAM for multiple Link Layer usage. + 0x7A0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_489 + Shared Packet RAM for multiple Link Layer usage. + 0x7A4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_490 + Shared Packet RAM for multiple Link Layer usage. + 0x7A8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_491 + Shared Packet RAM for multiple Link Layer usage. + 0x7AC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_492 + Shared Packet RAM for multiple Link Layer usage. + 0x7B0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_493 + Shared Packet RAM for multiple Link Layer usage. + 0x7B4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_494 + Shared Packet RAM for multiple Link Layer usage. + 0x7B8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_495 + Shared Packet RAM for multiple Link Layer usage. + 0x7BC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_496 + Shared Packet RAM for multiple Link Layer usage. + 0x7C0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_497 + Shared Packet RAM for multiple Link Layer usage. + 0x7C4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_498 + Shared Packet RAM for multiple Link Layer usage. + 0x7C8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_499 + Shared Packet RAM for multiple Link Layer usage. + 0x7CC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_500 + Shared Packet RAM for multiple Link Layer usage. + 0x7D0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_501 + Shared Packet RAM for multiple Link Layer usage. + 0x7D4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_502 + Shared Packet RAM for multiple Link Layer usage. + 0x7D8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_503 + Shared Packet RAM for multiple Link Layer usage. + 0x7DC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_504 + Shared Packet RAM for multiple Link Layer usage. + 0x7E0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_505 + Shared Packet RAM for multiple Link Layer usage. + 0x7E4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_506 + Shared Packet RAM for multiple Link Layer usage. + 0x7E8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_507 + Shared Packet RAM for multiple Link Layer usage. + 0x7EC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_508 + Shared Packet RAM for multiple Link Layer usage. + 0x7F0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_509 + Shared Packet RAM for multiple Link Layer usage. + 0x7F4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_510 + Shared Packet RAM for multiple Link Layer usage. + 0x7F8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_511 + Shared Packet RAM for multiple Link Layer usage. + 0x7FC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_512 + Shared Packet RAM for multiple Link Layer usage. + 0x800 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_513 + Shared Packet RAM for multiple Link Layer usage. + 0x804 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_514 + Shared Packet RAM for multiple Link Layer usage. + 0x808 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_515 + Shared Packet RAM for multiple Link Layer usage. + 0x80C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_516 + Shared Packet RAM for multiple Link Layer usage. + 0x810 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_517 + Shared Packet RAM for multiple Link Layer usage. + 0x814 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_518 + Shared Packet RAM for multiple Link Layer usage. + 0x818 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_519 + Shared Packet RAM for multiple Link Layer usage. + 0x81C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_520 + Shared Packet RAM for multiple Link Layer usage. + 0x820 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_521 + Shared Packet RAM for multiple Link Layer usage. + 0x824 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_522 + Shared Packet RAM for multiple Link Layer usage. + 0x828 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_523 + Shared Packet RAM for multiple Link Layer usage. + 0x82C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_524 + Shared Packet RAM for multiple Link Layer usage. + 0x830 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_525 + Shared Packet RAM for multiple Link Layer usage. + 0x834 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_526 + Shared Packet RAM for multiple Link Layer usage. + 0x838 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_527 + Shared Packet RAM for multiple Link Layer usage. + 0x83C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_528 + Shared Packet RAM for multiple Link Layer usage. + 0x840 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_529 + Shared Packet RAM for multiple Link Layer usage. + 0x844 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_530 + Shared Packet RAM for multiple Link Layer usage. + 0x848 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_531 + Shared Packet RAM for multiple Link Layer usage. + 0x84C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_532 + Shared Packet RAM for multiple Link Layer usage. + 0x850 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_533 + Shared Packet RAM for multiple Link Layer usage. + 0x854 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_534 + Shared Packet RAM for multiple Link Layer usage. + 0x858 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_535 + Shared Packet RAM for multiple Link Layer usage. + 0x85C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_536 + Shared Packet RAM for multiple Link Layer usage. + 0x860 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_537 + Shared Packet RAM for multiple Link Layer usage. + 0x864 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_538 + Shared Packet RAM for multiple Link Layer usage. + 0x868 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_539 + Shared Packet RAM for multiple Link Layer usage. + 0x86C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_540 + Shared Packet RAM for multiple Link Layer usage. + 0x870 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_541 + Shared Packet RAM for multiple Link Layer usage. + 0x874 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_542 + Shared Packet RAM for multiple Link Layer usage. + 0x878 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_543 + Shared Packet RAM for multiple Link Layer usage. + 0x87C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_544 + Shared Packet RAM for multiple Link Layer usage. + 0x880 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_545 + Shared Packet RAM for multiple Link Layer usage. + 0x884 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_546 + Shared Packet RAM for multiple Link Layer usage. + 0x888 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_547 + Shared Packet RAM for multiple Link Layer usage. + 0x88C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_548 + Shared Packet RAM for multiple Link Layer usage. + 0x890 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_549 + Shared Packet RAM for multiple Link Layer usage. + 0x894 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_550 + Shared Packet RAM for multiple Link Layer usage. + 0x898 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_551 + Shared Packet RAM for multiple Link Layer usage. + 0x89C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_552 + Shared Packet RAM for multiple Link Layer usage. + 0x8A0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_553 + Shared Packet RAM for multiple Link Layer usage. + 0x8A4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_554 + Shared Packet RAM for multiple Link Layer usage. + 0x8A8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_555 + Shared Packet RAM for multiple Link Layer usage. + 0x8AC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_556 + Shared Packet RAM for multiple Link Layer usage. + 0x8B0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_557 + Shared Packet RAM for multiple Link Layer usage. + 0x8B4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_558 + Shared Packet RAM for multiple Link Layer usage. + 0x8B8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_559 + Shared Packet RAM for multiple Link Layer usage. + 0x8BC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_560 + Shared Packet RAM for multiple Link Layer usage. + 0x8C0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_561 + Shared Packet RAM for multiple Link Layer usage. + 0x8C4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_562 + Shared Packet RAM for multiple Link Layer usage. + 0x8C8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_563 + Shared Packet RAM for multiple Link Layer usage. + 0x8CC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_564 + Shared Packet RAM for multiple Link Layer usage. + 0x8D0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_565 + Shared Packet RAM for multiple Link Layer usage. + 0x8D4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_566 + Shared Packet RAM for multiple Link Layer usage. + 0x8D8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_567 + Shared Packet RAM for multiple Link Layer usage. + 0x8DC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_568 + Shared Packet RAM for multiple Link Layer usage. + 0x8E0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_569 + Shared Packet RAM for multiple Link Layer usage. + 0x8E4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_570 + Shared Packet RAM for multiple Link Layer usage. + 0x8E8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_571 + Shared Packet RAM for multiple Link Layer usage. + 0x8EC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_572 + Shared Packet RAM for multiple Link Layer usage. + 0x8F0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_573 + Shared Packet RAM for multiple Link Layer usage. + 0x8F4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_574 + Shared Packet RAM for multiple Link Layer usage. + 0x8F8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_575 + Shared Packet RAM for multiple Link Layer usage. + 0x8FC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_576 + Shared Packet RAM for multiple Link Layer usage. + 0x900 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_577 + Shared Packet RAM for multiple Link Layer usage. + 0x904 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_578 + Shared Packet RAM for multiple Link Layer usage. + 0x908 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_579 + Shared Packet RAM for multiple Link Layer usage. + 0x90C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_580 + Shared Packet RAM for multiple Link Layer usage. + 0x910 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_581 + Shared Packet RAM for multiple Link Layer usage. + 0x914 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_582 + Shared Packet RAM for multiple Link Layer usage. + 0x918 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_583 + Shared Packet RAM for multiple Link Layer usage. + 0x91C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_584 + Shared Packet RAM for multiple Link Layer usage. + 0x920 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_585 + Shared Packet RAM for multiple Link Layer usage. + 0x924 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_586 + Shared Packet RAM for multiple Link Layer usage. + 0x928 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_587 + Shared Packet RAM for multiple Link Layer usage. + 0x92C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_588 + Shared Packet RAM for multiple Link Layer usage. + 0x930 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_589 + Shared Packet RAM for multiple Link Layer usage. + 0x934 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_590 + Shared Packet RAM for multiple Link Layer usage. + 0x938 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_591 + Shared Packet RAM for multiple Link Layer usage. + 0x93C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_592 + Shared Packet RAM for multiple Link Layer usage. + 0x940 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_593 + Shared Packet RAM for multiple Link Layer usage. + 0x944 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_594 + Shared Packet RAM for multiple Link Layer usage. + 0x948 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_595 + Shared Packet RAM for multiple Link Layer usage. + 0x94C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_596 + Shared Packet RAM for multiple Link Layer usage. + 0x950 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_597 + Shared Packet RAM for multiple Link Layer usage. + 0x954 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_598 + Shared Packet RAM for multiple Link Layer usage. + 0x958 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_599 + Shared Packet RAM for multiple Link Layer usage. + 0x95C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_600 + Shared Packet RAM for multiple Link Layer usage. + 0x960 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_601 + Shared Packet RAM for multiple Link Layer usage. + 0x964 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_602 + Shared Packet RAM for multiple Link Layer usage. + 0x968 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_603 + Shared Packet RAM for multiple Link Layer usage. + 0x96C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_604 + Shared Packet RAM for multiple Link Layer usage. + 0x970 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_605 + Shared Packet RAM for multiple Link Layer usage. + 0x974 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_606 + Shared Packet RAM for multiple Link Layer usage. + 0x978 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_607 + Shared Packet RAM for multiple Link Layer usage. + 0x97C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_608 + Shared Packet RAM for multiple Link Layer usage. + 0x980 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_609 + Shared Packet RAM for multiple Link Layer usage. + 0x984 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_610 + Shared Packet RAM for multiple Link Layer usage. + 0x988 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_611 + Shared Packet RAM for multiple Link Layer usage. + 0x98C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_612 + Shared Packet RAM for multiple Link Layer usage. + 0x990 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_613 + Shared Packet RAM for multiple Link Layer usage. + 0x994 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_614 + Shared Packet RAM for multiple Link Layer usage. + 0x998 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_615 + Shared Packet RAM for multiple Link Layer usage. + 0x99C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_616 + Shared Packet RAM for multiple Link Layer usage. + 0x9A0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_617 + Shared Packet RAM for multiple Link Layer usage. + 0x9A4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_618 + Shared Packet RAM for multiple Link Layer usage. + 0x9A8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_619 + Shared Packet RAM for multiple Link Layer usage. + 0x9AC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_620 + Shared Packet RAM for multiple Link Layer usage. + 0x9B0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_621 + Shared Packet RAM for multiple Link Layer usage. + 0x9B4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_622 + Shared Packet RAM for multiple Link Layer usage. + 0x9B8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_623 + Shared Packet RAM for multiple Link Layer usage. + 0x9BC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_624 + Shared Packet RAM for multiple Link Layer usage. + 0x9C0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_625 + Shared Packet RAM for multiple Link Layer usage. + 0x9C4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_626 + Shared Packet RAM for multiple Link Layer usage. + 0x9C8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_627 + Shared Packet RAM for multiple Link Layer usage. + 0x9CC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_628 + Shared Packet RAM for multiple Link Layer usage. + 0x9D0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_629 + Shared Packet RAM for multiple Link Layer usage. + 0x9D4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_630 + Shared Packet RAM for multiple Link Layer usage. + 0x9D8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_631 + Shared Packet RAM for multiple Link Layer usage. + 0x9DC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_632 + Shared Packet RAM for multiple Link Layer usage. + 0x9E0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_633 + Shared Packet RAM for multiple Link Layer usage. + 0x9E4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_634 + Shared Packet RAM for multiple Link Layer usage. + 0x9E8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_635 + Shared Packet RAM for multiple Link Layer usage. + 0x9EC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_636 + Shared Packet RAM for multiple Link Layer usage. + 0x9F0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_637 + Shared Packet RAM for multiple Link Layer usage. + 0x9F4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_638 + Shared Packet RAM for multiple Link Layer usage. + 0x9F8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_639 + Shared Packet RAM for multiple Link Layer usage. + 0x9FC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_640 + Shared Packet RAM for multiple Link Layer usage. + 0xA00 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_641 + Shared Packet RAM for multiple Link Layer usage. + 0xA04 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_642 + Shared Packet RAM for multiple Link Layer usage. + 0xA08 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_643 + Shared Packet RAM for multiple Link Layer usage. + 0xA0C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_644 + Shared Packet RAM for multiple Link Layer usage. + 0xA10 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_645 + Shared Packet RAM for multiple Link Layer usage. + 0xA14 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_646 + Shared Packet RAM for multiple Link Layer usage. + 0xA18 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_647 + Shared Packet RAM for multiple Link Layer usage. + 0xA1C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_648 + Shared Packet RAM for multiple Link Layer usage. + 0xA20 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_649 + Shared Packet RAM for multiple Link Layer usage. + 0xA24 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_650 + Shared Packet RAM for multiple Link Layer usage. + 0xA28 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_651 + Shared Packet RAM for multiple Link Layer usage. + 0xA2C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_652 + Shared Packet RAM for multiple Link Layer usage. + 0xA30 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_653 + Shared Packet RAM for multiple Link Layer usage. + 0xA34 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_654 + Shared Packet RAM for multiple Link Layer usage. + 0xA38 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_655 + Shared Packet RAM for multiple Link Layer usage. + 0xA3C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_656 + Shared Packet RAM for multiple Link Layer usage. + 0xA40 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_657 + Shared Packet RAM for multiple Link Layer usage. + 0xA44 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_658 + Shared Packet RAM for multiple Link Layer usage. + 0xA48 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_659 + Shared Packet RAM for multiple Link Layer usage. + 0xA4C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_660 + Shared Packet RAM for multiple Link Layer usage. + 0xA50 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_661 + Shared Packet RAM for multiple Link Layer usage. + 0xA54 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_662 + Shared Packet RAM for multiple Link Layer usage. + 0xA58 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_663 + Shared Packet RAM for multiple Link Layer usage. + 0xA5C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_664 + Shared Packet RAM for multiple Link Layer usage. + 0xA60 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_665 + Shared Packet RAM for multiple Link Layer usage. + 0xA64 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_666 + Shared Packet RAM for multiple Link Layer usage. + 0xA68 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_667 + Shared Packet RAM for multiple Link Layer usage. + 0xA6C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_668 + Shared Packet RAM for multiple Link Layer usage. + 0xA70 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_669 + Shared Packet RAM for multiple Link Layer usage. + 0xA74 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_670 + Shared Packet RAM for multiple Link Layer usage. + 0xA78 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_671 + Shared Packet RAM for multiple Link Layer usage. + 0xA7C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_672 + Shared Packet RAM for multiple Link Layer usage. + 0xA80 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_673 + Shared Packet RAM for multiple Link Layer usage. + 0xA84 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_674 + Shared Packet RAM for multiple Link Layer usage. + 0xA88 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_675 + Shared Packet RAM for multiple Link Layer usage. + 0xA8C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_676 + Shared Packet RAM for multiple Link Layer usage. + 0xA90 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_677 + Shared Packet RAM for multiple Link Layer usage. + 0xA94 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_678 + Shared Packet RAM for multiple Link Layer usage. + 0xA98 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_679 + Shared Packet RAM for multiple Link Layer usage. + 0xA9C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_680 + Shared Packet RAM for multiple Link Layer usage. + 0xAA0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_681 + Shared Packet RAM for multiple Link Layer usage. + 0xAA4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_682 + Shared Packet RAM for multiple Link Layer usage. + 0xAA8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_683 + Shared Packet RAM for multiple Link Layer usage. + 0xAAC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_684 + Shared Packet RAM for multiple Link Layer usage. + 0xAB0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_685 + Shared Packet RAM for multiple Link Layer usage. + 0xAB4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_686 + Shared Packet RAM for multiple Link Layer usage. + 0xAB8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_687 + Shared Packet RAM for multiple Link Layer usage. + 0xABC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_688 + Shared Packet RAM for multiple Link Layer usage. + 0xAC0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_689 + Shared Packet RAM for multiple Link Layer usage. + 0xAC4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_690 + Shared Packet RAM for multiple Link Layer usage. + 0xAC8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_691 + Shared Packet RAM for multiple Link Layer usage. + 0xACC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_692 + Shared Packet RAM for multiple Link Layer usage. + 0xAD0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_693 + Shared Packet RAM for multiple Link Layer usage. + 0xAD4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_694 + Shared Packet RAM for multiple Link Layer usage. + 0xAD8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_695 + Shared Packet RAM for multiple Link Layer usage. + 0xADC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_696 + Shared Packet RAM for multiple Link Layer usage. + 0xAE0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_697 + Shared Packet RAM for multiple Link Layer usage. + 0xAE4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_698 + Shared Packet RAM for multiple Link Layer usage. + 0xAE8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_699 + Shared Packet RAM for multiple Link Layer usage. + 0xAEC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_700 + Shared Packet RAM for multiple Link Layer usage. + 0xAF0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_701 + Shared Packet RAM for multiple Link Layer usage. + 0xAF4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_702 + Shared Packet RAM for multiple Link Layer usage. + 0xAF8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_703 + Shared Packet RAM for multiple Link Layer usage. + 0xAFC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_704 + Shared Packet RAM for multiple Link Layer usage. + 0xB00 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_705 + Shared Packet RAM for multiple Link Layer usage. + 0xB04 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_706 + Shared Packet RAM for multiple Link Layer usage. + 0xB08 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_707 + Shared Packet RAM for multiple Link Layer usage. + 0xB0C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_708 + Shared Packet RAM for multiple Link Layer usage. + 0xB10 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_709 + Shared Packet RAM for multiple Link Layer usage. + 0xB14 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_710 + Shared Packet RAM for multiple Link Layer usage. + 0xB18 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_711 + Shared Packet RAM for multiple Link Layer usage. + 0xB1C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_712 + Shared Packet RAM for multiple Link Layer usage. + 0xB20 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_713 + Shared Packet RAM for multiple Link Layer usage. + 0xB24 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_714 + Shared Packet RAM for multiple Link Layer usage. + 0xB28 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_715 + Shared Packet RAM for multiple Link Layer usage. + 0xB2C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_716 + Shared Packet RAM for multiple Link Layer usage. + 0xB30 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_717 + Shared Packet RAM for multiple Link Layer usage. + 0xB34 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_718 + Shared Packet RAM for multiple Link Layer usage. + 0xB38 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_719 + Shared Packet RAM for multiple Link Layer usage. + 0xB3C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_720 + Shared Packet RAM for multiple Link Layer usage. + 0xB40 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_721 + Shared Packet RAM for multiple Link Layer usage. + 0xB44 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_722 + Shared Packet RAM for multiple Link Layer usage. + 0xB48 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_723 + Shared Packet RAM for multiple Link Layer usage. + 0xB4C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_724 + Shared Packet RAM for multiple Link Layer usage. + 0xB50 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_725 + Shared Packet RAM for multiple Link Layer usage. + 0xB54 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_726 + Shared Packet RAM for multiple Link Layer usage. + 0xB58 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_727 + Shared Packet RAM for multiple Link Layer usage. + 0xB5C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_728 + Shared Packet RAM for multiple Link Layer usage. + 0xB60 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_729 + Shared Packet RAM for multiple Link Layer usage. + 0xB64 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_730 + Shared Packet RAM for multiple Link Layer usage. + 0xB68 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_731 + Shared Packet RAM for multiple Link Layer usage. + 0xB6C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_732 + Shared Packet RAM for multiple Link Layer usage. + 0xB70 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_733 + Shared Packet RAM for multiple Link Layer usage. + 0xB74 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_734 + Shared Packet RAM for multiple Link Layer usage. + 0xB78 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_735 + Shared Packet RAM for multiple Link Layer usage. + 0xB7C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_736 + Shared Packet RAM for multiple Link Layer usage. + 0xB80 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_737 + Shared Packet RAM for multiple Link Layer usage. + 0xB84 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_738 + Shared Packet RAM for multiple Link Layer usage. + 0xB88 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_739 + Shared Packet RAM for multiple Link Layer usage. + 0xB8C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_740 + Shared Packet RAM for multiple Link Layer usage. + 0xB90 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_741 + Shared Packet RAM for multiple Link Layer usage. + 0xB94 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_742 + Shared Packet RAM for multiple Link Layer usage. + 0xB98 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_743 + Shared Packet RAM for multiple Link Layer usage. + 0xB9C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_744 + Shared Packet RAM for multiple Link Layer usage. + 0xBA0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_745 + Shared Packet RAM for multiple Link Layer usage. + 0xBA4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_746 + Shared Packet RAM for multiple Link Layer usage. + 0xBA8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_747 + Shared Packet RAM for multiple Link Layer usage. + 0xBAC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_748 + Shared Packet RAM for multiple Link Layer usage. + 0xBB0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_749 + Shared Packet RAM for multiple Link Layer usage. + 0xBB4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_750 + Shared Packet RAM for multiple Link Layer usage. + 0xBB8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_751 + Shared Packet RAM for multiple Link Layer usage. + 0xBBC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_752 + Shared Packet RAM for multiple Link Layer usage. + 0xBC0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_753 + Shared Packet RAM for multiple Link Layer usage. + 0xBC4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_754 + Shared Packet RAM for multiple Link Layer usage. + 0xBC8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_755 + Shared Packet RAM for multiple Link Layer usage. + 0xBCC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_756 + Shared Packet RAM for multiple Link Layer usage. + 0xBD0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_757 + Shared Packet RAM for multiple Link Layer usage. + 0xBD4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_758 + Shared Packet RAM for multiple Link Layer usage. + 0xBD8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_759 + Shared Packet RAM for multiple Link Layer usage. + 0xBDC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_760 + Shared Packet RAM for multiple Link Layer usage. + 0xBE0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_761 + Shared Packet RAM for multiple Link Layer usage. + 0xBE4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_762 + Shared Packet RAM for multiple Link Layer usage. + 0xBE8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_763 + Shared Packet RAM for multiple Link Layer usage. + 0xBEC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_764 + Shared Packet RAM for multiple Link Layer usage. + 0xBF0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_765 + Shared Packet RAM for multiple Link Layer usage. + 0xBF4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_766 + Shared Packet RAM for multiple Link Layer usage. + 0xBF8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_767 + Shared Packet RAM for multiple Link Layer usage. + 0xBFC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_768 + Shared Packet RAM for multiple Link Layer usage. + 0xC00 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_769 + Shared Packet RAM for multiple Link Layer usage. + 0xC04 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_770 + Shared Packet RAM for multiple Link Layer usage. + 0xC08 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_771 + Shared Packet RAM for multiple Link Layer usage. + 0xC0C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_772 + Shared Packet RAM for multiple Link Layer usage. + 0xC10 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_773 + Shared Packet RAM for multiple Link Layer usage. + 0xC14 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_774 + Shared Packet RAM for multiple Link Layer usage. + 0xC18 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_775 + Shared Packet RAM for multiple Link Layer usage. + 0xC1C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_776 + Shared Packet RAM for multiple Link Layer usage. + 0xC20 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_777 + Shared Packet RAM for multiple Link Layer usage. + 0xC24 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_778 + Shared Packet RAM for multiple Link Layer usage. + 0xC28 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_779 + Shared Packet RAM for multiple Link Layer usage. + 0xC2C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_780 + Shared Packet RAM for multiple Link Layer usage. + 0xC30 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_781 + Shared Packet RAM for multiple Link Layer usage. + 0xC34 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_782 + Shared Packet RAM for multiple Link Layer usage. + 0xC38 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_783 + Shared Packet RAM for multiple Link Layer usage. + 0xC3C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_784 + Shared Packet RAM for multiple Link Layer usage. + 0xC40 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_785 + Shared Packet RAM for multiple Link Layer usage. + 0xC44 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_786 + Shared Packet RAM for multiple Link Layer usage. + 0xC48 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_787 + Shared Packet RAM for multiple Link Layer usage. + 0xC4C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_788 + Shared Packet RAM for multiple Link Layer usage. + 0xC50 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_789 + Shared Packet RAM for multiple Link Layer usage. + 0xC54 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_790 + Shared Packet RAM for multiple Link Layer usage. + 0xC58 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_791 + Shared Packet RAM for multiple Link Layer usage. + 0xC5C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_792 + Shared Packet RAM for multiple Link Layer usage. + 0xC60 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_793 + Shared Packet RAM for multiple Link Layer usage. + 0xC64 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_794 + Shared Packet RAM for multiple Link Layer usage. + 0xC68 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_795 + Shared Packet RAM for multiple Link Layer usage. + 0xC6C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_796 + Shared Packet RAM for multiple Link Layer usage. + 0xC70 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_797 + Shared Packet RAM for multiple Link Layer usage. + 0xC74 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_798 + Shared Packet RAM for multiple Link Layer usage. + 0xC78 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_799 + Shared Packet RAM for multiple Link Layer usage. + 0xC7C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_800 + Shared Packet RAM for multiple Link Layer usage. + 0xC80 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_801 + Shared Packet RAM for multiple Link Layer usage. + 0xC84 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_802 + Shared Packet RAM for multiple Link Layer usage. + 0xC88 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_803 + Shared Packet RAM for multiple Link Layer usage. + 0xC8C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_804 + Shared Packet RAM for multiple Link Layer usage. + 0xC90 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_805 + Shared Packet RAM for multiple Link Layer usage. + 0xC94 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_806 + Shared Packet RAM for multiple Link Layer usage. + 0xC98 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_807 + Shared Packet RAM for multiple Link Layer usage. + 0xC9C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_808 + Shared Packet RAM for multiple Link Layer usage. + 0xCA0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_809 + Shared Packet RAM for multiple Link Layer usage. + 0xCA4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_810 + Shared Packet RAM for multiple Link Layer usage. + 0xCA8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_811 + Shared Packet RAM for multiple Link Layer usage. + 0xCAC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_812 + Shared Packet RAM for multiple Link Layer usage. + 0xCB0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_813 + Shared Packet RAM for multiple Link Layer usage. + 0xCB4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_814 + Shared Packet RAM for multiple Link Layer usage. + 0xCB8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_815 + Shared Packet RAM for multiple Link Layer usage. + 0xCBC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_816 + Shared Packet RAM for multiple Link Layer usage. + 0xCC0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_817 + Shared Packet RAM for multiple Link Layer usage. + 0xCC4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_818 + Shared Packet RAM for multiple Link Layer usage. + 0xCC8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_819 + Shared Packet RAM for multiple Link Layer usage. + 0xCCC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_820 + Shared Packet RAM for multiple Link Layer usage. + 0xCD0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_821 + Shared Packet RAM for multiple Link Layer usage. + 0xCD4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_822 + Shared Packet RAM for multiple Link Layer usage. + 0xCD8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_823 + Shared Packet RAM for multiple Link Layer usage. + 0xCDC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_824 + Shared Packet RAM for multiple Link Layer usage. + 0xCE0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_825 + Shared Packet RAM for multiple Link Layer usage. + 0xCE4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_826 + Shared Packet RAM for multiple Link Layer usage. + 0xCE8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_827 + Shared Packet RAM for multiple Link Layer usage. + 0xCEC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_828 + Shared Packet RAM for multiple Link Layer usage. + 0xCF0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_829 + Shared Packet RAM for multiple Link Layer usage. + 0xCF4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_830 + Shared Packet RAM for multiple Link Layer usage. + 0xCF8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_831 + Shared Packet RAM for multiple Link Layer usage. + 0xCFC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_832 + Shared Packet RAM for multiple Link Layer usage. + 0xD00 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_833 + Shared Packet RAM for multiple Link Layer usage. + 0xD04 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_834 + Shared Packet RAM for multiple Link Layer usage. + 0xD08 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_835 + Shared Packet RAM for multiple Link Layer usage. + 0xD0C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_836 + Shared Packet RAM for multiple Link Layer usage. + 0xD10 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_837 + Shared Packet RAM for multiple Link Layer usage. + 0xD14 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_838 + Shared Packet RAM for multiple Link Layer usage. + 0xD18 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_839 + Shared Packet RAM for multiple Link Layer usage. + 0xD1C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_840 + Shared Packet RAM for multiple Link Layer usage. + 0xD20 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_841 + Shared Packet RAM for multiple Link Layer usage. + 0xD24 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_842 + Shared Packet RAM for multiple Link Layer usage. + 0xD28 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_843 + Shared Packet RAM for multiple Link Layer usage. + 0xD2C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_844 + Shared Packet RAM for multiple Link Layer usage. + 0xD30 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_845 + Shared Packet RAM for multiple Link Layer usage. + 0xD34 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_846 + Shared Packet RAM for multiple Link Layer usage. + 0xD38 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_847 + Shared Packet RAM for multiple Link Layer usage. + 0xD3C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_848 + Shared Packet RAM for multiple Link Layer usage. + 0xD40 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_849 + Shared Packet RAM for multiple Link Layer usage. + 0xD44 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_850 + Shared Packet RAM for multiple Link Layer usage. + 0xD48 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_851 + Shared Packet RAM for multiple Link Layer usage. + 0xD4C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_852 + Shared Packet RAM for multiple Link Layer usage. + 0xD50 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_853 + Shared Packet RAM for multiple Link Layer usage. + 0xD54 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_854 + Shared Packet RAM for multiple Link Layer usage. + 0xD58 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_855 + Shared Packet RAM for multiple Link Layer usage. + 0xD5C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_856 + Shared Packet RAM for multiple Link Layer usage. + 0xD60 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_857 + Shared Packet RAM for multiple Link Layer usage. + 0xD64 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_858 + Shared Packet RAM for multiple Link Layer usage. + 0xD68 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_859 + Shared Packet RAM for multiple Link Layer usage. + 0xD6C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_860 + Shared Packet RAM for multiple Link Layer usage. + 0xD70 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_861 + Shared Packet RAM for multiple Link Layer usage. + 0xD74 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_862 + Shared Packet RAM for multiple Link Layer usage. + 0xD78 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_863 + Shared Packet RAM for multiple Link Layer usage. + 0xD7C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_864 + Shared Packet RAM for multiple Link Layer usage. + 0xD80 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_865 + Shared Packet RAM for multiple Link Layer usage. + 0xD84 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_866 + Shared Packet RAM for multiple Link Layer usage. + 0xD88 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_867 + Shared Packet RAM for multiple Link Layer usage. + 0xD8C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_868 + Shared Packet RAM for multiple Link Layer usage. + 0xD90 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_869 + Shared Packet RAM for multiple Link Layer usage. + 0xD94 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_870 + Shared Packet RAM for multiple Link Layer usage. + 0xD98 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_871 + Shared Packet RAM for multiple Link Layer usage. + 0xD9C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_872 + Shared Packet RAM for multiple Link Layer usage. + 0xDA0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_873 + Shared Packet RAM for multiple Link Layer usage. + 0xDA4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_874 + Shared Packet RAM for multiple Link Layer usage. + 0xDA8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_875 + Shared Packet RAM for multiple Link Layer usage. + 0xDAC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_876 + Shared Packet RAM for multiple Link Layer usage. + 0xDB0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_877 + Shared Packet RAM for multiple Link Layer usage. + 0xDB4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_878 + Shared Packet RAM for multiple Link Layer usage. + 0xDB8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_879 + Shared Packet RAM for multiple Link Layer usage. + 0xDBC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_880 + Shared Packet RAM for multiple Link Layer usage. + 0xDC0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_881 + Shared Packet RAM for multiple Link Layer usage. + 0xDC4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_882 + Shared Packet RAM for multiple Link Layer usage. + 0xDC8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_883 + Shared Packet RAM for multiple Link Layer usage. + 0xDCC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_884 + Shared Packet RAM for multiple Link Layer usage. + 0xDD0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_885 + Shared Packet RAM for multiple Link Layer usage. + 0xDD4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_886 + Shared Packet RAM for multiple Link Layer usage. + 0xDD8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_887 + Shared Packet RAM for multiple Link Layer usage. + 0xDDC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_888 + Shared Packet RAM for multiple Link Layer usage. + 0xDE0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_889 + Shared Packet RAM for multiple Link Layer usage. + 0xDE4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_890 + Shared Packet RAM for multiple Link Layer usage. + 0xDE8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_891 + Shared Packet RAM for multiple Link Layer usage. + 0xDEC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_892 + Shared Packet RAM for multiple Link Layer usage. + 0xDF0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_893 + Shared Packet RAM for multiple Link Layer usage. + 0xDF4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_894 + Shared Packet RAM for multiple Link Layer usage. + 0xDF8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_895 + Shared Packet RAM for multiple Link Layer usage. + 0xDFC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_896 + Shared Packet RAM for multiple Link Layer usage. + 0xE00 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_897 + Shared Packet RAM for multiple Link Layer usage. + 0xE04 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_898 + Shared Packet RAM for multiple Link Layer usage. + 0xE08 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_899 + Shared Packet RAM for multiple Link Layer usage. + 0xE0C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_900 + Shared Packet RAM for multiple Link Layer usage. + 0xE10 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_901 + Shared Packet RAM for multiple Link Layer usage. + 0xE14 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_902 + Shared Packet RAM for multiple Link Layer usage. + 0xE18 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_903 + Shared Packet RAM for multiple Link Layer usage. + 0xE1C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_904 + Shared Packet RAM for multiple Link Layer usage. + 0xE20 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_905 + Shared Packet RAM for multiple Link Layer usage. + 0xE24 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_906 + Shared Packet RAM for multiple Link Layer usage. + 0xE28 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_907 + Shared Packet RAM for multiple Link Layer usage. + 0xE2C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_908 + Shared Packet RAM for multiple Link Layer usage. + 0xE30 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_909 + Shared Packet RAM for multiple Link Layer usage. + 0xE34 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_910 + Shared Packet RAM for multiple Link Layer usage. + 0xE38 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_911 + Shared Packet RAM for multiple Link Layer usage. + 0xE3C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_912 + Shared Packet RAM for multiple Link Layer usage. + 0xE40 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_913 + Shared Packet RAM for multiple Link Layer usage. + 0xE44 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_914 + Shared Packet RAM for multiple Link Layer usage. + 0xE48 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_915 + Shared Packet RAM for multiple Link Layer usage. + 0xE4C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_916 + Shared Packet RAM for multiple Link Layer usage. + 0xE50 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_917 + Shared Packet RAM for multiple Link Layer usage. + 0xE54 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_918 + Shared Packet RAM for multiple Link Layer usage. + 0xE58 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_919 + Shared Packet RAM for multiple Link Layer usage. + 0xE5C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_920 + Shared Packet RAM for multiple Link Layer usage. + 0xE60 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_921 + Shared Packet RAM for multiple Link Layer usage. + 0xE64 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_922 + Shared Packet RAM for multiple Link Layer usage. + 0xE68 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_923 + Shared Packet RAM for multiple Link Layer usage. + 0xE6C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_924 + Shared Packet RAM for multiple Link Layer usage. + 0xE70 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_925 + Shared Packet RAM for multiple Link Layer usage. + 0xE74 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_926 + Shared Packet RAM for multiple Link Layer usage. + 0xE78 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_927 + Shared Packet RAM for multiple Link Layer usage. + 0xE7C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_928 + Shared Packet RAM for multiple Link Layer usage. + 0xE80 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_929 + Shared Packet RAM for multiple Link Layer usage. + 0xE84 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_930 + Shared Packet RAM for multiple Link Layer usage. + 0xE88 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_931 + Shared Packet RAM for multiple Link Layer usage. + 0xE8C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_932 + Shared Packet RAM for multiple Link Layer usage. + 0xE90 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_933 + Shared Packet RAM for multiple Link Layer usage. + 0xE94 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_934 + Shared Packet RAM for multiple Link Layer usage. + 0xE98 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_935 + Shared Packet RAM for multiple Link Layer usage. + 0xE9C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_936 + Shared Packet RAM for multiple Link Layer usage. + 0xEA0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_937 + Shared Packet RAM for multiple Link Layer usage. + 0xEA4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_938 + Shared Packet RAM for multiple Link Layer usage. + 0xEA8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_939 + Shared Packet RAM for multiple Link Layer usage. + 0xEAC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_940 + Shared Packet RAM for multiple Link Layer usage. + 0xEB0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_941 + Shared Packet RAM for multiple Link Layer usage. + 0xEB4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_942 + Shared Packet RAM for multiple Link Layer usage. + 0xEB8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_943 + Shared Packet RAM for multiple Link Layer usage. + 0xEBC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_944 + Shared Packet RAM for multiple Link Layer usage. + 0xEC0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_945 + Shared Packet RAM for multiple Link Layer usage. + 0xEC4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_946 + Shared Packet RAM for multiple Link Layer usage. + 0xEC8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_947 + Shared Packet RAM for multiple Link Layer usage. + 0xECC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_948 + Shared Packet RAM for multiple Link Layer usage. + 0xED0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_949 + Shared Packet RAM for multiple Link Layer usage. + 0xED4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_950 + Shared Packet RAM for multiple Link Layer usage. + 0xED8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_951 + Shared Packet RAM for multiple Link Layer usage. + 0xEDC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_952 + Shared Packet RAM for multiple Link Layer usage. + 0xEE0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_953 + Shared Packet RAM for multiple Link Layer usage. + 0xEE4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_954 + Shared Packet RAM for multiple Link Layer usage. + 0xEE8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_955 + Shared Packet RAM for multiple Link Layer usage. + 0xEEC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_956 + Shared Packet RAM for multiple Link Layer usage. + 0xEF0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_957 + Shared Packet RAM for multiple Link Layer usage. + 0xEF4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_958 + Shared Packet RAM for multiple Link Layer usage. + 0xEF8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_959 + Shared Packet RAM for multiple Link Layer usage. + 0xEFC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_960 + Shared Packet RAM for multiple Link Layer usage. + 0xF00 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_961 + Shared Packet RAM for multiple Link Layer usage. + 0xF04 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_962 + Shared Packet RAM for multiple Link Layer usage. + 0xF08 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_963 + Shared Packet RAM for multiple Link Layer usage. + 0xF0C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_964 + Shared Packet RAM for multiple Link Layer usage. + 0xF10 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_965 + Shared Packet RAM for multiple Link Layer usage. + 0xF14 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_966 + Shared Packet RAM for multiple Link Layer usage. + 0xF18 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_967 + Shared Packet RAM for multiple Link Layer usage. + 0xF1C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_968 + Shared Packet RAM for multiple Link Layer usage. + 0xF20 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_969 + Shared Packet RAM for multiple Link Layer usage. + 0xF24 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_970 + Shared Packet RAM for multiple Link Layer usage. + 0xF28 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_971 + Shared Packet RAM for multiple Link Layer usage. + 0xF2C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_972 + Shared Packet RAM for multiple Link Layer usage. + 0xF30 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_973 + Shared Packet RAM for multiple Link Layer usage. + 0xF34 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_974 + Shared Packet RAM for multiple Link Layer usage. + 0xF38 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_975 + Shared Packet RAM for multiple Link Layer usage. + 0xF3C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_976 + Shared Packet RAM for multiple Link Layer usage. + 0xF40 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_977 + Shared Packet RAM for multiple Link Layer usage. + 0xF44 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_978 + Shared Packet RAM for multiple Link Layer usage. + 0xF48 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_979 + Shared Packet RAM for multiple Link Layer usage. + 0xF4C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_980 + Shared Packet RAM for multiple Link Layer usage. + 0xF50 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_981 + Shared Packet RAM for multiple Link Layer usage. + 0xF54 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_982 + Shared Packet RAM for multiple Link Layer usage. + 0xF58 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_983 + Shared Packet RAM for multiple Link Layer usage. + 0xF5C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_984 + Shared Packet RAM for multiple Link Layer usage. + 0xF60 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_985 + Shared Packet RAM for multiple Link Layer usage. + 0xF64 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_986 + Shared Packet RAM for multiple Link Layer usage. + 0xF68 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_987 + Shared Packet RAM for multiple Link Layer usage. + 0xF6C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_988 + Shared Packet RAM for multiple Link Layer usage. + 0xF70 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_989 + Shared Packet RAM for multiple Link Layer usage. + 0xF74 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_990 + Shared Packet RAM for multiple Link Layer usage. + 0xF78 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_991 + Shared Packet RAM for multiple Link Layer usage. + 0xF7C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_992 + Shared Packet RAM for multiple Link Layer usage. + 0xF80 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_993 + Shared Packet RAM for multiple Link Layer usage. + 0xF84 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_994 + Shared Packet RAM for multiple Link Layer usage. + 0xF88 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_995 + Shared Packet RAM for multiple Link Layer usage. + 0xF8C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_996 + Shared Packet RAM for multiple Link Layer usage. + 0xF90 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_997 + Shared Packet RAM for multiple Link Layer usage. + 0xF94 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_998 + Shared Packet RAM for multiple Link Layer usage. + 0xF98 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_999 + Shared Packet RAM for multiple Link Layer usage. + 0xF9C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1000 + Shared Packet RAM for multiple Link Layer usage. + 0xFA0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1001 + Shared Packet RAM for multiple Link Layer usage. + 0xFA4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1002 + Shared Packet RAM for multiple Link Layer usage. + 0xFA8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1003 + Shared Packet RAM for multiple Link Layer usage. + 0xFAC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1004 + Shared Packet RAM for multiple Link Layer usage. + 0xFB0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1005 + Shared Packet RAM for multiple Link Layer usage. + 0xFB4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1006 + Shared Packet RAM for multiple Link Layer usage. + 0xFB8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1007 + Shared Packet RAM for multiple Link Layer usage. + 0xFBC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1008 + Shared Packet RAM for multiple Link Layer usage. + 0xFC0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1009 + Shared Packet RAM for multiple Link Layer usage. + 0xFC4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1010 + Shared Packet RAM for multiple Link Layer usage. + 0xFC8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1011 + Shared Packet RAM for multiple Link Layer usage. + 0xFCC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1012 + Shared Packet RAM for multiple Link Layer usage. + 0xFD0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1013 + Shared Packet RAM for multiple Link Layer usage. + 0xFD4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1014 + Shared Packet RAM for multiple Link Layer usage. + 0xFD8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1015 + Shared Packet RAM for multiple Link Layer usage. + 0xFDC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1016 + Shared Packet RAM for multiple Link Layer usage. + 0xFE0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1017 + Shared Packet RAM for multiple Link Layer usage. + 0xFE4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1018 + Shared Packet RAM for multiple Link Layer usage. + 0xFE8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1019 + Shared Packet RAM for multiple Link Layer usage. + 0xFEC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1020 + Shared Packet RAM for multiple Link Layer usage. + 0xFF0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1021 + Shared Packet RAM for multiple Link Layer usage. + 0xFF4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1022 + Shared Packet RAM for multiple Link Layer usage. + 0xFF8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1023 + Shared Packet RAM for multiple Link Layer usage. + 0xFFC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1024 + Shared Packet RAM for multiple Link Layer usage. + 0x1000 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1025 + Shared Packet RAM for multiple Link Layer usage. + 0x1004 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1026 + Shared Packet RAM for multiple Link Layer usage. + 0x1008 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1027 + Shared Packet RAM for multiple Link Layer usage. + 0x100C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1028 + Shared Packet RAM for multiple Link Layer usage. + 0x1010 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1029 + Shared Packet RAM for multiple Link Layer usage. + 0x1014 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1030 + Shared Packet RAM for multiple Link Layer usage. + 0x1018 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1031 + Shared Packet RAM for multiple Link Layer usage. + 0x101C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1032 + Shared Packet RAM for multiple Link Layer usage. + 0x1020 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1033 + Shared Packet RAM for multiple Link Layer usage. + 0x1024 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1034 + Shared Packet RAM for multiple Link Layer usage. + 0x1028 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1035 + Shared Packet RAM for multiple Link Layer usage. + 0x102C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1036 + Shared Packet RAM for multiple Link Layer usage. + 0x1030 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1037 + Shared Packet RAM for multiple Link Layer usage. + 0x1034 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1038 + Shared Packet RAM for multiple Link Layer usage. + 0x1038 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1039 + Shared Packet RAM for multiple Link Layer usage. + 0x103C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1040 + Shared Packet RAM for multiple Link Layer usage. + 0x1040 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1041 + Shared Packet RAM for multiple Link Layer usage. + 0x1044 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1042 + Shared Packet RAM for multiple Link Layer usage. + 0x1048 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1043 + Shared Packet RAM for multiple Link Layer usage. + 0x104C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1044 + Shared Packet RAM for multiple Link Layer usage. + 0x1050 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1045 + Shared Packet RAM for multiple Link Layer usage. + 0x1054 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1046 + Shared Packet RAM for multiple Link Layer usage. + 0x1058 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1047 + Shared Packet RAM for multiple Link Layer usage. + 0x105C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1048 + Shared Packet RAM for multiple Link Layer usage. + 0x1060 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1049 + Shared Packet RAM for multiple Link Layer usage. + 0x1064 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1050 + Shared Packet RAM for multiple Link Layer usage. + 0x1068 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1051 + Shared Packet RAM for multiple Link Layer usage. + 0x106C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1052 + Shared Packet RAM for multiple Link Layer usage. + 0x1070 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1053 + Shared Packet RAM for multiple Link Layer usage. + 0x1074 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1054 + Shared Packet RAM for multiple Link Layer usage. + 0x1078 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1055 + Shared Packet RAM for multiple Link Layer usage. + 0x107C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1056 + Shared Packet RAM for multiple Link Layer usage. + 0x1080 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1057 + Shared Packet RAM for multiple Link Layer usage. + 0x1084 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1058 + Shared Packet RAM for multiple Link Layer usage. + 0x1088 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1059 + Shared Packet RAM for multiple Link Layer usage. + 0x108C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1060 + Shared Packet RAM for multiple Link Layer usage. + 0x1090 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1061 + Shared Packet RAM for multiple Link Layer usage. + 0x1094 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1062 + Shared Packet RAM for multiple Link Layer usage. + 0x1098 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1063 + Shared Packet RAM for multiple Link Layer usage. + 0x109C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1064 + Shared Packet RAM for multiple Link Layer usage. + 0x10A0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1065 + Shared Packet RAM for multiple Link Layer usage. + 0x10A4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1066 + Shared Packet RAM for multiple Link Layer usage. + 0x10A8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1067 + Shared Packet RAM for multiple Link Layer usage. + 0x10AC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1068 + Shared Packet RAM for multiple Link Layer usage. + 0x10B0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1069 + Shared Packet RAM for multiple Link Layer usage. + 0x10B4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1070 + Shared Packet RAM for multiple Link Layer usage. + 0x10B8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1071 + Shared Packet RAM for multiple Link Layer usage. + 0x10BC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1072 + Shared Packet RAM for multiple Link Layer usage. + 0x10C0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1073 + Shared Packet RAM for multiple Link Layer usage. + 0x10C4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1074 + Shared Packet RAM for multiple Link Layer usage. + 0x10C8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1075 + Shared Packet RAM for multiple Link Layer usage. + 0x10CC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1076 + Shared Packet RAM for multiple Link Layer usage. + 0x10D0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1077 + Shared Packet RAM for multiple Link Layer usage. + 0x10D4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1078 + Shared Packet RAM for multiple Link Layer usage. + 0x10D8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1079 + Shared Packet RAM for multiple Link Layer usage. + 0x10DC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1080 + Shared Packet RAM for multiple Link Layer usage. + 0x10E0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1081 + Shared Packet RAM for multiple Link Layer usage. + 0x10E4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1082 + Shared Packet RAM for multiple Link Layer usage. + 0x10E8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1083 + Shared Packet RAM for multiple Link Layer usage. + 0x10EC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1084 + Shared Packet RAM for multiple Link Layer usage. + 0x10F0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1085 + Shared Packet RAM for multiple Link Layer usage. + 0x10F4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1086 + Shared Packet RAM for multiple Link Layer usage. + 0x10F8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1087 + Shared Packet RAM for multiple Link Layer usage. + 0x10FC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1088 + Shared Packet RAM for multiple Link Layer usage. + 0x1100 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1089 + Shared Packet RAM for multiple Link Layer usage. + 0x1104 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1090 + Shared Packet RAM for multiple Link Layer usage. + 0x1108 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1091 + Shared Packet RAM for multiple Link Layer usage. + 0x110C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1092 + Shared Packet RAM for multiple Link Layer usage. + 0x1110 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1093 + Shared Packet RAM for multiple Link Layer usage. + 0x1114 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1094 + Shared Packet RAM for multiple Link Layer usage. + 0x1118 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1095 + Shared Packet RAM for multiple Link Layer usage. + 0x111C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1096 + Shared Packet RAM for multiple Link Layer usage. + 0x1120 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1097 + Shared Packet RAM for multiple Link Layer usage. + 0x1124 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1098 + Shared Packet RAM for multiple Link Layer usage. + 0x1128 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1099 + Shared Packet RAM for multiple Link Layer usage. + 0x112C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1100 + Shared Packet RAM for multiple Link Layer usage. + 0x1130 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1101 + Shared Packet RAM for multiple Link Layer usage. + 0x1134 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1102 + Shared Packet RAM for multiple Link Layer usage. + 0x1138 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1103 + Shared Packet RAM for multiple Link Layer usage. + 0x113C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1104 + Shared Packet RAM for multiple Link Layer usage. + 0x1140 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1105 + Shared Packet RAM for multiple Link Layer usage. + 0x1144 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1106 + Shared Packet RAM for multiple Link Layer usage. + 0x1148 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1107 + Shared Packet RAM for multiple Link Layer usage. + 0x114C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1108 + Shared Packet RAM for multiple Link Layer usage. + 0x1150 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1109 + Shared Packet RAM for multiple Link Layer usage. + 0x1154 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1110 + Shared Packet RAM for multiple Link Layer usage. + 0x1158 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1111 + Shared Packet RAM for multiple Link Layer usage. + 0x115C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1112 + Shared Packet RAM for multiple Link Layer usage. + 0x1160 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1113 + Shared Packet RAM for multiple Link Layer usage. + 0x1164 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1114 + Shared Packet RAM for multiple Link Layer usage. + 0x1168 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1115 + Shared Packet RAM for multiple Link Layer usage. + 0x116C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1116 + Shared Packet RAM for multiple Link Layer usage. + 0x1170 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1117 + Shared Packet RAM for multiple Link Layer usage. + 0x1174 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1118 + Shared Packet RAM for multiple Link Layer usage. + 0x1178 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1119 + Shared Packet RAM for multiple Link Layer usage. + 0x117C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1120 + Shared Packet RAM for multiple Link Layer usage. + 0x1180 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1121 + Shared Packet RAM for multiple Link Layer usage. + 0x1184 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1122 + Shared Packet RAM for multiple Link Layer usage. + 0x1188 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1123 + Shared Packet RAM for multiple Link Layer usage. + 0x118C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1124 + Shared Packet RAM for multiple Link Layer usage. + 0x1190 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1125 + Shared Packet RAM for multiple Link Layer usage. + 0x1194 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1126 + Shared Packet RAM for multiple Link Layer usage. + 0x1198 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1127 + Shared Packet RAM for multiple Link Layer usage. + 0x119C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1128 + Shared Packet RAM for multiple Link Layer usage. + 0x11A0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1129 + Shared Packet RAM for multiple Link Layer usage. + 0x11A4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1130 + Shared Packet RAM for multiple Link Layer usage. + 0x11A8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1131 + Shared Packet RAM for multiple Link Layer usage. + 0x11AC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1132 + Shared Packet RAM for multiple Link Layer usage. + 0x11B0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1133 + Shared Packet RAM for multiple Link Layer usage. + 0x11B4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1134 + Shared Packet RAM for multiple Link Layer usage. + 0x11B8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1135 + Shared Packet RAM for multiple Link Layer usage. + 0x11BC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1136 + Shared Packet RAM for multiple Link Layer usage. + 0x11C0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1137 + Shared Packet RAM for multiple Link Layer usage. + 0x11C4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1138 + Shared Packet RAM for multiple Link Layer usage. + 0x11C8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1139 + Shared Packet RAM for multiple Link Layer usage. + 0x11CC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1140 + Shared Packet RAM for multiple Link Layer usage. + 0x11D0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1141 + Shared Packet RAM for multiple Link Layer usage. + 0x11D4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1142 + Shared Packet RAM for multiple Link Layer usage. + 0x11D8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1143 + Shared Packet RAM for multiple Link Layer usage. + 0x11DC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1144 + Shared Packet RAM for multiple Link Layer usage. + 0x11E0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1145 + Shared Packet RAM for multiple Link Layer usage. + 0x11E4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1146 + Shared Packet RAM for multiple Link Layer usage. + 0x11E8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1147 + Shared Packet RAM for multiple Link Layer usage. + 0x11EC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1148 + Shared Packet RAM for multiple Link Layer usage. + 0x11F0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1149 + Shared Packet RAM for multiple Link Layer usage. + 0x11F4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1150 + Shared Packet RAM for multiple Link Layer usage. + 0x11F8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1151 + Shared Packet RAM for multiple Link Layer usage. + 0x11FC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1152 + Shared Packet RAM for multiple Link Layer usage. + 0x1200 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1153 + Shared Packet RAM for multiple Link Layer usage. + 0x1204 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1154 + Shared Packet RAM for multiple Link Layer usage. + 0x1208 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1155 + Shared Packet RAM for multiple Link Layer usage. + 0x120C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1156 + Shared Packet RAM for multiple Link Layer usage. + 0x1210 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1157 + Shared Packet RAM for multiple Link Layer usage. + 0x1214 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1158 + Shared Packet RAM for multiple Link Layer usage. + 0x1218 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1159 + Shared Packet RAM for multiple Link Layer usage. + 0x121C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1160 + Shared Packet RAM for multiple Link Layer usage. + 0x1220 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1161 + Shared Packet RAM for multiple Link Layer usage. + 0x1224 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1162 + Shared Packet RAM for multiple Link Layer usage. + 0x1228 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1163 + Shared Packet RAM for multiple Link Layer usage. + 0x122C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1164 + Shared Packet RAM for multiple Link Layer usage. + 0x1230 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1165 + Shared Packet RAM for multiple Link Layer usage. + 0x1234 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1166 + Shared Packet RAM for multiple Link Layer usage. + 0x1238 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1167 + Shared Packet RAM for multiple Link Layer usage. + 0x123C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1168 + Shared Packet RAM for multiple Link Layer usage. + 0x1240 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1169 + Shared Packet RAM for multiple Link Layer usage. + 0x1244 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1170 + Shared Packet RAM for multiple Link Layer usage. + 0x1248 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1171 + Shared Packet RAM for multiple Link Layer usage. + 0x124C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1172 + Shared Packet RAM for multiple Link Layer usage. + 0x1250 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1173 + Shared Packet RAM for multiple Link Layer usage. + 0x1254 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1174 + Shared Packet RAM for multiple Link Layer usage. + 0x1258 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1175 + Shared Packet RAM for multiple Link Layer usage. + 0x125C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1176 + Shared Packet RAM for multiple Link Layer usage. + 0x1260 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1177 + Shared Packet RAM for multiple Link Layer usage. + 0x1264 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1178 + Shared Packet RAM for multiple Link Layer usage. + 0x1268 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1179 + Shared Packet RAM for multiple Link Layer usage. + 0x126C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1180 + Shared Packet RAM for multiple Link Layer usage. + 0x1270 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1181 + Shared Packet RAM for multiple Link Layer usage. + 0x1274 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1182 + Shared Packet RAM for multiple Link Layer usage. + 0x1278 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1183 + Shared Packet RAM for multiple Link Layer usage. + 0x127C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1184 + Shared Packet RAM for multiple Link Layer usage. + 0x1280 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1185 + Shared Packet RAM for multiple Link Layer usage. + 0x1284 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1186 + Shared Packet RAM for multiple Link Layer usage. + 0x1288 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1187 + Shared Packet RAM for multiple Link Layer usage. + 0x128C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1188 + Shared Packet RAM for multiple Link Layer usage. + 0x1290 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1189 + Shared Packet RAM for multiple Link Layer usage. + 0x1294 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1190 + Shared Packet RAM for multiple Link Layer usage. + 0x1298 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1191 + Shared Packet RAM for multiple Link Layer usage. + 0x129C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1192 + Shared Packet RAM for multiple Link Layer usage. + 0x12A0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1193 + Shared Packet RAM for multiple Link Layer usage. + 0x12A4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1194 + Shared Packet RAM for multiple Link Layer usage. + 0x12A8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1195 + Shared Packet RAM for multiple Link Layer usage. + 0x12AC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1196 + Shared Packet RAM for multiple Link Layer usage. + 0x12B0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1197 + Shared Packet RAM for multiple Link Layer usage. + 0x12B4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1198 + Shared Packet RAM for multiple Link Layer usage. + 0x12B8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1199 + Shared Packet RAM for multiple Link Layer usage. + 0x12BC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1200 + Shared Packet RAM for multiple Link Layer usage. + 0x12C0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1201 + Shared Packet RAM for multiple Link Layer usage. + 0x12C4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1202 + Shared Packet RAM for multiple Link Layer usage. + 0x12C8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1203 + Shared Packet RAM for multiple Link Layer usage. + 0x12CC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1204 + Shared Packet RAM for multiple Link Layer usage. + 0x12D0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1205 + Shared Packet RAM for multiple Link Layer usage. + 0x12D4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1206 + Shared Packet RAM for multiple Link Layer usage. + 0x12D8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1207 + Shared Packet RAM for multiple Link Layer usage. + 0x12DC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1208 + Shared Packet RAM for multiple Link Layer usage. + 0x12E0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1209 + Shared Packet RAM for multiple Link Layer usage. + 0x12E4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1210 + Shared Packet RAM for multiple Link Layer usage. + 0x12E8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1211 + Shared Packet RAM for multiple Link Layer usage. + 0x12EC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1212 + Shared Packet RAM for multiple Link Layer usage. + 0x12F0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1213 + Shared Packet RAM for multiple Link Layer usage. + 0x12F4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1214 + Shared Packet RAM for multiple Link Layer usage. + 0x12F8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1215 + Shared Packet RAM for multiple Link Layer usage. + 0x12FC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1216 + Shared Packet RAM for multiple Link Layer usage. + 0x1300 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1217 + Shared Packet RAM for multiple Link Layer usage. + 0x1304 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1218 + Shared Packet RAM for multiple Link Layer usage. + 0x1308 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1219 + Shared Packet RAM for multiple Link Layer usage. + 0x130C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1220 + Shared Packet RAM for multiple Link Layer usage. + 0x1310 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1221 + Shared Packet RAM for multiple Link Layer usage. + 0x1314 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1222 + Shared Packet RAM for multiple Link Layer usage. + 0x1318 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1223 + Shared Packet RAM for multiple Link Layer usage. + 0x131C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1224 + Shared Packet RAM for multiple Link Layer usage. + 0x1320 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1225 + Shared Packet RAM for multiple Link Layer usage. + 0x1324 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1226 + Shared Packet RAM for multiple Link Layer usage. + 0x1328 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1227 + Shared Packet RAM for multiple Link Layer usage. + 0x132C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1228 + Shared Packet RAM for multiple Link Layer usage. + 0x1330 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1229 + Shared Packet RAM for multiple Link Layer usage. + 0x1334 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1230 + Shared Packet RAM for multiple Link Layer usage. + 0x1338 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1231 + Shared Packet RAM for multiple Link Layer usage. + 0x133C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1232 + Shared Packet RAM for multiple Link Layer usage. + 0x1340 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1233 + Shared Packet RAM for multiple Link Layer usage. + 0x1344 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1234 + Shared Packet RAM for multiple Link Layer usage. + 0x1348 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1235 + Shared Packet RAM for multiple Link Layer usage. + 0x134C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1236 + Shared Packet RAM for multiple Link Layer usage. + 0x1350 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1237 + Shared Packet RAM for multiple Link Layer usage. + 0x1354 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1238 + Shared Packet RAM for multiple Link Layer usage. + 0x1358 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1239 + Shared Packet RAM for multiple Link Layer usage. + 0x135C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1240 + Shared Packet RAM for multiple Link Layer usage. + 0x1360 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1241 + Shared Packet RAM for multiple Link Layer usage. + 0x1364 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1242 + Shared Packet RAM for multiple Link Layer usage. + 0x1368 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1243 + Shared Packet RAM for multiple Link Layer usage. + 0x136C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1244 + Shared Packet RAM for multiple Link Layer usage. + 0x1370 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1245 + Shared Packet RAM for multiple Link Layer usage. + 0x1374 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1246 + Shared Packet RAM for multiple Link Layer usage. + 0x1378 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1247 + Shared Packet RAM for multiple Link Layer usage. + 0x137C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1248 + Shared Packet RAM for multiple Link Layer usage. + 0x1380 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1249 + Shared Packet RAM for multiple Link Layer usage. + 0x1384 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1250 + Shared Packet RAM for multiple Link Layer usage. + 0x1388 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1251 + Shared Packet RAM for multiple Link Layer usage. + 0x138C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1252 + Shared Packet RAM for multiple Link Layer usage. + 0x1390 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1253 + Shared Packet RAM for multiple Link Layer usage. + 0x1394 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1254 + Shared Packet RAM for multiple Link Layer usage. + 0x1398 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1255 + Shared Packet RAM for multiple Link Layer usage. + 0x139C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1256 + Shared Packet RAM for multiple Link Layer usage. + 0x13A0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1257 + Shared Packet RAM for multiple Link Layer usage. + 0x13A4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1258 + Shared Packet RAM for multiple Link Layer usage. + 0x13A8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1259 + Shared Packet RAM for multiple Link Layer usage. + 0x13AC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1260 + Shared Packet RAM for multiple Link Layer usage. + 0x13B0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1261 + Shared Packet RAM for multiple Link Layer usage. + 0x13B4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1262 + Shared Packet RAM for multiple Link Layer usage. + 0x13B8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1263 + Shared Packet RAM for multiple Link Layer usage. + 0x13BC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1264 + Shared Packet RAM for multiple Link Layer usage. + 0x13C0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1265 + Shared Packet RAM for multiple Link Layer usage. + 0x13C4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1266 + Shared Packet RAM for multiple Link Layer usage. + 0x13C8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1267 + Shared Packet RAM for multiple Link Layer usage. + 0x13CC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1268 + Shared Packet RAM for multiple Link Layer usage. + 0x13D0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1269 + Shared Packet RAM for multiple Link Layer usage. + 0x13D4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1270 + Shared Packet RAM for multiple Link Layer usage. + 0x13D8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1271 + Shared Packet RAM for multiple Link Layer usage. + 0x13DC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1272 + Shared Packet RAM for multiple Link Layer usage. + 0x13E0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1273 + Shared Packet RAM for multiple Link Layer usage. + 0x13E4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1274 + Shared Packet RAM for multiple Link Layer usage. + 0x13E8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1275 + Shared Packet RAM for multiple Link Layer usage. + 0x13EC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1276 + Shared Packet RAM for multiple Link Layer usage. + 0x13F0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1277 + Shared Packet RAM for multiple Link Layer usage. + 0x13F4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1278 + Shared Packet RAM for multiple Link Layer usage. + 0x13F8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1279 + Shared Packet RAM for multiple Link Layer usage. + 0x13FC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1280 + Shared Packet RAM for multiple Link Layer usage. + 0x1400 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1281 + Shared Packet RAM for multiple Link Layer usage. + 0x1404 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1282 + Shared Packet RAM for multiple Link Layer usage. + 0x1408 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1283 + Shared Packet RAM for multiple Link Layer usage. + 0x140C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1284 + Shared Packet RAM for multiple Link Layer usage. + 0x1410 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1285 + Shared Packet RAM for multiple Link Layer usage. + 0x1414 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1286 + Shared Packet RAM for multiple Link Layer usage. + 0x1418 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1287 + Shared Packet RAM for multiple Link Layer usage. + 0x141C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1288 + Shared Packet RAM for multiple Link Layer usage. + 0x1420 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1289 + Shared Packet RAM for multiple Link Layer usage. + 0x1424 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1290 + Shared Packet RAM for multiple Link Layer usage. + 0x1428 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1291 + Shared Packet RAM for multiple Link Layer usage. + 0x142C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1292 + Shared Packet RAM for multiple Link Layer usage. + 0x1430 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1293 + Shared Packet RAM for multiple Link Layer usage. + 0x1434 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1294 + Shared Packet RAM for multiple Link Layer usage. + 0x1438 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1295 + Shared Packet RAM for multiple Link Layer usage. + 0x143C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1296 + Shared Packet RAM for multiple Link Layer usage. + 0x1440 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1297 + Shared Packet RAM for multiple Link Layer usage. + 0x1444 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1298 + Shared Packet RAM for multiple Link Layer usage. + 0x1448 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1299 + Shared Packet RAM for multiple Link Layer usage. + 0x144C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1300 + Shared Packet RAM for multiple Link Layer usage. + 0x1450 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1301 + Shared Packet RAM for multiple Link Layer usage. + 0x1454 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1302 + Shared Packet RAM for multiple Link Layer usage. + 0x1458 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1303 + Shared Packet RAM for multiple Link Layer usage. + 0x145C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1304 + Shared Packet RAM for multiple Link Layer usage. + 0x1460 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1305 + Shared Packet RAM for multiple Link Layer usage. + 0x1464 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1306 + Shared Packet RAM for multiple Link Layer usage. + 0x1468 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1307 + Shared Packet RAM for multiple Link Layer usage. + 0x146C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1308 + Shared Packet RAM for multiple Link Layer usage. + 0x1470 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1309 + Shared Packet RAM for multiple Link Layer usage. + 0x1474 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1310 + Shared Packet RAM for multiple Link Layer usage. + 0x1478 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1311 + Shared Packet RAM for multiple Link Layer usage. + 0x147C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1312 + Shared Packet RAM for multiple Link Layer usage. + 0x1480 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1313 + Shared Packet RAM for multiple Link Layer usage. + 0x1484 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1314 + Shared Packet RAM for multiple Link Layer usage. + 0x1488 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1315 + Shared Packet RAM for multiple Link Layer usage. + 0x148C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1316 + Shared Packet RAM for multiple Link Layer usage. + 0x1490 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1317 + Shared Packet RAM for multiple Link Layer usage. + 0x1494 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1318 + Shared Packet RAM for multiple Link Layer usage. + 0x1498 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1319 + Shared Packet RAM for multiple Link Layer usage. + 0x149C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1320 + Shared Packet RAM for multiple Link Layer usage. + 0x14A0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1321 + Shared Packet RAM for multiple Link Layer usage. + 0x14A4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1322 + Shared Packet RAM for multiple Link Layer usage. + 0x14A8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1323 + Shared Packet RAM for multiple Link Layer usage. + 0x14AC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1324 + Shared Packet RAM for multiple Link Layer usage. + 0x14B0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1325 + Shared Packet RAM for multiple Link Layer usage. + 0x14B4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1326 + Shared Packet RAM for multiple Link Layer usage. + 0x14B8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1327 + Shared Packet RAM for multiple Link Layer usage. + 0x14BC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1328 + Shared Packet RAM for multiple Link Layer usage. + 0x14C0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1329 + Shared Packet RAM for multiple Link Layer usage. + 0x14C4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1330 + Shared Packet RAM for multiple Link Layer usage. + 0x14C8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1331 + Shared Packet RAM for multiple Link Layer usage. + 0x14CC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1332 + Shared Packet RAM for multiple Link Layer usage. + 0x14D0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1333 + Shared Packet RAM for multiple Link Layer usage. + 0x14D4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1334 + Shared Packet RAM for multiple Link Layer usage. + 0x14D8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1335 + Shared Packet RAM for multiple Link Layer usage. + 0x14DC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1336 + Shared Packet RAM for multiple Link Layer usage. + 0x14E0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1337 + Shared Packet RAM for multiple Link Layer usage. + 0x14E4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1338 + Shared Packet RAM for multiple Link Layer usage. + 0x14E8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1339 + Shared Packet RAM for multiple Link Layer usage. + 0x14EC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1340 + Shared Packet RAM for multiple Link Layer usage. + 0x14F0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1341 + Shared Packet RAM for multiple Link Layer usage. + 0x14F4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1342 + Shared Packet RAM for multiple Link Layer usage. + 0x14F8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1343 + Shared Packet RAM for multiple Link Layer usage. + 0x14FC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1344 + Shared Packet RAM for multiple Link Layer usage. + 0x1500 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1345 + Shared Packet RAM for multiple Link Layer usage. + 0x1504 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1346 + Shared Packet RAM for multiple Link Layer usage. + 0x1508 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1347 + Shared Packet RAM for multiple Link Layer usage. + 0x150C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1348 + Shared Packet RAM for multiple Link Layer usage. + 0x1510 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1349 + Shared Packet RAM for multiple Link Layer usage. + 0x1514 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1350 + Shared Packet RAM for multiple Link Layer usage. + 0x1518 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1351 + Shared Packet RAM for multiple Link Layer usage. + 0x151C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1352 + Shared Packet RAM for multiple Link Layer usage. + 0x1520 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1353 + Shared Packet RAM for multiple Link Layer usage. + 0x1524 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1354 + Shared Packet RAM for multiple Link Layer usage. + 0x1528 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1355 + Shared Packet RAM for multiple Link Layer usage. + 0x152C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1356 + Shared Packet RAM for multiple Link Layer usage. + 0x1530 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1357 + Shared Packet RAM for multiple Link Layer usage. + 0x1534 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1358 + Shared Packet RAM for multiple Link Layer usage. + 0x1538 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1359 + Shared Packet RAM for multiple Link Layer usage. + 0x153C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1360 + Shared Packet RAM for multiple Link Layer usage. + 0x1540 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1361 + Shared Packet RAM for multiple Link Layer usage. + 0x1544 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1362 + Shared Packet RAM for multiple Link Layer usage. + 0x1548 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1363 + Shared Packet RAM for multiple Link Layer usage. + 0x154C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1364 + Shared Packet RAM for multiple Link Layer usage. + 0x1550 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1365 + Shared Packet RAM for multiple Link Layer usage. + 0x1554 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1366 + Shared Packet RAM for multiple Link Layer usage. + 0x1558 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1367 + Shared Packet RAM for multiple Link Layer usage. + 0x155C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1368 + Shared Packet RAM for multiple Link Layer usage. + 0x1560 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1369 + Shared Packet RAM for multiple Link Layer usage. + 0x1564 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1370 + Shared Packet RAM for multiple Link Layer usage. + 0x1568 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1371 + Shared Packet RAM for multiple Link Layer usage. + 0x156C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1372 + Shared Packet RAM for multiple Link Layer usage. + 0x1570 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1373 + Shared Packet RAM for multiple Link Layer usage. + 0x1574 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1374 + Shared Packet RAM for multiple Link Layer usage. + 0x1578 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1375 + Shared Packet RAM for multiple Link Layer usage. + 0x157C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1376 + Shared Packet RAM for multiple Link Layer usage. + 0x1580 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1377 + Shared Packet RAM for multiple Link Layer usage. + 0x1584 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1378 + Shared Packet RAM for multiple Link Layer usage. + 0x1588 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1379 + Shared Packet RAM for multiple Link Layer usage. + 0x158C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1380 + Shared Packet RAM for multiple Link Layer usage. + 0x1590 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1381 + Shared Packet RAM for multiple Link Layer usage. + 0x1594 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1382 + Shared Packet RAM for multiple Link Layer usage. + 0x1598 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1383 + Shared Packet RAM for multiple Link Layer usage. + 0x159C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1384 + Shared Packet RAM for multiple Link Layer usage. + 0x15A0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1385 + Shared Packet RAM for multiple Link Layer usage. + 0x15A4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1386 + Shared Packet RAM for multiple Link Layer usage. + 0x15A8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1387 + Shared Packet RAM for multiple Link Layer usage. + 0x15AC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1388 + Shared Packet RAM for multiple Link Layer usage. + 0x15B0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1389 + Shared Packet RAM for multiple Link Layer usage. + 0x15B4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1390 + Shared Packet RAM for multiple Link Layer usage. + 0x15B8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1391 + Shared Packet RAM for multiple Link Layer usage. + 0x15BC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1392 + Shared Packet RAM for multiple Link Layer usage. + 0x15C0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1393 + Shared Packet RAM for multiple Link Layer usage. + 0x15C4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1394 + Shared Packet RAM for multiple Link Layer usage. + 0x15C8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1395 + Shared Packet RAM for multiple Link Layer usage. + 0x15CC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1396 + Shared Packet RAM for multiple Link Layer usage. + 0x15D0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1397 + Shared Packet RAM for multiple Link Layer usage. + 0x15D4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1398 + Shared Packet RAM for multiple Link Layer usage. + 0x15D8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1399 + Shared Packet RAM for multiple Link Layer usage. + 0x15DC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1400 + Shared Packet RAM for multiple Link Layer usage. + 0x15E0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1401 + Shared Packet RAM for multiple Link Layer usage. + 0x15E4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1402 + Shared Packet RAM for multiple Link Layer usage. + 0x15E8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1403 + Shared Packet RAM for multiple Link Layer usage. + 0x15EC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1404 + Shared Packet RAM for multiple Link Layer usage. + 0x15F0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1405 + Shared Packet RAM for multiple Link Layer usage. + 0x15F4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1406 + Shared Packet RAM for multiple Link Layer usage. + 0x15F8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1407 + Shared Packet RAM for multiple Link Layer usage. + 0x15FC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1408 + Shared Packet RAM for multiple Link Layer usage. + 0x1600 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1409 + Shared Packet RAM for multiple Link Layer usage. + 0x1604 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1410 + Shared Packet RAM for multiple Link Layer usage. + 0x1608 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1411 + Shared Packet RAM for multiple Link Layer usage. + 0x160C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1412 + Shared Packet RAM for multiple Link Layer usage. + 0x1610 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1413 + Shared Packet RAM for multiple Link Layer usage. + 0x1614 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1414 + Shared Packet RAM for multiple Link Layer usage. + 0x1618 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1415 + Shared Packet RAM for multiple Link Layer usage. + 0x161C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1416 + Shared Packet RAM for multiple Link Layer usage. + 0x1620 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1417 + Shared Packet RAM for multiple Link Layer usage. + 0x1624 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1418 + Shared Packet RAM for multiple Link Layer usage. + 0x1628 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1419 + Shared Packet RAM for multiple Link Layer usage. + 0x162C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1420 + Shared Packet RAM for multiple Link Layer usage. + 0x1630 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1421 + Shared Packet RAM for multiple Link Layer usage. + 0x1634 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1422 + Shared Packet RAM for multiple Link Layer usage. + 0x1638 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1423 + Shared Packet RAM for multiple Link Layer usage. + 0x163C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1424 + Shared Packet RAM for multiple Link Layer usage. + 0x1640 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1425 + Shared Packet RAM for multiple Link Layer usage. + 0x1644 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1426 + Shared Packet RAM for multiple Link Layer usage. + 0x1648 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1427 + Shared Packet RAM for multiple Link Layer usage. + 0x164C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1428 + Shared Packet RAM for multiple Link Layer usage. + 0x1650 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1429 + Shared Packet RAM for multiple Link Layer usage. + 0x1654 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1430 + Shared Packet RAM for multiple Link Layer usage. + 0x1658 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1431 + Shared Packet RAM for multiple Link Layer usage. + 0x165C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1432 + Shared Packet RAM for multiple Link Layer usage. + 0x1660 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1433 + Shared Packet RAM for multiple Link Layer usage. + 0x1664 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1434 + Shared Packet RAM for multiple Link Layer usage. + 0x1668 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1435 + Shared Packet RAM for multiple Link Layer usage. + 0x166C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1436 + Shared Packet RAM for multiple Link Layer usage. + 0x1670 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1437 + Shared Packet RAM for multiple Link Layer usage. + 0x1674 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1438 + Shared Packet RAM for multiple Link Layer usage. + 0x1678 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1439 + Shared Packet RAM for multiple Link Layer usage. + 0x167C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1440 + Shared Packet RAM for multiple Link Layer usage. + 0x1680 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1441 + Shared Packet RAM for multiple Link Layer usage. + 0x1684 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1442 + Shared Packet RAM for multiple Link Layer usage. + 0x1688 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1443 + Shared Packet RAM for multiple Link Layer usage. + 0x168C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1444 + Shared Packet RAM for multiple Link Layer usage. + 0x1690 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1445 + Shared Packet RAM for multiple Link Layer usage. + 0x1694 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1446 + Shared Packet RAM for multiple Link Layer usage. + 0x1698 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1447 + Shared Packet RAM for multiple Link Layer usage. + 0x169C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1448 + Shared Packet RAM for multiple Link Layer usage. + 0x16A0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1449 + Shared Packet RAM for multiple Link Layer usage. + 0x16A4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1450 + Shared Packet RAM for multiple Link Layer usage. + 0x16A8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1451 + Shared Packet RAM for multiple Link Layer usage. + 0x16AC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1452 + Shared Packet RAM for multiple Link Layer usage. + 0x16B0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1453 + Shared Packet RAM for multiple Link Layer usage. + 0x16B4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1454 + Shared Packet RAM for multiple Link Layer usage. + 0x16B8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1455 + Shared Packet RAM for multiple Link Layer usage. + 0x16BC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1456 + Shared Packet RAM for multiple Link Layer usage. + 0x16C0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1457 + Shared Packet RAM for multiple Link Layer usage. + 0x16C4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1458 + Shared Packet RAM for multiple Link Layer usage. + 0x16C8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1459 + Shared Packet RAM for multiple Link Layer usage. + 0x16CC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1460 + Shared Packet RAM for multiple Link Layer usage. + 0x16D0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1461 + Shared Packet RAM for multiple Link Layer usage. + 0x16D4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1462 + Shared Packet RAM for multiple Link Layer usage. + 0x16D8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1463 + Shared Packet RAM for multiple Link Layer usage. + 0x16DC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1464 + Shared Packet RAM for multiple Link Layer usage. + 0x16E0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1465 + Shared Packet RAM for multiple Link Layer usage. + 0x16E4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1466 + Shared Packet RAM for multiple Link Layer usage. + 0x16E8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1467 + Shared Packet RAM for multiple Link Layer usage. + 0x16EC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1468 + Shared Packet RAM for multiple Link Layer usage. + 0x16F0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1469 + Shared Packet RAM for multiple Link Layer usage. + 0x16F4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1470 + Shared Packet RAM for multiple Link Layer usage. + 0x16F8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1471 + Shared Packet RAM for multiple Link Layer usage. + 0x16FC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1472 + Shared Packet RAM for multiple Link Layer usage. + 0x1700 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1473 + Shared Packet RAM for multiple Link Layer usage. + 0x1704 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1474 + Shared Packet RAM for multiple Link Layer usage. + 0x1708 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1475 + Shared Packet RAM for multiple Link Layer usage. + 0x170C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1476 + Shared Packet RAM for multiple Link Layer usage. + 0x1710 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1477 + Shared Packet RAM for multiple Link Layer usage. + 0x1714 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1478 + Shared Packet RAM for multiple Link Layer usage. + 0x1718 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1479 + Shared Packet RAM for multiple Link Layer usage. + 0x171C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1480 + Shared Packet RAM for multiple Link Layer usage. + 0x1720 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1481 + Shared Packet RAM for multiple Link Layer usage. + 0x1724 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1482 + Shared Packet RAM for multiple Link Layer usage. + 0x1728 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1483 + Shared Packet RAM for multiple Link Layer usage. + 0x172C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1484 + Shared Packet RAM for multiple Link Layer usage. + 0x1730 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1485 + Shared Packet RAM for multiple Link Layer usage. + 0x1734 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1486 + Shared Packet RAM for multiple Link Layer usage. + 0x1738 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1487 + Shared Packet RAM for multiple Link Layer usage. + 0x173C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1488 + Shared Packet RAM for multiple Link Layer usage. + 0x1740 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1489 + Shared Packet RAM for multiple Link Layer usage. + 0x1744 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1490 + Shared Packet RAM for multiple Link Layer usage. + 0x1748 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1491 + Shared Packet RAM for multiple Link Layer usage. + 0x174C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1492 + Shared Packet RAM for multiple Link Layer usage. + 0x1750 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1493 + Shared Packet RAM for multiple Link Layer usage. + 0x1754 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1494 + Shared Packet RAM for multiple Link Layer usage. + 0x1758 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1495 + Shared Packet RAM for multiple Link Layer usage. + 0x175C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1496 + Shared Packet RAM for multiple Link Layer usage. + 0x1760 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1497 + Shared Packet RAM for multiple Link Layer usage. + 0x1764 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1498 + Shared Packet RAM for multiple Link Layer usage. + 0x1768 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1499 + Shared Packet RAM for multiple Link Layer usage. + 0x176C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1500 + Shared Packet RAM for multiple Link Layer usage. + 0x1770 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1501 + Shared Packet RAM for multiple Link Layer usage. + 0x1774 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1502 + Shared Packet RAM for multiple Link Layer usage. + 0x1778 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1503 + Shared Packet RAM for multiple Link Layer usage. + 0x177C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1504 + Shared Packet RAM for multiple Link Layer usage. + 0x1780 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1505 + Shared Packet RAM for multiple Link Layer usage. + 0x1784 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1506 + Shared Packet RAM for multiple Link Layer usage. + 0x1788 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1507 + Shared Packet RAM for multiple Link Layer usage. + 0x178C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1508 + Shared Packet RAM for multiple Link Layer usage. + 0x1790 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1509 + Shared Packet RAM for multiple Link Layer usage. + 0x1794 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1510 + Shared Packet RAM for multiple Link Layer usage. + 0x1798 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1511 + Shared Packet RAM for multiple Link Layer usage. + 0x179C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1512 + Shared Packet RAM for multiple Link Layer usage. + 0x17A0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1513 + Shared Packet RAM for multiple Link Layer usage. + 0x17A4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1514 + Shared Packet RAM for multiple Link Layer usage. + 0x17A8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1515 + Shared Packet RAM for multiple Link Layer usage. + 0x17AC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1516 + Shared Packet RAM for multiple Link Layer usage. + 0x17B0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1517 + Shared Packet RAM for multiple Link Layer usage. + 0x17B4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1518 + Shared Packet RAM for multiple Link Layer usage. + 0x17B8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1519 + Shared Packet RAM for multiple Link Layer usage. + 0x17BC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1520 + Shared Packet RAM for multiple Link Layer usage. + 0x17C0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1521 + Shared Packet RAM for multiple Link Layer usage. + 0x17C4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1522 + Shared Packet RAM for multiple Link Layer usage. + 0x17C8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1523 + Shared Packet RAM for multiple Link Layer usage. + 0x17CC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1524 + Shared Packet RAM for multiple Link Layer usage. + 0x17D0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1525 + Shared Packet RAM for multiple Link Layer usage. + 0x17D4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1526 + Shared Packet RAM for multiple Link Layer usage. + 0x17D8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1527 + Shared Packet RAM for multiple Link Layer usage. + 0x17DC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1528 + Shared Packet RAM for multiple Link Layer usage. + 0x17E0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1529 + Shared Packet RAM for multiple Link Layer usage. + 0x17E4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1530 + Shared Packet RAM for multiple Link Layer usage. + 0x17E8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1531 + Shared Packet RAM for multiple Link Layer usage. + 0x17EC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1532 + Shared Packet RAM for multiple Link Layer usage. + 0x17F0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1533 + Shared Packet RAM for multiple Link Layer usage. + 0x17F4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1534 + Shared Packet RAM for multiple Link Layer usage. + 0x17F8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1535 + Shared Packet RAM for multiple Link Layer usage. + 0x17FC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1536 + Shared Packet RAM for multiple Link Layer usage. + 0x1800 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1537 + Shared Packet RAM for multiple Link Layer usage. + 0x1804 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1538 + Shared Packet RAM for multiple Link Layer usage. + 0x1808 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1539 + Shared Packet RAM for multiple Link Layer usage. + 0x180C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1540 + Shared Packet RAM for multiple Link Layer usage. + 0x1810 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1541 + Shared Packet RAM for multiple Link Layer usage. + 0x1814 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1542 + Shared Packet RAM for multiple Link Layer usage. + 0x1818 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1543 + Shared Packet RAM for multiple Link Layer usage. + 0x181C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1544 + Shared Packet RAM for multiple Link Layer usage. + 0x1820 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1545 + Shared Packet RAM for multiple Link Layer usage. + 0x1824 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1546 + Shared Packet RAM for multiple Link Layer usage. + 0x1828 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1547 + Shared Packet RAM for multiple Link Layer usage. + 0x182C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1548 + Shared Packet RAM for multiple Link Layer usage. + 0x1830 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1549 + Shared Packet RAM for multiple Link Layer usage. + 0x1834 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1550 + Shared Packet RAM for multiple Link Layer usage. + 0x1838 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1551 + Shared Packet RAM for multiple Link Layer usage. + 0x183C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1552 + Shared Packet RAM for multiple Link Layer usage. + 0x1840 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1553 + Shared Packet RAM for multiple Link Layer usage. + 0x1844 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1554 + Shared Packet RAM for multiple Link Layer usage. + 0x1848 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1555 + Shared Packet RAM for multiple Link Layer usage. + 0x184C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1556 + Shared Packet RAM for multiple Link Layer usage. + 0x1850 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1557 + Shared Packet RAM for multiple Link Layer usage. + 0x1854 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1558 + Shared Packet RAM for multiple Link Layer usage. + 0x1858 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1559 + Shared Packet RAM for multiple Link Layer usage. + 0x185C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1560 + Shared Packet RAM for multiple Link Layer usage. + 0x1860 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1561 + Shared Packet RAM for multiple Link Layer usage. + 0x1864 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1562 + Shared Packet RAM for multiple Link Layer usage. + 0x1868 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1563 + Shared Packet RAM for multiple Link Layer usage. + 0x186C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1564 + Shared Packet RAM for multiple Link Layer usage. + 0x1870 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1565 + Shared Packet RAM for multiple Link Layer usage. + 0x1874 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1566 + Shared Packet RAM for multiple Link Layer usage. + 0x1878 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1567 + Shared Packet RAM for multiple Link Layer usage. + 0x187C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1568 + Shared Packet RAM for multiple Link Layer usage. + 0x1880 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1569 + Shared Packet RAM for multiple Link Layer usage. + 0x1884 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1570 + Shared Packet RAM for multiple Link Layer usage. + 0x1888 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1571 + Shared Packet RAM for multiple Link Layer usage. + 0x188C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1572 + Shared Packet RAM for multiple Link Layer usage. + 0x1890 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1573 + Shared Packet RAM for multiple Link Layer usage. + 0x1894 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1574 + Shared Packet RAM for multiple Link Layer usage. + 0x1898 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1575 + Shared Packet RAM for multiple Link Layer usage. + 0x189C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1576 + Shared Packet RAM for multiple Link Layer usage. + 0x18A0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1577 + Shared Packet RAM for multiple Link Layer usage. + 0x18A4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1578 + Shared Packet RAM for multiple Link Layer usage. + 0x18A8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1579 + Shared Packet RAM for multiple Link Layer usage. + 0x18AC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1580 + Shared Packet RAM for multiple Link Layer usage. + 0x18B0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1581 + Shared Packet RAM for multiple Link Layer usage. + 0x18B4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1582 + Shared Packet RAM for multiple Link Layer usage. + 0x18B8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1583 + Shared Packet RAM for multiple Link Layer usage. + 0x18BC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1584 + Shared Packet RAM for multiple Link Layer usage. + 0x18C0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1585 + Shared Packet RAM for multiple Link Layer usage. + 0x18C4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1586 + Shared Packet RAM for multiple Link Layer usage. + 0x18C8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1587 + Shared Packet RAM for multiple Link Layer usage. + 0x18CC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1588 + Shared Packet RAM for multiple Link Layer usage. + 0x18D0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1589 + Shared Packet RAM for multiple Link Layer usage. + 0x18D4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1590 + Shared Packet RAM for multiple Link Layer usage. + 0x18D8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1591 + Shared Packet RAM for multiple Link Layer usage. + 0x18DC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1592 + Shared Packet RAM for multiple Link Layer usage. + 0x18E0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1593 + Shared Packet RAM for multiple Link Layer usage. + 0x18E4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1594 + Shared Packet RAM for multiple Link Layer usage. + 0x18E8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1595 + Shared Packet RAM for multiple Link Layer usage. + 0x18EC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1596 + Shared Packet RAM for multiple Link Layer usage. + 0x18F0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1597 + Shared Packet RAM for multiple Link Layer usage. + 0x18F4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1598 + Shared Packet RAM for multiple Link Layer usage. + 0x18F8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1599 + Shared Packet RAM for multiple Link Layer usage. + 0x18FC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1600 + Shared Packet RAM for multiple Link Layer usage. + 0x1900 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1601 + Shared Packet RAM for multiple Link Layer usage. + 0x1904 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1602 + Shared Packet RAM for multiple Link Layer usage. + 0x1908 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1603 + Shared Packet RAM for multiple Link Layer usage. + 0x190C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1604 + Shared Packet RAM for multiple Link Layer usage. + 0x1910 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1605 + Shared Packet RAM for multiple Link Layer usage. + 0x1914 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1606 + Shared Packet RAM for multiple Link Layer usage. + 0x1918 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1607 + Shared Packet RAM for multiple Link Layer usage. + 0x191C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1608 + Shared Packet RAM for multiple Link Layer usage. + 0x1920 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1609 + Shared Packet RAM for multiple Link Layer usage. + 0x1924 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1610 + Shared Packet RAM for multiple Link Layer usage. + 0x1928 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1611 + Shared Packet RAM for multiple Link Layer usage. + 0x192C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1612 + Shared Packet RAM for multiple Link Layer usage. + 0x1930 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1613 + Shared Packet RAM for multiple Link Layer usage. + 0x1934 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1614 + Shared Packet RAM for multiple Link Layer usage. + 0x1938 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1615 + Shared Packet RAM for multiple Link Layer usage. + 0x193C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1616 + Shared Packet RAM for multiple Link Layer usage. + 0x1940 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1617 + Shared Packet RAM for multiple Link Layer usage. + 0x1944 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1618 + Shared Packet RAM for multiple Link Layer usage. + 0x1948 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1619 + Shared Packet RAM for multiple Link Layer usage. + 0x194C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1620 + Shared Packet RAM for multiple Link Layer usage. + 0x1950 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1621 + Shared Packet RAM for multiple Link Layer usage. + 0x1954 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1622 + Shared Packet RAM for multiple Link Layer usage. + 0x1958 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1623 + Shared Packet RAM for multiple Link Layer usage. + 0x195C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1624 + Shared Packet RAM for multiple Link Layer usage. + 0x1960 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1625 + Shared Packet RAM for multiple Link Layer usage. + 0x1964 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1626 + Shared Packet RAM for multiple Link Layer usage. + 0x1968 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1627 + Shared Packet RAM for multiple Link Layer usage. + 0x196C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1628 + Shared Packet RAM for multiple Link Layer usage. + 0x1970 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1629 + Shared Packet RAM for multiple Link Layer usage. + 0x1974 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1630 + Shared Packet RAM for multiple Link Layer usage. + 0x1978 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1631 + Shared Packet RAM for multiple Link Layer usage. + 0x197C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1632 + Shared Packet RAM for multiple Link Layer usage. + 0x1980 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1633 + Shared Packet RAM for multiple Link Layer usage. + 0x1984 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1634 + Shared Packet RAM for multiple Link Layer usage. + 0x1988 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1635 + Shared Packet RAM for multiple Link Layer usage. + 0x198C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1636 + Shared Packet RAM for multiple Link Layer usage. + 0x1990 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1637 + Shared Packet RAM for multiple Link Layer usage. + 0x1994 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1638 + Shared Packet RAM for multiple Link Layer usage. + 0x1998 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1639 + Shared Packet RAM for multiple Link Layer usage. + 0x199C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1640 + Shared Packet RAM for multiple Link Layer usage. + 0x19A0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1641 + Shared Packet RAM for multiple Link Layer usage. + 0x19A4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1642 + Shared Packet RAM for multiple Link Layer usage. + 0x19A8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1643 + Shared Packet RAM for multiple Link Layer usage. + 0x19AC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1644 + Shared Packet RAM for multiple Link Layer usage. + 0x19B0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1645 + Shared Packet RAM for multiple Link Layer usage. + 0x19B4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1646 + Shared Packet RAM for multiple Link Layer usage. + 0x19B8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1647 + Shared Packet RAM for multiple Link Layer usage. + 0x19BC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1648 + Shared Packet RAM for multiple Link Layer usage. + 0x19C0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1649 + Shared Packet RAM for multiple Link Layer usage. + 0x19C4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1650 + Shared Packet RAM for multiple Link Layer usage. + 0x19C8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1651 + Shared Packet RAM for multiple Link Layer usage. + 0x19CC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1652 + Shared Packet RAM for multiple Link Layer usage. + 0x19D0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1653 + Shared Packet RAM for multiple Link Layer usage. + 0x19D4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1654 + Shared Packet RAM for multiple Link Layer usage. + 0x19D8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1655 + Shared Packet RAM for multiple Link Layer usage. + 0x19DC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1656 + Shared Packet RAM for multiple Link Layer usage. + 0x19E0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1657 + Shared Packet RAM for multiple Link Layer usage. + 0x19E4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1658 + Shared Packet RAM for multiple Link Layer usage. + 0x19E8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1659 + Shared Packet RAM for multiple Link Layer usage. + 0x19EC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1660 + Shared Packet RAM for multiple Link Layer usage. + 0x19F0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1661 + Shared Packet RAM for multiple Link Layer usage. + 0x19F4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1662 + Shared Packet RAM for multiple Link Layer usage. + 0x19F8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1663 + Shared Packet RAM for multiple Link Layer usage. + 0x19FC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1664 + Shared Packet RAM for multiple Link Layer usage. + 0x1A00 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1665 + Shared Packet RAM for multiple Link Layer usage. + 0x1A04 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1666 + Shared Packet RAM for multiple Link Layer usage. + 0x1A08 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1667 + Shared Packet RAM for multiple Link Layer usage. + 0x1A0C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1668 + Shared Packet RAM for multiple Link Layer usage. + 0x1A10 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1669 + Shared Packet RAM for multiple Link Layer usage. + 0x1A14 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1670 + Shared Packet RAM for multiple Link Layer usage. + 0x1A18 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1671 + Shared Packet RAM for multiple Link Layer usage. + 0x1A1C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1672 + Shared Packet RAM for multiple Link Layer usage. + 0x1A20 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1673 + Shared Packet RAM for multiple Link Layer usage. + 0x1A24 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1674 + Shared Packet RAM for multiple Link Layer usage. + 0x1A28 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1675 + Shared Packet RAM for multiple Link Layer usage. + 0x1A2C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1676 + Shared Packet RAM for multiple Link Layer usage. + 0x1A30 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1677 + Shared Packet RAM for multiple Link Layer usage. + 0x1A34 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1678 + Shared Packet RAM for multiple Link Layer usage. + 0x1A38 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1679 + Shared Packet RAM for multiple Link Layer usage. + 0x1A3C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1680 + Shared Packet RAM for multiple Link Layer usage. + 0x1A40 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1681 + Shared Packet RAM for multiple Link Layer usage. + 0x1A44 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1682 + Shared Packet RAM for multiple Link Layer usage. + 0x1A48 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1683 + Shared Packet RAM for multiple Link Layer usage. + 0x1A4C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1684 + Shared Packet RAM for multiple Link Layer usage. + 0x1A50 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1685 + Shared Packet RAM for multiple Link Layer usage. + 0x1A54 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1686 + Shared Packet RAM for multiple Link Layer usage. + 0x1A58 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1687 + Shared Packet RAM for multiple Link Layer usage. + 0x1A5C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1688 + Shared Packet RAM for multiple Link Layer usage. + 0x1A60 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1689 + Shared Packet RAM for multiple Link Layer usage. + 0x1A64 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1690 + Shared Packet RAM for multiple Link Layer usage. + 0x1A68 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1691 + Shared Packet RAM for multiple Link Layer usage. + 0x1A6C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1692 + Shared Packet RAM for multiple Link Layer usage. + 0x1A70 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1693 + Shared Packet RAM for multiple Link Layer usage. + 0x1A74 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1694 + Shared Packet RAM for multiple Link Layer usage. + 0x1A78 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1695 + Shared Packet RAM for multiple Link Layer usage. + 0x1A7C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1696 + Shared Packet RAM for multiple Link Layer usage. + 0x1A80 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1697 + Shared Packet RAM for multiple Link Layer usage. + 0x1A84 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1698 + Shared Packet RAM for multiple Link Layer usage. + 0x1A88 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1699 + Shared Packet RAM for multiple Link Layer usage. + 0x1A8C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1700 + Shared Packet RAM for multiple Link Layer usage. + 0x1A90 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1701 + Shared Packet RAM for multiple Link Layer usage. + 0x1A94 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1702 + Shared Packet RAM for multiple Link Layer usage. + 0x1A98 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1703 + Shared Packet RAM for multiple Link Layer usage. + 0x1A9C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1704 + Shared Packet RAM for multiple Link Layer usage. + 0x1AA0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1705 + Shared Packet RAM for multiple Link Layer usage. + 0x1AA4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1706 + Shared Packet RAM for multiple Link Layer usage. + 0x1AA8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1707 + Shared Packet RAM for multiple Link Layer usage. + 0x1AAC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1708 + Shared Packet RAM for multiple Link Layer usage. + 0x1AB0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1709 + Shared Packet RAM for multiple Link Layer usage. + 0x1AB4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1710 + Shared Packet RAM for multiple Link Layer usage. + 0x1AB8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1711 + Shared Packet RAM for multiple Link Layer usage. + 0x1ABC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1712 + Shared Packet RAM for multiple Link Layer usage. + 0x1AC0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1713 + Shared Packet RAM for multiple Link Layer usage. + 0x1AC4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1714 + Shared Packet RAM for multiple Link Layer usage. + 0x1AC8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1715 + Shared Packet RAM for multiple Link Layer usage. + 0x1ACC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1716 + Shared Packet RAM for multiple Link Layer usage. + 0x1AD0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1717 + Shared Packet RAM for multiple Link Layer usage. + 0x1AD4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1718 + Shared Packet RAM for multiple Link Layer usage. + 0x1AD8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1719 + Shared Packet RAM for multiple Link Layer usage. + 0x1ADC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1720 + Shared Packet RAM for multiple Link Layer usage. + 0x1AE0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1721 + Shared Packet RAM for multiple Link Layer usage. + 0x1AE4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1722 + Shared Packet RAM for multiple Link Layer usage. + 0x1AE8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1723 + Shared Packet RAM for multiple Link Layer usage. + 0x1AEC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1724 + Shared Packet RAM for multiple Link Layer usage. + 0x1AF0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1725 + Shared Packet RAM for multiple Link Layer usage. + 0x1AF4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1726 + Shared Packet RAM for multiple Link Layer usage. + 0x1AF8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1727 + Shared Packet RAM for multiple Link Layer usage. + 0x1AFC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1728 + Shared Packet RAM for multiple Link Layer usage. + 0x1B00 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1729 + Shared Packet RAM for multiple Link Layer usage. + 0x1B04 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1730 + Shared Packet RAM for multiple Link Layer usage. + 0x1B08 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1731 + Shared Packet RAM for multiple Link Layer usage. + 0x1B0C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1732 + Shared Packet RAM for multiple Link Layer usage. + 0x1B10 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1733 + Shared Packet RAM for multiple Link Layer usage. + 0x1B14 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1734 + Shared Packet RAM for multiple Link Layer usage. + 0x1B18 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1735 + Shared Packet RAM for multiple Link Layer usage. + 0x1B1C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1736 + Shared Packet RAM for multiple Link Layer usage. + 0x1B20 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1737 + Shared Packet RAM for multiple Link Layer usage. + 0x1B24 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1738 + Shared Packet RAM for multiple Link Layer usage. + 0x1B28 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1739 + Shared Packet RAM for multiple Link Layer usage. + 0x1B2C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1740 + Shared Packet RAM for multiple Link Layer usage. + 0x1B30 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1741 + Shared Packet RAM for multiple Link Layer usage. + 0x1B34 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1742 + Shared Packet RAM for multiple Link Layer usage. + 0x1B38 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1743 + Shared Packet RAM for multiple Link Layer usage. + 0x1B3C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1744 + Shared Packet RAM for multiple Link Layer usage. + 0x1B40 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1745 + Shared Packet RAM for multiple Link Layer usage. + 0x1B44 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1746 + Shared Packet RAM for multiple Link Layer usage. + 0x1B48 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1747 + Shared Packet RAM for multiple Link Layer usage. + 0x1B4C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1748 + Shared Packet RAM for multiple Link Layer usage. + 0x1B50 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1749 + Shared Packet RAM for multiple Link Layer usage. + 0x1B54 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1750 + Shared Packet RAM for multiple Link Layer usage. + 0x1B58 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1751 + Shared Packet RAM for multiple Link Layer usage. + 0x1B5C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1752 + Shared Packet RAM for multiple Link Layer usage. + 0x1B60 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1753 + Shared Packet RAM for multiple Link Layer usage. + 0x1B64 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1754 + Shared Packet RAM for multiple Link Layer usage. + 0x1B68 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1755 + Shared Packet RAM for multiple Link Layer usage. + 0x1B6C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1756 + Shared Packet RAM for multiple Link Layer usage. + 0x1B70 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1757 + Shared Packet RAM for multiple Link Layer usage. + 0x1B74 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1758 + Shared Packet RAM for multiple Link Layer usage. + 0x1B78 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1759 + Shared Packet RAM for multiple Link Layer usage. + 0x1B7C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1760 + Shared Packet RAM for multiple Link Layer usage. + 0x1B80 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1761 + Shared Packet RAM for multiple Link Layer usage. + 0x1B84 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1762 + Shared Packet RAM for multiple Link Layer usage. + 0x1B88 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1763 + Shared Packet RAM for multiple Link Layer usage. + 0x1B8C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1764 + Shared Packet RAM for multiple Link Layer usage. + 0x1B90 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1765 + Shared Packet RAM for multiple Link Layer usage. + 0x1B94 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1766 + Shared Packet RAM for multiple Link Layer usage. + 0x1B98 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1767 + Shared Packet RAM for multiple Link Layer usage. + 0x1B9C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1768 + Shared Packet RAM for multiple Link Layer usage. + 0x1BA0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1769 + Shared Packet RAM for multiple Link Layer usage. + 0x1BA4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1770 + Shared Packet RAM for multiple Link Layer usage. + 0x1BA8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1771 + Shared Packet RAM for multiple Link Layer usage. + 0x1BAC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1772 + Shared Packet RAM for multiple Link Layer usage. + 0x1BB0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1773 + Shared Packet RAM for multiple Link Layer usage. + 0x1BB4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1774 + Shared Packet RAM for multiple Link Layer usage. + 0x1BB8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1775 + Shared Packet RAM for multiple Link Layer usage. + 0x1BBC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1776 + Shared Packet RAM for multiple Link Layer usage. + 0x1BC0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1777 + Shared Packet RAM for multiple Link Layer usage. + 0x1BC4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1778 + Shared Packet RAM for multiple Link Layer usage. + 0x1BC8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1779 + Shared Packet RAM for multiple Link Layer usage. + 0x1BCC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1780 + Shared Packet RAM for multiple Link Layer usage. + 0x1BD0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1781 + Shared Packet RAM for multiple Link Layer usage. + 0x1BD4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1782 + Shared Packet RAM for multiple Link Layer usage. + 0x1BD8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1783 + Shared Packet RAM for multiple Link Layer usage. + 0x1BDC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1784 + Shared Packet RAM for multiple Link Layer usage. + 0x1BE0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1785 + Shared Packet RAM for multiple Link Layer usage. + 0x1BE4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1786 + Shared Packet RAM for multiple Link Layer usage. + 0x1BE8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1787 + Shared Packet RAM for multiple Link Layer usage. + 0x1BEC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1788 + Shared Packet RAM for multiple Link Layer usage. + 0x1BF0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1789 + Shared Packet RAM for multiple Link Layer usage. + 0x1BF4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1790 + Shared Packet RAM for multiple Link Layer usage. + 0x1BF8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1791 + Shared Packet RAM for multiple Link Layer usage. + 0x1BFC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1792 + Shared Packet RAM for multiple Link Layer usage. + 0x1C00 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1793 + Shared Packet RAM for multiple Link Layer usage. + 0x1C04 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1794 + Shared Packet RAM for multiple Link Layer usage. + 0x1C08 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1795 + Shared Packet RAM for multiple Link Layer usage. + 0x1C0C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1796 + Shared Packet RAM for multiple Link Layer usage. + 0x1C10 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1797 + Shared Packet RAM for multiple Link Layer usage. + 0x1C14 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1798 + Shared Packet RAM for multiple Link Layer usage. + 0x1C18 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1799 + Shared Packet RAM for multiple Link Layer usage. + 0x1C1C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1800 + Shared Packet RAM for multiple Link Layer usage. + 0x1C20 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1801 + Shared Packet RAM for multiple Link Layer usage. + 0x1C24 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1802 + Shared Packet RAM for multiple Link Layer usage. + 0x1C28 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1803 + Shared Packet RAM for multiple Link Layer usage. + 0x1C2C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1804 + Shared Packet RAM for multiple Link Layer usage. + 0x1C30 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1805 + Shared Packet RAM for multiple Link Layer usage. + 0x1C34 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1806 + Shared Packet RAM for multiple Link Layer usage. + 0x1C38 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1807 + Shared Packet RAM for multiple Link Layer usage. + 0x1C3C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1808 + Shared Packet RAM for multiple Link Layer usage. + 0x1C40 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1809 + Shared Packet RAM for multiple Link Layer usage. + 0x1C44 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1810 + Shared Packet RAM for multiple Link Layer usage. + 0x1C48 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1811 + Shared Packet RAM for multiple Link Layer usage. + 0x1C4C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1812 + Shared Packet RAM for multiple Link Layer usage. + 0x1C50 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1813 + Shared Packet RAM for multiple Link Layer usage. + 0x1C54 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1814 + Shared Packet RAM for multiple Link Layer usage. + 0x1C58 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1815 + Shared Packet RAM for multiple Link Layer usage. + 0x1C5C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1816 + Shared Packet RAM for multiple Link Layer usage. + 0x1C60 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1817 + Shared Packet RAM for multiple Link Layer usage. + 0x1C64 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1818 + Shared Packet RAM for multiple Link Layer usage. + 0x1C68 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1819 + Shared Packet RAM for multiple Link Layer usage. + 0x1C6C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1820 + Shared Packet RAM for multiple Link Layer usage. + 0x1C70 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1821 + Shared Packet RAM for multiple Link Layer usage. + 0x1C74 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1822 + Shared Packet RAM for multiple Link Layer usage. + 0x1C78 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1823 + Shared Packet RAM for multiple Link Layer usage. + 0x1C7C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1824 + Shared Packet RAM for multiple Link Layer usage. + 0x1C80 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1825 + Shared Packet RAM for multiple Link Layer usage. + 0x1C84 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1826 + Shared Packet RAM for multiple Link Layer usage. + 0x1C88 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1827 + Shared Packet RAM for multiple Link Layer usage. + 0x1C8C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1828 + Shared Packet RAM for multiple Link Layer usage. + 0x1C90 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1829 + Shared Packet RAM for multiple Link Layer usage. + 0x1C94 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1830 + Shared Packet RAM for multiple Link Layer usage. + 0x1C98 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1831 + Shared Packet RAM for multiple Link Layer usage. + 0x1C9C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1832 + Shared Packet RAM for multiple Link Layer usage. + 0x1CA0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1833 + Shared Packet RAM for multiple Link Layer usage. + 0x1CA4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1834 + Shared Packet RAM for multiple Link Layer usage. + 0x1CA8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1835 + Shared Packet RAM for multiple Link Layer usage. + 0x1CAC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1836 + Shared Packet RAM for multiple Link Layer usage. + 0x1CB0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1837 + Shared Packet RAM for multiple Link Layer usage. + 0x1CB4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1838 + Shared Packet RAM for multiple Link Layer usage. + 0x1CB8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1839 + Shared Packet RAM for multiple Link Layer usage. + 0x1CBC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1840 + Shared Packet RAM for multiple Link Layer usage. + 0x1CC0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1841 + Shared Packet RAM for multiple Link Layer usage. + 0x1CC4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1842 + Shared Packet RAM for multiple Link Layer usage. + 0x1CC8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1843 + Shared Packet RAM for multiple Link Layer usage. + 0x1CCC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1844 + Shared Packet RAM for multiple Link Layer usage. + 0x1CD0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1845 + Shared Packet RAM for multiple Link Layer usage. + 0x1CD4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1846 + Shared Packet RAM for multiple Link Layer usage. + 0x1CD8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1847 + Shared Packet RAM for multiple Link Layer usage. + 0x1CDC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1848 + Shared Packet RAM for multiple Link Layer usage. + 0x1CE0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1849 + Shared Packet RAM for multiple Link Layer usage. + 0x1CE4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1850 + Shared Packet RAM for multiple Link Layer usage. + 0x1CE8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1851 + Shared Packet RAM for multiple Link Layer usage. + 0x1CEC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1852 + Shared Packet RAM for multiple Link Layer usage. + 0x1CF0 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1853 + Shared Packet RAM for multiple Link Layer usage. + 0x1CF4 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1854 + Shared Packet RAM for multiple Link Layer usage. + 0x1CF8 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1855 + Shared Packet RAM for multiple Link Layer usage. + 0x1CFC + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1856 + Shared Packet RAM for multiple Link Layer usage. + 0x1D00 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1857 + Shared Packet RAM for multiple Link Layer usage. + 0x1D04 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1858 + Shared Packet RAM for multiple Link Layer usage. + 0x1D08 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1859 + Shared Packet RAM for multiple Link Layer usage. + 0x1D0C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1860 + Shared Packet RAM for multiple Link Layer usage. + 0x1D10 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1861 + Shared Packet RAM for multiple Link Layer usage. + 0x1D14 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1862 + Shared Packet RAM for multiple Link Layer usage. + 0x1D18 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1863 + Shared Packet RAM for multiple Link Layer usage. + 0x1D1C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1864 + Shared Packet RAM for multiple Link Layer usage. + 0x1D20 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1865 + Shared Packet RAM for multiple Link Layer usage. + 0x1D24 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1866 + Shared Packet RAM for multiple Link Layer usage. + 0x1D28 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1867 + Shared Packet RAM for multiple Link Layer usage. + 0x1D2C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1868 + Shared Packet RAM for multiple Link Layer usage. + 0x1D30 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1869 + Shared Packet RAM for multiple Link Layer usage. + 0x1D34 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1870 + Shared Packet RAM for multiple Link Layer usage. + 0x1D38 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1871 + Shared Packet RAM for multiple Link Layer usage. + 0x1D3C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1872 + Shared Packet RAM for multiple Link Layer usage. + 0x1D40 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1873 + Shared Packet RAM for multiple Link Layer usage. + 0x1D44 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1874 + Shared Packet RAM for multiple Link Layer usage. + 0x1D48 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1875 + Shared Packet RAM for multiple Link Layer usage. + 0x1D4C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1876 + Shared Packet RAM for multiple Link Layer usage. + 0x1D50 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1877 + Shared Packet RAM for multiple Link Layer usage. + 0x1D54 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1878 + Shared Packet RAM for multiple Link Layer usage. + 0x1D58 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1879 + Shared Packet RAM for multiple Link Layer usage. + 0x1D5C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1880 + Shared Packet RAM for multiple Link Layer usage. + 0x1D60 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1881 + Shared Packet RAM for multiple Link Layer usage. + 0x1D64 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1882 + Shared Packet RAM for multiple Link Layer usage. + 0x1D68 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1883 + Shared Packet RAM for multiple Link Layer usage. + 0x1D6C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1884 + Shared Packet RAM for multiple Link Layer usage. + 0x1D70 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1885 + Shared Packet RAM for multiple Link Layer usage. + 0x1D74 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1886 + Shared Packet RAM for multiple Link Layer usage. + 0x1D78 + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + PACKET_RAM_1887 + Shared Packet RAM for multiple Link Layer usage. + 0x1D7C + 32 + read-write + 0 + 0 + + + RAM + One entry in the packet RAM + 0 + 32 + read-write + + + + + + + GPIOA + General Purpose Input/Output + GPIO + GPIOA_ + 0x400FF000 + + 0 + 0x18 + registers + + + PORTA + 30 + + + + PDOR + Port Data Output Register + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + PDO0 + Port Data Output + 0 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO1 + Port Data Output + 1 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO2 + Port Data Output + 2 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO3 + Port Data Output + 3 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO4 + Port Data Output + 4 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO5 + Port Data Output + 5 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO6 + Port Data Output + 6 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO7 + Port Data Output + 7 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO8 + Port Data Output + 8 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO9 + Port Data Output + 9 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO10 + Port Data Output + 10 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO11 + Port Data Output + 11 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO12 + Port Data Output + 12 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO13 + Port Data Output + 13 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO14 + Port Data Output + 14 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO15 + Port Data Output + 15 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO16 + Port Data Output + 16 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO17 + Port Data Output + 17 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO18 + Port Data Output + 18 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO19 + Port Data Output + 19 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO20 + Port Data Output + 20 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO21 + Port Data Output + 21 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO22 + Port Data Output + 22 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO23 + Port Data Output + 23 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO24 + Port Data Output + 24 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO25 + Port Data Output + 25 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO26 + Port Data Output + 26 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO27 + Port Data Output + 27 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO28 + Port Data Output + 28 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO29 + Port Data Output + 29 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO30 + Port Data Output + 30 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO31 + Port Data Output + 31 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + + + PSOR + Port Set Output Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + PTSO0 + Port Set Output + 0 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO1 + Port Set Output + 1 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO2 + Port Set Output + 2 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO3 + Port Set Output + 3 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO4 + Port Set Output + 4 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO5 + Port Set Output + 5 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO6 + Port Set Output + 6 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO7 + Port Set Output + 7 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO8 + Port Set Output + 8 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO9 + Port Set Output + 9 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO10 + Port Set Output + 10 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO11 + Port Set Output + 11 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO12 + Port Set Output + 12 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO13 + Port Set Output + 13 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO14 + Port Set Output + 14 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO15 + Port Set Output + 15 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO16 + Port Set Output + 16 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO17 + Port Set Output + 17 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO18 + Port Set Output + 18 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO19 + Port Set Output + 19 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO20 + Port Set Output + 20 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO21 + Port Set Output + 21 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO22 + Port Set Output + 22 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO23 + Port Set Output + 23 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO24 + Port Set Output + 24 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO25 + Port Set Output + 25 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO26 + Port Set Output + 26 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO27 + Port Set Output + 27 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO28 + Port Set Output + 28 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO29 + Port Set Output + 29 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO30 + Port Set Output + 30 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO31 + Port Set Output + 31 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + + + PCOR + Port Clear Output Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + PTCO0 + Port Clear Output + 0 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO1 + Port Clear Output + 1 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO2 + Port Clear Output + 2 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO3 + Port Clear Output + 3 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO4 + Port Clear Output + 4 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO5 + Port Clear Output + 5 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO6 + Port Clear Output + 6 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO7 + Port Clear Output + 7 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO8 + Port Clear Output + 8 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO9 + Port Clear Output + 9 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO10 + Port Clear Output + 10 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO11 + Port Clear Output + 11 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO12 + Port Clear Output + 12 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO13 + Port Clear Output + 13 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO14 + Port Clear Output + 14 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO15 + Port Clear Output + 15 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO16 + Port Clear Output + 16 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO17 + Port Clear Output + 17 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO18 + Port Clear Output + 18 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO19 + Port Clear Output + 19 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO20 + Port Clear Output + 20 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO21 + Port Clear Output + 21 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO22 + Port Clear Output + 22 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO23 + Port Clear Output + 23 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO24 + Port Clear Output + 24 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO25 + Port Clear Output + 25 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO26 + Port Clear Output + 26 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO27 + Port Clear Output + 27 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO28 + Port Clear Output + 28 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO29 + Port Clear Output + 29 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO30 + Port Clear Output + 30 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO31 + Port Clear Output + 31 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + + + PTOR + Port Toggle Output Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + PTTO0 + Port Toggle Output + 0 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO1 + Port Toggle Output + 1 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO2 + Port Toggle Output + 2 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO3 + Port Toggle Output + 3 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO4 + Port Toggle Output + 4 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO5 + Port Toggle Output + 5 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO6 + Port Toggle Output + 6 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO7 + Port Toggle Output + 7 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO8 + Port Toggle Output + 8 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO9 + Port Toggle Output + 9 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO10 + Port Toggle Output + 10 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO11 + Port Toggle Output + 11 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO12 + Port Toggle Output + 12 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO13 + Port Toggle Output + 13 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO14 + Port Toggle Output + 14 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO15 + Port Toggle Output + 15 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO16 + Port Toggle Output + 16 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO17 + Port Toggle Output + 17 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO18 + Port Toggle Output + 18 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO19 + Port Toggle Output + 19 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO20 + Port Toggle Output + 20 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO21 + Port Toggle Output + 21 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO22 + Port Toggle Output + 22 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO23 + Port Toggle Output + 23 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO24 + Port Toggle Output + 24 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO25 + Port Toggle Output + 25 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO26 + Port Toggle Output + 26 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO27 + Port Toggle Output + 27 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO28 + Port Toggle Output + 28 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO29 + Port Toggle Output + 29 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO30 + Port Toggle Output + 30 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO31 + Port Toggle Output + 31 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + + + PDIR + Port Data Input Register + 0x10 + 32 + read-only + 0 + 0xFFFFFFFF + + + PDI0 + Port Data Input + 0 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI1 + Port Data Input + 1 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI2 + Port Data Input + 2 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI3 + Port Data Input + 3 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI4 + Port Data Input + 4 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI5 + Port Data Input + 5 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI6 + Port Data Input + 6 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI7 + Port Data Input + 7 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI8 + Port Data Input + 8 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI9 + Port Data Input + 9 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI10 + Port Data Input + 10 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI11 + Port Data Input + 11 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI12 + Port Data Input + 12 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI13 + Port Data Input + 13 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI14 + Port Data Input + 14 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI15 + Port Data Input + 15 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI16 + Port Data Input + 16 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI17 + Port Data Input + 17 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI18 + Port Data Input + 18 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI19 + Port Data Input + 19 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI20 + Port Data Input + 20 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI21 + Port Data Input + 21 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI22 + Port Data Input + 22 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI23 + Port Data Input + 23 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI24 + Port Data Input + 24 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI25 + Port Data Input + 25 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI26 + Port Data Input + 26 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI27 + Port Data Input + 27 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI28 + Port Data Input + 28 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI29 + Port Data Input + 29 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI30 + Port Data Input + 30 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI31 + Port Data Input + 31 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + + + PDDR + Port Data Direction Register + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + PDD0 + Port Data Direction + 0 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD1 + Port Data Direction + 1 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD2 + Port Data Direction + 2 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD3 + Port Data Direction + 3 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD4 + Port Data Direction + 4 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD5 + Port Data Direction + 5 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD6 + Port Data Direction + 6 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD7 + Port Data Direction + 7 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD8 + Port Data Direction + 8 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD9 + Port Data Direction + 9 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD10 + Port Data Direction + 10 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD11 + Port Data Direction + 11 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD12 + Port Data Direction + 12 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD13 + Port Data Direction + 13 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD14 + Port Data Direction + 14 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD15 + Port Data Direction + 15 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD16 + Port Data Direction + 16 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD17 + Port Data Direction + 17 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD18 + Port Data Direction + 18 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD19 + Port Data Direction + 19 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD20 + Port Data Direction + 20 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD21 + Port Data Direction + 21 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD22 + Port Data Direction + 22 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD23 + Port Data Direction + 23 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD24 + Port Data Direction + 24 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD25 + Port Data Direction + 25 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD26 + Port Data Direction + 26 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD27 + Port Data Direction + 27 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD28 + Port Data Direction + 28 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD29 + Port Data Direction + 29 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD30 + Port Data Direction + 30 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD31 + Port Data Direction + 31 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + + + + + GPIOB + General Purpose Input/Output + GPIO + GPIOB_ + 0x400FF040 + + 0 + 0x18 + registers + + + PORTB_PORTC + 31 + + + + PDOR + Port Data Output Register + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + PDO0 + Port Data Output + 0 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO1 + Port Data Output + 1 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO2 + Port Data Output + 2 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO3 + Port Data Output + 3 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO4 + Port Data Output + 4 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO5 + Port Data Output + 5 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO6 + Port Data Output + 6 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO7 + Port Data Output + 7 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO8 + Port Data Output + 8 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO9 + Port Data Output + 9 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO10 + Port Data Output + 10 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO11 + Port Data Output + 11 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO12 + Port Data Output + 12 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO13 + Port Data Output + 13 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO14 + Port Data Output + 14 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO15 + Port Data Output + 15 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO16 + Port Data Output + 16 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO17 + Port Data Output + 17 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO18 + Port Data Output + 18 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO19 + Port Data Output + 19 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO20 + Port Data Output + 20 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO21 + Port Data Output + 21 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO22 + Port Data Output + 22 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO23 + Port Data Output + 23 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO24 + Port Data Output + 24 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO25 + Port Data Output + 25 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO26 + Port Data Output + 26 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO27 + Port Data Output + 27 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO28 + Port Data Output + 28 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO29 + Port Data Output + 29 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO30 + Port Data Output + 30 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO31 + Port Data Output + 31 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + + + PSOR + Port Set Output Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + PTSO0 + Port Set Output + 0 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO1 + Port Set Output + 1 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO2 + Port Set Output + 2 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO3 + Port Set Output + 3 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO4 + Port Set Output + 4 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO5 + Port Set Output + 5 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO6 + Port Set Output + 6 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO7 + Port Set Output + 7 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO8 + Port Set Output + 8 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO9 + Port Set Output + 9 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO10 + Port Set Output + 10 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO11 + Port Set Output + 11 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO12 + Port Set Output + 12 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO13 + Port Set Output + 13 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO14 + Port Set Output + 14 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO15 + Port Set Output + 15 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO16 + Port Set Output + 16 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO17 + Port Set Output + 17 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO18 + Port Set Output + 18 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO19 + Port Set Output + 19 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO20 + Port Set Output + 20 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO21 + Port Set Output + 21 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO22 + Port Set Output + 22 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO23 + Port Set Output + 23 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO24 + Port Set Output + 24 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO25 + Port Set Output + 25 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO26 + Port Set Output + 26 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO27 + Port Set Output + 27 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO28 + Port Set Output + 28 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO29 + Port Set Output + 29 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO30 + Port Set Output + 30 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO31 + Port Set Output + 31 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + + + PCOR + Port Clear Output Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + PTCO0 + Port Clear Output + 0 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO1 + Port Clear Output + 1 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO2 + Port Clear Output + 2 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO3 + Port Clear Output + 3 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO4 + Port Clear Output + 4 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO5 + Port Clear Output + 5 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO6 + Port Clear Output + 6 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO7 + Port Clear Output + 7 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO8 + Port Clear Output + 8 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO9 + Port Clear Output + 9 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO10 + Port Clear Output + 10 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO11 + Port Clear Output + 11 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO12 + Port Clear Output + 12 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO13 + Port Clear Output + 13 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO14 + Port Clear Output + 14 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO15 + Port Clear Output + 15 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO16 + Port Clear Output + 16 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO17 + Port Clear Output + 17 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO18 + Port Clear Output + 18 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO19 + Port Clear Output + 19 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO20 + Port Clear Output + 20 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO21 + Port Clear Output + 21 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO22 + Port Clear Output + 22 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO23 + Port Clear Output + 23 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO24 + Port Clear Output + 24 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO25 + Port Clear Output + 25 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO26 + Port Clear Output + 26 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO27 + Port Clear Output + 27 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO28 + Port Clear Output + 28 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO29 + Port Clear Output + 29 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO30 + Port Clear Output + 30 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO31 + Port Clear Output + 31 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + + + PTOR + Port Toggle Output Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + PTTO0 + Port Toggle Output + 0 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO1 + Port Toggle Output + 1 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO2 + Port Toggle Output + 2 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO3 + Port Toggle Output + 3 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO4 + Port Toggle Output + 4 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO5 + Port Toggle Output + 5 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO6 + Port Toggle Output + 6 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO7 + Port Toggle Output + 7 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO8 + Port Toggle Output + 8 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO9 + Port Toggle Output + 9 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO10 + Port Toggle Output + 10 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO11 + Port Toggle Output + 11 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO12 + Port Toggle Output + 12 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO13 + Port Toggle Output + 13 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO14 + Port Toggle Output + 14 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO15 + Port Toggle Output + 15 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO16 + Port Toggle Output + 16 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO17 + Port Toggle Output + 17 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO18 + Port Toggle Output + 18 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO19 + Port Toggle Output + 19 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO20 + Port Toggle Output + 20 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO21 + Port Toggle Output + 21 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO22 + Port Toggle Output + 22 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO23 + Port Toggle Output + 23 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO24 + Port Toggle Output + 24 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO25 + Port Toggle Output + 25 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO26 + Port Toggle Output + 26 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO27 + Port Toggle Output + 27 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO28 + Port Toggle Output + 28 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO29 + Port Toggle Output + 29 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO30 + Port Toggle Output + 30 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO31 + Port Toggle Output + 31 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + + + PDIR + Port Data Input Register + 0x10 + 32 + read-only + 0 + 0xFFFFFFFF + + + PDI0 + Port Data Input + 0 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI1 + Port Data Input + 1 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI2 + Port Data Input + 2 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI3 + Port Data Input + 3 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI4 + Port Data Input + 4 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI5 + Port Data Input + 5 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI6 + Port Data Input + 6 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI7 + Port Data Input + 7 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI8 + Port Data Input + 8 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI9 + Port Data Input + 9 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI10 + Port Data Input + 10 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI11 + Port Data Input + 11 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI12 + Port Data Input + 12 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI13 + Port Data Input + 13 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI14 + Port Data Input + 14 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI15 + Port Data Input + 15 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI16 + Port Data Input + 16 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI17 + Port Data Input + 17 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI18 + Port Data Input + 18 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI19 + Port Data Input + 19 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI20 + Port Data Input + 20 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI21 + Port Data Input + 21 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI22 + Port Data Input + 22 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI23 + Port Data Input + 23 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI24 + Port Data Input + 24 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI25 + Port Data Input + 25 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI26 + Port Data Input + 26 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI27 + Port Data Input + 27 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI28 + Port Data Input + 28 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI29 + Port Data Input + 29 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI30 + Port Data Input + 30 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI31 + Port Data Input + 31 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + + + PDDR + Port Data Direction Register + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + PDD0 + Port Data Direction + 0 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD1 + Port Data Direction + 1 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD2 + Port Data Direction + 2 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD3 + Port Data Direction + 3 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD4 + Port Data Direction + 4 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD5 + Port Data Direction + 5 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD6 + Port Data Direction + 6 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD7 + Port Data Direction + 7 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD8 + Port Data Direction + 8 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD9 + Port Data Direction + 9 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD10 + Port Data Direction + 10 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD11 + Port Data Direction + 11 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD12 + Port Data Direction + 12 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD13 + Port Data Direction + 13 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD14 + Port Data Direction + 14 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD15 + Port Data Direction + 15 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD16 + Port Data Direction + 16 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD17 + Port Data Direction + 17 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD18 + Port Data Direction + 18 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD19 + Port Data Direction + 19 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD20 + Port Data Direction + 20 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD21 + Port Data Direction + 21 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD22 + Port Data Direction + 22 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD23 + Port Data Direction + 23 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD24 + Port Data Direction + 24 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD25 + Port Data Direction + 25 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD26 + Port Data Direction + 26 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD27 + Port Data Direction + 27 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD28 + Port Data Direction + 28 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD29 + Port Data Direction + 29 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD30 + Port Data Direction + 30 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD31 + Port Data Direction + 31 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + + + + + GPIOC + General Purpose Input/Output + GPIO + GPIOC_ + 0x400FF080 + + 0 + 0x18 + registers + + + PORTB_PORTC + 31 + + + + PDOR + Port Data Output Register + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + PDO0 + Port Data Output + 0 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO1 + Port Data Output + 1 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO2 + Port Data Output + 2 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO3 + Port Data Output + 3 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO4 + Port Data Output + 4 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO5 + Port Data Output + 5 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO6 + Port Data Output + 6 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO7 + Port Data Output + 7 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO8 + Port Data Output + 8 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO9 + Port Data Output + 9 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO10 + Port Data Output + 10 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO11 + Port Data Output + 11 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO12 + Port Data Output + 12 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO13 + Port Data Output + 13 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO14 + Port Data Output + 14 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO15 + Port Data Output + 15 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO16 + Port Data Output + 16 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO17 + Port Data Output + 17 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO18 + Port Data Output + 18 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO19 + Port Data Output + 19 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO20 + Port Data Output + 20 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO21 + Port Data Output + 21 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO22 + Port Data Output + 22 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO23 + Port Data Output + 23 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO24 + Port Data Output + 24 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO25 + Port Data Output + 25 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO26 + Port Data Output + 26 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO27 + Port Data Output + 27 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO28 + Port Data Output + 28 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO29 + Port Data Output + 29 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO30 + Port Data Output + 30 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + PDO31 + Port Data Output + 31 + 1 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + + + PSOR + Port Set Output Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + PTSO0 + Port Set Output + 0 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO1 + Port Set Output + 1 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO2 + Port Set Output + 2 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO3 + Port Set Output + 3 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO4 + Port Set Output + 4 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO5 + Port Set Output + 5 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO6 + Port Set Output + 6 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO7 + Port Set Output + 7 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO8 + Port Set Output + 8 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO9 + Port Set Output + 9 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO10 + Port Set Output + 10 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO11 + Port Set Output + 11 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO12 + Port Set Output + 12 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO13 + Port Set Output + 13 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO14 + Port Set Output + 14 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO15 + Port Set Output + 15 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO16 + Port Set Output + 16 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO17 + Port Set Output + 17 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO18 + Port Set Output + 18 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO19 + Port Set Output + 19 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO20 + Port Set Output + 20 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO21 + Port Set Output + 21 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO22 + Port Set Output + 22 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO23 + Port Set Output + 23 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO24 + Port Set Output + 24 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO25 + Port Set Output + 25 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO26 + Port Set Output + 26 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO27 + Port Set Output + 27 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO28 + Port Set Output + 28 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO29 + Port Set Output + 29 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO30 + Port Set Output + 30 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + PTSO31 + Port Set Output + 31 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + + + PCOR + Port Clear Output Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + PTCO0 + Port Clear Output + 0 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO1 + Port Clear Output + 1 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO2 + Port Clear Output + 2 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO3 + Port Clear Output + 3 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO4 + Port Clear Output + 4 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO5 + Port Clear Output + 5 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO6 + Port Clear Output + 6 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO7 + Port Clear Output + 7 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO8 + Port Clear Output + 8 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO9 + Port Clear Output + 9 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO10 + Port Clear Output + 10 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO11 + Port Clear Output + 11 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO12 + Port Clear Output + 12 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO13 + Port Clear Output + 13 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO14 + Port Clear Output + 14 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO15 + Port Clear Output + 15 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO16 + Port Clear Output + 16 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO17 + Port Clear Output + 17 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO18 + Port Clear Output + 18 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO19 + Port Clear Output + 19 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO20 + Port Clear Output + 20 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO21 + Port Clear Output + 21 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO22 + Port Clear Output + 22 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO23 + Port Clear Output + 23 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO24 + Port Clear Output + 24 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO25 + Port Clear Output + 25 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO26 + Port Clear Output + 26 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO27 + Port Clear Output + 27 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO28 + Port Clear Output + 28 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO29 + Port Clear Output + 29 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO30 + Port Clear Output + 30 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + PTCO31 + Port Clear Output + 31 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + + + PTOR + Port Toggle Output Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + PTTO0 + Port Toggle Output + 0 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO1 + Port Toggle Output + 1 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO2 + Port Toggle Output + 2 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO3 + Port Toggle Output + 3 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO4 + Port Toggle Output + 4 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO5 + Port Toggle Output + 5 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO6 + Port Toggle Output + 6 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO7 + Port Toggle Output + 7 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO8 + Port Toggle Output + 8 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO9 + Port Toggle Output + 9 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO10 + Port Toggle Output + 10 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO11 + Port Toggle Output + 11 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO12 + Port Toggle Output + 12 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO13 + Port Toggle Output + 13 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO14 + Port Toggle Output + 14 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO15 + Port Toggle Output + 15 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO16 + Port Toggle Output + 16 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO17 + Port Toggle Output + 17 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO18 + Port Toggle Output + 18 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO19 + Port Toggle Output + 19 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO20 + Port Toggle Output + 20 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO21 + Port Toggle Output + 21 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO22 + Port Toggle Output + 22 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO23 + Port Toggle Output + 23 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO24 + Port Toggle Output + 24 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO25 + Port Toggle Output + 25 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO26 + Port Toggle Output + 26 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO27 + Port Toggle Output + 27 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO28 + Port Toggle Output + 28 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO29 + Port Toggle Output + 29 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO30 + Port Toggle Output + 30 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + PTTO31 + Port Toggle Output + 31 + 1 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + + + PDIR + Port Data Input Register + 0x10 + 32 + read-only + 0 + 0xFFFFFFFF + + + PDI0 + Port Data Input + 0 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI1 + Port Data Input + 1 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI2 + Port Data Input + 2 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI3 + Port Data Input + 3 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI4 + Port Data Input + 4 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI5 + Port Data Input + 5 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI6 + Port Data Input + 6 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI7 + Port Data Input + 7 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI8 + Port Data Input + 8 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI9 + Port Data Input + 9 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI10 + Port Data Input + 10 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI11 + Port Data Input + 11 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI12 + Port Data Input + 12 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI13 + Port Data Input + 13 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI14 + Port Data Input + 14 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI15 + Port Data Input + 15 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI16 + Port Data Input + 16 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI17 + Port Data Input + 17 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI18 + Port Data Input + 18 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI19 + Port Data Input + 19 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI20 + Port Data Input + 20 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI21 + Port Data Input + 21 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI22 + Port Data Input + 22 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI23 + Port Data Input + 23 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI24 + Port Data Input + 24 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI25 + Port Data Input + 25 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI26 + Port Data Input + 26 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI27 + Port Data Input + 27 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI28 + Port Data Input + 28 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI29 + Port Data Input + 29 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI30 + Port Data Input + 30 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + PDI31 + Port Data Input + 31 + 1 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + + + PDDR + Port Data Direction Register + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + PDD0 + Port Data Direction + 0 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD1 + Port Data Direction + 1 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD2 + Port Data Direction + 2 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD3 + Port Data Direction + 3 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD4 + Port Data Direction + 4 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD5 + Port Data Direction + 5 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD6 + Port Data Direction + 6 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD7 + Port Data Direction + 7 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD8 + Port Data Direction + 8 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD9 + Port Data Direction + 9 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD10 + Port Data Direction + 10 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD11 + Port Data Direction + 11 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD12 + Port Data Direction + 12 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD13 + Port Data Direction + 13 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD14 + Port Data Direction + 14 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD15 + Port Data Direction + 15 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD16 + Port Data Direction + 16 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD17 + Port Data Direction + 17 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD18 + Port Data Direction + 18 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD19 + Port Data Direction + 19 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD20 + Port Data Direction + 20 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD21 + Port Data Direction + 21 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD22 + Port Data Direction + 22 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD23 + Port Data Direction + 23 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD24 + Port Data Direction + 24 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD25 + Port Data Direction + 25 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD26 + Port Data Direction + 26 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD27 + Port Data Direction + 27 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD28 + Port Data Direction + 28 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD29 + Port Data Direction + 29 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD30 + Port Data Direction + 30 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + PDD31 + Port Data Direction + 31 + 1 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + + + + + SystemControl + System Control Block + SCB_ + 0xE000E000 + + 0x8 + 0xD2C + registers + + + + ACTLR + Auxiliary Control Register, + 0x8 + 32 + read-only + 0 + 0xFFFFFFFF + + + CPUID + CPUID Base Register + 0xD00 + 32 + read-only + 0x410CC601 + 0xFFFFFFFF + + + REVISION + Minor revision number m in the rnpm revision status + 0 + 4 + read-only + + + PARTNO + Indicates part number + 4 + 12 + read-only + + + ARCHITECTURE + Indicates the architecture + 16 + 4 + read-only + + + VARIANT + Major revision number n in the npm revision status + 20 + 4 + read-only + + + IMPLEMENTER + Implementer code + 24 + 8 + read-only + + + + + ICSR + Interrupt Control and State Register + 0xD04 + 32 + read-write + 0 + 0xFFFFFFFF + + + VECTPENDING + Exception number of the highest priority pending enabled exception + 12 + 6 + read-only + + + PENDSTCLR + SysTick exception clear-pending bit + 25 + 1 + write-only + + + 0 + no effect + #0 + + + 1 + removes the pending state from the SysTick exception + #1 + + + + + PENDSTSET + SysTick exception set-pending bit + 26 + 1 + read-write + + + 0 + write: no effect; read: SysTick exception is not pending + #0 + + + 1 + write: changes SysTick exception state to pending; read: SysTick exception is pending + #1 + + + + + PENDSVCLR + PendSV clear-pending bit + 27 + 1 + write-only + + + 0 + no effect + #0 + + + 1 + removes the pending state from the PendSV exception + #1 + + + + + PENDSVSET + PendSV set-pending bit + 28 + 1 + read-write + + + 0 + write: no effect; read: PendSV exception is not pending + #0 + + + 1 + write: changes PendSV exception state to pending; read: PendSV exception is pending + #1 + + + + + NMIPENDSET + NMI set-pending bit + 31 + 1 + read-write + + + 0 + write: no effect; read: NMI exception is not pending + #0 + + + 1 + write: changes NMI exception state to pending; read: NMI exception is pending + #1 + + + + + + + VTOR + Vector Table Offset Register + 0xD08 + 32 + read-write + 0 + 0xFFFFFFFF + + + TBLOFF + Vector table base offset + 7 + 25 + read-write + + + + + AIRCR + Application Interrupt and Reset Control Register + 0xD0C + 32 + read-write + 0xFA050000 + 0xFFFFFFFF + + + VECTCLRACTIVE + Reserved for Debug use + 1 + 1 + write-only + + + SYSRESETREQ + System reset request + 2 + 1 + write-only + + + 0 + no system reset request + #0 + + + 1 + asserts a signal to the outer system that requests a reset + #1 + + + + + ENDIANNESS + Data endianness bit + 15 + 1 + read-only + + + 0 + Little-endian + #0 + + + 1 + Big-endian + #1 + + + + + VECTKEY + Register key + 16 + 16 + read-write + + + + + SCR + System Control Register + 0xD10 + 32 + read-write + 0 + 0xFFFFFFFF + + + SLEEPONEXIT + Indicates sleep-on-exit when returning from Handler mode to Thread mode + 1 + 1 + read-write + + + 0 + do not sleep when returning to Thread mode + #0 + + + 1 + enter sleep, or deep sleep, on return from an ISR + #1 + + + + + SLEEPDEEP + Controls whether the processor uses sleep or deep sleep as its low power mode + 2 + 1 + read-write + + + 0 + sleep + #0 + + + 1 + deep sleep + #1 + + + + + SEVONPEND + Send Event on Pending bit + 4 + 1 + read-write + + + 0 + only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded + #0 + + + 1 + enabled events and all interrupts, including disabled interrupts, can wakeup the processor + #1 + + + + + + + CCR + Configuration and Control Register + 0xD14 + 32 + read-only + 0x208 + 0xFFFFFFFF + + + UNALIGN_TRP + Always reads as one, indicates that all unaligned accesses generate a HardFault + 3 + 1 + read-only + + + STKALIGN + Indicates stack alignment on exception entry + 9 + 1 + read-only + + + + + SHPR2 + System Handler Priority Register 2 + 0xD1C + 32 + read-write + 0 + 0xFFFFFFFF + + + PRI_11 + Priority of system handler 11, SVCall + 30 + 2 + read-write + + + + + SHPR3 + System Handler Priority Register 3 + 0xD20 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRI_14 + Priority of system handler 14, PendSV + 22 + 2 + read-write + + + PRI_15 + Priority of system handler 15, SysTick exception + 30 + 2 + read-write + + + + + SHCSR + System Handler Control and State Register + 0xD24 + 32 + read-write + 0 + 0xFFFFFFFF + + + SVCALLPENDED + no description available + 15 + 1 + read-write + + + 0 + exception is not pending + #0 + + + 1 + exception is pending + #1 + + + + + + + DFSR + Debug Fault Status Register + 0xD30 + 32 + read-write + 0 + 0xFFFFFFFF + + + HALTED + no description available + 0 + 1 + read-write + + + 0 + No active halt request debug event + #0 + + + 1 + Halt request debug event active + #1 + + + + + BKPT + no description available + 1 + 1 + read-write + + + 0 + No current breakpoint debug event + #0 + + + 1 + At least one current breakpoint debug event + #1 + + + + + DWTTRAP + no description available + 2 + 1 + read-write + + + 0 + No current debug events generated by the DWT + #0 + + + 1 + At least one current debug event generated by the DWT + #1 + + + + + VCATCH + no description available + 3 + 1 + read-write + + + 0 + No Vector catch triggered + #0 + + + 1 + Vector catch triggered + #1 + + + + + EXTERNAL + no description available + 4 + 1 + read-write + + + 0 + No EDBGRQ debug event + #0 + + + 1 + EDBGRQ debug event + #1 + + + + + + + + + SysTick + System timer + SYST_ + 0xE000E010 + + 0 + 0x10 + registers + + + + CSR + SysTick Control and Status Register + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENABLE + no description available + 0 + 1 + read-write + + + 0 + counter disabled + #0 + + + 1 + counter enabled + #1 + + + + + TICKINT + no description available + 1 + 1 + read-write + + + 0 + counting down to 0 does not assert the SysTick exception request + #0 + + + 1 + counting down to 0 asserts the SysTick exception request + #1 + + + + + CLKSOURCE + no description available + 2 + 1 + read-write + + + 0 + external clock + #0 + + + 1 + processor clock + #1 + + + + + COUNTFLAG + no description available + 16 + 1 + read-write + + + + + RVR + SysTick Reload Value Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + RELOAD + Value to load into the SysTick Current Value Register when the counter reaches 0 + 0 + 24 + read-write + + + + + CVR + SysTick Current Value Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + CURRENT + Current value at the time the register is accessed + 0 + 24 + read-write + + + + + CALIB + SysTick Calibration Value Register + 0xC + 32 + read-only + 0 + 0xFFFFFFFF + + + TENMS + Reload value to use for 10ms timing + 0 + 24 + read-only + + + SKEW + no description available + 30 + 1 + read-only + + + 0 + 10ms calibration value is exact + #0 + + + 1 + 10ms calibration value is inexact, because of the clock frequency + #1 + + + + + NOREF + no description available + 31 + 1 + read-only + + + 0 + The reference clock is provided + #0 + + + 1 + The reference clock is not provided + #1 + + + + + + + + + NVIC + Nested Vectored Interrupt Controller + 0xE000E100 + + 0 + 0x320 + registers + + + + NVIC_ISER + Interrupt Set Enable Register + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + SETENA0 + DMA channel 0 transfer complete/error interrupt set-enable bit + 0 + 1 + read-write + + + 0 + write: no effect; read: DMA channel 0 transfer complete/error interrupt disabled + #0 + + + 1 + write: enable DMA channel 0 transfer complete/error interrupt; read: DMA channel 0 transfer complete/error interrupt enabled + #1 + + + + + SETENA1 + DMA channel 1 transfer complete/error interrupt set-enable bit + 1 + 1 + read-write + + + 0 + write: no effect; read: DMA channel 1 transfer complete/error interrupt disabled + #0 + + + 1 + write: enable DMA channel 1 transfer complete/error interrupt; read: DMA channel 1 transfer complete/error interrupt enabled + #1 + + + + + SETENA2 + DMA channel 2 transfer complete/error interrupt set-enable bit + 2 + 1 + read-write + + + 0 + write: no effect; read: DMA channel 2 transfer complete/error interrupt disabled + #0 + + + 1 + write: enable DMA channel 2 transfer complete/error interrupt; read: DMA channel 2 transfer complete/error interrupt enabled + #1 + + + + + SETENA3 + DMA channel 3 transfer complete/error interrupt set-enable bit + 3 + 1 + read-write + + + 0 + write: no effect; read: DMA channel 3 transfer complete/error interrupt disabled + #0 + + + 1 + write: enable DMA channel 3 transfer complete/error interrupt; read: DMA channel 3 transfer complete/error interrupt enabled + #1 + + + + + SETENA4 + FIFO underrun, FIFO overflow, data ready, transfer complete and error interrupt set-enable bit + 4 + 1 + read-write + + + 0 + write: no effect; read: FIFO underrun, FIFO overflow, data ready, transfer complete and error interrupt disabled + #0 + + + 1 + write: enable FIFO underrun, FIFO overflow, data ready, transfer complete and error interrupt; read: FIFO underrun, FIFO overflow, data ready, transfer complete and error interrupt enabled + #1 + + + + + SETENA5 + Command complete and read collision, Flash ECC Errors interrupt set-enable bit + 5 + 1 + read-write + + + 0 + write: no effect; read: Command complete and read collision, Flash ECC Errors interrupt disabled + #0 + + + 1 + write: enable Command complete and read collision, Flash ECC Errors interrupt; read: Command complete and read collision, Flash ECC Errors interrupt enabled + #1 + + + + + SETENA6 + Low-voltage detect, low-voltage warning and DCDC PSWITCH interrupt interrupt set-enable bit + 6 + 1 + read-write + + + 0 + write: no effect; read: Low-voltage detect, low-voltage warning and DCDC PSWITCH interrupt interrupt disabled + #0 + + + 1 + write: enable Low-voltage detect, low-voltage warning and DCDC PSWITCH interrupt interrupt; read: Low-voltage detect, low-voltage warning and DCDC PSWITCH interrupt interrupt enabled + #1 + + + + + SETENA7 + Low Leakage Wakeup interrupt set-enable bit + 7 + 1 + read-write + + + 0 + write: no effect; read: Low Leakage Wakeup interrupt disabled + #0 + + + 1 + write: enable Low Leakage Wakeup interrupt; read: Low Leakage Wakeup interrupt enabled + #1 + + + + + SETENA8 + Inter-Integrated Circuit 0 interrupt set-enable bit + 8 + 1 + read-write + + + 0 + write: no effect; read: Inter-Integrated Circuit 0 interrupt disabled + #0 + + + 1 + write: enable Inter-Integrated Circuit 0 interrupt; read: Inter-Integrated Circuit 0 interrupt enabled + #1 + + + + + SETENA9 + Inter-Integrated Circuit 1 interrupt set-enable bit + 9 + 1 + read-write + + + 0 + write: no effect; read: Inter-Integrated Circuit 1 interrupt disabled + #0 + + + 1 + write: enable Inter-Integrated Circuit 1 interrupt; read: Inter-Integrated Circuit 1 interrupt enabled + #1 + + + + + SETENA10 + Serial Peripheral Interface 0 interrupt set-enable bit + 10 + 1 + read-write + + + 0 + write: no effect; read: Serial Peripheral Interface 0 interrupt disabled + #0 + + + 1 + write: enable Serial Peripheral Interface 0 interrupt; read: Serial Peripheral Interface 0 interrupt enabled + #1 + + + + + SETENA11 + FlexCAN0 ORed Error, Bus off, Transmit/Receive Warning, Wake up interrupt set-enable bit + 11 + 1 + read-write + + + 0 + write: no effect; read: FlexCAN0 ORed Error, Bus off, Transmit/Receive Warning, Wake up interrupt disabled + #0 + + + 1 + write: enable FlexCAN0 ORed Error, Bus off, Transmit/Receive Warning, Wake up interrupt; read: FlexCAN0 ORed Error, Bus off, Transmit/Receive Warning, Wake up interrupt enabled + #1 + + + + + SETENA12 + LPUART0 or LPUART1 status and error interrupt set-enable bit + 12 + 1 + read-write + + + 0 + write: no effect; read: LPUART0 or LPUART1 status and error interrupt disabled + #0 + + + 1 + write: enable LPUART0 or LPUART1 status and error interrupt; read: LPUART0 or LPUART1 status and error interrupt enabled + #1 + + + + + SETENA13 + True Random Number Generator interrupt set-enable bit + 13 + 1 + read-write + + + 0 + write: no effect; read: True Random Number Generator interrupt disabled + #0 + + + 1 + write: enable True Random Number Generator interrupt; read: True Random Number Generator interrupt enabled + #1 + + + + + SETENA14 + Carrier modulator transmitter interrupt set-enable bit + 14 + 1 + read-write + + + 0 + write: no effect; read: Carrier modulator transmitter interrupt disabled + #0 + + + 1 + write: enable Carrier modulator transmitter interrupt; read: Carrier modulator transmitter interrupt enabled + #1 + + + + + SETENA15 + Analog-to-Digital Converter 0 interrupt set-enable bit + 15 + 1 + read-write + + + 0 + write: no effect; read: Analog-to-Digital Converter 0 interrupt disabled + #0 + + + 1 + write: enable Analog-to-Digital Converter 0 interrupt; read: Analog-to-Digital Converter 0 interrupt enabled + #1 + + + + + SETENA16 + DMA channel 0 - 31 error interrupt set-enable bit + 16 + 1 + read-write + + + 0 + write: no effect; read: DMA channel 0 - 31 error interrupt disabled + #0 + + + 1 + write: enable DMA channel 0 - 31 error interrupt; read: DMA channel 0 - 31 error interrupt enabled + #1 + + + + + SETENA17 + Timer/PWM module 0 interrupt set-enable bit + 17 + 1 + read-write + + + 0 + write: no effect; read: Timer/PWM module 0 interrupt disabled + #0 + + + 1 + write: enable Timer/PWM module 0 interrupt; read: Timer/PWM module 0 interrupt enabled + #1 + + + + + SETENA18 + Timer/PWM module 1 interrupt set-enable bit + 18 + 1 + read-write + + + 0 + write: no effect; read: Timer/PWM module 1 interrupt disabled + #0 + + + 1 + write: enable Timer/PWM module 1 interrupt; read: Timer/PWM module 1 interrupt enabled + #1 + + + + + SETENA19 + Timer/PWM module 2 interrupt set-enable bit + 19 + 1 + read-write + + + 0 + write: no effect; read: Timer/PWM module 2 interrupt disabled + #0 + + + 1 + write: enable Timer/PWM module 2 interrupt; read: Timer/PWM module 2 interrupt enabled + #1 + + + + + SETENA20 + Real-time counter interrupt set-enable bit + 20 + 1 + read-write + + + 0 + write: no effect; read: Real-time counter interrupt disabled + #0 + + + 1 + write: enable Real-time counter interrupt; read: Real-time counter interrupt enabled + #1 + + + + + SETENA21 + RTC seconds interrupt set-enable bit + 21 + 1 + read-write + + + 0 + write: no effect; read: RTC seconds interrupt disabled + #0 + + + 1 + write: enable RTC seconds interrupt; read: RTC seconds interrupt enabled + #1 + + + + + SETENA22 + Periodic Interrupt Timer interrupt set-enable bit + 22 + 1 + read-write + + + 0 + write: no effect; read: Periodic Interrupt Timer interrupt disabled + #0 + + + 1 + write: enable Periodic Interrupt Timer interrupt; read: Periodic Interrupt Timer interrupt enabled + #1 + + + + + SETENA23 + LTC0 interrupt set-enable bit + 23 + 1 + read-write + + + 0 + write: no effect; read: LTC0 interrupt disabled + #0 + + + 1 + write: enable LTC0 interrupt; read: LTC0 interrupt enabled + #1 + + + + + SETENA24 + Radio 0 interrupt set-enable bit + 24 + 1 + read-write + + + 0 + write: no effect; read: Radio 0 interrupt disabled + #0 + + + 1 + write: enable Radio 0 interrupt; read: Radio 0 interrupt enabled + #1 + + + + + SETENA25 + FlexCAN0 ORed Message Buffer (MB0-31) interrupt interrupt set-enable bit + 25 + 1 + read-write + + + 0 + write: no effect; read: FlexCAN0 ORed Message Buffer (MB0-31) interrupt interrupt disabled + #0 + + + 1 + write: enable FlexCAN0 ORed Message Buffer (MB0-31) interrupt interrupt; read: FlexCAN0 ORed Message Buffer (MB0-31) interrupt interrupt enabled + #1 + + + + + SETENA26 + Radio 1 interrupt set-enable bit + 26 + 1 + read-write + + + 0 + write: no effect; read: Radio 1 interrupt disabled + #0 + + + 1 + write: enable Radio 1 interrupt; read: Radio 1 interrupt enabled + #1 + + + + + SETENA27 + Multipurpose Clock Generator interrupt set-enable bit + 27 + 1 + read-write + + + 0 + write: no effect; read: Multipurpose Clock Generator interrupt disabled + #0 + + + 1 + write: enable Multipurpose Clock Generator interrupt; read: Multipurpose Clock Generator interrupt enabled + #1 + + + + + SETENA28 + Low-Power Timer 0 interrupt set-enable bit + 28 + 1 + read-write + + + 0 + write: no effect; read: Low-Power Timer 0 interrupt disabled + #0 + + + 1 + write: enable Low-Power Timer 0 interrupt; read: Low-Power Timer 0 interrupt enabled + #1 + + + + + SETENA29 + Serial Peripheral Interface 1 interrupt set-enable bit + 29 + 1 + read-write + + + 0 + write: no effect; read: Serial Peripheral Interface 1 interrupt disabled + #0 + + + 1 + write: enable Serial Peripheral Interface 1 interrupt; read: Serial Peripheral Interface 1 interrupt enabled + #1 + + + + + SETENA30 + Pin detect Port A interrupt set-enable bit + 30 + 1 + read-write + + + 0 + write: no effect; read: Pin detect Port A interrupt disabled + #0 + + + 1 + write: enable Pin detect Port A interrupt; read: Pin detect Port A interrupt enabled + #1 + + + + + SETENA31 + Pin detect Port B and C interrupt set-enable bit + 31 + 1 + read-write + + + 0 + write: no effect; read: Pin detect Port B and C interrupt disabled + #0 + + + 1 + write: enable Pin detect Port B and C interrupt; read: Pin detect Port B and C interrupt enabled + #1 + + + + + + + NVIC_ICER + Interrupt Clear Enable Register + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + CLRENA0 + DMA channel 0 transfer complete/error interrupt clear-enable bit + 0 + 1 + read-write + + + 0 + write: no effect; read: DMA channel 0 transfer complete/error interrupt disabled + #0 + + + 1 + write: disable DMA channel 0 transfer complete/error interrupt; read: DMA channel 0 transfer complete/error interrupt enabled + #1 + + + + + CLRENA1 + DMA channel 1 transfer complete/error interrupt clear-enable bit + 1 + 1 + read-write + + + 0 + write: no effect; read: DMA channel 1 transfer complete/error interrupt disabled + #0 + + + 1 + write: disable DMA channel 1 transfer complete/error interrupt; read: DMA channel 1 transfer complete/error interrupt enabled + #1 + + + + + CLRENA2 + DMA channel 2 transfer complete/error interrupt clear-enable bit + 2 + 1 + read-write + + + 0 + write: no effect; read: DMA channel 2 transfer complete/error interrupt disabled + #0 + + + 1 + write: disable DMA channel 2 transfer complete/error interrupt; read: DMA channel 2 transfer complete/error interrupt enabled + #1 + + + + + CLRENA3 + DMA channel 3 transfer complete/error interrupt clear-enable bit + 3 + 1 + read-write + + + 0 + write: no effect; read: DMA channel 3 transfer complete/error interrupt disabled + #0 + + + 1 + write: disable DMA channel 3 transfer complete/error interrupt; read: DMA channel 3 transfer complete/error interrupt enabled + #1 + + + + + CLRENA4 + FIFO underrun, FIFO overflow, data ready, transfer complete and error interrupt clear-enable bit + 4 + 1 + read-write + + + 0 + write: no effect; read: FIFO underrun, FIFO overflow, data ready, transfer complete and error interrupt disabled + #0 + + + 1 + write: disable FIFO underrun, FIFO overflow, data ready, transfer complete and error interrupt; read: FIFO underrun, FIFO overflow, data ready, transfer complete and error interrupt enabled + #1 + + + + + CLRENA5 + Command complete and read collision, Flash ECC Errors interrupt clear-enable bit + 5 + 1 + read-write + + + 0 + write: no effect; read: Command complete and read collision, Flash ECC Errors interrupt disabled + #0 + + + 1 + write: disable Command complete and read collision, Flash ECC Errors interrupt; read: Command complete and read collision, Flash ECC Errors interrupt enabled + #1 + + + + + CLRENA6 + Low-voltage detect, low-voltage warning and DCDC PSWITCH interrupt interrupt clear-enable bit + 6 + 1 + read-write + + + 0 + write: no effect; read: Low-voltage detect, low-voltage warning and DCDC PSWITCH interrupt interrupt disabled + #0 + + + 1 + write: disable Low-voltage detect, low-voltage warning and DCDC PSWITCH interrupt interrupt; read: Low-voltage detect, low-voltage warning and DCDC PSWITCH interrupt interrupt enabled + #1 + + + + + CLRENA7 + Low Leakage Wakeup interrupt clear-enable bit + 7 + 1 + read-write + + + 0 + write: no effect; read: Low Leakage Wakeup interrupt disabled + #0 + + + 1 + write: disable Low Leakage Wakeup interrupt; read: Low Leakage Wakeup interrupt enabled + #1 + + + + + CLRENA8 + Inter-Integrated Circuit 0 interrupt clear-enable bit + 8 + 1 + read-write + + + 0 + write: no effect; read: Inter-Integrated Circuit 0 interrupt disabled + #0 + + + 1 + write: disable Inter-Integrated Circuit 0 interrupt; read: Inter-Integrated Circuit 0 interrupt enabled + #1 + + + + + CLRENA9 + Inter-Integrated Circuit 1 interrupt clear-enable bit + 9 + 1 + read-write + + + 0 + write: no effect; read: Inter-Integrated Circuit 1 interrupt disabled + #0 + + + 1 + write: disable Inter-Integrated Circuit 1 interrupt; read: Inter-Integrated Circuit 1 interrupt enabled + #1 + + + + + CLRENA10 + Serial Peripheral Interface 0 interrupt clear-enable bit + 10 + 1 + read-write + + + 0 + write: no effect; read: Serial Peripheral Interface 0 interrupt disabled + #0 + + + 1 + write: disable Serial Peripheral Interface 0 interrupt; read: Serial Peripheral Interface 0 interrupt enabled + #1 + + + + + CLRENA11 + FlexCAN0 ORed Error, Bus off, Transmit/Receive Warning, Wake up interrupt clear-enable bit + 11 + 1 + read-write + + + 0 + write: no effect; read: FlexCAN0 ORed Error, Bus off, Transmit/Receive Warning, Wake up interrupt disabled + #0 + + + 1 + write: disable FlexCAN0 ORed Error, Bus off, Transmit/Receive Warning, Wake up interrupt; read: FlexCAN0 ORed Error, Bus off, Transmit/Receive Warning, Wake up interrupt enabled + #1 + + + + + CLRENA12 + LPUART0 or LPUART1 status and error interrupt clear-enable bit + 12 + 1 + read-write + + + 0 + write: no effect; read: LPUART0 or LPUART1 status and error interrupt disabled + #0 + + + 1 + write: disable LPUART0 or LPUART1 status and error interrupt; read: LPUART0 or LPUART1 status and error interrupt enabled + #1 + + + + + CLRENA13 + True Random Number Generator interrupt clear-enable bit + 13 + 1 + read-write + + + 0 + write: no effect; read: True Random Number Generator interrupt disabled + #0 + + + 1 + write: disable True Random Number Generator interrupt; read: True Random Number Generator interrupt enabled + #1 + + + + + CLRENA14 + Carrier modulator transmitter interrupt clear-enable bit + 14 + 1 + read-write + + + 0 + write: no effect; read: Carrier modulator transmitter interrupt disabled + #0 + + + 1 + write: disable Carrier modulator transmitter interrupt; read: Carrier modulator transmitter interrupt enabled + #1 + + + + + CLRENA15 + Analog-to-Digital Converter 0 interrupt clear-enable bit + 15 + 1 + read-write + + + 0 + write: no effect; read: Analog-to-Digital Converter 0 interrupt disabled + #0 + + + 1 + write: disable Analog-to-Digital Converter 0 interrupt; read: Analog-to-Digital Converter 0 interrupt enabled + #1 + + + + + CLRENA16 + DMA channel 0 - 31 error interrupt clear-enable bit + 16 + 1 + read-write + + + 0 + write: no effect; read: DMA channel 0 - 31 error interrupt disabled + #0 + + + 1 + write: disable DMA channel 0 - 31 error interrupt; read: DMA channel 0 - 31 error interrupt enabled + #1 + + + + + CLRENA17 + Timer/PWM module 0 interrupt clear-enable bit + 17 + 1 + read-write + + + 0 + write: no effect; read: Timer/PWM module 0 interrupt disabled + #0 + + + 1 + write: disable Timer/PWM module 0 interrupt; read: Timer/PWM module 0 interrupt enabled + #1 + + + + + CLRENA18 + Timer/PWM module 1 interrupt clear-enable bit + 18 + 1 + read-write + + + 0 + write: no effect; read: Timer/PWM module 1 interrupt disabled + #0 + + + 1 + write: disable Timer/PWM module 1 interrupt; read: Timer/PWM module 1 interrupt enabled + #1 + + + + + CLRENA19 + Timer/PWM module 2 interrupt clear-enable bit + 19 + 1 + read-write + + + 0 + write: no effect; read: Timer/PWM module 2 interrupt disabled + #0 + + + 1 + write: disable Timer/PWM module 2 interrupt; read: Timer/PWM module 2 interrupt enabled + #1 + + + + + CLRENA20 + Real-time counter interrupt clear-enable bit + 20 + 1 + read-write + + + 0 + write: no effect; read: Real-time counter interrupt disabled + #0 + + + 1 + write: disable Real-time counter interrupt; read: Real-time counter interrupt enabled + #1 + + + + + CLRENA21 + RTC seconds interrupt clear-enable bit + 21 + 1 + read-write + + + 0 + write: no effect; read: RTC seconds interrupt disabled + #0 + + + 1 + write: disable RTC seconds interrupt; read: RTC seconds interrupt enabled + #1 + + + + + CLRENA22 + Periodic Interrupt Timer interrupt clear-enable bit + 22 + 1 + read-write + + + 0 + write: no effect; read: Periodic Interrupt Timer interrupt disabled + #0 + + + 1 + write: disable Periodic Interrupt Timer interrupt; read: Periodic Interrupt Timer interrupt enabled + #1 + + + + + CLRENA23 + LTC0 interrupt clear-enable bit + 23 + 1 + read-write + + + 0 + write: no effect; read: LTC0 interrupt disabled + #0 + + + 1 + write: disable LTC0 interrupt; read: LTC0 interrupt enabled + #1 + + + + + CLRENA24 + Radio 0 interrupt clear-enable bit + 24 + 1 + read-write + + + 0 + write: no effect; read: Radio 0 interrupt disabled + #0 + + + 1 + write: disable Radio 0 interrupt; read: Radio 0 interrupt enabled + #1 + + + + + CLRENA25 + FlexCAN0 ORed Message Buffer (MB0-31) interrupt interrupt clear-enable bit + 25 + 1 + read-write + + + 0 + write: no effect; read: FlexCAN0 ORed Message Buffer (MB0-31) interrupt interrupt disabled + #0 + + + 1 + write: disable FlexCAN0 ORed Message Buffer (MB0-31) interrupt interrupt; read: FlexCAN0 ORed Message Buffer (MB0-31) interrupt interrupt enabled + #1 + + + + + CLRENA26 + Radio 1 interrupt clear-enable bit + 26 + 1 + read-write + + + 0 + write: no effect; read: Radio 1 interrupt disabled + #0 + + + 1 + write: disable Radio 1 interrupt; read: Radio 1 interrupt enabled + #1 + + + + + CLRENA27 + Multipurpose Clock Generator interrupt clear-enable bit + 27 + 1 + read-write + + + 0 + write: no effect; read: Multipurpose Clock Generator interrupt disabled + #0 + + + 1 + write: disable Multipurpose Clock Generator interrupt; read: Multipurpose Clock Generator interrupt enabled + #1 + + + + + CLRENA28 + Low-Power Timer 0 interrupt clear-enable bit + 28 + 1 + read-write + + + 0 + write: no effect; read: Low-Power Timer 0 interrupt disabled + #0 + + + 1 + write: disable Low-Power Timer 0 interrupt; read: Low-Power Timer 0 interrupt enabled + #1 + + + + + CLRENA29 + Serial Peripheral Interface 1 interrupt clear-enable bit + 29 + 1 + read-write + + + 0 + write: no effect; read: Serial Peripheral Interface 1 interrupt disabled + #0 + + + 1 + write: disable Serial Peripheral Interface 1 interrupt; read: Serial Peripheral Interface 1 interrupt enabled + #1 + + + + + CLRENA30 + Pin detect Port A interrupt clear-enable bit + 30 + 1 + read-write + + + 0 + write: no effect; read: Pin detect Port A interrupt disabled + #0 + + + 1 + write: disable Pin detect Port A interrupt; read: Pin detect Port A interrupt enabled + #1 + + + + + CLRENA31 + Pin detect Port B and C interrupt clear-enable bit + 31 + 1 + read-write + + + 0 + write: no effect; read: Pin detect Port B and C interrupt disabled + #0 + + + 1 + write: disable Pin detect Port B and C interrupt; read: Pin detect Port B and C interrupt enabled + #1 + + + + + + + NVIC_ISPR + Interrupt Set Pending Register + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + SETPEND0 + DMA channel 0 transfer complete/error interrupt set-pending bit + 0 + 1 + read-write + + + 0 + write: no effect; read: DMA channel 0 transfer complete/error interrupt is not pending + #0 + + + 1 + write: changes the DMA channel 0 transfer complete/error interrupt state to pending; read: DMA channel 0 transfer complete/error interrupt is pending + #1 + + + + + SETPEND1 + DMA channel 1 transfer complete/error interrupt set-pending bit + 1 + 1 + read-write + + + 0 + write: no effect; read: DMA channel 1 transfer complete/error interrupt is not pending + #0 + + + 1 + write: changes the DMA channel 1 transfer complete/error interrupt state to pending; read: DMA channel 1 transfer complete/error interrupt is pending + #1 + + + + + SETPEND2 + DMA channel 2 transfer complete/error interrupt set-pending bit + 2 + 1 + read-write + + + 0 + write: no effect; read: DMA channel 2 transfer complete/error interrupt is not pending + #0 + + + 1 + write: changes the DMA channel 2 transfer complete/error interrupt state to pending; read: DMA channel 2 transfer complete/error interrupt is pending + #1 + + + + + SETPEND3 + DMA channel 3 transfer complete/error interrupt set-pending bit + 3 + 1 + read-write + + + 0 + write: no effect; read: DMA channel 3 transfer complete/error interrupt is not pending + #0 + + + 1 + write: changes the DMA channel 3 transfer complete/error interrupt state to pending; read: DMA channel 3 transfer complete/error interrupt is pending + #1 + + + + + SETPEND4 + FIFO underrun, FIFO overflow, data ready, transfer complete and error interrupt set-pending bit + 4 + 1 + read-write + + + 0 + write: no effect; read: FIFO underrun, FIFO overflow, data ready, transfer complete and error interrupt is not pending + #0 + + + 1 + write: changes the FIFO underrun, FIFO overflow, data ready, transfer complete and error interrupt state to pending; read: FIFO underrun, FIFO overflow, data ready, transfer complete and error interrupt is pending + #1 + + + + + SETPEND5 + Command complete and read collision, Flash ECC Errors interrupt set-pending bit + 5 + 1 + read-write + + + 0 + write: no effect; read: Command complete and read collision, Flash ECC Errors interrupt is not pending + #0 + + + 1 + write: changes the Command complete and read collision, Flash ECC Errors interrupt state to pending; read: Command complete and read collision, Flash ECC Errors interrupt is pending + #1 + + + + + SETPEND6 + Low-voltage detect, low-voltage warning and DCDC PSWITCH interrupt interrupt set-pending bit + 6 + 1 + read-write + + + 0 + write: no effect; read: Low-voltage detect, low-voltage warning and DCDC PSWITCH interrupt interrupt is not pending + #0 + + + 1 + write: changes the Low-voltage detect, low-voltage warning and DCDC PSWITCH interrupt interrupt state to pending; read: Low-voltage detect, low-voltage warning and DCDC PSWITCH interrupt interrupt is pending + #1 + + + + + SETPEND7 + Low Leakage Wakeup interrupt set-pending bit + 7 + 1 + read-write + + + 0 + write: no effect; read: Low Leakage Wakeup interrupt is not pending + #0 + + + 1 + write: changes the Low Leakage Wakeup interrupt state to pending; read: Low Leakage Wakeup interrupt is pending + #1 + + + + + SETPEND8 + Inter-Integrated Circuit 0 interrupt set-pending bit + 8 + 1 + read-write + + + 0 + write: no effect; read: Inter-Integrated Circuit 0 interrupt is not pending + #0 + + + 1 + write: changes the Inter-Integrated Circuit 0 interrupt state to pending; read: Inter-Integrated Circuit 0 interrupt is pending + #1 + + + + + SETPEND9 + Inter-Integrated Circuit 1 interrupt set-pending bit + 9 + 1 + read-write + + + 0 + write: no effect; read: Inter-Integrated Circuit 1 interrupt is not pending + #0 + + + 1 + write: changes the Inter-Integrated Circuit 1 interrupt state to pending; read: Inter-Integrated Circuit 1 interrupt is pending + #1 + + + + + SETPEND10 + Serial Peripheral Interface 0 interrupt set-pending bit + 10 + 1 + read-write + + + 0 + write: no effect; read: Serial Peripheral Interface 0 interrupt is not pending + #0 + + + 1 + write: changes the Serial Peripheral Interface 0 interrupt state to pending; read: Serial Peripheral Interface 0 interrupt is pending + #1 + + + + + SETPEND11 + FlexCAN0 ORed Error, Bus off, Transmit/Receive Warning, Wake up interrupt set-pending bit + 11 + 1 + read-write + + + 0 + write: no effect; read: FlexCAN0 ORed Error, Bus off, Transmit/Receive Warning, Wake up interrupt is not pending + #0 + + + 1 + write: changes the FlexCAN0 ORed Error, Bus off, Transmit/Receive Warning, Wake up interrupt state to pending; read: FlexCAN0 ORed Error, Bus off, Transmit/Receive Warning, Wake up interrupt is pending + #1 + + + + + SETPEND12 + LPUART0 or LPUART1 status and error interrupt set-pending bit + 12 + 1 + read-write + + + 0 + write: no effect; read: LPUART0 or LPUART1 status and error interrupt is not pending + #0 + + + 1 + write: changes the LPUART0 or LPUART1 status and error interrupt state to pending; read: LPUART0 or LPUART1 status and error interrupt is pending + #1 + + + + + SETPEND13 + True Random Number Generator interrupt set-pending bit + 13 + 1 + read-write + + + 0 + write: no effect; read: True Random Number Generator interrupt is not pending + #0 + + + 1 + write: changes the True Random Number Generator interrupt state to pending; read: True Random Number Generator interrupt is pending + #1 + + + + + SETPEND14 + Carrier modulator transmitter interrupt set-pending bit + 14 + 1 + read-write + + + 0 + write: no effect; read: Carrier modulator transmitter interrupt is not pending + #0 + + + 1 + write: changes the Carrier modulator transmitter interrupt state to pending; read: Carrier modulator transmitter interrupt is pending + #1 + + + + + SETPEND15 + Analog-to-Digital Converter 0 interrupt set-pending bit + 15 + 1 + read-write + + + 0 + write: no effect; read: Analog-to-Digital Converter 0 interrupt is not pending + #0 + + + 1 + write: changes the Analog-to-Digital Converter 0 interrupt state to pending; read: Analog-to-Digital Converter 0 interrupt is pending + #1 + + + + + SETPEND16 + DMA channel 0 - 31 error interrupt set-pending bit + 16 + 1 + read-write + + + 0 + write: no effect; read: DMA channel 0 - 31 error interrupt is not pending + #0 + + + 1 + write: changes the DMA channel 0 - 31 error interrupt state to pending; read: DMA channel 0 - 31 error interrupt is pending + #1 + + + + + SETPEND17 + Timer/PWM module 0 interrupt set-pending bit + 17 + 1 + read-write + + + 0 + write: no effect; read: Timer/PWM module 0 interrupt is not pending + #0 + + + 1 + write: changes the Timer/PWM module 0 interrupt state to pending; read: Timer/PWM module 0 interrupt is pending + #1 + + + + + SETPEND18 + Timer/PWM module 1 interrupt set-pending bit + 18 + 1 + read-write + + + 0 + write: no effect; read: Timer/PWM module 1 interrupt is not pending + #0 + + + 1 + write: changes the Timer/PWM module 1 interrupt state to pending; read: Timer/PWM module 1 interrupt is pending + #1 + + + + + SETPEND19 + Timer/PWM module 2 interrupt set-pending bit + 19 + 1 + read-write + + + 0 + write: no effect; read: Timer/PWM module 2 interrupt is not pending + #0 + + + 1 + write: changes the Timer/PWM module 2 interrupt state to pending; read: Timer/PWM module 2 interrupt is pending + #1 + + + + + SETPEND20 + Real-time counter interrupt set-pending bit + 20 + 1 + read-write + + + 0 + write: no effect; read: Real-time counter interrupt is not pending + #0 + + + 1 + write: changes the Real-time counter interrupt state to pending; read: Real-time counter interrupt is pending + #1 + + + + + SETPEND21 + RTC seconds interrupt set-pending bit + 21 + 1 + read-write + + + 0 + write: no effect; read: RTC seconds interrupt is not pending + #0 + + + 1 + write: changes the RTC seconds interrupt state to pending; read: RTC seconds interrupt is pending + #1 + + + + + SETPEND22 + Periodic Interrupt Timer interrupt set-pending bit + 22 + 1 + read-write + + + 0 + write: no effect; read: Periodic Interrupt Timer interrupt is not pending + #0 + + + 1 + write: changes the Periodic Interrupt Timer interrupt state to pending; read: Periodic Interrupt Timer interrupt is pending + #1 + + + + + SETPEND23 + LTC0 interrupt set-pending bit + 23 + 1 + read-write + + + 0 + write: no effect; read: LTC0 interrupt is not pending + #0 + + + 1 + write: changes the LTC0 interrupt state to pending; read: LTC0 interrupt is pending + #1 + + + + + SETPEND24 + Radio 0 interrupt set-pending bit + 24 + 1 + read-write + + + 0 + write: no effect; read: Radio 0 interrupt is not pending + #0 + + + 1 + write: changes the Radio 0 interrupt state to pending; read: Radio 0 interrupt is pending + #1 + + + + + SETPEND25 + FlexCAN0 ORed Message Buffer (MB0-31) interrupt interrupt set-pending bit + 25 + 1 + read-write + + + 0 + write: no effect; read: FlexCAN0 ORed Message Buffer (MB0-31) interrupt interrupt is not pending + #0 + + + 1 + write: changes the FlexCAN0 ORed Message Buffer (MB0-31) interrupt interrupt state to pending; read: FlexCAN0 ORed Message Buffer (MB0-31) interrupt interrupt is pending + #1 + + + + + SETPEND26 + Radio 1 interrupt set-pending bit + 26 + 1 + read-write + + + 0 + write: no effect; read: Radio 1 interrupt is not pending + #0 + + + 1 + write: changes the Radio 1 interrupt state to pending; read: Radio 1 interrupt is pending + #1 + + + + + SETPEND27 + Multipurpose Clock Generator interrupt set-pending bit + 27 + 1 + read-write + + + 0 + write: no effect; read: Multipurpose Clock Generator interrupt is not pending + #0 + + + 1 + write: changes the Multipurpose Clock Generator interrupt state to pending; read: Multipurpose Clock Generator interrupt is pending + #1 + + + + + SETPEND28 + Low-Power Timer 0 interrupt set-pending bit + 28 + 1 + read-write + + + 0 + write: no effect; read: Low-Power Timer 0 interrupt is not pending + #0 + + + 1 + write: changes the Low-Power Timer 0 interrupt state to pending; read: Low-Power Timer 0 interrupt is pending + #1 + + + + + SETPEND29 + Serial Peripheral Interface 1 interrupt set-pending bit + 29 + 1 + read-write + + + 0 + write: no effect; read: Serial Peripheral Interface 1 interrupt is not pending + #0 + + + 1 + write: changes the Serial Peripheral Interface 1 interrupt state to pending; read: Serial Peripheral Interface 1 interrupt is pending + #1 + + + + + SETPEND30 + Pin detect Port A interrupt set-pending bit + 30 + 1 + read-write + + + 0 + write: no effect; read: Pin detect Port A interrupt is not pending + #0 + + + 1 + write: changes the Pin detect Port A interrupt state to pending; read: Pin detect Port A interrupt is pending + #1 + + + + + SETPEND31 + Pin detect Port B and C interrupt set-pending bit + 31 + 1 + read-write + + + 0 + write: no effect; read: Pin detect Port B and C interrupt is not pending + #0 + + + 1 + write: changes the Pin detect Port B and C interrupt state to pending; read: Pin detect Port B and C interrupt is pending + #1 + + + + + + + NVIC_ICPR + Interrupt Clear Pending Register + 0x180 + 32 + read-write + 0 + 0xFFFFFFFF + + + CLRPEND0 + DMA channel 0 transfer complete/error interrupt clear-pending bit + 0 + 1 + read-write + + + 0 + write: no effect; read: DMA channel 0 transfer complete/error interrupt is not pending + #0 + + + 1 + write: removes pending state from the DMA channel 0 transfer complete/error interrupt; read: DMA channel 0 transfer complete/error interrupt is pending + #1 + + + + + CLRPEND1 + DMA channel 1 transfer complete/error interrupt clear-pending bit + 1 + 1 + read-write + + + 0 + write: no effect; read: DMA channel 1 transfer complete/error interrupt is not pending + #0 + + + 1 + write: removes pending state from the DMA channel 1 transfer complete/error interrupt; read: DMA channel 1 transfer complete/error interrupt is pending + #1 + + + + + CLRPEND2 + DMA channel 2 transfer complete/error interrupt clear-pending bit + 2 + 1 + read-write + + + 0 + write: no effect; read: DMA channel 2 transfer complete/error interrupt is not pending + #0 + + + 1 + write: removes pending state from the DMA channel 2 transfer complete/error interrupt; read: DMA channel 2 transfer complete/error interrupt is pending + #1 + + + + + CLRPEND3 + DMA channel 3 transfer complete/error interrupt clear-pending bit + 3 + 1 + read-write + + + 0 + write: no effect; read: DMA channel 3 transfer complete/error interrupt is not pending + #0 + + + 1 + write: removes pending state from the DMA channel 3 transfer complete/error interrupt; read: DMA channel 3 transfer complete/error interrupt is pending + #1 + + + + + CLRPEND4 + FIFO underrun, FIFO overflow, data ready, transfer complete and error interrupt clear-pending bit + 4 + 1 + read-write + + + 0 + write: no effect; read: FIFO underrun, FIFO overflow, data ready, transfer complete and error interrupt is not pending + #0 + + + 1 + write: removes pending state from the FIFO underrun, FIFO overflow, data ready, transfer complete and error interrupt; read: FIFO underrun, FIFO overflow, data ready, transfer complete and error interrupt is pending + #1 + + + + + CLRPEND5 + Command complete and read collision, Flash ECC Errors interrupt clear-pending bit + 5 + 1 + read-write + + + 0 + write: no effect; read: Command complete and read collision, Flash ECC Errors interrupt is not pending + #0 + + + 1 + write: removes pending state from the Command complete and read collision, Flash ECC Errors interrupt; read: Command complete and read collision, Flash ECC Errors interrupt is pending + #1 + + + + + CLRPEND6 + Low-voltage detect, low-voltage warning and DCDC PSWITCH interrupt interrupt clear-pending bit + 6 + 1 + read-write + + + 0 + write: no effect; read: Low-voltage detect, low-voltage warning and DCDC PSWITCH interrupt interrupt is not pending + #0 + + + 1 + write: removes pending state from the Low-voltage detect, low-voltage warning and DCDC PSWITCH interrupt interrupt; read: Low-voltage detect, low-voltage warning and DCDC PSWITCH interrupt interrupt is pending + #1 + + + + + CLRPEND7 + Low Leakage Wakeup interrupt clear-pending bit + 7 + 1 + read-write + + + 0 + write: no effect; read: Low Leakage Wakeup interrupt is not pending + #0 + + + 1 + write: removes pending state from the Low Leakage Wakeup interrupt; read: Low Leakage Wakeup interrupt is pending + #1 + + + + + CLRPEND8 + Inter-Integrated Circuit 0 interrupt clear-pending bit + 8 + 1 + read-write + + + 0 + write: no effect; read: Inter-Integrated Circuit 0 interrupt is not pending + #0 + + + 1 + write: removes pending state from the Inter-Integrated Circuit 0 interrupt; read: Inter-Integrated Circuit 0 interrupt is pending + #1 + + + + + CLRPEND9 + Inter-Integrated Circuit 1 interrupt clear-pending bit + 9 + 1 + read-write + + + 0 + write: no effect; read: Inter-Integrated Circuit 1 interrupt is not pending + #0 + + + 1 + write: removes pending state from the Inter-Integrated Circuit 1 interrupt; read: Inter-Integrated Circuit 1 interrupt is pending + #1 + + + + + CLRPEND10 + Serial Peripheral Interface 0 interrupt clear-pending bit + 10 + 1 + read-write + + + 0 + write: no effect; read: Serial Peripheral Interface 0 interrupt is not pending + #0 + + + 1 + write: removes pending state from the Serial Peripheral Interface 0 interrupt; read: Serial Peripheral Interface 0 interrupt is pending + #1 + + + + + CLRPEND11 + FlexCAN0 ORed Error, Bus off, Transmit/Receive Warning, Wake up interrupt clear-pending bit + 11 + 1 + read-write + + + 0 + write: no effect; read: FlexCAN0 ORed Error, Bus off, Transmit/Receive Warning, Wake up interrupt is not pending + #0 + + + 1 + write: removes pending state from the FlexCAN0 ORed Error, Bus off, Transmit/Receive Warning, Wake up interrupt; read: FlexCAN0 ORed Error, Bus off, Transmit/Receive Warning, Wake up interrupt is pending + #1 + + + + + CLRPEND12 + LPUART0 or LPUART1 status and error interrupt clear-pending bit + 12 + 1 + read-write + + + 0 + write: no effect; read: LPUART0 or LPUART1 status and error interrupt is not pending + #0 + + + 1 + write: removes pending state from the LPUART0 or LPUART1 status and error interrupt; read: LPUART0 or LPUART1 status and error interrupt is pending + #1 + + + + + CLRPEND13 + True Random Number Generator interrupt clear-pending bit + 13 + 1 + read-write + + + 0 + write: no effect; read: True Random Number Generator interrupt is not pending + #0 + + + 1 + write: removes pending state from the True Random Number Generator interrupt; read: True Random Number Generator interrupt is pending + #1 + + + + + CLRPEND14 + Carrier modulator transmitter interrupt clear-pending bit + 14 + 1 + read-write + + + 0 + write: no effect; read: Carrier modulator transmitter interrupt is not pending + #0 + + + 1 + write: removes pending state from the Carrier modulator transmitter interrupt; read: Carrier modulator transmitter interrupt is pending + #1 + + + + + CLRPEND15 + Analog-to-Digital Converter 0 interrupt clear-pending bit + 15 + 1 + read-write + + + 0 + write: no effect; read: Analog-to-Digital Converter 0 interrupt is not pending + #0 + + + 1 + write: removes pending state from the Analog-to-Digital Converter 0 interrupt; read: Analog-to-Digital Converter 0 interrupt is pending + #1 + + + + + CLRPEND16 + DMA channel 0 - 31 error interrupt clear-pending bit + 16 + 1 + read-write + + + 0 + write: no effect; read: DMA channel 0 - 31 error interrupt is not pending + #0 + + + 1 + write: removes pending state from the DMA channel 0 - 31 error interrupt; read: DMA channel 0 - 31 error interrupt is pending + #1 + + + + + CLRPEND17 + Timer/PWM module 0 interrupt clear-pending bit + 17 + 1 + read-write + + + 0 + write: no effect; read: Timer/PWM module 0 interrupt is not pending + #0 + + + 1 + write: removes pending state from the Timer/PWM module 0 interrupt; read: Timer/PWM module 0 interrupt is pending + #1 + + + + + CLRPEND18 + Timer/PWM module 1 interrupt clear-pending bit + 18 + 1 + read-write + + + 0 + write: no effect; read: Timer/PWM module 1 interrupt is not pending + #0 + + + 1 + write: removes pending state from the Timer/PWM module 1 interrupt; read: Timer/PWM module 1 interrupt is pending + #1 + + + + + CLRPEND19 + Timer/PWM module 2 interrupt clear-pending bit + 19 + 1 + read-write + + + 0 + write: no effect; read: Timer/PWM module 2 interrupt is not pending + #0 + + + 1 + write: removes pending state from the Timer/PWM module 2 interrupt; read: Timer/PWM module 2 interrupt is pending + #1 + + + + + CLRPEND20 + Real-time counter interrupt clear-pending bit + 20 + 1 + read-write + + + 0 + write: no effect; read: Real-time counter interrupt is not pending + #0 + + + 1 + write: removes pending state from the Real-time counter interrupt; read: Real-time counter interrupt is pending + #1 + + + + + CLRPEND21 + RTC seconds interrupt clear-pending bit + 21 + 1 + read-write + + + 0 + write: no effect; read: RTC seconds interrupt is not pending + #0 + + + 1 + write: removes pending state from the RTC seconds interrupt; read: RTC seconds interrupt is pending + #1 + + + + + CLRPEND22 + Periodic Interrupt Timer interrupt clear-pending bit + 22 + 1 + read-write + + + 0 + write: no effect; read: Periodic Interrupt Timer interrupt is not pending + #0 + + + 1 + write: removes pending state from the Periodic Interrupt Timer interrupt; read: Periodic Interrupt Timer interrupt is pending + #1 + + + + + CLRPEND23 + LTC0 interrupt clear-pending bit + 23 + 1 + read-write + + + 0 + write: no effect; read: LTC0 interrupt is not pending + #0 + + + 1 + write: removes pending state from the LTC0 interrupt; read: LTC0 interrupt is pending + #1 + + + + + CLRPEND24 + Radio 0 interrupt clear-pending bit + 24 + 1 + read-write + + + 0 + write: no effect; read: Radio 0 interrupt is not pending + #0 + + + 1 + write: removes pending state from the Radio 0 interrupt; read: Radio 0 interrupt is pending + #1 + + + + + CLRPEND25 + FlexCAN0 ORed Message Buffer (MB0-31) interrupt interrupt clear-pending bit + 25 + 1 + read-write + + + 0 + write: no effect; read: FlexCAN0 ORed Message Buffer (MB0-31) interrupt interrupt is not pending + #0 + + + 1 + write: removes pending state from the FlexCAN0 ORed Message Buffer (MB0-31) interrupt interrupt; read: FlexCAN0 ORed Message Buffer (MB0-31) interrupt interrupt is pending + #1 + + + + + CLRPEND26 + Radio 1 interrupt clear-pending bit + 26 + 1 + read-write + + + 0 + write: no effect; read: Radio 1 interrupt is not pending + #0 + + + 1 + write: removes pending state from the Radio 1 interrupt; read: Radio 1 interrupt is pending + #1 + + + + + CLRPEND27 + Multipurpose Clock Generator interrupt clear-pending bit + 27 + 1 + read-write + + + 0 + write: no effect; read: Multipurpose Clock Generator interrupt is not pending + #0 + + + 1 + write: removes pending state from the Multipurpose Clock Generator interrupt; read: Multipurpose Clock Generator interrupt is pending + #1 + + + + + CLRPEND28 + Low-Power Timer 0 interrupt clear-pending bit + 28 + 1 + read-write + + + 0 + write: no effect; read: Low-Power Timer 0 interrupt is not pending + #0 + + + 1 + write: removes pending state from the Low-Power Timer 0 interrupt; read: Low-Power Timer 0 interrupt is pending + #1 + + + + + CLRPEND29 + Serial Peripheral Interface 1 interrupt clear-pending bit + 29 + 1 + read-write + + + 0 + write: no effect; read: Serial Peripheral Interface 1 interrupt is not pending + #0 + + + 1 + write: removes pending state from the Serial Peripheral Interface 1 interrupt; read: Serial Peripheral Interface 1 interrupt is pending + #1 + + + + + CLRPEND30 + Pin detect Port A interrupt clear-pending bit + 30 + 1 + read-write + + + 0 + write: no effect; read: Pin detect Port A interrupt is not pending + #0 + + + 1 + write: removes pending state from the Pin detect Port A interrupt; read: Pin detect Port A interrupt is pending + #1 + + + + + CLRPEND31 + Pin detect Port B and C interrupt clear-pending bit + 31 + 1 + read-write + + + 0 + write: no effect; read: Pin detect Port B and C interrupt is not pending + #0 + + + 1 + write: removes pending state from the Pin detect Port B and C interrupt; read: Pin detect Port B and C interrupt is pending + #1 + + + + + + + NVIC_IPR0 + Interrupt Priority Register 0 + 0x300 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRI_0 + Priority of the DMA channel 0 transfer complete/error interrupt + 6 + 2 + read-write + + + PRI_1 + Priority of the DMA channel 1 transfer complete/error interrupt + 14 + 2 + read-write + + + PRI_2 + Priority of the DMA channel 2 transfer complete/error interrupt + 22 + 2 + read-write + + + PRI_3 + Priority of the DMA channel 3 transfer complete/error interrupt + 30 + 2 + read-write + + + + + NVIC_IPR1 + Interrupt Priority Register 1 + 0x304 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRI_4 + Priority of the FIFO underrun, FIFO overflow, data ready, transfer complete and error interrupt + 6 + 2 + read-write + + + PRI_5 + Priority of the Command complete and read collision, Flash ECC Errors interrupt + 14 + 2 + read-write + + + PRI_6 + Priority of the Low-voltage detect, low-voltage warning and DCDC PSWITCH interrupt interrupt + 22 + 2 + read-write + + + PRI_7 + Priority of the Low Leakage Wakeup interrupt + 30 + 2 + read-write + + + + + NVIC_IPR2 + Interrupt Priority Register 2 + 0x308 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRI_8 + Priority of the Inter-Integrated Circuit 0 interrupt + 6 + 2 + read-write + + + PRI_9 + Priority of the Inter-Integrated Circuit 1 interrupt + 14 + 2 + read-write + + + PRI_10 + Priority of the Serial Peripheral Interface 0 interrupt + 22 + 2 + read-write + + + PRI_11 + Priority of the FlexCAN0 ORed Error, Bus off, Transmit/Receive Warning, Wake up interrupt + 30 + 2 + read-write + + + + + NVIC_IPR3 + Interrupt Priority Register 3 + 0x30C + 32 + read-write + 0 + 0xFFFFFFFF + + + PRI_12 + Priority of the LPUART0 or LPUART1 status and error interrupt + 6 + 2 + read-write + + + PRI_13 + Priority of the True Random Number Generator interrupt + 14 + 2 + read-write + + + PRI_14 + Priority of the Carrier modulator transmitter interrupt + 22 + 2 + read-write + + + PRI_15 + Priority of the Analog-to-Digital Converter 0 interrupt + 30 + 2 + read-write + + + + + NVIC_IPR4 + Interrupt Priority Register 4 + 0x310 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRI_16 + Priority of the DMA channel 0 - 31 error interrupt + 6 + 2 + read-write + + + PRI_17 + Priority of the Timer/PWM module 0 interrupt + 14 + 2 + read-write + + + PRI_18 + Priority of the Timer/PWM module 1 interrupt + 22 + 2 + read-write + + + PRI_19 + Priority of the Timer/PWM module 2 interrupt + 30 + 2 + read-write + + + + + NVIC_IPR5 + Interrupt Priority Register 5 + 0x314 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRI_20 + Priority of the Real-time counter interrupt + 6 + 2 + read-write + + + PRI_21 + Priority of the RTC seconds interrupt + 14 + 2 + read-write + + + PRI_22 + Priority of the Periodic Interrupt Timer interrupt + 22 + 2 + read-write + + + PRI_23 + Priority of the LTC0 interrupt + 30 + 2 + read-write + + + + + NVIC_IPR6 + Interrupt Priority Register 6 + 0x318 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRI_24 + Priority of the Radio 0 interrupt + 6 + 2 + read-write + + + PRI_25 + Priority of the FlexCAN0 ORed Message Buffer (MB0-31) interrupt interrupt + 14 + 2 + read-write + + + PRI_26 + Priority of the Radio 1 interrupt + 22 + 2 + read-write + + + PRI_27 + Priority of the Multipurpose Clock Generator interrupt + 30 + 2 + read-write + + + + + NVIC_IPR7 + Interrupt Priority Register 7 + 0x31C + 32 + read-write + 0 + 0xFFFFFFFF + + + PRI_28 + Priority of the Low-Power Timer 0 interrupt + 6 + 2 + read-write + + + PRI_29 + Priority of the Serial Peripheral Interface 1 interrupt + 14 + 2 + read-write + + + PRI_30 + Priority of the Pin detect Port A interrupt + 22 + 2 + read-write + + + PRI_31 + Priority of the Pin detect Port B and C interrupt + 30 + 2 + read-write + + + + + + + MTB + Micro Trace Buffer + MTB_ + 0xF0000000 + + 0 + 0x1000 + registers + + + + POSITION + MTB Position Register + 0 + 32 + read-write + 0 + 0x3 + + + WRAP + WRAP + 2 + 1 + read-write + + + POINTER + Trace Packet Address Pointer[28:0] + 3 + 29 + read-write + + + + + MASTER + MTB Master Register + 0x4 + 32 + read-write + 0x80 + 0xFFFFFFE0 + + + MASK + Mask + 0 + 5 + read-write + + + TSTARTEN + Trace Start Input Enable + 5 + 1 + read-write + + + TSTOPEN + Trace Stop Input Enable + 6 + 1 + read-write + + + SFRWPRIV + Special Function Register Write Privilege + 7 + 1 + read-write + + + RAMPRIV + RAM Privilege + 8 + 1 + read-write + + + HALTREQ + Halt Request + 9 + 1 + read-write + + + EN + Main Trace Enable + 31 + 1 + read-write + + + + + FLOW + MTB Flow Register + 0x8 + 32 + read-write + 0 + 0x4 + + + AUTOSTOP + AUTOSTOP + 0 + 1 + read-write + + + AUTOHALT + AUTOHALT + 1 + 1 + read-write + + + WATERMARK + WATERMARK[28:0] + 3 + 29 + read-write + + + + + BASE + MTB Base Register + 0xC + 32 + read-only + 0 + 0 + + + BASEADDR + BASEADDR + 0 + 32 + read-only + + + + + MODECTRL + Integration Mode Control Register + 0xF00 + 32 + read-only + 0 + 0xFFFFFFFF + + + MODECTRL + MODECTRL + 0 + 32 + read-only + + + + + TAGSET + Claim TAG Set Register + 0xFA0 + 32 + read-only + 0 + 0xFFFFFFFF + + + TAGSET + TAGSET + 0 + 32 + read-only + + + + + TAGCLEAR + Claim TAG Clear Register + 0xFA4 + 32 + read-only + 0 + 0xFFFFFFFF + + + TAGCLEAR + TAGCLEAR + 0 + 32 + read-only + + + + + LOCKACCESS + Lock Access Register + 0xFB0 + 32 + read-only + 0 + 0xFFFFFFFF + + + LOCKACCESS + Hardwired to 0x0000_0000 + 0 + 32 + read-only + + + + + LOCKSTAT + Lock Status Register + 0xFB4 + 32 + read-only + 0 + 0xFFFFFFFF + + + LOCKSTAT + LOCKSTAT + 0 + 32 + read-only + + + + + AUTHSTAT + Authentication Status Register + 0xFB8 + 32 + read-only + 0 + 0xFFFFFFFF + + + BIT0 + Connected to DBGEN. + 0 + 1 + read-only + + + BIT2 + BIT2 + 2 + 1 + read-only + + + + + DEVICEARCH + Device Architecture Register + 0xFBC + 32 + read-only + 0x47700A31 + 0xFFFFFFFF + + + DEVICEARCH + DEVICEARCH + 0 + 32 + read-only + + + + + DEVICECFG + Device Configuration Register + 0xFC8 + 32 + read-only + 0 + 0xFFFFFFFF + + + DEVICECFG + DEVICECFG + 0 + 32 + read-only + + + + + DEVICETYPID + Device Type Identifier Register + 0xFCC + 32 + read-only + 0x31 + 0xFFFFFFFF + + + DEVICETYPID + DEVICETYPID + 0 + 32 + read-only + + + + + 8 + 0x4 + 4,5,6,7,0,1,2,3 + PERIPHID%s + Peripheral ID Register + 0xFD0 + 32 + read-only + 0 + 0 + + + PERIPHID + PERIPHID + 0 + 32 + read-only + + + + + 4 + 0x4 + 0,1,2,3 + COMPID%s + Component ID Register + 0xFF0 + 32 + read-only + 0 + 0 + + + COMPID + Component ID + 0 + 32 + read-only + + + + + + + MTBDWT + MTB data watchpoint and trace + MTBDWT_ + 0xF0001000 + + 0 + 0x1000 + registers + + + + CTRL + MTB DWT Control Register + 0 + 32 + read-only + 0x2F000000 + 0xFFFFFFFF + + + DWTCFGCTRL + DWT configuration controls + 0 + 28 + read-only + + + NUMCMP + Number of comparators + 28 + 4 + read-only + + + + + 2 + 0x10 + 0,1 + COMP%s + MTB_DWT Comparator Register + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + COMP + Reference value for comparison + 0 + 32 + read-write + + + + + 2 + 0x10 + 0,1 + MASK%s + MTB_DWT Comparator Mask Register + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + MASK + MASK + 0 + 5 + read-write + + + + + FCT0 + MTB_DWT Comparator Function Register 0 + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + FUNCTION + Function + 0 + 4 + read-write + + + 000 + Disabled. + #0000 + + + 100 + Instruction fetch. + #0100 + + + 101 + Data operand read. + #0101 + + + 110 + Data operand write. + #0110 + + + 111 + Data operand (read + write). + #0111 + + + + + DATAVMATCH + Data Value Match + 8 + 1 + read-write + + + 0 + Perform address comparison. + #0 + + + 1 + Perform data value comparison. + #1 + + + + + DATAVSIZE + Data Value Size + 10 + 2 + read-write + + + 00 + Byte. + #00 + + + 01 + Halfword. + #01 + + + 10 + Word. + #10 + + + 11 + Reserved. Any attempts to use this value results in UNPREDICTABLE behavior. + #11 + + + + + DATAVADDR0 + Data Value Address 0 + 12 + 4 + read-write + + + MATCHED + Comparator match + 24 + 1 + read-only + + + 0 + No match. + #0 + + + 1 + Match occurred. + #1 + + + + + + + FCT1 + MTB_DWT Comparator Function Register 1 + 0x38 + 32 + read-write + 0 + 0xFFFFFFFF + + + FUNCTION + Function + 0 + 4 + read-write + + + 000 + Disabled. + #0000 + + + 100 + Instruction fetch. + #0100 + + + 101 + Data operand read. + #0101 + + + 110 + Data operand write. + #0110 + + + 111 + Data operand (read + write). + #0111 + + + + + MATCHED + Comparator match + 24 + 1 + read-only + + + 0 + No match. + #0 + + + 1 + Match occurred. + #1 + + + + + + + TBCTRL + MTB_DWT Trace Buffer Control Register + 0x200 + 32 + read-write + 0x20000000 + 0xFFFFFFFF + + + ACOMP0 + Action based on Comparator 0 match + 0 + 1 + read-write + + + 0 + Trigger TSTOP based on the assertion of MTBDWT_FCT0[MATCHED]. + #0 + + + 1 + Trigger TSTART based on the assertion of MTBDWT_FCT0[MATCHED]. + #1 + + + + + ACOMP1 + Action based on Comparator 1 match + 1 + 1 + read-write + + + 0 + Trigger TSTOP based on the assertion of MTBDWT_FCT1[MATCHED]. + #0 + + + 1 + Trigger TSTART based on the assertion of MTBDWT_FCT1[MATCHED]. + #1 + + + + + NUMCOMP + Number of Comparators + 28 + 4 + read-only + + + + + DEVICECFG + Device Configuration Register + 0xFC8 + 32 + read-only + 0 + 0xFFFFFFFF + + + DEVICECFG + DEVICECFG + 0 + 32 + read-only + + + + + DEVICETYPID + Device Type Identifier Register + 0xFCC + 32 + read-only + 0x4 + 0xFFFFFFFF + + + DEVICETYPID + DEVICETYPID + 0 + 32 + read-only + + + + + 8 + 0x4 + 4,5,6,7,0,1,2,3 + PERIPHID%s + Peripheral ID Register + 0xFD0 + 32 + read-only + 0 + 0 + + + PERIPHID + PERIPHID + 0 + 32 + read-only + + + + + 4 + 0x4 + 0,1,2,3 + COMPID%s + Component ID Register + 0xFF0 + 32 + read-only + 0 + 0 + + + COMPID + Component ID + 0 + 32 + read-only + + + + + + + ROM + System ROM + ROM_ + 0xF0002000 + + 0 + 0x1000 + registers + + + + 3 + 0x4 + 0,1,2 + ENTRY%s + Entry + 0 + 32 + read-only + 0 + 0 + + + ENTRY + ENTRY + 0 + 32 + read-only + + + + + TABLEMARK + End of Table Marker Register + 0xC + 32 + read-only + 0 + 0xFFFFFFFF + + + MARK + MARK + 0 + 32 + read-only + + + + + SYSACCESS + System Access Register + 0xFCC + 32 + read-only + 0x1 + 0xFFFFFFFF + + + SYSACCESS + SYSACCESS + 0 + 32 + read-only + + + + + 8 + 0x4 + 4,5,6,7,0,1,2,3 + PERIPHID%s + Peripheral ID Register + 0xFD0 + 32 + read-only + 0 + 0 + + + PERIPHID + PERIPHID + 0 + 32 + read-only + + + + + 4 + 0x4 + 0,1,2,3 + COMPID%s + Component ID Register + 0xFF0 + 32 + read-only + 0 + 0 + + + COMPID + Component ID + 0 + 32 + read-only + + + + + + + MCM + Core Platform Miscellaneous Control Module + MCM_ + 0xF0003000 + + 0x8 + 0x3C + registers + + + + PLASC + Crossbar Switch (AXBS) Slave Configuration + 0x8 + 16 + read-only + 0xF + 0xFFFF + + + ASC + Each bit in the ASC field indicates whether there is a corresponding connection to the crossbar switch's slave input port. + 0 + 8 + read-only + + + 0 + A bus slave connection to AXBS input port n is absent. + #0 + + + 1 + A bus slave connection to AXBS input port n is present. + #1 + + + + + + + PLAMC + Crossbar Switch (AXBS) Master Configuration + 0xA + 16 + read-only + 0xD + 0xFFFF + + + AMC + Each bit in the AMC field indicates whether there is a corresponding connection to the AXBS master input port. + 0 + 8 + read-only + + + 0 + A bus master connection to AXBS input port n is absent + #0 + + + 1 + A bus master connection to AXBS input port n is present + #1 + + + + + + + PLACR + Platform Control Register + 0xC + 32 + read-write + 0x50 + 0xFFFFFFFF + + + ARB + Arbitration select + 9 + 1 + read-write + + + 0 + Fixed-priority arbitration for the crossbar masters + #0 + + + 1 + Round-robin arbitration for the crossbar masters + #1 + + + + + CFCC + Clear Flash Controller Cache + 10 + 1 + read-write + + + DFCDA + Disable Flash Controller Data Caching + 11 + 1 + read-write + + + 0 + Enable flash controller data caching + #0 + + + 1 + Disable flash controller data caching. + #1 + + + + + DFCIC + Disable Flash Controller Instruction Caching + 12 + 1 + read-write + + + 0 + Enable flash controller instruction caching. + #0 + + + 1 + Disable flash controller instruction caching. + #1 + + + + + DFCC + Disable Flash Controller Cache + 13 + 1 + read-write + + + 0 + Enable flash controller cache. + #0 + + + 1 + Disable flash controller cache. + #1 + + + + + EFDS + Enable Flash Data Speculation + 14 + 1 + read-write + + + 0 + Disable flash data speculation. + #0 + + + 1 + Enable flash data speculation. + #1 + + + + + DFCS + Disable Flash Controller Speculation + 15 + 1 + read-write + + + 0 + Enable flash controller speculation. + #0 + + + 1 + Disable flash controller speculation. + #1 + + + + + ESFC + Enable Stalling Flash Controller + 16 + 1 + read-write + + + 0 + Disable stalling flash controller when flash is busy. + #0 + + + 1 + Enable stalling flash controller when flash is busy. + #1 + + + + + + + CPO + Compute Operation Control Register + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + CPOREQ + Compute Operation Request + 0 + 1 + read-write + + + 0 + Request is cleared. + #0 + + + 1 + Request Compute Operation. + #1 + + + + + CPOACK + Compute Operation Acknowledge + 1 + 1 + read-only + + + 0 + Compute operation entry has not completed or compute operation exit has completed. + #0 + + + 1 + Compute operation entry has completed or compute operation exit has not completed. + #1 + + + + + CPOWOI + Compute Operation Wake-up on Interrupt + 2 + 1 + read-write + + + 0 + No effect. + #0 + + + 1 + When set, the CPOREQ is cleared on any interrupt or exception vector fetch. + #1 + + + + + + + + + FGPIOA + General Purpose Input/Output + FGPIO + FGPIOA_ + 0xF8000000 + + 0 + 0x18 + registers + + + + PDOR + Port Data Output Register + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + PDO + Port Data Output + 0 + 32 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + + + PSOR + Port Set Output Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + PTSO + Port Set Output + 0 + 32 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + + + PCOR + Port Clear Output Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + PTCO + Port Clear Output + 0 + 32 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + + + PTOR + Port Toggle Output Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + PTTO + Port Toggle Output + 0 + 32 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + + + PDIR + Port Data Input Register + 0x10 + 32 + read-only + 0 + 0xFFFFFFFF + + + PDI + Port Data Input + 0 + 32 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + + + PDDR + Port Data Direction Register + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + PDD + Port Data Direction + 0 + 32 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + + + + + FGPIOB + General Purpose Input/Output + FGPIO + FGPIOB_ + 0xF8000040 + + 0 + 0x18 + registers + + + + PDOR + Port Data Output Register + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + PDO + Port Data Output + 0 + 32 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + + + PSOR + Port Set Output Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + PTSO + Port Set Output + 0 + 32 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + + + PCOR + Port Clear Output Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + PTCO + Port Clear Output + 0 + 32 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + + + PTOR + Port Toggle Output Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + PTTO + Port Toggle Output + 0 + 32 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + + + PDIR + Port Data Input Register + 0x10 + 32 + read-only + 0 + 0xFFFFFFFF + + + PDI + Port Data Input + 0 + 32 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + + + PDDR + Port Data Direction Register + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + PDD + Port Data Direction + 0 + 32 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + + + + + FGPIOC + General Purpose Input/Output + FGPIO + FGPIOC_ + 0xF8000080 + + 0 + 0x18 + registers + + + + PDOR + Port Data Output Register + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + PDO + Port Data Output + 0 + 32 + read-write + + + 0 + Logic level 0 is driven on pin, provided pin is configured for general-purpose output. + #0 + + + 1 + Logic level 1 is driven on pin, provided pin is configured for general-purpose output. + #1 + + + + + + + PSOR + Port Set Output Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + PTSO + Port Set Output + 0 + 32 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to logic 1. + #1 + + + + + + + PCOR + Port Clear Output Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + PTCO + Port Clear Output + 0 + 32 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is cleared to logic 0. + #1 + + + + + + + PTOR + Port Toggle Output Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + PTTO + Port Toggle Output + 0 + 32 + read-write + + + 0 + Corresponding bit in PDORn does not change. + #0 + + + 1 + Corresponding bit in PDORn is set to the inverse of its existing logic state. + #1 + + + + + + + PDIR + Port Data Input Register + 0x10 + 32 + read-only + 0 + 0xFFFFFFFF + + + PDI + Port Data Input + 0 + 32 + read-only + + + 0 + Pin logic level is logic 0, or is not configured for use by digital function. + #0 + + + 1 + Pin logic level is logic 1. + #1 + + + + + + + PDDR + Port Data Direction Register + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + PDD + Port Data Direction + 0 + 32 + read-write + + + 0 + Pin is configured as general-purpose input, for the GPIO function. + #0 + + + 1 + Pin is configured as general-purpose output, for the GPIO function. + #1 + + + + + + + + + diff --git a/pyocd/target/builtin/__init__.py b/pyocd/target/builtin/__init__.py index 4f22a8483..803766968 100644 --- a/pyocd/target/builtin/__init__.py +++ b/pyocd/target/builtin/__init__.py @@ -41,6 +41,7 @@ from . import target_MKW01Z128xxx4 from . import target_MKW24D512xxx5 from . import target_MKW36Z512xxx4 +from . import target_MKW38A512xxx4 from . import target_MKW40Z160xxx4 from . import target_MKW41Z512xxx4 from . import target_MK22FN1M0Axxx12 @@ -174,6 +175,7 @@ 'kw01z4': target_MKW01Z128xxx4.KW01Z4, 'kw24d5': target_MKW24D512xxx5.KW24D5, 'kw36z4': target_MKW36Z512xxx4.KW36Z4, + 'kw38a4': target_MKW38A512xxx4.KW38A4, 'kw40z4': target_MKW40Z160xxx4.KW40Z4, 'kw41z4': target_MKW41Z512xxx4.KW41Z4, 'k20d50m': target_MK20DX128xxx5.K20D50M, diff --git a/pyocd/target/builtin/target_MKW38A512xxx4.py b/pyocd/target/builtin/target_MKW38A512xxx4.py new file mode 100644 index 000000000..5b108fe10 --- /dev/null +++ b/pyocd/target/builtin/target_MKW38A512xxx4.py @@ -0,0 +1,220 @@ +# pyOCD debugger +# Copyright (c) 2017-2018 Arm Limited +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +from ..family.target_kinetis import Kinetis +from ..family.flash_kinetis import Flash_Kinetis +from ...core.memory_map import (FlashRegion, RamRegion, MemoryMap) +from ...debug.svd.loader import SVDFile + +FLASH_ALGO = { + 'load_address' : 0x20000000, + + # Flash algorithm as a hex string + 'instructions': [ + 0xe7fdbe00, + 0x4605b570, 0x4616460c, 0xcc0fe002, 0x3e10c50f, 0xd2fa2e10, 0xd3022e08, 0xc503cc03, 0x2e043e08, + 0xcc01d307, 0x1f36c501, 0x7821e003, 0x1c647029, 0x1e761c6d, 0xbd70d2f9, 0x4827b510, 0x220568c1, + 0x43110352, 0xbf0060c1, 0x49242000, 0x48246008, 0x444821ff, 0x70417001, 0x70c17081, 0x710222fe, + 0x71817141, 0x481f71c1, 0xf0004448, 0x2800f949, 0x2001d000, 0x2000bd10, 0x481a4770, 0x491ab510, + 0xf0004448, 0x2800f983, 0x4a15d10a, 0x21814815, 0x444a2308, 0x444800c9, 0xfa07f000, 0xd0002800, + 0xbd102001, 0x480f4601, 0x2201b510, 0x02d24b0e, 0xf0004448, 0x2800f9a7, 0x2001d000, 0x1dc9bd10, + 0x460108cb, 0xb5104807, 0x444800db, 0xf9edf000, 0xd0002800, 0xbd102001, 0xf0003000, 0x40048100, + 0x00000004, 0x0000000c, 0x6b65666b, 0x217048f9, 0x21807001, 0x78017001, 0xd5fc0609, 0x06817800, + 0x2067d501, 0x06c14770, 0x2068d501, 0x07c04770, 0x2069d0fc, 0xb5f84770, 0x0005460e, 0xd0134614, + 0x46102120, 0xfe3ef000, 0x27086aa8, 0xd80d42b0, 0x18416ae9, 0xd30942b1, 0x05391a30, 0x60201840, + 0x60601308, 0xe00a6ae8, 0xbdf82004, 0x1a306828, 0x68e86020, 0x7a296060, 0xf0006868, 0x60e7fe36, + 0x61676127, 0x60a061a7, 0x61e02004, 0xbdf82000, 0xb089b5ff, 0x9f129809, 0x4614461d, 0x2800460e, + 0x2c00d00d, 0x466ad00b, 0xffc5f7ff, 0x46399806, 0x42061e40, 0x4205d101, 0x2065d004, 0x2004e01a, + 0xbdf0b00d, 0x20001972, 0x29011e52, 0x2f00d002, 0xe003d006, 0xd1012e08, 0xd00b2d08, 0xe0092004, + 0x02892101, 0xd305428a, 0x429e034b, 0x49c2d3f6, 0xd8f3428a, 0x4ac10639, 0x18894fbe, 0x28009108, + 0xe01fd1de, 0x21030230, 0x06090a00, 0x60781840, 0x28049806, 0x2808d002, 0xe004d003, 0x60f89808, + 0x9808e001, 0x980960b8, 0xff70f7ff, 0xd1c72800, 0xc40268b9, 0x29089906, 0x68f9d101, 0x9906c402, + 0x1a6d198e, 0xd1dd2d00, 0xb5fee7ba, 0xd00b0004, 0x250049a9, 0xaa012308, 0x95001fc9, 0xff98f7ff, + 0xd0032800, 0xbdfe206e, 0xbdfe2004, 0x7a404668, 0x0f090701, 0x72414668, 0x000b48a1, 0xfe62f000, + 0x0e0b0910, 0x1a171411, 0x09211f1d, 0x09090909, 0x63200923, 0x2001e018, 0xe7fa0340, 0x03002001, + 0x2001e7f7, 0xe7f402c0, 0x02802001, 0x2001e7f1, 0xe7ee0240, 0x300120ff, 0x2080e7eb, 0x2040e7e9, + 0x2020e7e7, 0x6325e7e5, 0x7a004668, 0x07012201, 0x46680f09, 0x04927201, 0x43c02000, 0x000b1056, + 0xfe30f000, 0x0b0b0910, 0x1513100d, 0x0b0b150b, 0x09131b18, 0x62e20b09, 0x62e0e00a, 0x2007e008, + 0xe7fa03c0, 0x04002003, 0x62e6e7f7, 0x62e5e000, 0xbdfe2000, 0x03c02001, 0x2001e7ef, 0xe7ec0400, + 0x2800b430, 0x4977d024, 0x010968c9, 0x290f0f09, 0x4a75d021, 0x447a0049, 0x02895a51, 0x60032300, + 0x21016041, 0x02c97201, 0x496a60c1, 0x7a0c3120, 0x40a2158a, 0x7ac96142, 0x61816103, 0x06892105, + 0x21016201, 0x62410349, 0x628103c9, 0xe76cbc30, 0x2004bc30, 0x21014770, 0xe7df0489, 0xd0022800, + 0x20006101, 0x20044770, 0x48604770, 0x22016801, 0x43110292, 0xf3bf6001, 0xf3bf8f6f, 0x47708f4f, + 0x4603b500, 0xf7ff4618, 0xbd00fff0, 0x0005b570, 0x4a50d011, 0x60504856, 0xf0004608, 0x2800fcd7, + 0x4628d10a, 0xfea2f7ff, 0x46284604, 0xffe8f7ff, 0xd0022c00, 0x2004e005, 0x4628bd70, 0xff35f7ff, + 0x46204604, 0xb510bd70, 0xd0062800, 0x42191e5b, 0x421ad101, 0x2065d003, 0x2004bd10, 0x6a83bd10, + 0x428b188a, 0x6ac4d803, 0x4293191b, 0x6803d206, 0xd805428b, 0x18186840, 0xd3014290, 0xbd102000, + 0xbd102066, 0xb089b5ff, 0x460c4616, 0x9809466a, 0xfe81f7ff, 0x46214632, 0x98099b04, 0xffd3f7ff, + 0xd12b0005, 0x9f019c00, 0x1e7619a6, 0x46304639, 0xfccbf000, 0xd01b2900, 0x43781c40, 0xe0171e46, + 0x20090221, 0x06000a09, 0x48221809, 0x980c6041, 0xfc7cf000, 0xd1112800, 0xf7ff9809, 0x4605fe47, + 0x69009809, 0xd0002800, 0x2d004780, 0x19e4d102, 0xd9e542b4, 0xf7ff9809, 0x4628ff83, 0xb570e690, + 0xd0100004, 0x481b4a13, 0x46086050, 0xfc5ef000, 0xd1072800, 0xf7ff4620, 0x4605fe29, 0xf7ff4620, + 0x4628ff6f, 0x2004bd70, 0xb5ffbd70, 0x461fb089, 0x460d0014, 0x466ad020, 0xf7ff9809, 0x463afe2c, + 0x9b034629, 0xf7ff9809, 0x0006ff7e, 0x9d00d115, 0x0000e03a, 0x40020000, 0x008003ff, 0x00ffffff, + 0x0000ffff, 0x40048040, 0x00000c2e, 0xf000300c, 0x44ffffff, 0x4bffffff, 0xe6512004, 0x48facc02, + 0x99036081, 0xd0022904, 0xd0072908, 0x0229e00e, 0x0a092203, 0x18890652, 0xe0076041, 0x60c1cc02, + 0x22070229, 0x06120a09, 0x60411889, 0xf7ff9809, 0x4606fddd, 0x69009809, 0xd0002800, 0x2e004780, + 0x9803d104, 0x1a3f1945, 0xd1d72f00, 0xf7ff9809, 0x4630ff17, 0xb570e624, 0xd0140004, 0xd0122a00, + 0x49e20608, 0x18400a00, 0x604849df, 0x60886810, 0x60c86850, 0xf7ff4620, 0x4605fdb9, 0xf7ff4620, + 0x4628feff, 0x2004bd70, 0xb510bd70, 0xd0050002, 0xd00529ff, 0xd0032900, 0xe0022004, 0xbd102004, + 0x28002000, 0x0408d1fb, 0x184049d1, 0x604849ce, 0xf7ff4610, 0xbd10fd9b, 0xb08bb5ff, 0x90092000, + 0x460c980d, 0xd01f2800, 0x980baa01, 0xfda3f7ff, 0x9b064621, 0x980b9a0e, 0xfef5f7ff, 0x28009000, + 0x9802d110, 0x48c0900a, 0x78409e01, 0xd45b0780, 0x90092001, 0x980b21ff, 0xffc7f7ff, 0x28009000, + 0x2071d052, 0xbdf0b00f, 0xe7fb2004, 0x4270990a, 0x40084249, 0x24004240, 0xd10142b0, 0x1840990a, + 0x1989990e, 0xd9014281, 0xe0321b85, 0xe0309d0e, 0x02bf2701, 0xd80042bd, 0x08a1462f, 0x0089980d, + 0x20051809, 0x0680463a, 0xfcdaf7ff, 0x02001930, 0x0a00210b, 0x18410609, 0x604148a3, 0x99064638, + 0xfbb3f000, 0x040049a3, 0x489f1841, 0x980b6081, 0xfd3cf7ff, 0x980b9000, 0x28006900, 0x4780d000, + 0x28009800, 0x980bd003, 0xfe7af7ff, 0x1bede01e, 0x2d0019e4, 0x08a1d1cc, 0x0089980d, 0x900d1808, + 0x1936980e, 0x900e1b00, 0x2800980e, 0x980bd1ae, 0xfe66f7ff, 0x28009809, 0x2100d008, 0xf7ff980b, + 0x9000ff64, 0xd0012800, 0xe79b2072, 0xe7999800, 0x4607b5f8, 0x461d2000, 0x460c4616, 0x2f009000, + 0x6a38d009, 0xd80442a0, 0x18406b39, 0x42881961, 0x2066d203, 0x2004bdf8, 0x497bbdf8, 0x78492000, + 0xd12807c9, 0x90002001, 0xf7ff4638, 0x2800ff3e, 0x206fd021, 0x07a1bdf8, 0x2d04d105, 0xce02d303, + 0xc4021f2d, 0x07e1e00e, 0x2d02d107, 0x8831d305, 0x1ca48021, 0x1cb61ead, 0x7831e004, 0x1c647021, + 0x1c761e6d, 0x784a4968, 0xd0fc07d2, 0x06c97809, 0x2068d501, 0x2d00bdf8, 0x9900d1dd, 0xd0f92900, + 0x463821ff, 0xff11f7ff, 0xd0f32800, 0xbdf82070, 0x4614b570, 0xd0102800, 0xd00e2c00, 0x4a5e0609, + 0x4d590a09, 0x60691889, 0xfcb0f7ff, 0xd1032800, 0x602168a9, 0x606168e9, 0x2004bd70, 0x2800bd70, + 0x2900d00e, 0x4850d00c, 0x07827880, 0x2a020f92, 0x0980d008, 0xd0072802, 0x70082002, 0x47702000, + 0x47702004, 0xe7f82000, 0xe7f62001, 0x460cb570, 0xd0200006, 0xd01e2c00, 0x20004d43, 0x078978a9, + 0x29020f89, 0x4845d016, 0x46206068, 0xfadcf000, 0x0a00ba00, 0x020078e1, 0x60a84308, 0xf0001d20, + 0xba00fad3, 0x79e10a00, 0x43080200, 0x463060e8, 0xfc6cf7ff, 0x2004bd70, 0xb510bd70, 0xd0072800, + 0x04094a37, 0x4a301889, 0xf7ff6051, 0xbd10fc5f, 0xbd102004, 0xb089b5ff, 0x460d4614, 0x9809466a, + 0xfc69f7ff, 0x46294622, 0x98099b05, 0xfdbbf7ff, 0xd12f2800, 0x4629466a, 0xf7ff9809, 0x9d00fc5c, + 0x90089802, 0x42404269, 0x424f4001, 0xd10142af, 0x183f9808, 0xd01c2c00, 0x42a61b7e, 0x4626d900, + 0x99054630, 0xfaa1f000, 0x22010229, 0x06120a09, 0x4915188a, 0x9a0c604a, 0x02120400, 0x30ff4310, + 0x98096088, 0xfc22f7ff, 0xd1032800, 0x19ad1ba4, 0x2000e7de, 0xb5ffe474, 0x9f12b089, 0x4616001d, + 0xd021460c, 0x9809466a, 0xfc25f7ff, 0x46214632, 0x98099b07, 0xfd77f7ff, 0xd1162800, 0x06394a09, + 0x9c00188f, 0x0000e032, 0x40020000, 0x4300ffff, 0x8100ffff, 0x0000ffff, 0x4100ffff, 0x45ffffff, + 0x4000ffff, 0x00ffffff, 0xe4492004, 0x20010221, 0x06400a09, 0x48fb1809, 0x60876041, 0x60c16829, + 0xf7ff9809, 0x2800fbe3, 0x9913d009, 0xd0002900, 0x9914600c, 0xd0e82900, 0x600a2200, 0x9907e430, + 0x08891a76, 0x194d0089, 0x190c9907, 0xd1dd2e00, 0xb510e426, 0xd0072800, 0x04094aeb, 0x4ae91889, + 0xf7ff6051, 0xbd10fbc3, 0xbd102004, 0xb0adb5f0, 0x4616001d, 0x4607460c, 0x2308d013, 0xfd23f7ff, + 0xd10f2800, 0xd00f2f00, 0x90019000, 0x683a9002, 0x92006879, 0x92022220, 0x42910292, 0x0949d906, + 0x2004e006, 0xbdf0b02d, 0xe0022004, 0x02892101, 0x28009101, 0x19a1d1f6, 0x2100468c, 0x9a01e007, + 0x434a9b00, 0x008e189b, 0x5193aa03, 0x9a021c49, 0xd2f4428a, 0x49cb2200, 0xe01cae24, 0xd2042a08, + 0x40d37c0b, 0x0fdb07db, 0x4613e013, 0x2b083b08, 0x7c4fd201, 0x4613e00a, 0x2b083b10, 0x7c8fd201, + 0x4613e004, 0x2b083b18, 0x7ccfd208, 0x07fb40df, 0x54b30fdb, 0x9b021c52, 0xd8df4293, 0x460b2100, + 0xe012460a, 0xaf03008e, 0x42a759bf, 0xaf03d80c, 0x687619f6, 0xd90742a6, 0x5c76ae24, 0x2e001c5b, + 0x1c52d100, 0x19349e01, 0x45641c49, 0x2a00d3ea, 0x429ad003, 0x2101d103, 0x2100e002, 0x2102e000, + 0xe79f7029, 0xb085b5f0, 0x4617001e, 0x4605460c, 0x2308d022, 0xfca7f7ff, 0xd11e2800, 0xd01e2d00, + 0x90019000, 0x68289002, 0x69689000, 0x69a89001, 0x20009002, 0x28009003, 0x9801d10f, 0x424019e7, + 0x42794602, 0x40224008, 0x25001880, 0x99014240, 0xf98bf000, 0xe01b9004, 0xb0052004, 0x2004bdf0, + 0x9800e7e8, 0x1a209901, 0xf97ff000, 0xd2022820, 0x69c9498c, 0x9902e005, 0xd90b4281, 0x69894989, + 0x22013820, 0x438a4082, 0x1c6dd000, 0x19049801, 0xd3e642bc, 0xd0042d00, 0x42859804, 0x2002d203, + 0x2000e002, 0x2001e000, 0x98037030, 0xb510e7d5, 0xd0112800, 0xd00f2a00, 0x000b2401, 0xfa02f000, + 0x11110e16, 0x1a171513, 0x2e201e1c, 0x2e2e2e2e, 0x2725222e, 0x2e2c2a17, 0xbd102004, 0x601068c0, + 0x6840e006, 0x7a00e7fb, 0x6800e7f9, 0x6014e7f7, 0xbd102000, 0xe7f26940, 0xe7f06980, 0xe7ee6a00, + 0xe7ec6a40, 0x02c02001, 0x6ac0e7e9, 0x2001e7e7, 0xe7e40480, 0xe7e26a80, 0xe7e06b00, 0xbd10206a, + 0x4604b510, 0x2c002000, 0x000bd014, 0xf9caf000, 0x1c1c1c22, 0x1c1c1c1c, 0x1e1c1c1c, 0x1e1e1e1e, + 0x1c1c1c1e, 0x1e1c1c1c, 0x1e1e1e1e, 0x1e1e1e1e, 0x1e141e1e, 0xbd102004, 0xd0032a00, 0xd0012a01, + 0xbd102077, 0xbd1072a2, 0xbd102076, 0xbd10206a, 0x0004b570, 0x484dd017, 0x484a1809, 0x06116041, + 0x0a12061a, 0x43114d4a, 0x60811949, 0xf7ff4620, 0x4606fa7d, 0xf7ff4620, 0x2000fbc3, 0x632543c0, + 0x463062e0, 0x2004bd70, 0x2800bd70, 0x483dd008, 0x6102680a, 0x69006809, 0xd0034281, 0x47702069, + 0x47702004, 0x47702000, 0xd0062800, 0xd0042900, 0x69004834, 0x20006008, 0x20044770, 0x28004770, + 0x6ac0d00b, 0xd00a2800, 0xd0081c40, 0x75c1482d, 0x42887dc0, 0x2069d005, 0x20044770, 0x20734770, + 0x20004770, 0x28004770, 0x2900d00b, 0x6ac0d009, 0xd0082800, 0xd0061c40, 0x7dc04822, 0x20007008, + 0x20044770, 0x20734770, 0x28004770, 0x6b00d007, 0xd0022800, 0x42904a1e, 0x2073d103, 0x20044770, + 0x48184770, 0x7d807581, 0xd0014288, 0x47702069, 0x47702000, 0xd0092800, 0xd0072900, 0x28006b00, + 0x4a13d002, 0xd1034290, 0x47702073, 0x47702004, 0x7d80480c, 0x20007008, 0x23004770, 0x220156c3, + 0x03d2490c, 0xd0171c5b, 0x4393680b, 0x7842600b, 0x03802001, 0x680a2a00, 0x4382d017, 0x2000600a, + 0x00004770, 0x40020000, 0x4a00ffff, 0x80ffff00, 0x0000ffff, 0xf000300c, 0x28007840, 0x6808d003, + 0x60084310, 0x2078e7eb, 0x4302e7ea, 0x2100e7e6, 0x70417001, 0x68c94909, 0x040b4a09, 0x7002d501, + 0x0449e001, 0x7042d400, 0xe7d92000, 0x42884905, 0x206bd001, 0x2000e7d4, 0x0000e7d2, 0xf0003000, + 0xffffffff, 0x6b65666b, 0xc004e001, 0x29041f09, 0x078bd2fb, 0x8002d501, 0x07c91c80, 0x7002d000, + 0x29004770, 0x07c3d00b, 0x7002d002, 0x1e491c40, 0xd3042902, 0xd5020783, 0x1c808002, 0xe7e31e89, + 0xe7ee2200, 0xe7df2200, 0x78c27803, 0x78434619, 0x021b0612, 0x78834319, 0x041b78c0, 0x43114319, + 0x0a090209, 0x43080600, 0x22004770, 0x428b0903, 0x0a03d32c, 0xd311428b, 0x469c2300, 0x4603e04e, + 0xd43c430b, 0x08432200, 0xd331428b, 0x428b0903, 0x0a03d31c, 0xd301428b, 0xe03f4694, 0x428b09c3, + 0x01cbd301, 0x41521ac0, 0x428b0983, 0x018bd301, 0x41521ac0, 0x428b0943, 0x014bd301, 0x41521ac0, + 0x428b0903, 0x010bd301, 0x41521ac0, 0x428b08c3, 0x00cbd301, 0x41521ac0, 0x428b0883, 0x008bd301, + 0x41521ac0, 0x428b0843, 0x004bd301, 0x41521ac0, 0xd2001a41, 0x41524601, 0x47704610, 0x0fcae05d, + 0x4249d000, 0xd3001003, 0x40534240, 0x469c2200, 0x428b0903, 0x0a03d32d, 0xd312428b, 0x018922fc, + 0x0a03ba12, 0xd30c428b, 0x11920189, 0xd308428b, 0x11920189, 0xd304428b, 0xd03a0189, 0xe0001192, + 0x09c30989, 0xd301428b, 0x1ac001cb, 0x09834152, 0xd301428b, 0x1ac0018b, 0x09434152, 0xd301428b, + 0x1ac0014b, 0x09034152, 0xd301428b, 0x1ac0010b, 0x08c34152, 0xd301428b, 0x1ac000cb, 0x08834152, + 0xd301428b, 0x1ac0008b, 0xd2d94152, 0x428b0843, 0x004bd301, 0x41521ac0, 0xd2001a41, 0x46634601, + 0x105b4152, 0xd3014610, 0x2b004240, 0x4249d500, 0x46634770, 0xd300105b, 0xb5014240, 0x46c02000, + 0xbd0246c0, 0x4674b430, 0x78251e64, 0x42ab1c64, 0x461dd200, 0x005b5d63, 0xbc3018e3, 0x00004718, + 0x40020004, 0x40020010, 0x00100008, 0x00200018, 0x00400030, 0x00800060, 0x010000c0, 0x02000180, + 0x04000300, 0x00000600, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000 + ], + + # Relative function addresses + 'pc_init': 0x2000003d, + 'pc_unInit': 0x2000007b, + 'pc_program_page': 0x200000c3, + 'pc_erase_sector': 0x200000a9, + 'pc_eraseAll': 0x2000007f, + + 'static_base' : 0x20000000 + 0x00000004 + 0x00000f68, + 'begin_stack' : 0x200023b0, + 'end_stack' : 0x200013b0, + 'begin_data' : 0x20000000 + 0x1000, + 'page_size' : 0x200, + 'analyzer_supported' : False, + 'analyzer_address' : 0x00000000, + # Enable double buffering + 'page_buffers' : [ + 0x20000fb0, + 0x200011b0 + ], + 'min_program_length' : 0x200, + + # Relative region addresses and sizes + 'ro_start': 0x4, + 'ro_size': 0xf68, + 'rw_start': 0xf6c, + 'rw_size': 0xc, + 'zi_start': 0xf78, + 'zi_size': 0x34, + + # Flash information + 'flash_start': 0x10000000, + 'flash_size': 0x40000, + 'sector_sizes': ( + (0x0, 0x800), + ) +} + + +class KW38A4(Kinetis): + + MEMORY_MAP = MemoryMap( + FlashRegion( + name="flash", + start=0x00000000, + length=0x00080000, # 512 KB Flash + blocksize=0x1000, # 4 KB erase sector + is_boot_memory=True, + algo=FLASH_ALGO, + flash_class=Flash_Kinetis + ), + RamRegion( + name="sram", + start=0x20000000, + length=0x00008000 # 32 KB SRAM + ), + RamRegion( + name="flexram", + start=0x14000000, + length=0x00002000 + ), + ) + + def __init__(self, session): + super(KW38A4, self).__init__(session, self.MEMORY_MAP) + self._svd_location = SVDFile.from_builtin("MKW38A4.svd")