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Merge pull request #74 from pulp-platform/bluewww/soc-reg-tests
Improve SW helper functions and mixed fixes
2 parents 342ace2 + f4c5219 commit 7b4a200

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10 files changed

+530
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lines changed

‎carfield.mk‎

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@@ -99,6 +99,10 @@ hw/regs/carfield_regs.hjson: hw/regs/carfield_regs.csv | venv
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hw/regs/carfield_reg_pkg.sv hw/regs/carfield_reg_top.sv: hw/regs/carfield_regs.hjson | venv
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$(VENV)/python utils/reggen/regtool.py -r $< --outdir $(dir $@)
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.PHONY: sw/include/regs/soc_ctrl.h
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sw/include/regs/soc_ctrl.h: hw/regs/carfield_regs.hjson | venv
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$(VENV)/python utils/reggen/regtool.py -D $< > $@
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## @section Carfield SoC HW Generation
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.PHONY: regenerate_soc_regs
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## Regenerate the toplevel SoC Control Register file from the CSV description of all registers in

‎hw/carfield.sv‎

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@@ -63,8 +63,6 @@ module carfield
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output logic jtag_safety_island_tdo_o,
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// Secure Subsystem BOOT pins
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input logic [1:0] bootmode_ot_i,
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// unused by safety island -- tdo pad always out mode
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output logic jtag_safe_isln_tdo_oe_o,
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// Safety Island BOOT pins
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input logic [1:0] bootmode_safe_isln_i,
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// Host UART Interface
@@ -1548,7 +1546,7 @@ secure_subsystem_synth_wrap #(
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.jtag_trst_n_i ( jtag_ot_trst_ni ),
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.jtag_tdi_i ( jtag_ot_tdi_i ),
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.jtag_tdo_o ( jtag_ot_tdo_o ),
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.jtag_tdo_oe_o ( ),
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.jtag_tdo_oe_o ( jtag_ot_tdo_oe_o),
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// Asynch axi port
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.async_axi_out_aw_data_o ( axi_mst_ext_aw_data [SecurityIslandMstIdx] ),
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.async_axi_out_aw_wptr_o ( axi_mst_ext_aw_wptr [SecurityIslandMstIdx] ),

‎sw/include/car_memory_map.h‎

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Original file line numberDiff line numberDiff line change
@@ -5,12 +5,15 @@
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// Nicole Narr <[email protected]>
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// Christopher Reinwardt <[email protected]>
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// Paul Scheffler <[email protected]>
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// Robert Balas <[email protected]>
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// Alessandro Ottaviano <[email protected]>
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//
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// This header provides information defined by hardware parameters, such as
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// the address map. In the future, it should be generated automatically as
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// part of the SoC generation process.
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#pragma once
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#ifndef __CAR_MEMORY_MAP_H
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#define __CAR_MEMORY_MAP_H
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// Base addresses provided at link time
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extern void *__base_l2;
@@ -46,20 +49,26 @@ extern void *__base_l2;
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#define CAR_HYPERRAM_END_ADDR 0x80800000
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4851
// Peripheral devices
49-
#define CAR_ETHERNET_BASE_ADDR 0x20000000
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#define CAR_PERIPHS_BASE_ADDR 0x20001000
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#define CAR_PERIPHS_BASE_ADDR 0x20000000
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52-
#define CAR_CAN_OFFSET 0x0000
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#define CAR_SYSTEM_TIMER_OFFSET 0x3000
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#define CAR_ADVANCED_TIMER_OFFSET 0x4000
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#define CAR_WATCHDOG_TIMER_OFFSET 0x6000
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#define CAR_HYPERBUS_CFG_OFFSET 0x8000
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#define CAR_ETHERNET_OFFSET 0x0000
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#define CAR_CAN_OFFSET 0x1000
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#define CAR_SYSTEM_TIMER_OFFSET 0x4000
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#define CAR_ADVANCED_TIMER_OFFSET 0x5000
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#define CAR_WATCHDOG_TIMER_OFFSET 0x7000
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#define CAR_HYPERBUS_CFG_OFFSET 0x9000
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#define CAR_PAD_CFG_OFFSET 0xa000
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#define CAR_SOC_CTRL_OFFSET 0x10000
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#define CAR_ETHERNET_BASE_ADDR (CAR_PERIPHS_BASE_ADDR + CAR_ETHERNET_OFFSET)
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#define CAR_CAN_BASE_ADDR (CAR_PERIPHS_BASE_ADDR + CAR_CAN_OFFSET)
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#define CAR_SYSTEM_TIMER_BASE_ADDR (CAR_PERIPHS_BASE_ADDR + CAR_SYSTEM_TIMER_OFFSET)
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#define CAR_ADVANCED_TIMER_BASE_ADDR (CAR_PERIPHS_BASE_ADDR + CAR_ADVANCED_TIMER_OFFSET)
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#define CAR_WATCHDOG_TIMER_BASE_ADDR (CAR_PERIPHS_BASE_ADDR + CAR_WATCHDOG_TIMER_OFFSET)
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#define CAR_HYPERBUS_CFG_BASE_ADDR (CAR_PERIPHS_BASE_ADDR + CAR_HYPERBUS_CFG_OFFSET)
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#define CAR_PAD_CFG_BASE_ADDR (CAR_PERIPHS_BASE_ADDR + CAR_PAD_CFG_OFFSET)
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#define CAR_SOC_CTRL_BASE_ADDR (CAR_PERIPHS_BASE_ADDR + CAR_SOC_CTRL_OFFSET)
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#define CAR_MBOX_BASE_ADDR 0x40000000
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#endif /* __CAR_MEMORY_MAP_H */

‎sw/include/car_util.h‎

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This file was deleted.

‎sw/include/csr.h‎

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@@ -0,0 +1,76 @@
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// Copyright 2023 ETH Zurich and University of Bologna.
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// Licensed under the Apache License, Version 2.0, see LICENSE for details.
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// SPDX-License-Identifier: Apache-2.0
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//
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// Robert Balas <[email protected]>
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//
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/* Description: CSR access macros
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* Authors: Robert Balas ([email protected])
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*/
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#ifndef __CSR_H
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#define __CSR_H
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/* TODO: complete this */
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#define CSR_MSTATUS 0x300
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#define CSR_MISA 0x301
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#define CSR_MIE 0x304
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#define CSR_MTVEC 0x305
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#define CSR_MSCRATCH 0x340
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#define CSR_MEPC 0x341
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#define CSR_MCAUSE 0x342
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#define CSR_MTVAL 0x343
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#define CSR_MIP 0x344
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#define CSR_MNXTI 0x345
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#define CSR_PMPCFG0 0x3a0
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#define CSR_PMPADDR0 0x3b0
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#define CSR_MHARTID 0xf14
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#define CSR_MINTSTATUS 0x346
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#define CSR_MINTTHRESH 0x347
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#define CSR_MCLICBASE 0x350
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#define MIE 8
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#define __CSR_EXPAND(x) #x
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#define csr_read(csr) \
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({ \
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register unsigned long __val; \
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asm volatile("csrr %0, " __CSR_EXPAND(csr) \
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: "=r"(__val) \
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: \
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: "memory"); \
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__val; \
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})
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#define csr_write(csr, val) \
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({ \
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unsigned long __val = (unsigned long)(val); \
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asm volatile("csrw " __CSR_EXPAND(csr) ", %0" \
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: \
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: "rK"(__val) \
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: "memory"); \
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})
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/* I hope this properly does a memory barrier with the "memory" hint */
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#define csr_read_clear(csr, val) \
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({ \
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unsigned long __val = (unsigned long)(val); \
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asm volatile("csrrc %0, " __CSR_EXPAND(csr) ", %1" \
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: "=r"(__val) \
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: "rK"(__val) \
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: "memory"); \
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__val; \
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})
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#define csr_read_set(csr, val) \
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({ \
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unsigned long __val = (unsigned long)(val); \
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asm volatile("csrrs %0, " __CSR_EXPAND(csr) ", %1" \
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: "=r"(__val) \
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: "rK"(__val) \
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: "memory"); \
73+
__val; \
74+
})
75+
76+
#endif

‎sw/include/io.h‎

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// Copyright 2023 ETH Zurich and University of Bologna.
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// Licensed under the Apache License, Version 2.0, see LICENSE for details.
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// SPDX-License-Identifier: Apache-2.0
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//
5+
// Robert Balas <[email protected]>
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//
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8+
/* Description: Memory mapped register I/O access
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*/
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#ifndef __IO_H
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#define __IO_H
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#include <stdint.h>
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/* generic I/O write */
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static inline void writeb(uint8_t val, uintptr_t addr)
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{
20+
asm volatile("sb %0, 0(%1)"
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:
22+
: "r"(val), "r"((volatile uint8_t *)addr)
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: "memory");
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}
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26+
static inline void writeh(uint16_t val, uintptr_t addr)
27+
{
28+
asm volatile("sh %0, 0(%1)"
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:
30+
: "r"(val), "r"((volatile uint16_t *)addr)
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: "memory");
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}
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static inline void writew(uint32_t val, uintptr_t addr)
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{
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asm volatile("sw %0, 0(%1)"
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:
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: "r"(val), "r"((volatile uint32_t *)addr)
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: "memory");
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}
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static inline void writed(uint64_t val, uintptr_t addr)
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{
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asm volatile("sd %0, 0(%1)"
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:
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: "r"(val), "r"((volatile uint64_t *)addr)
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: "memory");
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}
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/* generic I/O read */
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static inline uint8_t readb(const uintptr_t addr)
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{
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uint8_t val;
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55+
asm volatile("lb %0, 0(%1)"
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: "=r"(val)
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: "r"((const volatile uint8_t *)addr)
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: "memory");
59+
return val;
60+
}
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62+
static inline uint16_t readh(const uintptr_t addr)
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{
64+
uint16_t val;
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asm volatile("lh %0, 0(%1)"
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: "=r"(val)
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: "r"((const volatile uint16_t *)addr)
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: "memory");
70+
return val;
71+
}
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static inline uint32_t readw(const uintptr_t addr)
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{
75+
uint32_t val;
76+
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asm volatile("lw %0, 0(%1)"
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: "=r"(val)
79+
: "r"((const volatile uint32_t *)addr)
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: "memory");
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return val;
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}
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static inline uint64_t readd(const uintptr_t addr)
85+
{
86+
uint64_t val;
87+
88+
asm volatile("ld %0, 0(%1)"
89+
: "=r"(val)
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: "r"((const volatile uint64_t *)addr)
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: "memory");
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return val;
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}
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#endif

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