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DiyouSalex96295
DiyouS
authored and
alex96295
committed
treewide: Add LLC partitioning feature to cheshire
1 parent 2011a9c commit 6afae3e

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9 files changed

+201
-23
lines changed

9 files changed

+201
-23
lines changed

‎Bender.lock‎

Lines changed: 13 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -24,8 +24,8 @@ packages:
2424
- common_verification
2525
- tech_cells_generic
2626
axi_llc:
27-
revision: 559bcbd09a5a884dbe31e2d72fd95d024e357f39
28-
version: 0.2.1
27+
revision: 7d7fc1349d4915a657de535a491bc26fbf0d2cfa
28+
version: null
2929
source:
3030
Git: https://github.com/pulp-platform/axi_llc.git
3131
dependencies:
@@ -171,6 +171,17 @@ packages:
171171
- axi
172172
- common_cells
173173
- register_interface
174+
tagger:
175+
revision: 2149244de2a9914cff33722d0d527ca3c1b3c877
176+
version: null
177+
source:
178+
Git: [email protected]:dishen/tagger.git
179+
dependencies:
180+
- axi
181+
- common_cells
182+
- common_verification
183+
- register_interface
184+
- tech_cells_generic
174185
tech_cells_generic:
175186
revision: 7968dd6e6180df2c644636bc6d2908a49f2190cf
176187
version: 0.2.13

‎Bender.yml‎

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -13,8 +13,8 @@ package:
1313

1414
dependencies:
1515
apb_uart: { git: "https://github.com/pulp-platform/apb_uart.git", version: 0.2.1 }
16-
axi: { git: "https://github.com/pulp-platform/axi.git", version: 0.39.0 }
17-
axi_llc: { git: "https://github.com/pulp-platform/axi_llc.git", version: 0.2.1 }
16+
axi: { git: "https://github.com/pulp-platform/axi", rev: 4fb5a02 }
17+
axi_llc: { git: "https://github.com/pulp-platform/axi_llc", rev: 7d7fc13 }
1818
axi_riscv_atomics: { git: "https://github.com/pulp-platform/axi_riscv_atomics.git", version: 0.8.1 }
1919
axi_rt: { git: "https://github.com/pulp-platform/axi_rt.git", version: 0.0.0-alpha.3 }
2020
axi_vga: { git: "https://github.com/pulp-platform/axi_vga.git", version: 0.1.1 }
@@ -29,6 +29,7 @@ dependencies:
2929
register_interface: { git: "https://github.com/pulp-platform/register_interface.git", version: 0.4.2 }
3030
riscv-dbg: { git: "https://github.com/pulp-platform/riscv-dbg.git", version: 0.8.0 }
3131
serial_link: { git: "https://github.com/pulp-platform/serial_link.git", version: 1.1.0 }
32+
tagger: { git: "[email protected]:dishen/tagger.git", rev: 2149244 }
3233
unbent: { git: "https://github.com/pulp-platform/unbent.git", version: 0.1.5 }
3334

3435
export_include_dirs:

‎cheshire.mk‎

Lines changed: 17 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -11,11 +11,16 @@ BENDER ?= bender
1111
VLOG_ARGS ?= -suppress 2583 -suppress 13314
1212
VSIM ?= vsim
1313

14+
MAXPARTITION ?= 16
15+
CACHE_PARTITION ?= 1
16+
17+
1418
# Define used paths (prefixed to avoid name conflicts)
1519
CHS_ROOT ?= $(shell $(BENDER) path cheshire)
1620
CHS_REG_DIR := $(shell $(BENDER) path register_interface)
1721
CHS_SLINK_DIR := $(shell $(BENDER) path serial_link)
1822
CHS_LLC_DIR := $(shell $(BENDER) path axi_llc)
23+
CHS_TAGGER_DIR := $(shell $(BENDER) path tagger)
1924

2025
# Define paths used in dependencies
2126
OTPROOT := $(shell $(BENDER) path opentitan_peripherals)
@@ -103,12 +108,24 @@ $(CHS_SLINK_DIR)/.generated: $(CHS_ROOT)/hw/serial_link.hjson
103108
cp $< $(dir $@)/src/regs/serial_link_single_channel.hjson
104109
flock -x $@ $(MAKE) -C $(CHS_SLINK_DIR) update-regs BENDER="$(BENDER)" && touch $@
105110

111+
# LLC partitioning configuration
112+
$(CHS_LLC_DIR)/.generated:
113+
$(MAKE) -C $(CHS_LLC_DIR) REGWIDTH=64 CACHENUMLINES=256 MAXPARTITION=$(MAXPARTITION) CACHE_PARTITION=$(CACHE_PARTITION) regs
114+
@touch $@
115+
116+
# Tagger configuration
117+
$(CHS_TAGGER_DIR)/.generated:
118+
$(MAKE) -C $(CHS_TAGGER_DIR) REGWIDTH=32 MAXPARTITION=$(MAXPARTITION) PATID_LEN=5 regs
119+
@touch $@
120+
106121
CHS_HW_ALL += $(CHS_ROOT)/hw/regs/cheshire_reg_pkg.sv $(CHS_ROOT)/hw/regs/cheshire_reg_top.sv
107122
CHS_HW_ALL += $(CLINTROOT)/.generated
108123
CHS_HW_ALL += $(OTPROOT)/.generated
109124
CHS_HW_ALL += $(AXIRTROOT)/.generated
110125
CHS_HW_ALL += $(AXI_VGA_ROOT)/.generated
111126
CHS_HW_ALL += $(CHS_SLINK_DIR)/.generated
127+
CHS_HW_ALL += $(CHS_LLC_DIR)/.generated
128+
CHS_HW_ALL += $(CHS_TAGGER_DIR)/.generated
112129

113130
#####################
114131
# Generate Boot ROM #

‎hw/bootrom/cheshire_bootrom.S‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -62,6 +62,7 @@ _start:
6262
andi t0, t0, 2 // regs.HW_FEATURES.llc
6363
beqz t0, _prom_check_run
6464
la t0, __base_llc
65+
// Only configure half of LLC as SPM
6566
_wait_llc_bist:
6667
lw t1, 72(t0) // llc.BIST_STATUS_DONE_BIT
6768
beqz t1, _wait_llc_bist

‎hw/cheshire_pkg.sv‎

Lines changed: 14 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -147,13 +147,18 @@ package cheshire_pkg;
147147
shrt_bt LlcSetAssoc;
148148
shrt_bt LlcNumLines;
149149
shrt_bt LlcNumBlocks;
150+
bit LlcCachePartition;
151+
shrt_bt LlcMaxPartition;
152+
axi_llc_pkg::algorithm_e LlcRemapHash;
150153
dw_bt LlcMaxReadTxns;
151154
dw_bt LlcMaxWriteTxns;
152155
aw_bt LlcAmoNumCuts;
153156
bit LlcAmoPostCut;
154157
bit LlcOutConnect;
155158
doub_bt LlcOutRegionStart;
156159
doub_bt LlcOutRegionEnd;
160+
dw_bt LlcUserAmoMsb;
161+
dw_bt LlcUserAmoLsb;
157162
// Parameters for VGA
158163
byte_bt VgaRedWidth;
159164
byte_bt VgaGreenWidth;
@@ -384,6 +389,7 @@ package cheshire_pkg;
384389
aw_bt irq_router;
385390
aw_bt [2**MaxCoresWidth-1:0] bus_err;
386391
aw_bt [2**MaxCoresWidth-1:0] clic;
392+
aw_bt tagger;
387393
aw_bt ext_base;
388394
aw_bt num_out;
389395
aw_bt num_rules;
@@ -404,6 +410,7 @@ package cheshire_pkg;
404410
if (cfg.Gpio) begin i++; ret.gpio = i; r++; ret.map[r] = '{i, 'h0300_5000, 'h0300_6000}; end
405411
if (cfg.SerialLink) begin i++; ret.slink = i; r++; ret.map[r] = '{i, AmSlink, AmSlink +'h1000}; end
406412
if (cfg.Vga) begin i++; ret.vga = i; r++; ret.map[r] = '{i, 'h0300_7000, 'h0300_8000}; end
413+
if (cfg.LlcCachePartition) begin i++; ret.tagger = i; r++; ret.map[r] = '{i, 'h0300_a000, 'h0300_b000}; end
407414
if (cfg.IrqRouter) begin i++; ret.irq_router = i; r++; ret.map[r] = '{i, 'h0208_0000, 'h020c_0000}; end
408415
if (cfg.AxiRt) begin i++; ret.axirt = i; r++; ret.map[r] = '{i, 'h020c_0000, 'h0210_0000}; end
409416
if (cfg.Clic) for (int j = 0; j < cfg.NumCores; j++) begin
@@ -521,7 +528,7 @@ package cheshire_pkg;
521528
// Interconnect
522529
AddrWidth : 48,
523530
AxiDataWidth : 64,
524-
AxiUserWidth : 2, // AMO(2)
531+
AxiUserWidth : 2, // Convention: bit 0 for core(s), bit 1 for serial link
525532
AxiMstIdWidth : 2,
526533
AxiMaxMstTrans : 24,
527534
AxiMaxSlvTrans : 24,
@@ -568,6 +575,12 @@ package cheshire_pkg;
568575
LlcOutConnect : 1,
569576
LlcOutRegionStart : 'h8000_0000,
570577
LlcOutRegionEnd : 'h1_0000_0000,
578+
LlcUserAmoMsb : 6,
579+
LlcUserAmoLsb : 2,
580+
// LLC Partitioning
581+
LlcCachePartition : 0,
582+
LlcMaxPartition : 0,
583+
LlcRemapHash : axi_llc_pkg::Modulo,
571584
// VGA: RGB332
572585
VgaRedWidth : 3,
573586
VgaGreenWidth : 3,

‎hw/cheshire_soc.sv‎

Lines changed: 78 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -495,6 +495,7 @@ module cheshire_soc import cheshire_pkg::*; #(
495495
// This is necessary for routing in the LLC-internal interconnect.
496496
always_comb begin
497497
axi_llc_remap_req = axi_llc_cut_req;
498+
498499
if (axi_llc_cut_req.aw.addr & ~AmSpmRegionMask == AmSpmBaseUncached & ~AmSpmRegionMask)
499500
axi_llc_remap_req.aw.addr = AmSpm | (AmSpmRegionMask & axi_llc_cut_req.aw.addr);
500501
if (axi_llc_cut_req.ar.addr & ~AmSpmRegionMask == AmSpmBaseUncached & ~AmSpmRegionMask)
@@ -503,20 +504,25 @@ module cheshire_soc import cheshire_pkg::*; #(
503504
end
504505

505506
axi_llc_reg_wrap #(
506-
.SetAssociativity ( Cfg.LlcSetAssoc ),
507-
.NumLines ( Cfg.LlcNumLines ),
508-
.NumBlocks ( Cfg.LlcNumBlocks ),
509-
.AxiIdWidth ( AxiSlvIdWidth ),
510-
.AxiAddrWidth ( Cfg.AddrWidth ),
511-
.AxiDataWidth ( Cfg.AxiDataWidth ),
512-
.AxiUserWidth ( Cfg.AxiUserWidth ),
513-
.slv_req_t ( axi_slv_req_t ),
514-
.slv_resp_t ( axi_slv_rsp_t ),
515-
.mst_req_t ( axi_ext_llc_req_t ),
516-
.mst_resp_t ( axi_ext_llc_rsp_t ),
517-
.reg_req_t ( reg_req_t ),
518-
.reg_resp_t ( reg_rsp_t ),
519-
.rule_full_t ( addr_rule_t )
507+
.SetAssociativity ( Cfg.LlcSetAssoc ),
508+
.NumLines ( Cfg.LlcNumLines ),
509+
.NumBlocks ( Cfg.LlcNumBlocks ),
510+
.CachePartition ( Cfg.LlcCachePartition ),
511+
.MaxPartition ( Cfg.LlcMaxPartition ),
512+
.RemapHash ( Cfg.LlcRemapHash ),
513+
.AxiIdWidth ( AxiSlvIdWidth ),
514+
.AxiAddrWidth ( Cfg.AddrWidth ),
515+
.AxiDataWidth ( Cfg.AxiDataWidth ),
516+
.AxiUserWidth ( Cfg.AxiUserWidth ),
517+
.AxiUserIdMsb ( Cfg.LlcUserAmoMsb ),
518+
.AxiUserIdLsb ( Cfg.LlcUserAmoLsb ),
519+
.slv_req_t ( axi_slv_req_t ),
520+
.slv_resp_t ( axi_slv_rsp_t ),
521+
.mst_req_t ( axi_ext_llc_req_t ),
522+
.mst_resp_t ( axi_ext_llc_rsp_t ),
523+
.reg_req_t ( reg_req_t ),
524+
.reg_resp_t ( reg_rsp_t ),
525+
.rule_full_t ( addr_rule_t )
520526
) i_llc (
521527
.clk_i,
522528
.rst_ni,
@@ -581,6 +587,9 @@ module cheshire_soc import cheshire_pkg::*; #(
581587

582588
assign intr.intn.bus_err.cores = core_bus_err_intr_comb;
583589

590+
axi_mst_req_t [AxiIn.num_in-1:0] tagger_req;
591+
axi_mst_rsp_t [AxiIn.num_in-1:0] tagger_rsp;
592+
584593
for (genvar i = 0; i < NumIntHarts; i++) begin : gen_cva6_cores
585594
axi_cva6_req_t core_out_req, core_ur_req;
586595
axi_cva6_rsp_t core_out_rsp, core_ur_rsp;
@@ -740,11 +749,62 @@ module cheshire_soc import cheshire_pkg::*; #(
740749
) i_axi_id_serialize (
741750
.clk_i,
742751
.rst_ni,
743-
.slv_req_i ( core_ur_req ),
744-
.slv_resp_o ( core_ur_rsp ),
745-
.mst_req_o ( axi_in_req[AxiIn.cores[i]] ),
746-
.mst_resp_i ( axi_in_rsp[AxiIn.cores[i]] )
752+
.slv_req_i ( core_ur_req ),
753+
.slv_resp_o ( core_ur_rsp ),
754+
.mst_req_o ( tagger_req[i] ),
755+
.mst_resp_i ( tagger_rsp[i] )
747756
);
757+
758+
if (Cfg.LlcCachePartition) begin : gen_tagger
759+
if (i == 0) begin : gen_wr_tagger
760+
tagger #(
761+
.DATA_WIDTH ( Cfg.AxiDataWidth ),
762+
.ADDR_WIDTH ( Cfg.AddrWidth ),
763+
.MAXPARTITION ( Cfg.LlcMaxPartition ),
764+
.AXI_USER_ID_MSB ( Cfg.LlcUserAmoMsb ),
765+
.AXI_USER_ID_LSB ( Cfg.LlcUserAmoLsb ),
766+
.TAGGER_GRAN ( 3 ),
767+
.axi_req_t ( axi_mst_req_t ),
768+
.axi_rsp_t ( axi_mst_rsp_t ),
769+
.reg_req_t ( reg_req_t ),
770+
.reg_rsp_t ( reg_rsp_t )
771+
) i_tagger (
772+
.clk_i,
773+
.rst_ni,
774+
.slv_req_i ( tagger_req[i] ),
775+
.slv_rsp_o ( tagger_rsp[i] ),
776+
.mst_req_o ( axi_in_req[AxiIn.cores[i]] ),
777+
.mst_rsp_i ( axi_in_rsp[AxiIn.cores[i]] ),
778+
.cfg_req_i ( reg_out_req[RegOut.tagger] ),
779+
.cfg_rsp_o ( reg_out_rsp[RegOut.tagger] )
780+
);
781+
end else begin : gen_r_tagger
782+
tagger #(
783+
.DATA_WIDTH ( Cfg.AxiDataWidth ),
784+
.ADDR_WIDTH ( Cfg.AddrWidth ),
785+
.MAXPARTITION ( Cfg.LlcMaxPartition ),
786+
.AXI_USER_ID_MSB ( Cfg.LlcUserAmoMsb ),
787+
.AXI_USER_ID_LSB ( Cfg.LlcUserAmoLsb ),
788+
.TAGGER_GRAN ( 3 ),
789+
.axi_req_t ( axi_mst_req_t ),
790+
.axi_rsp_t ( axi_mst_rsp_t ),
791+
.reg_req_t ( reg_req_t ),
792+
.reg_rsp_t ( reg_rsp_t )
793+
) i_tagger (
794+
.clk_i,
795+
.rst_ni,
796+
.slv_req_i ( tagger_req[i] ),
797+
.slv_rsp_o ( tagger_rsp[i] ),
798+
.mst_req_o ( axi_in_req[AxiIn.cores[i]] ),
799+
.mst_rsp_i ( axi_in_rsp[AxiIn.cores[i]] ),
800+
.cfg_req_i ( reg_out_req[RegOut.tagger] ),
801+
.cfg_rsp_o ( )
802+
);
803+
end
804+
end else begin : gen_no_tagger
805+
assign axi_in_req[AxiIn.cores[i]] = tagger_req[i];
806+
assign tagger_rsp[i] = axi_in_rsp[AxiIn.cores[i]];
807+
end
748808
end
749809

750810
/////////////////////////

‎sw/include/regs/axi_llc.h‎

Lines changed: 68 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -72,6 +72,74 @@ extern "C" {
7272
#define AXI_LLC_BIST_STATUS_REG_OFFSET 0x48
7373
#define AXI_LLC_BIST_STATUS_DONE_BIT 0
7474

75+
// Index-based Partition Flush Configuration [31:0] (lower 32 bit)
76+
#define AXI_LLC_CFG_FLUSH_PARTITION_LOW_REG_OFFSET 0x4c
77+
78+
// Index-based Partition Flush Configuration [63:32] (upper 32 bit)
79+
#define AXI_LLC_CFG_FLUSH_PARTITION_HIGH_REG_OFFSET 0x50
80+
81+
// Index-based Partition Configuration [31:0] (lower 32 bit) (common
82+
// parameters)
83+
#define AXI_LLC_CFG_SET_PARTITION_LOW_LOW_FIELD_WIDTH 32
84+
#define AXI_LLC_CFG_SET_PARTITION_LOW_LOW_FIELDS_PER_REG 1
85+
#define AXI_LLC_CFG_SET_PARTITION_LOW_MULTIREG_COUNT 2
86+
87+
// Index-based Partition Configuration [31:0] (lower 32 bit)
88+
#define AXI_LLC_CFG_SET_PARTITION_LOW_0_REG_OFFSET 0x54
89+
90+
// Index-based Partition Configuration [31:0] (lower 32 bit)
91+
#define AXI_LLC_CFG_SET_PARTITION_LOW_1_REG_OFFSET 0x58
92+
93+
// Index-based Partition Configuration [63:32] (higher 32 bit) (common
94+
// parameters)
95+
#define AXI_LLC_CFG_SET_PARTITION_HIGH_HIGH_FIELD_WIDTH 32
96+
#define AXI_LLC_CFG_SET_PARTITION_HIGH_HIGH_FIELDS_PER_REG 1
97+
#define AXI_LLC_CFG_SET_PARTITION_HIGH_MULTIREG_COUNT 2
98+
99+
// Index-based Partition Configuration [63:32] (higher 32 bit)
100+
#define AXI_LLC_CFG_SET_PARTITION_HIGH_0_REG_OFFSET 0x5c
101+
102+
// Index-based Partition Configuration [63:32] (higher 32 bit)
103+
#define AXI_LLC_CFG_SET_PARTITION_HIGH_1_REG_OFFSET 0x60
104+
105+
// Commit the set partition configuration
106+
#define AXI_LLC_COMMIT_PARTITION_CFG_REG_OFFSET 0x64
107+
#define AXI_LLC_COMMIT_PARTITION_CFG_COMMIT_BIT 0
108+
109+
// Index-based Flushed Flag (lower 32 bit) (common parameters)
110+
#define AXI_LLC_FLUSHED_SET_LOW_LOW_FIELD_WIDTH 32
111+
#define AXI_LLC_FLUSHED_SET_LOW_LOW_FIELDS_PER_REG 1
112+
#define AXI_LLC_FLUSHED_SET_LOW_MULTIREG_COUNT 4
113+
114+
// Index-based Flushed Flag (lower 32 bit)
115+
#define AXI_LLC_FLUSHED_SET_LOW_0_REG_OFFSET 0x6c
116+
117+
// Index-based Flushed Flag (lower 32 bit)
118+
#define AXI_LLC_FLUSHED_SET_LOW_1_REG_OFFSET 0x70
119+
120+
// Index-based Flushed Flag (lower 32 bit)
121+
#define AXI_LLC_FLUSHED_SET_LOW_2_REG_OFFSET 0x74
122+
123+
// Index-based Flushed Flag (lower 32 bit)
124+
#define AXI_LLC_FLUSHED_SET_LOW_3_REG_OFFSET 0x78
125+
126+
// Index-based Flushed Flag (upper 32 bit) (common parameters)
127+
#define AXI_LLC_FLUSHED_SET_HIGH_HIGH_FIELD_WIDTH 32
128+
#define AXI_LLC_FLUSHED_SET_HIGH_HIGH_FIELDS_PER_REG 1
129+
#define AXI_LLC_FLUSHED_SET_HIGH_MULTIREG_COUNT 4
130+
131+
// Index-based Flushed Flag (upper 32 bit)
132+
#define AXI_LLC_FLUSHED_SET_HIGH_0_REG_OFFSET 0x7c
133+
134+
// Index-based Flushed Flag (upper 32 bit)
135+
#define AXI_LLC_FLUSHED_SET_HIGH_1_REG_OFFSET 0x80
136+
137+
// Index-based Flushed Flag (upper 32 bit)
138+
#define AXI_LLC_FLUSHED_SET_HIGH_2_REG_OFFSET 0x84
139+
140+
// Index-based Flushed Flag (upper 32 bit)
141+
#define AXI_LLC_FLUSHED_SET_HIGH_3_REG_OFFSET 0x88
142+
75143
#ifdef __cplusplus
76144
} // extern "C"
77145
#endif

‎sw/tests/helloworld.c‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -12,6 +12,7 @@
1212
#include "dif/uart.h"
1313
#include "params.h"
1414
#include "util.h"
15+
#include "regs/axi_llc.h"
1516

1617
int main(void) {
1718
char str[] = "Hello World!\r\n";

‎target/xilinx/src/cheshire_top_xilinx.sv‎

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -123,6 +123,12 @@ module cheshire_top_xilinx
123123
LlcOutConnect : 1,
124124
LlcOutRegionStart : 'h8000_0000,
125125
LlcOutRegionEnd : 'h1_0000_0000,
126+
// LLC partitioning
127+
LlcCachePartition : 0,
128+
LlcMaxPartition : 0,
129+
LlcRemapHash : axi_llc_pkg::Modulo,
130+
LlcUserAmoMsb : 0,
131+
LlcUserAmoLsb : 0,
126132
// VGA: RGB332
127133
VgaRedWidth : 5,
128134
VgaGreenWidth : 6,

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