LLC Partition: Add LLC partitioning part into cheshire.

Update the axi-test for llc partitioning tests.

WIP: Ensure correct FPGA behavior (CI test)

Author: DiyouS

Bender.lock

@@ -15,17 +15,17 @@ packages:
     - apb
     - register_interface
   axi:
-    revision: bfee21757bf090ec8e358456314b0b0fd3c90809
-    version: 0.39.0
+    revision: 4fb5a02ef5c96396ac2157bcaf09bb6a05b6a87d
+    version: null
     source:
       Git: https://github.com/pulp-platform/axi.git
     dependencies:
     - common_cells
     - common_verification
     - tech_cells_generic
   axi_llc:
-    revision: 559bcbd09a5a884dbe31e2d72fd95d024e357f39
-    version: 0.2.1
+    revision: 39ee9575279b3d1fe119616be07f485eb33df52b
+    version: null
     source:
       Git: https://github.com/pulp-platform/axi_llc.git
     dependencies:
@@ -179,9 +179,20 @@ packages:
     - axi
     - common_cells
     - register_interface
+  tagger:
+    revision: 044d92c17728e7c608cd6678d01ec2d749c7ab83
+    version: null
+    source:
+      Git: [email protected]:dishen/tagger.git
+    dependencies:
+    - axi
+    - common_cells
+    - common_verification
+    - register_interface
+    - tech_cells_generic
   tech_cells_generic:
-    revision: 298b7297d220ba2601d0f24f684f97ff32f61123
-    version: 0.2.12
+    revision: c53f93c327ec3cceceef46a38fb03bcd93c166db
+    version: null
     source:
       Git: https://github.com/pulp-platform/tech_cells_generic.git
     dependencies:

Bender.yml

@@ -13,8 +13,8 @@ package:
 
 dependencies:
   apb_uart:                 { git: "https://github.com/pulp-platform/apb_uart.git",               version: 0.2.1  }
-  axi:                      { git: "https://github.com/pulp-platform/axi.git",                    version: 0.39.0 }
-  axi_llc:                  { git: "https://github.com/pulp-platform/axi_llc.git",                version: 0.2.1  }
+  axi:                      { git: "https://github.com/pulp-platform/axi",                        rev: 4fb5a02    }
+  axi_llc:                  { git: "https://github.com/pulp-platform/axi_llc",                    rev: 39ee957    }
   axi_riscv_atomics:        { git: "https://github.com/pulp-platform/axi_riscv_atomics.git",      version: 0.8.1  }
   axi_rt:                   { git: "https://github.com/pulp-platform/axi_rt.git",                 rev: 6c00b92    }
   axi_vga:                  { git: "https://github.com/pulp-platform/axi_vga.git",                version: 0.1.1  }
@@ -30,6 +30,7 @@ dependencies:
   clic:                     { git: "https://github.com/pulp-platform/clic.git",                   version: 2.0.0  }
   irq_router:               { git: "https://github.com/pulp-platform/irq_router.git",             rev: d1d3135    }  # TODO: master commit; use next release once out
   bus_err_unit:             { git: "[email protected]:carfield/bus_err_unit.git",            rev: "47a6436"  } # branch: main
+  tagger:                   { git: "[email protected]:dishen/tagger.git",                    rev: 044d92c    }
 
 export_include_dirs:
   - hw/include

cheshire.mk

@@ -11,11 +11,16 @@ BENDER ?= bender
 VLOG_ARGS ?= -suppress 2583 -suppress 13314
 VSIM      ?= vsim
 
+MAXPARTITION 	?= 16
+CACHE_PARTITION ?= 1
+
+
 # Define used paths (prefixed to avoid name conflicts)
 CHS_ROOT      ?= $(shell $(BENDER) path cheshire)
 CHS_REG_DIR   := $(shell $(BENDER) path register_interface)
 CHS_SLINK_DIR := $(shell $(BENDER) path serial_link)
 CHS_LLC_DIR   := $(shell $(BENDER) path axi_llc)
+CHS_TAGGER_DIR := $(shell $(BENDER) path tagger)
 
 # Define paths used in dependencies
 OTPROOT      := $(shell $(BENDER) path opentitan_peripherals)
@@ -102,12 +107,24 @@ $(CHS_SLINK_DIR)/.generated: $(CHS_ROOT)/hw/serial_link.hjson
 	cp $< $(dir $@)/src/regs/serial_link_single_channel.hjson
 	flock -x $@ $(MAKE) -C $(CHS_SLINK_DIR) update-regs && touch $@
 
+# LLC partitioning configuration
+$(CHS_LLC_DIR)/.generated: 
+	$(MAKE) -C $(CHS_LLC_DIR) REGWIDTH=64 CACHENUMLINES=256 MAXPARTITION=$(MAXPARTITION) CACHE_PARTITION=$(CACHE_PARTITION) regs
+	@touch $@
+
+# Tagger configuration
+$(CHS_TAGGER_DIR)/.generated: 
+	$(MAKE) -C $(CHS_TAGGER_DIR) REGWIDTH=32 MAXPARTITION=$(MAXPARTITION) PATID_LEN=5 regs
+	@touch $@
+
 CHS_HW_ALL += $(CHS_ROOT)/hw/regs/cheshire_reg_pkg.sv $(CHS_ROOT)/hw/regs/cheshire_reg_top.sv
 CHS_HW_ALL += $(CLINTROOT)/.generated
 CHS_HW_ALL += $(OTPROOT)/.generated
 CHS_HW_ALL += $(AXIRTROOT)/.generated
 CHS_HW_ALL += $(AXI_VGA_ROOT)/.generated
 CHS_HW_ALL += $(CHS_SLINK_DIR)/.generated
+CHS_HW_ALL += $(CHS_LLC_DIR)/.generated
+CHS_HW_ALL += $(CHS_TAGGER_DIR)/.generated
 
 #####################
 # Generate Boot ROM #

hw/bootrom/cheshire_bootrom.S

@@ -62,9 +62,44 @@ _start:
     andi t0, t0, 2  // regs.HW_FEATURES.llc
     beqz t0, _prom_check_run
     la t0, __base_llc
+    // Only configure half of LLC as SPM
 _wait_llc_bist:
     lw t1, 72(t0)   // llc.BIST_STATUS_DONE_BIT
     beqz t1, _wait_llc_bist
+
+    // Cache partitioning
+    
+    // li t1, 0xFF          // Flush LLC
+    // sw t1, 8(t0)
+    // li t1, 1
+    // sw t1, 16(t0)
+
+    // Set tagger region
+    lui t1, 0x9
+    add t0, t1, t0
+    lui t1, 0xFFFFF // 0xFFFF_F000
+    sw t1, 4(t0)
+
+    // set patid to 0
+    li t1, 0
+    sw t1, 68(t0)   // 0x44
+
+    // set mode to TOR
+    li t1, 0x1
+    sw t1, 80(t0)   // 0x50
+
+    // commit changes
+    li t1, 0x1
+    sw t1, 0(t0)
+
+    la t0, __base_llc
+
+    // lui t1, 0x4         // give partition 2 size 64
+    // sw t1, 84(t0)       // partition table configuration
+    // li t1, 1
+    // sw t1, 100(t0)      // commit partition configuration
+
+    
     li t1, -1
     sw t1, 0(t0)    // llc.CFG_SPM_LOW
     sw t1, 4(t0)    // llc.CFG_SPM_HIGH