cleanup

Author: chaoqun-liang

Bender.lock

@@ -15,8 +15,8 @@ packages:
     - apb
     - register_interface
   axi:
-    revision: fccffb5953ec8564218ba05e20adbedec845e014
-    version: 0.39.1
+    revision: ac5deb3ff086aa34b168f392c051e92603d6c0e2
+    version: 0.39.2
     source:
       Git: https://github.com/pulp-platform/axi.git
     dependencies:
@@ -67,8 +67,8 @@ packages:
     dependencies:
     - common_cells
   axi_vga:
-    revision: 07be187d1e954d8090031b32d236ad76dc62ce45
-    version: 0.1.1
+    revision: 3718b9930f94a9eaad8ee50b4bccc71df0403084
+    version: 0.1.3
     source:
       Git: https://github.com/pulp-platform/axi_vga.git
     dependencies:
@@ -92,8 +92,8 @@ packages:
     - common_cells
     - register_interface
   common_cells:
-    revision: 2bd027cb87eaa9bf7d17196ec5f69864b35b630f
-    version: 1.32.0
+    revision: 7773d971b9d7bef7f5f6a2ef36ee1e4d02cefcd3
+    version: 1.34.0
     source:
       Git: https://github.com/pulp-platform/common_cells.git
     dependencies:
@@ -116,7 +116,7 @@ packages:
     - fpnew
     - tech_cells_generic
   ethernet:
-    revision: ab333c946fbfea18132904f8de0dc6702d67e741
+    revision: d7d14161b8f129bccfcf9717f33760cb0a027856
     version: null
     source:
       Git: [email protected]:pulp-platform/pulp-ethernet.git
@@ -179,8 +179,8 @@ packages:
     - register_interface
     - tech_cells_generic
   register_interface:
-    revision: d7693be4aef1fc7e7eb2b00b41c42e87d959866c
-    version: 0.4.2
+    revision: ae616e5a1ec2b41e72d200e5ab09c65e94aebd3d
+    version: 0.4.4
     source:
       Git: https://github.com/pulp-platform/register_interface.git
     dependencies:

Bender.yml

@@ -30,7 +30,7 @@ dependencies:
   riscv-dbg:                { git: "https://github.com/pulp-platform/riscv-dbg.git",              version: 0.8.0  }
   serial_link:              { git: "https://github.com/pulp-platform/serial_link.git",            version: 1.1.0  }
   unbent:                   { git: "https://github.com/pulp-platform/unbent.git",                 version: 0.1.6  }
-  ethernet:                 { git: "[email protected]:pulp-platform/pulp-ethernet.git",              rev: "ab333c9"  }
+  ethernet:                 { git: "[email protected]:pulp-platform/pulp-ethernet.git",              rev: "d7d1416"  }
 
 export_include_dirs:
   - hw/include

Makefile

@@ -13,7 +13,7 @@ include cheshire.mk
 
 # Inside the repo, forward (prefixed) all, nonfree, and clean targets
 all:
-	@$(MAKE) chs-all
+	@$(MAKE) chs-all 
 
 %-all:
 	@$(MAKE) chs-$*-all

cheshire.mk

@@ -23,6 +23,7 @@ CLINTROOT    := $(shell $(BENDER) path clint)
 AXIRTROOT    := $(shell $(BENDER) path axi_rt)
 AXI_VGA_ROOT := $(shell $(BENDER) path axi_vga)
 IDMA_ROOT    := $(shell $(BENDER) path idma)
+ETH_ROOT     := $(shell $(BENDER) path ethernet)
 
 REGTOOL ?= $(CHS_REG_DIR)/vendor/lowrisc_opentitan/util/regtool.py
 
@@ -43,6 +44,11 @@ ifeq ($(shell test -f $(BENDER_ROOT)/.chs_deps && echo 1),)
 -include $(BENDER_ROOT)/.chs_deps
 endif
 
+idma-gen:
+	make -C $(IDMA_ROOT) idma_hw_all
+	make -C $(IDMA_ROOT) target/rtl/idma_reg64_2d.hjson
+	make -C $(ETH_ROOT) eth-gen
+
 # Running this target will reset dependencies (without updating the checked-in Bender.lock)
 chs-clean-deps:
 	rm -rf .bender
@@ -171,7 +177,7 @@ CHS_XILINX_ALL += $(CHS_ROOT)/target/xilinx/scripts/add_sources.tcl
 
 CHS_ALL += $(CHS_SW_ALL) $(CHS_HW_ALL) $(CHS_SIM_ALL) $(CHS_XILINX_ALL)
 
-chs-all:         $(CHS_ALL)
+chs-all:         $(CHS_ALL) idma-gen
 chs-sw-all:      $(CHS_SW_ALL)
 chs-hw-all:      $(CHS_HW_ALL)
 chs-bootrom-all: $(CHS_BOOTROM_ALL)

hw/cheshire_soc.sv

@@ -28,6 +28,8 @@ module cheshire_soc import cheshire_pkg::*; #(
   input  logic        test_mode_i,
   input  logic [1:0]  boot_mode_i,
   input  logic        rtc_i,
+  input  logic        eth_clk_125,
+  input  logic        eth_clk_90, 
   // External AXI LLC (DRAM) port
   output axi_ext_llc_req_t axi_llc_mst_req_o,
   input  axi_ext_llc_rsp_t axi_llc_mst_rsp_i,
@@ -81,9 +83,7 @@ module cheshire_soc import cheshire_pkg::*; #(
   output logic        eth_txck_o,
   output logic [3:0]  eth_txd_o,
   output logic        eth_txctl_o,
-  output logic        eth_rstn_o,  
-  input  logic        eth_intn_i,
-  input  logic        eth_pme_i,
+  output logic        eth_rstn_o,
   input  logic        eth_mdio_i,
   output logic        eth_mdio_o,
   output logic        eth_mdio_oe,
@@ -1313,7 +1313,9 @@ module cheshire_soc import cheshire_pkg::*; #(
       .reg_rsp_t           ( reg_rsp_t         )
     ) i_tx_eth_idma_wrap (
       .clk_i,
-      .rst_ni,
+      .rst_ni, 
+      .eth_clk_i           ( eth_clk_125 ),
+      .eth_clk90_i         ( eth_clk_90  ),
       .phy_rx_clk_i        ( eth_rxck_i  ),
       .phy_rxd_i           ( eth_rxd_i   ),
       .phy_rx_ctl_i        ( eth_rxctl_i ),
@@ -1323,7 +1325,7 @@ module cheshire_soc import cheshire_pkg::*; #(
       .phy_resetn_o        ( eth_rstn_o  ),  
       .phy_intn_i          ( 1'b1        ),
       .phy_pme_i           ( 1'b1        ),
-      .phy_mdio_i          ( 1'b0        ),
+      .phy_mdio_i          ( eth_mdio_i  ),
       .phy_mdio_o          ( eth_mdio_o  ),
       .phy_mdio_oe         ( eth_mdio_oe ),
       .phy_mdc_o           ( eth_mdc_o   ), 

sw/tests/ethernet.c

@@ -38,7 +38,6 @@ int main(void) {
         *tx_addr = data_to_write[i];
   }
 
-
   *reg32(ETH_BASE, MACLO_OFFSET)  = 0x98001032;  
   *reg32(ETH_BASE, MACHI_OFFSET) = 0x00012070;  
 
@@ -52,21 +51,8 @@ int main(void) {
   *reg32(ETH_BASE, IDMA_REQ_VALID_OFFSET) = 0x1;
   *reg32(ETH_BASE, IDMA_REQ_VALID_OFFSET) = 0x0;
   *reg32(ETH_BASE, IDMA_RSP_READY_OFFSET) = 0x1;
-
-  // pulp_write32( ETH_BASE + IDMA_REQ_VALID_OFFSET ,   0x1);
-
-  // pulp_write32( ETH_BASE + IDMA_REQ_VALID_OFFSET ,   0x0);
-  
-
-  //  // data
-  //  pulp_write32( ETH_BASE + IDMA_RSP_READY_OFFSET , 0x1);
 
-   // to-do deassert rsp_ready when rx transaction is complete
-
-
- 
-    while(1);
-
-  //return 0;
+   // can leave rsp_ready high  
+  return 0;
 
 }

target/sim/src/fixture_cheshire_soc.sv

@@ -49,19 +49,19 @@ module fixture_cheshire_soc #(
   logic i2c_scl_i;
   logic i2c_scl_en;
 
-  logic       eth_rxck_i;
-  logic [3:0] eth_rxd_i;
-  logic       eth_rxctl_i;
-  logic       eth_txck_o;
-  logic [3:0] eth_txd_o;
-  logic       eth_txctl_o;
-  logic       eth_rstn_o;  
-  logic       eth_intn_i;
-  logic       eth_pme_i;
+  logic       eth_clk_125;
+  logic       eth_clk_90;
+  logic       eth_rxck;
+  logic [3:0] eth_rxd;
+  logic       eth_rxctl;
+  logic       eth_txck;
+  logic [3:0] eth_txd;
+  logic       eth_txctl;
+  logic       eth_rstn;  
   logic       eth_mdio_i;
   logic       eth_mdio_o;
   logic       eth_mdio_en;
-  logic       eth_mdc_o;
+  logic       eth_mdc;
 
   logic                 spih_sck_o;
   logic                 spih_sck_en;
@@ -129,19 +129,19 @@ module fixture_cheshire_soc #(
     .i2c_scl_o          ( i2c_scl_o  ),
     .i2c_scl_i          ( i2c_scl_i  ),
     .i2c_scl_en_o       ( i2c_scl_en ),
-    .eth_rxck_i         ( eth_rxck_i  ),
-    .eth_rxd_i          ( eth_rxd_i   ),
-    .eth_rxctl_i        ( eth_rxctl_i ),
-    .eth_txck_o         ( eth_txck_o  ),
-    .eth_txd_o          ( eth_txd_o   ),
-    .eth_txctl_o        ( eth_txctl_o ),
-    .eth_rstn_o         ( eth_rstn_o  ),  
-    .eth_intn_i         ( eth_intn_i  ),
-    .eth_pme_i          ( eth_pme_i   ),
+    .eth_clk_125        ( eth_clk_125 ),
+    .eth_clk_90         ( eth_clk_90  ),
+    .eth_rxck_i         ( eth_rxck    ),
+    .eth_rxd_i          ( eth_rxd     ),
+    .eth_rxctl_i        ( eth_rxctl   ),
+    .eth_txck_o         ( eth_txck    ),
+    .eth_txd_o          ( eth_txd     ),
+    .eth_txctl_o        ( eth_txctl   ),
+    .eth_rstn_o         ( eth_rstn    ),  
     .eth_mdio_i         ( eth_mdio_i  ),
     .eth_mdio_o         ( eth_mdio_o  ),
     .eth_mdio_oe        ( eth_mdio_en ),
-    .eth_mdc_o          ( eth_mdc_o   ),
+    .eth_mdc_o          ( eth_mdc     ),
     .spih_sck_o         ( spih_sck_o  ),
     .spih_sck_en_o      ( spih_sck_en ),
     .spih_csb_o         ( spih_csb_o  ),
@@ -174,15 +174,7 @@ module fixture_cheshire_soc #(
   wire [SpihNumCs-1:0] spih_csb;
   wire [ 3:0]          spih_sd;
 
-  wire [ 3:0]          eth_txd;
-  wire [ 3:0]          eth_rxd;
-  wire                 eth_txck;
-  wire                 eth_rxck;
-  wire                 eth_txctl;
-  wire                 eth_rxctl;
-  wire                 eth_rstn;
   wire                 eth_mdio;
-  wire                 eth_mdc;
 
   vip_cheshire_soc_tristate vip_tristate (.*);