diff --git a/Verilog.tmLanguage b/Verilog.tmLanguage
index 00debcd..a45b31f 100644
--- a/Verilog.tmLanguage
+++ b/Verilog.tmLanguage
@@ -24,7 +24,7 @@
1
name
- storage.type.verilog
+ storage.verilog
2
@@ -50,12 +50,12 @@
2
name
- entity.name.type.instance.verilog
+ variable.function.verilog
3
name
- keyword.operator.parenthesis.round.verilog
+ text.operator.parenthesis.round.verilog
match
@@ -82,7 +82,7 @@
3
name
- keyword.operator.parenthesis.round.verilog
+ text.operator.parenthesis.round.verilog
4
@@ -92,7 +92,7 @@
5
name
- keyword.operator.parenthesis.round.verilog
+ text.operator.parenthesis.round.verilog
6
@@ -102,7 +102,7 @@
7
name
- keyword.operator.parenthesis.round.verilog
+ text.operator.parenthesis.round.verilog
match
@@ -201,12 +201,12 @@
name
- meta.preprocessor.verilog
+ keyword.preprocessor.verilog
2
name
- entity.name.type.include.verilog
+ entity.name.filename.include.verilog
match
@@ -220,7 +220,7 @@
1
name
- meta.preprocessor.verilog
+ keyword.preprocessor.verilog
2
@@ -237,7 +237,7 @@
match
`(celldefine|default_nettype|define|else|elsif|endcelldefine|endif|ifdef|ifndef|include|line|nounconnected_drive|resetall|timescale|unconnected_drive|undef)\b
name
- meta.preprocessor.verilog
+ keyword.preprocessor.verilog
match
@@ -259,7 +259,7 @@
match
\b(endmodule|endfunction|endprimitive)\b
name
- storage.type.verilog
+ storage.verilog
captures
@@ -308,7 +308,7 @@
name
keyword.operator.bitwise.verilog
-
+
match
(#|@|=)