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Copy file name to clipboardExpand all lines: nova/README.md
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@@ -14,18 +14,27 @@ Each instruction is compiled into a step circuit, following Nova(Supernova) pape
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An augmented circuit := step circuit + nova folding verification circuit.
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Furthermore, an augmented circuit has it own isolated constraints system, means there will be no shared circuit among different augmented circuits. Due to the fact, we can also call it instruction-circuit. There will be `#inst` instruction-circuit (More accurate, `#inst + 1` for 2 cycle curve implementation)
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### Nova state & Constraints
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public input layout as z0 = `(pc, [writable register...] + [rom_value_pc1, rom_value_pc2, rom_value_pc3...])`
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### Nova state & constraints
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Nova state layout as z0 = `(pc, [writable register...] ++ ROM)`
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where the ROM is defined as an array `[rom_value_pc1, rom_value_pc2, rom_value_pc3...]`
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Each round an instruction is invoked, and in instruction-circuit it will constraints
2. writable register read/write are value are constraint and match.
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> While which instruction-circuit is invoked determined by prover, an maliculous prover can not invoke arbitrary any instruction-circuit, otherwise sequence constraints will be failed to pass `is_sat` check in the final stage.
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### Sequence constraints
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As mentioned, to constraints the sequence, a ROM array is introduced and attach at the end of Nova state. For input params in different type, the linear combination strategy will be adjust accordingly.
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-`reg index`, i.e. x2. `2` will be treat as unsigned index and put into the value
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-`sign/unsigned` const. For unsigned value will be put in lc directly. While signed part, it will be convert to signed limb, and on circuit side, signed limb will be convert to negative field value accordingly.
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-`label`. i.e. `loop_start`, label will be convert to integer
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Since each instruction circuit has it own params type definition, different constraints circuit will be compiled to handle above situation automatically.
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### R1CS constraints
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An augmented circuit can be viewed as a individual constraint system. PIL in powdr-asm instruction definition body will be compile into respective R1CS constraints. More detail, constraints can be categorized into 2 group
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1. sequence constraints + writable register RW => this constraints will be insert into R1CS circuit automatically and transparent to powdr-asm PIL.
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1. sequence constraints + writable register RW (or signed/unsigned/label) => this constraints will be insert into R1CS circuit automatically and transparent to powdr-asm PIL.
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2. Powdr-asm PIL constraints: will be compiled into R1CS constraints
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