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Commit 4949871
feat: Verilog, SystemVerilog, and VHDL code is syntax highlighted
Bump @pierre/highlights to 0.3.0, which adds Verilog/SystemVerilog and
VHDL lexers, and regenerate the mobile native highlighter for the new
token and language IDs. @pierre/diffs already maps .v/.vh, .sv/.svh and
.vhd/.vhdl to these languages. Add the three languages to the code-block
language picker.
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>1 parent 47f2c8d commit 4949871
8 files changed
Lines changed: 125419 additions & 75662 deletions
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- apps
- mobile
- modules/t3-highlights/Vendor/highlights
- src/lib
- web/src
- lib
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