deps: V8: cherry-pick 3805a698f7b6

Original commit message:

    PPC/s390: [wasm][liftoff] Always zero-extend 32 bit offsets

    Port 2b77ca200c56667c68895e49c96c10ff77834f09

    Original Commit Message:

        The upper 32 bits of the 64 bit offset register are not guaranteed to be
        cleared, so a zero-extension is needed. We already do the zero-extension
        in the case of explicit bounds checking, but this should also be done if
        the trap handler is enabled.

    [email protected], [email protected], [email protected], [email protected]
    BUG=
    LOG=N

    Change-Id: Ife3ae4f93b85fe1b2c76fe4b98fa408b5b51ed71
    Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2929661
    Reviewed-by: Junliang Yan <[email protected]>
    Commit-Queue: Milad Fa <[email protected]>
    Cr-Commit-Position: refs/heads/master@{#74886}

Refs: v8/v8@3805a69

PR-URL: #39337
Reviewed-By: Matteo Collina <[email protected]>
Reviewed-By: James M Snell <[email protected]>

Author: targos

common.gypi

@@ -36,7 +36,7 @@
 
     # Reset this number to 0 on major V8 upgrades.
     # Increment by one for each non-official patch applied to deps/v8.
-    'v8_embedder_string': '-node.15',
+    'v8_embedder_string': '-node.16',
 
     ##### V8 defaults for Node.js #####
 

deps/v8/src/wasm/baseline/ppc/liftoff-assembler-ppc.h

@@ -203,7 +203,8 @@ void LiftoffAssembler::StoreTaggedPointer(Register dst_addr,
 void LiftoffAssembler::Load(LiftoffRegister dst, Register src_addr,
                             Register offset_reg, uintptr_t offset_imm,
                             LoadType type, LiftoffRegList pinned,
-                            uint32_t* protected_load_pc, bool is_load_mem) {
+                            uint32_t* protected_load_pc, bool is_load_mem,
+                            bool i64_offset) {
   bailout(kUnsupportedArchitecture, "Load");
 }
 

deps/v8/src/wasm/baseline/s390/liftoff-assembler-s390.h

@@ -279,11 +279,17 @@ void LiftoffAssembler::StoreTaggedPointer(Register dst_addr,
 void LiftoffAssembler::Load(LiftoffRegister dst, Register src_addr,
                             Register offset_reg, uintptr_t offset_imm,
                             LoadType type, LiftoffRegList pinned,
-                            uint32_t* protected_load_pc, bool is_load_mem) {
+                            uint32_t* protected_load_pc, bool is_load_mem,
+                            bool i64_offset) {
   UseScratchRegisterScope temps(this);
   if (!is_int20(offset_imm)) {
     mov(ip, Operand(offset_imm));
     if (offset_reg != no_reg) {
+      if (!i64_offset) {
+        // Clear the upper 32 bits of the 64 bit offset register.
+        llgfr(r0, offset_reg);
+        offset_reg = r0;
+      }
       AddS64(ip, offset_reg);
     }
     offset_reg = ip;