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riscv-dbg
riscv-dbg PublicForked from pulp-platform/riscv-dbg
RISC-V Debug Support for our PULP RISC-V Cores
SystemVerilog
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opentitan
opentitan PublicForked from lowRISC/opentitan
OpenTitan: Open source silicon root of trust
SystemVerilog
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axi
axi PublicForked from pulp-platform/axi
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
SystemVerilog
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- tech_cells_generic Public Forked from pulp-platform/tech_cells_generic
Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
mosaic-soc/tech_cells_generic’s past year of commit activity - hwpe-ctrl Public Forked from pulp-platform/hwpe-ctrl
IPs for control-plane integration of Hardware Processing Engines (HWPEs) within a PULP system
mosaic-soc/hwpe-ctrl’s past year of commit activity - hwpe-stream Public Forked from pulp-platform/hwpe-stream
IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system
mosaic-soc/hwpe-stream’s past year of commit activity - cluster_icache Public Forked from pulp-platform/cluster_icache
An instruction cache for processor clusters, originally developed for the snitch cluster.
mosaic-soc/cluster_icache’s past year of commit activity - axi Public Forked from pulp-platform/axi
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
mosaic-soc/axi’s past year of commit activity - PeakRDL-addrpkg Public
mosaic-soc/PeakRDL-addrpkg’s past year of commit activity - PeakRDL-ld Public
mosaic-soc/PeakRDL-ld’s past year of commit activity
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