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[DAGCombiner] Combine vp.strided.load with unit stride to vp.load
This is the VP equivalent of llvm#65674. We already combine MGATHER loads with unit stride to MLOAD, so this extends it for EXPERIMENTAL_VP_STRIDED_LOAD.
1 parent 33dac56 commit 6ef5440

3 files changed

Lines changed: 35 additions & 28 deletions

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‎llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp‎

Lines changed: 21 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -539,6 +539,7 @@ namespace {
539539
SDValue visitMSCATTER(SDNode *N);
540540
SDValue visitVPGATHER(SDNode *N);
541541
SDValue visitVPSCATTER(SDNode *N);
542+
SDValue visitVP_STRIDED_LOAD(SDNode *N);
542543
SDValue visitFP_TO_FP16(SDNode *N);
543544
SDValue visitFP16_TO_FP(SDNode *N);
544545
SDValue visitFP_TO_BF16(SDNode *N);
@@ -11959,6 +11960,22 @@ SDValue DAGCombiner::visitMLOAD(SDNode *N) {
1195911960
return SDValue();
1196011961
}
1196111962

11963+
SDValue DAGCombiner::visitVP_STRIDED_LOAD(SDNode *N) {
11964+
auto *SLD = cast<VPStridedLoadSDNode>(N);
11965+
EVT EltVT = SLD->getValueType(0).getVectorElementType();
11966+
// Combine strided loads with unit-stride to a regular load.
11967+
if (auto *CStride = dyn_cast<ConstantSDNode>(SLD->getStride());
11968+
CStride && CStride->getZExtValue() == EltVT.getStoreSize()) {
11969+
SDValue NewLd = DAG.getLoadVP(
11970+
SLD->getAddressingMode(), SLD->getExtensionType(), SLD->getValueType(0),
11971+
SDLoc(N), SLD->getChain(), SLD->getBasePtr(), SLD->getOffset(),
11972+
SLD->getMask(), SLD->getVectorLength(), SLD->getMemoryVT(),
11973+
SLD->getMemOperand(), SLD->isExpandingLoad());
11974+
return CombineTo(N, NewLd, NewLd.getValue(1));
11975+
}
11976+
return SDValue();
11977+
}
11978+
1196211979
/// A vector select of 2 constant vectors can be simplified to math/logic to
1196311980
/// avoid a variable select instruction and possibly avoid constant loads.
1196411981
SDValue DAGCombiner::foldVSelectOfConstants(SDNode *N) {
@@ -25976,6 +25993,10 @@ SDValue DAGCombiner::visitVPOp(SDNode *N) {
2597625993
if (SDValue SD = visitVPSCATTER(N))
2597725994
return SD;
2597825995

25996+
if (N->getOpcode() == ISD::EXPERIMENTAL_VP_STRIDED_LOAD)
25997+
if (SDValue SD = visitVP_STRIDED_LOAD(N))
25998+
return SD;
25999+
2597926000
// VP operations in which all vector elements are disabled - either by
2598026001
// determining that the mask is all false or that the EVL is 0 - can be
2598126002
// eliminated.

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-vpload.ll‎

Lines changed: 7 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -99,9 +99,8 @@ define <8 x i8> @strided_vpload_v8i8(ptr %ptr, i32 signext %stride, <8 x i1> %m,
9999
define <8 x i8> @strided_vpload_v8i8_unit_stride(ptr %ptr, <8 x i1> %m, i32 zeroext %evl) {
100100
; CHECK-LABEL: strided_vpload_v8i8_unit_stride:
101101
; CHECK: # %bb.0:
102-
; CHECK-NEXT: li a2, 1
103102
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
104-
; CHECK-NEXT: vlse8.v v8, (a0), a2, v0.t
103+
; CHECK-NEXT: vle8.v v8, (a0), v0.t
105104
; CHECK-NEXT: ret
106105
%load = call <8 x i8> @llvm.experimental.vp.strided.load.v8i8.p0.i32(ptr %ptr, i32 1, <8 x i1> %m, i32 %evl)
107106
ret <8 x i8> %load
@@ -146,9 +145,8 @@ define <8 x i16> @strided_vpload_v8i16(ptr %ptr, i32 signext %stride, <8 x i1> %
146145
define <8 x i16> @strided_vpload_v8i16_unit_stride(ptr %ptr, <8 x i1> %m, i32 zeroext %evl) {
147146
; CHECK-LABEL: strided_vpload_v8i16_unit_stride:
148147
; CHECK: # %bb.0:
149-
; CHECK-NEXT: li a2, 2
150148
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
151-
; CHECK-NEXT: vlse16.v v8, (a0), a2, v0.t
149+
; CHECK-NEXT: vle16.v v8, (a0), v0.t
152150
; CHECK-NEXT: ret
153151
%load = call <8 x i16> @llvm.experimental.vp.strided.load.v8i16.p0.i32(ptr %ptr, i32 2, <8 x i1> %m, i32 %evl)
154152
ret <8 x i16> %load
@@ -193,9 +191,8 @@ define <4 x i32> @strided_vpload_v4i32(ptr %ptr, i32 signext %stride, <4 x i1> %
193191
define <4 x i32> @strided_vpload_v4i32_unit_stride(ptr %ptr, <4 x i1> %m, i32 zeroext %evl) {
194192
; CHECK-LABEL: strided_vpload_v4i32_unit_stride:
195193
; CHECK: # %bb.0:
196-
; CHECK-NEXT: li a2, 4
197194
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
198-
; CHECK-NEXT: vlse32.v v8, (a0), a2, v0.t
195+
; CHECK-NEXT: vle32.v v8, (a0), v0.t
199196
; CHECK-NEXT: ret
200197
%load = call <4 x i32> @llvm.experimental.vp.strided.load.v4i32.p0.i32(ptr %ptr, i32 4, <4 x i1> %m, i32 %evl)
201198
ret <4 x i32> %load
@@ -240,9 +237,8 @@ define <2 x i64> @strided_vpload_v2i64(ptr %ptr, i32 signext %stride, <2 x i1> %
240237
define <2 x i64> @strided_vpload_v2i64_unit_stride(ptr %ptr, <2 x i1> %m, i32 zeroext %evl) {
241238
; CHECK-LABEL: strided_vpload_v2i64_unit_stride:
242239
; CHECK: # %bb.0:
243-
; CHECK-NEXT: li a2, 8
244240
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
245-
; CHECK-NEXT: vlse64.v v8, (a0), a2, v0.t
241+
; CHECK-NEXT: vle64.v v8, (a0), v0.t
246242
; CHECK-NEXT: ret
247243
%load = call <2 x i64> @llvm.experimental.vp.strided.load.v2i64.p0.i32(ptr %ptr, i32 8, <2 x i1> %m, i32 %evl)
248244
ret <2 x i64> %load
@@ -335,9 +331,8 @@ define <8 x half> @strided_vpload_v8f16(ptr %ptr, i32 signext %stride, <8 x i1>
335331
define <8 x half> @strided_vpload_v8f16_unit_stride(ptr %ptr, <8 x i1> %m, i32 zeroext %evl) {
336332
; CHECK-LABEL: strided_vpload_v8f16_unit_stride:
337333
; CHECK: # %bb.0:
338-
; CHECK-NEXT: li a2, 2
339334
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
340-
; CHECK-NEXT: vlse16.v v8, (a0), a2, v0.t
335+
; CHECK-NEXT: vle16.v v8, (a0), v0.t
341336
; CHECK-NEXT: ret
342337
%load = call <8 x half> @llvm.experimental.vp.strided.load.v8f16.p0.i32(ptr %ptr, i32 2, <8 x i1> %m, i32 %evl)
343338
ret <8 x half> %load
@@ -370,9 +365,8 @@ define <4 x float> @strided_vpload_v4f32(ptr %ptr, i32 signext %stride, <4 x i1>
370365
define <4 x float> @strided_vpload_v4f32_unit_stride(ptr %ptr, <4 x i1> %m, i32 zeroext %evl) {
371366
; CHECK-LABEL: strided_vpload_v4f32_unit_stride:
372367
; CHECK: # %bb.0:
373-
; CHECK-NEXT: li a2, 4
374368
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
375-
; CHECK-NEXT: vlse32.v v8, (a0), a2, v0.t
369+
; CHECK-NEXT: vle32.v v8, (a0), v0.t
376370
; CHECK-NEXT: ret
377371
%load = call <4 x float> @llvm.experimental.vp.strided.load.v4f32.p0.i32(ptr %ptr, i32 4, <4 x i1> %m, i32 %evl)
378372
ret <4 x float> %load
@@ -417,9 +411,8 @@ define <2 x double> @strided_vpload_v2f64(ptr %ptr, i32 signext %stride, <2 x i1
417411
define <2 x double> @strided_vpload_v2f64_unit_stride(ptr %ptr, <2 x i1> %m, i32 zeroext %evl) {
418412
; CHECK-LABEL: strided_vpload_v2f64_unit_stride:
419413
; CHECK: # %bb.0:
420-
; CHECK-NEXT: li a2, 8
421414
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
422-
; CHECK-NEXT: vlse64.v v8, (a0), a2, v0.t
415+
; CHECK-NEXT: vle64.v v8, (a0), v0.t
423416
; CHECK-NEXT: ret
424417
%load = call <2 x double> @llvm.experimental.vp.strided.load.v2f64.p0.i32(ptr %ptr, i32 8, <2 x i1> %m, i32 %evl)
425418
ret <2 x double> %load

‎llvm/test/CodeGen/RISCV/rvv/strided-vpload.ll‎

Lines changed: 7 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -129,9 +129,8 @@ define <vscale x 8 x i8> @strided_vpload_nxv8i8(ptr %ptr, i32 signext %stride, <
129129
define <vscale x 8 x i8> @strided_vpload_nxv8i8_unit_stride(ptr %ptr, <vscale x 8 x i1> %m, i32 zeroext %evl) {
130130
; CHECK-LABEL: strided_vpload_nxv8i8_unit_stride:
131131
; CHECK: # %bb.0:
132-
; CHECK-NEXT: li a2, 1
133132
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
134-
; CHECK-NEXT: vlse8.v v8, (a0), a2, v0.t
133+
; CHECK-NEXT: vle8.v v8, (a0), v0.t
135134
; CHECK-NEXT: ret
136135
%load = call <vscale x 8 x i8> @llvm.experimental.vp.strided.load.nxv8i8.p0.i32(ptr %ptr, i32 1, <vscale x 8 x i1> %m, i32 %evl)
137136
ret <vscale x 8 x i8> %load
@@ -200,9 +199,8 @@ define <vscale x 4 x i16> @strided_vpload_nxv4i16(ptr %ptr, i32 signext %stride,
200199
define <vscale x 4 x i16> @strided_vpload_nxv4i16_unit_stride(ptr %ptr, <vscale x 4 x i1> %m, i32 zeroext %evl) {
201200
; CHECK-LABEL: strided_vpload_nxv4i16_unit_stride:
202201
; CHECK: # %bb.0:
203-
; CHECK-NEXT: li a2, 2
204202
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
205-
; CHECK-NEXT: vlse16.v v8, (a0), a2, v0.t
203+
; CHECK-NEXT: vle16.v v8, (a0), v0.t
206204
; CHECK-NEXT: ret
207205
%load = call <vscale x 4 x i16> @llvm.experimental.vp.strided.load.nxv4i16.p0.i32(ptr %ptr, i32 2, <vscale x 4 x i1> %m, i32 %evl)
208206
ret <vscale x 4 x i16> %load
@@ -247,9 +245,8 @@ define <vscale x 2 x i32> @strided_vpload_nxv2i32(ptr %ptr, i32 signext %stride,
247245
define <vscale x 2 x i32> @strided_vpload_nxv2i32_unit_stride(ptr %ptr, <vscale x 2 x i1> %m, i32 zeroext %evl) {
248246
; CHECK-LABEL: strided_vpload_nxv2i32_unit_stride:
249247
; CHECK: # %bb.0:
250-
; CHECK-NEXT: li a2, 4
251248
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
252-
; CHECK-NEXT: vlse32.v v8, (a0), a2, v0.t
249+
; CHECK-NEXT: vle32.v v8, (a0), v0.t
253250
; CHECK-NEXT: ret
254251
%load = call <vscale x 2 x i32> @llvm.experimental.vp.strided.load.nxv2i32.p0.i32(ptr %ptr, i32 4, <vscale x 2 x i1> %m, i32 %evl)
255252
ret <vscale x 2 x i32> %load
@@ -306,9 +303,8 @@ define <vscale x 1 x i64> @strided_vpload_nxv1i64(ptr %ptr, i32 signext %stride,
306303
define <vscale x 1 x i64> @strided_vpload_nxv1i64_unit_stride(ptr %ptr, <vscale x 1 x i1> %m, i32 zeroext %evl) {
307304
; CHECK-LABEL: strided_vpload_nxv1i64_unit_stride:
308305
; CHECK: # %bb.0:
309-
; CHECK-NEXT: li a2, 8
310306
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
311-
; CHECK-NEXT: vlse64.v v8, (a0), a2, v0.t
307+
; CHECK-NEXT: vle64.v v8, (a0), v0.t
312308
; CHECK-NEXT: ret
313309
%load = call <vscale x 1 x i64> @llvm.experimental.vp.strided.load.nxv1i64.p0.i32(ptr %ptr, i32 8, <vscale x 1 x i1> %m, i32 %evl)
314310
ret <vscale x 1 x i64> %load
@@ -413,9 +409,8 @@ define <vscale x 4 x half> @strided_vpload_nxv4f16(ptr %ptr, i32 signext %stride
413409
define <vscale x 4 x half> @strided_vpload_nxv4f16_unit_stride(ptr %ptr, <vscale x 4 x i1> %m, i32 zeroext %evl) {
414410
; CHECK-LABEL: strided_vpload_nxv4f16_unit_stride:
415411
; CHECK: # %bb.0:
416-
; CHECK-NEXT: li a2, 2
417412
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
418-
; CHECK-NEXT: vlse16.v v8, (a0), a2, v0.t
413+
; CHECK-NEXT: vle16.v v8, (a0), v0.t
419414
; CHECK-NEXT: ret
420415
%load = call <vscale x 4 x half> @llvm.experimental.vp.strided.load.nxv4f16.p0.i32(ptr %ptr, i32 2, <vscale x 4 x i1> %m, i32 %evl)
421416
ret <vscale x 4 x half> %load
@@ -460,9 +455,8 @@ define <vscale x 2 x float> @strided_vpload_nxv2f32(ptr %ptr, i32 signext %strid
460455
define <vscale x 2 x float> @strided_vpload_nxv2f32_unit_stride(ptr %ptr, <vscale x 2 x i1> %m, i32 zeroext %evl) {
461456
; CHECK-LABEL: strided_vpload_nxv2f32_unit_stride:
462457
; CHECK: # %bb.0:
463-
; CHECK-NEXT: li a2, 4
464458
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
465-
; CHECK-NEXT: vlse32.v v8, (a0), a2, v0.t
459+
; CHECK-NEXT: vle32.v v8, (a0), v0.t
466460
; CHECK-NEXT: ret
467461
%load = call <vscale x 2 x float> @llvm.experimental.vp.strided.load.nxv2f32.p0.i32(ptr %ptr, i32 4, <vscale x 2 x i1> %m, i32 %evl)
468462
ret <vscale x 2 x float> %load
@@ -519,9 +513,8 @@ define <vscale x 1 x double> @strided_vpload_nxv1f64(ptr %ptr, i32 signext %stri
519513
define <vscale x 1 x double> @strided_vpload_nxv1f64_unit_stride(ptr %ptr, <vscale x 1 x i1> %m, i32 zeroext %evl) {
520514
; CHECK-LABEL: strided_vpload_nxv1f64_unit_stride:
521515
; CHECK: # %bb.0:
522-
; CHECK-NEXT: li a2, 8
523516
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
524-
; CHECK-NEXT: vlse64.v v8, (a0), a2, v0.t
517+
; CHECK-NEXT: vle64.v v8, (a0), v0.t
525518
; CHECK-NEXT: ret
526519
%load = call <vscale x 1 x double> @llvm.experimental.vp.strided.load.nxv1f64.p0.i32(ptr %ptr, i32 8, <vscale x 1 x i1> %m, i32 %evl)
527520
ret <vscale x 1 x double> %load

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