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ziuziakowskaziuziakowska
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Update Binutils to 2.44
Upstream binutils now supports the ratified 1.0.0 bitmanip extensions, so we now use upstream and add the unratified extensions in the patch. The updated binutils also contain a fix for generating verilog memory (vmem) files that is useful for OpenTitan. The glob and ELF BFD patches are no longer required for this version of binutils to build correctly so they are removed. Signed-off-by: Alice Ziuziakowska <a.ziuziakowska@lowrisc.org>
1 parent 0c31d90 commit 6d268fa

7 files changed

Lines changed: 345 additions & 507 deletions

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‎local-run-in-container.sh‎

100755100644
File mode changed.

‎patches/binutils/001-bfd-elf.patch‎

Lines changed: 0 additions & 19 deletions
This file was deleted.

‎patches/binutils/001-bitmanip.patch‎

Lines changed: 0 additions & 458 deletions
This file was deleted.

‎patches/binutils/001-glob-libc-config.patch‎

Lines changed: 0 additions & 25 deletions
This file was deleted.

‎patches/binutils/001-unratified-bitmanip.patch‎

Lines changed: 337 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,337 @@
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Add Unratified bitmanip instructions
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Author: James Wainwright <james.wainwright@lowrisc.org>
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diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
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index c9e4b03b17d..b0a8c07ff5c 100644
7+
--- a/bfd/elfxx-riscv.c
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+++ b/bfd/elfxx-riscv.c
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@@ -1381,6 +1381,13 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
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{"zba", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
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{"zbc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
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{"zbs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
13+
+ {"zbs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
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+ {"zbp", ISA_SPEC_CLASS_DRAFT, 0, 93, 0 },
15+
+ {"zbe", ISA_SPEC_CLASS_DRAFT, 0, 93, 0 },
16+
+ {"zbf", ISA_SPEC_CLASS_DRAFT, 0, 93, 0 },
17+
+ {"zbm", ISA_SPEC_CLASS_DRAFT, 0, 93, 0 },
18+
+ {"zbr", ISA_SPEC_CLASS_DRAFT, 0, 93, 0 },
19+
+ {"zbt", ISA_SPEC_CLASS_DRAFT, 0, 93, 0 },
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{"zbkb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
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{"zbkc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
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{"zbkx", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
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@@ -2679,6 +2686,18 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
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return riscv_subset_supports (rps, "zbc");
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case INSN_CLASS_ZBS:
26+
return riscv_subset_supports (rps, "zbs");
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+ case INSN_CLASS_ZBP:
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+ return riscv_subset_supports (rps, "zbp");
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+ case INSN_CLASS_ZBE:
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+ return riscv_subset_supports (rps, "zbe");
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+ case INSN_CLASS_ZBF:
32+
+ return riscv_subset_supports (rps, "zbf");
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+ case INSN_CLASS_ZBM:
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+ return riscv_subset_supports (rps, "zbm");
35+
+ case INSN_CLASS_ZBR:
36+
+ return riscv_subset_supports (rps, "zbr");
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+ case INSN_CLASS_ZBT:
38+
+ return riscv_subset_supports (rps, "zbt");
39+
case INSN_CLASS_ZBKB:
40+
return riscv_subset_supports (rps, "zbkb");
41+
case INSN_CLASS_ZBKC:
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@@ -2997,6 +3016,18 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
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return "zbc";
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case INSN_CLASS_ZBS:
45+
return "zbs";
46+
+ case INSN_CLASS_ZBP:
47+
+ return "zbp";
48+
+ case INSN_CLASS_ZBE:
49+
+ return "zbe";
50+
+ case INSN_CLASS_ZBF:
51+
+ return "zbf";
52+
+ case INSN_CLASS_ZBM:
53+
+ return "zbm";
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+ case INSN_CLASS_ZBR:
55+
+ return "zbr";
56+
+ case INSN_CLASS_ZBT:
57+
+ return "zbt";
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case INSN_CLASS_ZBKB:
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return "zbkb";
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case INSN_CLASS_ZBKC:
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diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
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index 71ad7fff84d..64033885032 100644
63+
--- a/include/opcode/riscv-opc.h
64+
+++ b/include/opcode/riscv-opc.h
65+
@@ -3786,6 +3786,109 @@
66+
#define MASK_SFVFNRCLIPXUFQF 0xfe00707f
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#define MATCH_SFVFNRCLIPXFQF 0x8e00505b
68+
#define MASK_SFVFNRCLIPXFQF 0xfe00707f
69+
+/* Unratified Zbp instructions */
70+
+#define MATCH_PACKU 0x48004033
71+
+#define MASK_PACKU 0xfe00707f
72+
+#define MATCH_PACKUW 0x4800403b
73+
+#define MASK_PACKUW 0xfe00707f
74+
+#define MATCH_GREV 0x68005033
75+
+#define MASK_GREV 0xfe00707f
76+
+#define MATCH_GREVIW 0x68005013
77+
+#define MASK_GREVIW 0xfc00707f
78+
+#define MATCH_GREVW 0x6800503b
79+
+#define MASK_GREVW 0xfe00707f
80+
+#define MATCH_GORC 0x28005033
81+
+#define MASK_GORC 0xfe00707f
82+
+#define MATCH_GORCIW 0x2800501b
83+
+#define MASK_GORCIW 0xfe00707f
84+
+#define MATCH_GORCW 0x2800503b
85+
+#define MASK_GORCW 0xfe00707f
86+
+#define MATCH_SHFL 0x8001033
87+
+#define MASK_SHFL 0xfe00707f
88+
+#define MATCH_SHFLW 0x800103b
89+
+#define MASK_SHFLW 0xfe00707f
90+
+#define MATCH_UNSHFL 0x8005033
91+
+#define MASK_UNSHFL 0xfe00707f
92+
+#define MATCH_UNSHFLW 0x800503b
93+
+#define MASK_UNSHFLW 0xfe00707f
94+
+#define MATCH_XPERM_N 0x28002033
95+
+#define MASK_XPERM_N 0xfe00707f
96+
+#define MATCH_XPERM_B 0x28004033
97+
+#define MASK_XPERM_B 0xfe00707f
98+
+#define MATCH_XPERM_H 0x28006033
99+
+#define MASK_XPERM_H 0xfe00707f
100+
+#define MATCH_XPERM_W 0x28000033
101+
+#define MASK_XPERM_W 0xfe00707f
102+
+/* Unratified Zbs instructions */
103+
+#define MATCH_BSETW 0x2800103b
104+
+#define MASK_BSETW 0xfe00707f
105+
+#define MATCH_BSETIW 0x2800101b
106+
+#define MASK_BSETIW 0xfe00707f
107+
+#define MATCH_BCLRW 0x4800103b
108+
+#define MASK_BCLRW 0xfe00707f
109+
+#define MATCH_BCLRIW 0x4800101b
110+
+#define MASK_BCLRIW 0xfe00707f
111+
+#define MATCH_BEXTW 0x4800503b
112+
+#define MASK_BEXTW 0xfe00707f
113+
+#define MATCH_BINVW 0x6800103b
114+
+#define MASK_BINVW 0xfe00707f
115+
+#define MATCH_BINVIW 0x6800101b
116+
+#define MASK_BINVIW 0xfe00707f
117+
+/* Unratified Zbe instructions */
118+
+#define MATCH_BCOMPRESS 0x8006033
119+
+#define MASK_BCOMPRESS 0xfe00707f
120+
+#define MATCH_BDECOMPRESS 0x48006033
121+
+#define MASK_BDECOMPRESS 0xfe00707f
122+
+#define MATCH_BCOMPRESSW 0x800603b
123+
+#define MASK_BCOMPRESSW 0xfe00707f
124+
+#define MATCH_BDECOMPRESSW 0x4800603b
125+
+#define MASK_BDECOMPRESSW 0xfe00707f
126+
+/* Unratified Zbf instructions */
127+
+#define MATCH_BFP 0x48007033
128+
+#define MASK_BFP 0xfe00707f
129+
+#define MATCH_BFPW 0x4800703b
130+
+#define MASK_BFPW 0xfe00707f
131+
+/* Unratified Zbm instructions */
132+
+#define MATCH_BMATFLIP 0x60301013
133+
+#define MASK_BMATFLIP 0xfff0707f
134+
+#define MATCH_BMATOR 0x8003033
135+
+#define MASK_BMATOR 0xfe00707f
136+
+#define MATCH_BMATXOR 0x48003033
137+
+#define MASK_BMATXOR 0xfe00707f
138+
+/* Unratified Zbr instructions */
139+
+#define MATCH_CRC32_B 0x61001013
140+
+#define MASK_CRC32_B 0xfff0707f
141+
+#define MATCH_CRC32C_B 0x61801013
142+
+#define MASK_CRC32C_B 0xfff0707f
143+
+#define MATCH_CRC32_H 0x61101013
144+
+#define MASK_CRC32_H 0xfff0707f
145+
+#define MATCH_CRC32C_H 0x61901013
146+
+#define MASK_CRC32C_H 0xfff0707f
147+
+#define MATCH_CRC32_W 0x61201013
148+
+#define MASK_CRC32_W 0xfff0707f
149+
+#define MATCH_CRC32C_W 0x61a01013
150+
+#define MASK_CRC32C_W 0xfff0707f
151+
+#define MATCH_CRC32_D 0x61301013
152+
+#define MASK_CRC32_D 0xfff0707f
153+
+#define MATCH_CRC32C_D 0x61b01013
154+
+#define MASK_CRC32C_D 0xfff0707f
155+
+/* Unratified Zbt instructions */
156+
+#define MATCH_CMIX 0x6001033
157+
+#define MASK_CMIX 0x600707f
158+
+#define MATCH_CMOV 0x6005033
159+
+#define MASK_CMOV 0x600707f
160+
+#define MATCH_FSL 0x4001033
161+
+#define MASK_FSL 0x600707f
162+
+#define MATCH_FSLW 0x400103b
163+
+#define MASK_FSLW 0x600707f
164+
+#define MATCH_FSR 0x4005033
165+
+#define MASK_FSR 0x600707f
166+
+#define MATCH_FSRI 0x4005013
167+
+#define MASK_FSRI 0x400707f
168+
+#define MATCH_FSRW 0x400503b
169+
+#define MASK_FSRW 0x600707f
170+
+#define MATCH_FSRIW 0x400501b
171+
+#define MASK_FSRIW 0x600707f
172+
/* Unprivileged Counter/Timers CSR addresses. */
173+
#define CSR_CYCLE 0xc00
174+
#define CSR_TIME 0xc01
175+
@@ -4923,6 +5026,61 @@ DECLARE_INSN(ssamoswap_w, MATCH_SSAMOSWAP_W, MASK_SSAMOSWAP_W)
176+
DECLARE_INSN(ssamoswap_d, MATCH_SSAMOSWAP_D, MASK_SSAMOSWAP_D)
177+
/* Zicfilp instructions. */
178+
DECLARE_INSN(lpad, MATCH_LPAD, MASK_LPAD)
179+
+/* Unratified Zbp instructions */
180+
+DECLARE_INSN(packu, MATCH_PACKU, MASK_PACKU)
181+
+DECLARE_INSN(packuw, MATCH_PACKUW, MASK_PACKUW)
182+
+DECLARE_INSN(grev, MATCH_GREV, MASK_GREV)
183+
+DECLARE_INSN(greviw, MATCH_GREVIW, MASK_GREVIW)
184+
+DECLARE_INSN(grevw, MATCH_GREVW, MASK_GREVW)
185+
+DECLARE_INSN(gorc, MATCH_GORC, MASK_GORC)
186+
+DECLARE_INSN(gorciw, MATCH_GORCIW, MASK_GORCIW)
187+
+DECLARE_INSN(gorcw, MATCH_GORCW, MASK_GORCW)
188+
+DECLARE_INSN(shfl, MATCH_SHFL, MASK_SHFL)
189+
+DECLARE_INSN(shflw, MATCH_SHFLW, MASK_SHFLW)
190+
+DECLARE_INSN(unshfl, MATCH_UNSHFL, MASK_UNSHFL)
191+
+DECLARE_INSN(unshflw, MATCH_UNSHFLW, MASK_UNSHFLW)
192+
+DECLARE_INSN(xperm_n, MATCH_XPERM_N, MASK_XPERM_N)
193+
+DECLARE_INSN(xperm_b, MATCH_XPERM_B, MASK_XPERM_B)
194+
+DECLARE_INSN(xperm_h, MATCH_XPERM_H, MASK_XPERM_H)
195+
+DECLARE_INSN(xperm_w, MATCH_XPERM_W, MASK_XPERM_W)
196+
+/* Unratified Zbs instructions */
197+
+DECLARE_INSN(bsetw, MATCH_BSETW, MASK_BSETW)
198+
+DECLARE_INSN(bsetiw, MATCH_BSETIW, MASK_BSETIW)
199+
+DECLARE_INSN(bclrw, MATCH_BCLRW, MASK_BCLRW)
200+
+DECLARE_INSN(bclriw, MATCH_BCLRIW, MASK_BCLRIW)
201+
+DECLARE_INSN(bextw, MATCH_BEXTW, MASK_BEXTW)
202+
+DECLARE_INSN(binvw, MATCH_BINVW, MASK_BINVW)
203+
+DECLARE_INSN(binviw, MATCH_BINVIW, MASK_BINVIW)
204+
+/* Unratified Zbe instructions */
205+
+DECLARE_INSN(bcompress, MATCH_BCOMPRESS, MASK_BCOMPRESS)
206+
+DECLARE_INSN(bdecompress, MATCH_BDECOMPRESS, MASK_BDECOMPRESS)
207+
+DECLARE_INSN(bcompressw, MATCH_BCOMPRESSW, MASK_BCOMPRESSW)
208+
+DECLARE_INSN(bdecompressw, MATCH_BDECOMPRESSW, MASK_BDECOMPRESSW)
209+
+/* Unratified Zbf instructions */
210+
+DECLARE_INSN(bfp, MATCH_BFP, MASK_BFP)
211+
+DECLARE_INSN(bfpw, MATCH_BFPW, MASK_BFPW)
212+
+/* Unratified Zbm instructions */
213+
+DECLARE_INSN(bmatflip, MATCH_BMATFLIP, MASK_BMATFLIP)
214+
+DECLARE_INSN(bmator, MATCH_BMATOR, MASK_BMATOR)
215+
+DECLARE_INSN(bmatxor, MATCH_BMATXOR, MASK_BMATXOR)
216+
+/* Unratified Zbr instructions */
217+
+DECLARE_INSN(crc32_b, MATCH_CRC32_B, MASK_CRC32_B)
218+
+DECLARE_INSN(crc32c_b, MATCH_CRC32C_B, MASK_CRC32C_B)
219+
+DECLARE_INSN(crc32_h, MATCH_CRC32_H, MASK_CRC32_H)
220+
+DECLARE_INSN(crc32c_h, MATCH_CRC32C_H, MASK_CRC32C_H)
221+
+DECLARE_INSN(crc32_w, MATCH_CRC32_W, MASK_CRC32_W)
222+
+DECLARE_INSN(crc32c_w, MATCH_CRC32C_W, MASK_CRC32C_W)
223+
+DECLARE_INSN(crc32_d, MATCH_CRC32_D, MASK_CRC32_D)
224+
+DECLARE_INSN(crc32c_d, MATCH_CRC32C_D, MASK_CRC32C_D)
225+
+/* Unratified Zbt instructions */
226+
+DECLARE_INSN(cmix, MATCH_CMIX, MASK_CMIX)
227+
+DECLARE_INSN(cmov, MATCH_CMOV, MASK_CMOV)
228+
+DECLARE_INSN(fsl, MATCH_FSL, MASK_FSL)
229+
+DECLARE_INSN(fslw, MATCH_FSLW, MASK_FSLW)
230+
+DECLARE_INSN(fsr, MATCH_FSR, MASK_FSR)
231+
+DECLARE_INSN(fsri, MATCH_FSRI, MASK_FSRI)
232+
+DECLARE_INSN(fsrw, MATCH_FSRW, MASK_FSRW)
233+
+DECLARE_INSN(fsriw, MATCH_FSRIW, MASK_FSRIW)
234+
#endif /* DECLARE_INSN */
235+
#ifdef DECLARE_CSR
236+
/* Unprivileged Counter/Timers CSRs. */
237+
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
238+
index 6bcea638025..24916f1a4d8 100644
239+
--- a/include/opcode/riscv.h
240+
+++ b/include/opcode/riscv.h
241+
@@ -492,6 +492,12 @@ enum riscv_insn_class
242+
INSN_CLASS_ZBB,
243+
INSN_CLASS_ZBC,
244+
INSN_CLASS_ZBS,
245+
+ INSN_CLASS_ZBP,
246+
+ INSN_CLASS_ZBE,
247+
+ INSN_CLASS_ZBF,
248+
+ INSN_CLASS_ZBM,
249+
+ INSN_CLASS_ZBR,
250+
+ INSN_CLASS_ZBT,
251+
INSN_CLASS_ZBKB,
252+
INSN_CLASS_ZBKC,
253+
INSN_CLASS_ZBKX,
254+
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
255+
index ceb94a563e2..4a6cf65a08d 100644
256+
--- a/opcodes/riscv-opc.c
257+
+++ b/opcodes/riscv-opc.c
258+
@@ -3510,6 +3510,79 @@ const struct riscv_opcode riscv_opcodes[] =
259+
{"sf.vfnrclip.xu.f.qf", 0, INSN_CLASS_XSFVFNRCLIPXFQF, "Vd,Vt,S", MATCH_SFVFNRCLIPXUFQF, MASK_SFVFNRCLIPXUFQF, match_opcode, 0},
260+
{"sf.vfnrclip.x.f.qf", 0, INSN_CLASS_XSFVFNRCLIPXFQF, "Vd,Vt,S", MATCH_SFVFNRCLIPXFQF, MASK_SFVFNRCLIPXFQF, match_opcode, 0},
261+
262+
+/* Unratified Zbp instructions */
263+
+{"packu", 0, INSN_CLASS_ZBP, "d,s,t", MATCH_PACKU, MASK_PACKU, match_opcode, 0 },
264+
+{"packuw", 64, INSN_CLASS_ZBP, "d,s,t", MATCH_PACKUW, MASK_PACKUW, match_opcode, 0 },
265+
+{"grev", 0, INSN_CLASS_ZBP, "d,s,t", MATCH_GREV, MASK_GREV, match_opcode, 0 },
266+
+{"grev", 0, INSN_CLASS_ZBP, "d,s,>", MATCH_GREVI, MASK_GREVI, match_opcode, INSN_ALIAS },
267+
+{"greviw", 64, INSN_CLASS_ZBP, "d,s,<", MATCH_GREVIW, MASK_GREVIW, match_opcode, 0 },
268+
+{"grevw", 64, INSN_CLASS_ZBP, "d,s,t", MATCH_GREVW, MASK_GREVW, match_opcode, 0 },
269+
+{"grevw", 64, INSN_CLASS_ZBP, "d,s,<", MATCH_GREVIW, MASK_GREVIW, match_opcode, INSN_ALIAS },
270+
+{"gorc", 0, INSN_CLASS_ZBP, "d,s,t", MATCH_GORC, MASK_GORC, match_opcode, 0 },
271+
+{"gorc", 0, INSN_CLASS_ZBP, "d,s,>", MATCH_GORCI, MASK_GORCI, match_opcode, INSN_ALIAS },
272+
+{"gorciw", 64, INSN_CLASS_ZBP, "d,s,<", MATCH_GORCIW, MASK_GORCIW, match_opcode, 0 },
273+
+{"gorcw", 64, INSN_CLASS_ZBP, "d,s,t", MATCH_GORCW, MASK_GORCW, match_opcode, 0 },
274+
+{"gorcw", 64, INSN_CLASS_ZBP, "d,s,<", MATCH_GORCIW, MASK_GORCIW, match_opcode, INSN_ALIAS },
275+
+{"shfl", 0, INSN_CLASS_ZBP, "d,s,t", MATCH_SHFL, MASK_SHFL, match_opcode, 0 },
276+
+{"shfl", 0, INSN_CLASS_ZBP, "d,s,|", MATCH_SHFLI, MASK_SHFLI, match_opcode, INSN_ALIAS },
277+
+{"shflw", 64, INSN_CLASS_ZBP, "d,s,t", MATCH_SHFLW, MASK_SHFLW, match_opcode, 0 },
278+
+{"unshfl", 0, INSN_CLASS_ZBP, "d,s,t", MATCH_UNSHFL, MASK_UNSHFL, match_opcode, 0 },
279+
+{"unshfl", 0, INSN_CLASS_ZBP, "d,s,|", MATCH_UNSHFLI, MASK_UNSHFLI, match_opcode, INSN_ALIAS },
280+
+{"unshflw", 64, INSN_CLASS_ZBP, "d,s,t", MATCH_UNSHFLW, MASK_UNSHFLW, match_opcode, 0 },
281+
+{"xperm.n", 0, INSN_CLASS_ZBP, "d,s,t", MATCH_XPERM_N, MASK_XPERM_N, match_opcode, 0 },
282+
+{"xperm.b", 0, INSN_CLASS_ZBP, "d,s,t", MATCH_XPERM_B, MASK_XPERM_B, match_opcode, 0 },
283+
+{"xperm.h", 0, INSN_CLASS_ZBP, "d,s,t", MATCH_XPERM_H, MASK_XPERM_H, match_opcode, 0 },
284+
+{"xperm.w", 64, INSN_CLASS_ZBP, "d,s,t", MATCH_XPERM_W, MASK_XPERM_W, match_opcode, 0 },
285+
+
286+
+/* Unratified Zbs instructions */
287+
+{"bsetw", 64, INSN_CLASS_ZBS, "d,s,t", MATCH_BSETW, MASK_BSETW, match_opcode, 0 },
288+
+{"bsetw", 64, INSN_CLASS_ZBS, "d,s,<", MATCH_BSETIW, MASK_BSETIW, match_opcode, INSN_ALIAS },
289+
+{"bsetiw", 64, INSN_CLASS_ZBS, "d,s,<", MATCH_BSETIW, MASK_BSETIW, match_opcode, 0 },
290+
+{"bclrw", 64, INSN_CLASS_ZBS, "d,s,t", MATCH_BCLRW, MASK_BCLRW, match_opcode, 0 },
291+
+{"bclrw", 64, INSN_CLASS_ZBS, "d,s,<", MATCH_BCLRIW, MASK_BCLRIW, match_opcode, INSN_ALIAS },
292+
+{"bclriw", 64, INSN_CLASS_ZBS, "d,s,<", MATCH_BCLRIW, MASK_BCLRIW, match_opcode, 0 },
293+
+{"bextw", 64, INSN_CLASS_ZBS, "d,s,t", MATCH_BEXTW, MASK_BEXTW, match_opcode, 0 },
294+
+{"binvw", 64, INSN_CLASS_ZBS, "d,s,t", MATCH_BINVW, MASK_BINVW, match_opcode, 0 },
295+
+{"binvw", 64, INSN_CLASS_ZBS, "d,s,<", MATCH_BINVIW, MASK_BINVIW, match_opcode, INSN_ALIAS },
296+
+{"binviw", 64, INSN_CLASS_ZBS, "d,s,<", MATCH_BINVIW, MASK_BINVIW, match_opcode, 0 },
297+
+
298+
+/* Unratified Zbe instructions */
299+
+{"bcompress", 0, INSN_CLASS_ZBE, "d,s,t", MATCH_BCOMPRESS, MASK_BCOMPRESS, match_opcode, 0 },
300+
+{"bdecompress", 0, INSN_CLASS_ZBE, "d,s,t", MATCH_BDECOMPRESS, MASK_BDECOMPRESS, match_opcode, 0 },
301+
+{"bcompressw", 64, INSN_CLASS_ZBE, "d,s,t", MATCH_BCOMPRESSW, MASK_BCOMPRESSW, match_opcode, 0 },
302+
+{"bdecompressw", 64, INSN_CLASS_ZBE, "d,s,t", MATCH_BDECOMPRESSW, MASK_BDECOMPRESSW, match_opcode, 0 },
303+
+
304+
+/* Unratified Zbf instructions */
305+
+{"bfp", 0, INSN_CLASS_ZBF, "d,s,t", MATCH_BFP, MASK_BFP, match_opcode, 0 },
306+
+{"bfpw", 64, INSN_CLASS_ZBF, "d,s,t", MATCH_BFPW, MASK_BFPW, match_opcode, 0 },
307+
+
308+
+/* Unratified Zbm instructions */
309+
+{"bmatflip", 64, INSN_CLASS_ZBM, "d,s", MATCH_BMATFLIP, MASK_BMATFLIP, match_opcode, 0 },
310+
+{"bmator", 64, INSN_CLASS_ZBM, "d,s,t", MATCH_BMATOR, MASK_BMATOR, match_opcode, 0 },
311+
+{"bmatxor", 64, INSN_CLASS_ZBM, "d,s,t", MATCH_BMATXOR, MASK_BMATXOR, match_opcode, 0 },
312+
+
313+
+/* Unratified Zbr instructions */
314+
+{"crc32.b", 0, INSN_CLASS_ZBR, "d,s", MATCH_CRC32_B, MASK_CRC32_B, match_opcode, 0 },
315+
+{"crc32.h", 0, INSN_CLASS_ZBR, "d,s", MATCH_CRC32_H, MASK_CRC32_H, match_opcode, 0 },
316+
+{"crc32.w", 0, INSN_CLASS_ZBR, "d,s", MATCH_CRC32_W, MASK_CRC32_W, match_opcode, 0 },
317+
+{"crc32.d", 64, INSN_CLASS_ZBR, "d,s", MATCH_CRC32_D, MASK_CRC32_D, match_opcode, 0 },
318+
+{"crc32c.b", 0, INSN_CLASS_ZBR, "d,s", MATCH_CRC32C_B, MASK_CRC32C_B, match_opcode, 0 },
319+
+{"crc32c.h", 0, INSN_CLASS_ZBR, "d,s", MATCH_CRC32C_H, MASK_CRC32C_H, match_opcode, 0 },
320+
+{"crc32c.w", 0, INSN_CLASS_ZBR, "d,s", MATCH_CRC32C_W, MASK_CRC32C_W, match_opcode, 0 },
321+
+{"crc32c.d", 64, INSN_CLASS_ZBR, "d,s", MATCH_CRC32C_D, MASK_CRC32C_D, match_opcode, 0 },
322+
+
323+
+/* Unratified Zbt instructions */
324+
+{"cmix", 0, INSN_CLASS_ZBT, "d,t,s,r", MATCH_CMIX, MASK_CMIX, match_opcode, 0 },
325+
+{"cmov", 0, INSN_CLASS_ZBT, "d,t,s,r", MATCH_CMOV, MASK_CMOV, match_opcode, 0 },
326+
+{"fsl", 0, INSN_CLASS_ZBT, "d,s,r,t", MATCH_FSL, MASK_FSL, match_opcode, 0 },
327+
+{"fslw", 64, INSN_CLASS_ZBT, "d,s,r,t", MATCH_FSLW, MASK_FSLW, match_opcode, 0 },
328+
+{"fsr", 0, INSN_CLASS_ZBT, "d,s,r,t", MATCH_FSR, MASK_FSR, match_opcode, 0 },
329+
+{"fsr", 0, INSN_CLASS_ZBT, "d,s,r,>", MATCH_FSRI, MASK_FSRI, match_opcode, INSN_ALIAS },
330+
+{"fsri", 0, INSN_CLASS_ZBT, "d,s,r,>", MATCH_FSRI, MASK_FSRI, match_opcode, 0 },
331+
+{"fsrw", 64, INSN_CLASS_ZBT, "d,s,r,t", MATCH_FSRW, MASK_FSRW, match_opcode, 0 },
332+
+{"fsrw", 64, INSN_CLASS_ZBT, "d,s,r,<", MATCH_FSRIW, MASK_FSRIW, match_opcode, INSN_ALIAS },
333+
+{"fsriw", 64, INSN_CLASS_ZBT, "d,s,r,<", MATCH_FSRIW, MASK_FSRIW, match_opcode, 0 },
334+
+
335+
/* Terminate the list. */
336+
{0, 0, INSN_CLASS_NONE, 0, 0, 0, 0, 0}
337+
};

‎prepare-host.sh‎

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -31,4 +31,6 @@ dnf install -y \
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zlib-devel \
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zlib-static \
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libffi-devel \
34-
expat-static
34+
expat-static \
35+
gmp-devel \
36+
mpfr-devel

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