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[dv] Add co-simulation framework
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‎dv/cosim/cosim.core‎

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CAPI=2:
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# Copyright lowRISC contributors.
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# Licensed under the Apache License, Version 2.0, see LICENSE for details.
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# SPDX-License-Identifier: Apache-2.0
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name: "lowrisc:dv:cosim"
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description: "Co-simulator framework"
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filesets:
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files_cpp:
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files:
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- cosim.h: { is_include_file: true }
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- spike_cosim.cc
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- spike_cosim.h: { is_include_file: true }
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file_type: cppSource
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targets:
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default:
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filesets:
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- files_cpp

‎dv/cosim/cosim.h‎

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// Copyright lowRISC contributors.
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// Licensed under the Apache License, Version 2.0, see LICENSE for details.
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// SPDX-License-Identifier: Apache-2.0
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#include <string>
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#include <vector>
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#ifndef COSIM_H_
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#define COSIM_H_
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// Information about a dside transaction observed on the DUT memory interface
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struct DSideAccessInfo {
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// set when the access is a store, in which case `data` is the store data from
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// the DUT. Otherwise `data` is the load data provided to the DUT.
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bool store;
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// `addr` is the address and must be 32-bit aligned. `data` and `be` are
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// aligned to the address. For example an 8-bit store of 0xff to 0x12 has
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// `data` as 0x00ff0000, `addr` as 0x10 and `be` as 0b0100.
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uint32_t data;
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uint32_t addr;
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uint32_t be;
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// set if an error response to the transaction is seen.
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bool error;
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// `misaligned_first` and `misaligned_second` are set when the transaction is
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// generated for a misaligned store or load instruction. `misaligned_first`
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// is true when the transaction is for the lower half and `misaligned_second`
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// is true when the transaction is for the upper half, if it exists.
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//
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// For example an unaligned 32-bit load to 0x3 produces a transaction with
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// `addr` as 0x0 and `misaligned_first` set to true, then a transaction with
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// `addr` as 0x4 and `misaligned_second` set to true. An unaligned 16-bit load
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// to 0x01 only produces a transaction with `addr` as 0x0 and
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// `misaligned_first` set to true, there is no second half.
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bool misaligned_first;
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bool misaligned_second;
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};
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class Cosim {
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public:
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virtual ~Cosim() {}
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// Add a memory to the co-simulator environment.
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//
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// Use `backdoor_write_mem`/`backdoor_read_mem` to access it from the
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// simulation environment.
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virtual void add_memory(uint32_t base_addr, size_t size) = 0;
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// Write bytes to co-simulator memory.
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//
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// returns false if write fails (e.g. because no memory exists at the bytes
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// being written).
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virtual bool backdoor_write_mem(uint32_t addr, size_t len,
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const uint8_t *data_in) = 0;
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// Read bytes from co-simulator memory.
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//
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// returns false if read fails (e.g. because no memory exists at the bytes
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// being read).
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virtual bool backdoor_read_mem(uint32_t addr, size_t len,
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uint8_t *data_out) = 0;
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// Step the co-simulator, checking register write and PC of executed
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// instruction match the supplied values. `write_reg` gives the index of the
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// written register along with `write_reg_data` which provides the data. A
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// `write_reg` of 0 indicates no register write occurred.
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//
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// `sync_trap` is set to true when the instruction caused a synchronous trap.
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// In this case the instruction doesn't retire so no register write occurs (so
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// `write_reg` must be 0).
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//
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// Returns false if there are any errors; use `get_errors` to obtain details
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virtual bool step(uint32_t write_reg, uint32_t write_reg_data, uint32_t pc,
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bool sync_trap) = 0;
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// When more than one of `set_mip`, `set_nmi` or `set_debug_req` is called
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// before `step` which one takes effect is chosen by the co-simulator. Which
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// should take priority is architecturally defined by the RISC-V
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// specification.
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// Set the value of MIP.
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//
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// At the next call of `step`, the MIP value will take effect (i.e. if it's a
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// new interrupt that is enabled it will step straight to that handler).
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virtual void set_mip(uint32_t mip) = 0;
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// Set the state of the NMI (non-maskable interrupt) line.
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//
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// The NMI signal is a level triggered interrupt. When the NMI is taken the
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// CPU ignores the NMI line until an `mret` instruction is executed. If the
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// NMI is high following the `mret` (regardless of whether it has been low or
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// not whilst the first NMI is being handled) a new NMI is taken.
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//
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// When an NMI is due to be taken that will occur at the next call of `step`.
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virtual void set_nmi(bool nmi) = 0;
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// Set the debug request.
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//
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// When set to true the core will enter debug mode at the next step
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virtual void set_debug_req(bool debug_req) = 0;
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// Set the value of mcycle.
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//
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// The co-simulation model doesn't alter the value of mcycle itself (other
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// than instructions that do a direct CSR write). mcycle should be set to the
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// correct value before any `step` call that may execute an instruction that
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// observes the value of mcycle.
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//
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// A full 64-bit value is provided setting both the mcycle and mcycleh CSRs.
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virtual void set_mcycle(uint64_t mcycle) = 0;
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// Tell the co-simulation model about observed transactions on the dside
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// memory interface of the DUT. Accesses are notified once the response to a
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// transaction is seen.
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//
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// Observed transactions for the DUT are checked against accesses from the
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// co-simulation model when a memory access occurs during a `step`. If there
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// is a mismatch an error is reported which can be obtained via `get_errors`.
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virtual void notify_dside_access(const DSideAccessInfo &access_info) = 0;
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// Tell the co-simulation model about an error response to an iside fetch.
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//
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// `addr` must be 32-bit aligned.
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//
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// The next step following a call to `set_iside_error` must produce an
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// instruction fault at the given address.
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virtual void set_iside_error(uint32_t addr) = 0;
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// Get a vector of strings describing errors that have occurred during `step`
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virtual const std::vector<std::string> &get_errors() = 0;
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// Clear internal vector of error descriptions
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virtual void clear_errors() = 0;
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};
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#endif // COSIM_H_

‎dv/cosim/cosim_dpi.cc‎

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// Copyright lowRISC contributors.
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// Licensed under the Apache License, Version 2.0, see LICENSE for details.
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// SPDX-License-Identifier: Apache-2.0
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#include <svdpi.h>
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#include <cassert>
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#include "cosim.h"
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#include "cosim_dpi.h"
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int riscv_cosim_step(Cosim *cosim, const svBitVecVal *write_reg,
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const svBitVecVal *write_reg_data, const svBitVecVal *pc,
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svBit sync_trap) {
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assert(cosim);
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return cosim->step(write_reg[0], write_reg_data[0], pc[0], sync_trap) ? 1 : 0;
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}
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void riscv_cosim_set_mip(Cosim *cosim, const svBitVecVal *mip) {
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assert(cosim);
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cosim->set_mip(mip[0]);
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}
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void riscv_cosim_set_nmi(Cosim *cosim, svBit nmi) {
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assert(cosim);
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cosim->set_nmi(nmi);
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}
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void riscv_cosim_set_debug_req(Cosim *cosim, svBit debug_req) {
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assert(cosim);
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cosim->set_debug_req(debug_req);
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}
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void riscv_cosim_set_mcycle(Cosim *cosim, svBitVecVal *mcycle) {
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assert(cosim);
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uint64_t mcycle_full = mcycle[0] | (uint64_t)mcycle[1] << 32;
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cosim->set_mcycle(mcycle_full);
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}
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void riscv_cosim_notify_dside_access(Cosim *cosim, svBit store,
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svBitVecVal *addr, svBitVecVal *data,
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svBitVecVal *be, svBit error,
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svBit misaligned_first,
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svBit misaligned_second) {
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assert(cosim);
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cosim->notify_dside_access(
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DSideAccessInfo{.store = store,
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.data = data[0],
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.addr = addr[0],
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.be = be[0],
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.error = error,
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.misaligned_first = misaligned_first,
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.misaligned_second = misaligned_second});
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}
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void riscv_cosim_set_iside_error(Cosim *cosim, svBitVecVal *addr) {
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assert(cosim);
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cosim->set_iside_error(addr[0]);
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}
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int riscv_cosim_get_num_errors(Cosim *cosim) {
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assert(cosim);
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return cosim->get_errors().size();
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}
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const char *riscv_cosim_get_error(Cosim *cosim, int index) {
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assert(cosim);
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if (index >= cosim->get_errors().size()) {
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return nullptr;
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}
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return cosim->get_errors()[index].c_str();
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}
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void riscv_cosim_clear_errors(Cosim *cosim) {
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assert(cosim);
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cosim->clear_errors();
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}
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void riscv_cosim_write_mem_byte(Cosim *cosim, const svBitVecVal *addr,
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const svBitVecVal *d) {
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assert(cosim);
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uint8_t byte = d[0] & 0xff;
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cosim->backdoor_write_mem(addr[0], 1, &byte);
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}

‎dv/cosim/cosim_dpi.core‎

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CAPI=2:
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# Copyright lowRISC contributors.
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# Licensed under the Apache License, Version 2.0, see LICENSE for details.
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# SPDX-License-Identifier: Apache-2.0
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name: "lowrisc:dv:cosim_dpi"
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description: "DPI wrapper for Co-simulator framework"
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filesets:
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files_cpp:
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depend:
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- lowrisc:dv:cosim
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files:
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- cosim_dpi.cc: { file_type: cppSource }
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- cosim_dpi.h: { file_type: cppSource, is_include_file: true }
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- cosim_dpi.svh: {file_type: systemVerilogSource }
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targets:
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default:
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filesets:
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- files_cpp

‎dv/cosim/cosim_dpi.h‎

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// Copyright lowRISC contributors.
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// Licensed under the Apache License, Version 2.0, see LICENSE for details.
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// SPDX-License-Identifier: Apache-2.0
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#ifndef COSIM_DPI_H_
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#define COSIM_DPI_H_
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#include <stdint.h>
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#include <svdpi.h>
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// This adapts the C++ interface of the `Cosim` class to be used via DPI. See
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// the documentation in cosim.h for further details
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extern "C" {
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int riscv_cosim_step(Cosim *cosim, const svBitVecVal *write_reg,
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const svBitVecVal *write_reg_data, const svBitVecVal *pc,
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svBit sync_trap);
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void riscv_cosim_set_mip(Cosim *cosim, const svBitVecVal *mip);
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void riscv_cosim_set_nmi(Cosim *cosim, svBit nmi);
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void riscv_cosim_set_debug_req(Cosim *cosim, svBit debug_req);
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void riscv_cosim_set_mcycle(Cosim *cosim, svBitVecVal *mcycle);
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void riscv_cosim_notify_dside_access(Cosim *cosim, svBit store,
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svBitVecVal *addr, svBitVecVal *data,
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svBitVecVal *be, svBit error,
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svBit misaligned_first,
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svBit misaligned_second);
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void riscv_cosim_set_iside_error(Cosim *cosim, svBitVecVal *addr);
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int riscv_cosim_get_num_errors(Cosim *cosim);
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const char *riscv_cosim_get_error(Cosim *cosim, int index);
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void riscv_cosim_clear_errors(Cosim *cosim);
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void riscv_cosim_write_mem_byte(Cosim *cosim, const svBitVecVal *addr,
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const svBitVecVal *d);
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}
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#endif // COSIM_DPI_H_

‎dv/cosim/cosim_dpi.svh‎

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// Copyright lowRISC contributors.
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// Licensed under the Apache License, Version 2.0, see LICENSE for details.
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// SPDX-License-Identifier: Apache-2.0
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// DPI interface to co-simulation model, see `cosim.h` for the interface description.
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// Implemented as a header file as VCS needs `import` declarations included in each verilog file
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// that uses them.
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import "DPI-C" function int riscv_cosim_step(chandle cosim_handle, bit [4:0] write_reg,
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bit [31:0] write_reg_data, bit [31:0] pc, bit sync_trap);
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import "DPI-C" function void riscv_cosim_set_mip(chandle cosim_handle, bit [31:0] mip);
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import "DPI-C" function void riscv_cosim_set_nmi(chandle cosim_handle, bit nmi);
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import "DPI-C" function void riscv_cosim_set_debug_req(chandle cosim_handle, bit debug_req);
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import "DPI-C" function void riscv_cosim_set_mcycle(chandle cosim_handle, bit [63:0] mcycle);
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import "DPI-C" function void riscv_cosim_notify_dside_access(chandle cosim_handle, bit store,
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bit [31:0] addr, bit [31:0] data, bit [3:0] be, bit error, bit misaligned_first,
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bit misaligned_second);
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import "DPI-C" function int riscv_cosim_set_iside_error(chandle cosim_handle, bit [31:0] addr);
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import "DPI-C" function int riscv_cosim_get_num_errors(chandle cosim_handle);
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import "DPI-C" function string riscv_cosim_get_error(chandle cosim_handle, int index);
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import "DPI-C" function void riscv_cosim_clear_errors(chandle cosim_handle);
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import "DPI-C" function void riscv_cosim_write_mem_byte(chandle cosim_handle, bit [31:0] addr,
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bit [7:0] d);

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