From 13788ab5a49798842926a90f73b1a42b661adc9e Mon Sep 17 00:00:00 2001 From: Yingwei Zheng Date: Sun, 17 Mar 2024 01:12:40 +0800 Subject: [PATCH 1/2] [InstCombine] Add pre-commit tests for PR85536. NFC. --- .../InstCombine/intrinsic-select.ll | 40 +++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/llvm/test/Transforms/InstCombine/intrinsic-select.ll b/llvm/test/Transforms/InstCombine/intrinsic-select.ll index a203b28bcb82a..abb2eab2d729e 100644 --- a/llvm/test/Transforms/InstCombine/intrinsic-select.ll +++ b/llvm/test/Transforms/InstCombine/intrinsic-select.ll @@ -240,3 +240,43 @@ define i32 @vec_to_scalar_select_vector(<2 x i1> %b) { %c = call i32 @llvm.vector.reduce.add.v2i32(<2 x i32> %s) ret i32 %c } + +define i8 @test_drop_noundef(i1 %cond, i8 %val) { +; CHECK-LABEL: @test_drop_noundef( +; CHECK-NEXT: entry: +; CHECK-NEXT: [[TMP0:%.*]] = call noundef i8 @llvm.smin.i8(i8 [[VAL:%.*]], i8 0) +; CHECK-NEXT: [[RET:%.*]] = select i1 [[COND:%.*]], i8 -1, i8 [[TMP0]] +; CHECK-NEXT: ret i8 [[RET]] +; +entry: + %sel = select i1 %cond, i8 -1, i8 %val + %ret = call noundef i8 @llvm.smin.i8(i8 %sel, i8 0) + ret i8 %ret +} + +define i1 @pr85536(i32 %a) { +; CHECK-LABEL: @pr85536( +; CHECK-NEXT: entry: +; CHECK-NEXT: [[CMP1:%.*]] = icmp ult i32 [[A:%.*]], 31 +; CHECK-NEXT: [[SHL1:%.*]] = shl nsw i32 -1, [[A]] +; CHECK-NEXT: [[ZEXT:%.*]] = zext i32 [[SHL1]] to i64 +; CHECK-NEXT: [[SHL2:%.*]] = shl i64 [[ZEXT]], 48 +; CHECK-NEXT: [[SHR:%.*]] = ashr exact i64 [[SHL2]], 48 +; CHECK-NEXT: [[TMP0:%.*]] = call noundef i64 @llvm.smin.i64(i64 [[SHR]], i64 0) +; CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 65535 +; CHECK-NEXT: [[RET1:%.*]] = icmp eq i64 [[TMP1]], 0 +; CHECK-NEXT: [[RET:%.*]] = and i1 [[CMP1]], [[RET1]] +; CHECK-NEXT: ret i1 [[RET]] +; +entry: + %cmp1 = icmp ugt i32 %a, 30 + %shl1 = shl nsw i32 -1, %a + %zext = zext i32 %shl1 to i64 + %shl2 = shl i64 %zext, 48 + %shr = ashr exact i64 %shl2, 48 + %sel = select i1 %cmp1, i64 -1, i64 %shr + %smin = call noundef i64 @llvm.smin.i64(i64 %sel, i64 0) + %masked = and i64 %smin, 65535 + %ret = icmp eq i64 %masked, 0 + ret i1 %ret +} From caf2a3b2b784b516071a4e9d201467f5a05d167c Mon Sep 17 00:00:00 2001 From: Yingwei Zheng Date: Sun, 17 Mar 2024 01:12:59 +0800 Subject: [PATCH 2/2] [InstCombine] Drop ub-implying attrs and metadata after speculating an instruction --- llvm/lib/Transforms/InstCombine/InstructionCombining.cpp | 1 + llvm/test/Transforms/InstCombine/intrinsic-select.ll | 6 +++--- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp b/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp index edb046defbc1c..5d3e41fb5f29c 100644 --- a/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp +++ b/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp @@ -1650,6 +1650,7 @@ static Value *foldOperationIntoSelectOperand(Instruction &I, SelectInst *SI, Value *NewOp, InstCombiner &IC) { Instruction *Clone = I.clone(); Clone->replaceUsesOfWith(SI, NewOp); + Clone->dropUBImplyingAttrsAndMetadata(); IC.InsertNewInstBefore(Clone, SI->getIterator()); return Clone; } diff --git a/llvm/test/Transforms/InstCombine/intrinsic-select.ll b/llvm/test/Transforms/InstCombine/intrinsic-select.ll index abb2eab2d729e..f37226bbd5b09 100644 --- a/llvm/test/Transforms/InstCombine/intrinsic-select.ll +++ b/llvm/test/Transforms/InstCombine/intrinsic-select.ll @@ -244,7 +244,7 @@ define i32 @vec_to_scalar_select_vector(<2 x i1> %b) { define i8 @test_drop_noundef(i1 %cond, i8 %val) { ; CHECK-LABEL: @test_drop_noundef( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = call noundef i8 @llvm.smin.i8(i8 [[VAL:%.*]], i8 0) +; CHECK-NEXT: [[TMP0:%.*]] = call i8 @llvm.smin.i8(i8 [[VAL:%.*]], i8 0) ; CHECK-NEXT: [[RET:%.*]] = select i1 [[COND:%.*]], i8 -1, i8 [[TMP0]] ; CHECK-NEXT: ret i8 [[RET]] ; @@ -262,10 +262,10 @@ define i1 @pr85536(i32 %a) { ; CHECK-NEXT: [[ZEXT:%.*]] = zext i32 [[SHL1]] to i64 ; CHECK-NEXT: [[SHL2:%.*]] = shl i64 [[ZEXT]], 48 ; CHECK-NEXT: [[SHR:%.*]] = ashr exact i64 [[SHL2]], 48 -; CHECK-NEXT: [[TMP0:%.*]] = call noundef i64 @llvm.smin.i64(i64 [[SHR]], i64 0) +; CHECK-NEXT: [[TMP0:%.*]] = call i64 @llvm.smin.i64(i64 [[SHR]], i64 0) ; CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 65535 ; CHECK-NEXT: [[RET1:%.*]] = icmp eq i64 [[TMP1]], 0 -; CHECK-NEXT: [[RET:%.*]] = and i1 [[CMP1]], [[RET1]] +; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP1]], i1 [[RET1]], i1 false ; CHECK-NEXT: ret i1 [[RET]] ; entry: