Adding isel lowering for Zalasr. Not sure if is matches the psABI yet though

Author: mehnadnerd

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

@@ -19764,6 +19764,14 @@ unsigned RISCVTargetLowering::getCustomCtpopCost(EVT VT,
   return isCtpopFast(VT) ? 0 : 1;
 }
 
+bool RISCVTargetLowering::shouldInsertFencesForAtomic(const Instruction *I) const {
+  if (Subtarget.hasStdExtZalasr()) {
+    return false;
+  } else {
+    return isa<LoadInst>(I) || isa<StoreInst>(I);
+  }
+}
+
 bool RISCVTargetLowering::fallBackToDAGISel(const Instruction &Inst) const {
   // At the moment, the only scalable instruction GISel knows how to lower is
   // ret with scalable argument.

llvm/lib/Target/RISCV/RISCVISelLowering.h

@@ -615,9 +615,8 @@ class RISCVTargetLowering : public TargetLowering {
 
   bool preferZeroCompareBranch() const override { return true; }
 
-  bool shouldInsertFencesForAtomic(const Instruction *I) const override {
-    return isa<LoadInst>(I) || isa<StoreInst>(I);
-  }
+  bool shouldInsertFencesForAtomic(const Instruction *I) const override;
+
   Instruction *emitLeadingFence(IRBuilderBase &Builder, Instruction *Inst,
                                 AtomicOrdering Ord) const override;
   Instruction *emitTrailingFence(IRBuilderBase &Builder, Instruction *Inst,

llvm/lib/Target/RISCV/RISCVInstrInfoA.td

@@ -109,22 +109,63 @@ defm AMOCAS_Q : AMO_rr_aq_rl<0b00101, 0b100, "amocas.q">;
 // Pseudo-instructions and codegen patterns
 //===----------------------------------------------------------------------===//
 
+// An atomic load operation that does not need either acquire or release
+// semantics.
+class relaxed_load<PatFrags base>
+  : PatFrag<(ops node:$ptr), (base node:$ptr)> {
+  let IsAtomic = 1;
+  let IsAtomicOrderingMonotonic = 1;
+}
+
+// A atomic load operation that actually needs acquire semantics.
+class acquiring_load<PatFrags base>
+  : PatFrag<(ops node:$ptr), (base node:$ptr)> {
+  let IsAtomic = 1;
+  let IsAtomicOrderingAcquire = 1;
+}
+
+// An atomic load operation that needs sequential consistency.
+class seq_cst_load<PatFrags base>
+  : PatFrag<(ops node:$ptr), (base node:$ptr)> {
+  let IsAtomic = 1;
+  let IsAtomicOrderingSequentiallyConsistent = 1;
+}
+
+// An atomic store operation that doesn't actually need to be atomic on RISCV.
+class relaxed_store<PatFrag base>
+  : PatFrag<(ops node:$ptr, node:$val), (base node:$val, node:$ptr)> {
+  let IsAtomic = 1;
+  let IsAtomicOrderingMonotonic = 1;
+}
+
+// A store operation that actually needs release semantics.
+class releasing_store<PatFrag base>
+  : PatFrag<(ops node:$ptr, node:$val), (base node:$val, node:$ptr)> {
+  let IsAtomic = 1;
+  let IsAtomicOrderingReleaseOrStronger = 1;
+}
+
+// A store operation that actually needs sequential consistency.
+class seq_cst_store<PatFrag base>
+  : PatFrag<(ops node:$ptr, node:$val), (base node:$val, node:$ptr)> {
+  let IsAtomic = 1;
+  let IsAtomicOrderingSequentiallyConsistent = 1;
+}
+
 // Atomic load/store are available under both +a and +force-atomics.
-// Fences will be inserted for atomic load/stores according to the logic in
-// RISCVTargetLowering::{emitLeadingFence,emitTrailingFence}.
 let Predicates = [HasAtomicLdSt] in {
-  def : LdPat<atomic_load_8,  LB>;
-  def : LdPat<atomic_load_16, LH>;
-  def : LdPat<atomic_load_32, LW>;
+  def : LdPat<relaxed_load<atomic_load_8>,  LB>;
+  def : LdPat<relaxed_load<atomic_load_16>, LH>;
+  def : LdPat<relaxed_load<atomic_load_32>, LW>;
 
-  def : StPat<atomic_store_8,  SB, GPR, XLenVT>;
-  def : StPat<atomic_store_16, SH, GPR, XLenVT>;
-  def : StPat<atomic_store_32, SW, GPR, XLenVT>;
+  def : StPat<relaxed_store<atomic_store_8>,  SB, GPR, XLenVT>;
+  def : StPat<relaxed_store<atomic_store_16>, SH, GPR, XLenVT>;
+  def : StPat<relaxed_store<atomic_store_32>, SW, GPR, XLenVT>;
 }
 
 let Predicates = [HasAtomicLdSt, IsRV64] in {
-  def : LdPat<atomic_load_64, LD, i64>;
-  def : StPat<atomic_store_64, SD, GPR, i64>;
+  def : LdPat<relaxed_load<atomic_load_64>, LD, i64>;
+  def : StPat<relaxed_store<atomic_store_64>, SD, GPR, i64>;
 }
 
 /// AMOs

llvm/lib/Target/RISCV/RISCVInstrInfoZalasr.td

@@ -63,4 +63,36 @@ defm SD_RL : SRL_r_aq_rl<0b011, "sd">;
 // Pseudo-instructions and codegen patterns
 //===----------------------------------------------------------------------===//
 
-// Future work: Work out mapping with leading/trailing fences, &c
+class PatLAQ<SDPatternOperator OpNode, RVInst Inst, ValueType vt = XLenVT>
+    : Pat<(vt (OpNode (vt GPRMemZeroOffset:$rs1))), (Inst GPRMemZeroOffset:$rs1)>;
+
+class PatSRL<SDPatternOperator OpNode, RVInst Inst, ValueType vt = XLenVT>
+    : Pat<(OpNode (vt GPR:$rs2), (vt GPRMemZeroOffset:$rs1)), (Inst GPR:$rs2, GPRMemZeroOffset:$rs1)>;
+
+let Predicates = [HasStdExtZalasr] in {
+  def : PatLAQ<acquiring_load<atomic_load_8>, LB_AQ_AQ>;
+  def : PatLAQ<seq_cst_load<atomic_load_8>, LB_AQ_AQ_RL>;
+
+  def : PatLAQ<acquiring_load<atomic_load_16>, LH_AQ_AQ>;
+  def : PatLAQ<seq_cst_load<atomic_load_16>, LH_AQ_AQ_RL>;
+
+  def : PatLAQ<acquiring_load<atomic_load_32>, LW_AQ_AQ>;
+  def : PatLAQ<seq_cst_load<atomic_load_32>, LW_AQ_AQ_RL>;
+
+  def : PatSRL<releasing_store<atomic_store_8>, SB_RL_RL>;
+  def : PatSRL<seq_cst_store<atomic_store_8>, SB_RL_AQ_RL>;
+
+  def : PatSRL<releasing_store<atomic_store_16>, SH_RL_RL>;
+  def : PatSRL<seq_cst_store<atomic_store_16>, SH_RL_AQ_RL>;
+
+  def : PatSRL<releasing_store<atomic_store_32>, SW_RL_RL>;
+  def : PatSRL<seq_cst_store<atomic_store_32>, SW_RL_AQ_RL>;
+} // Predicates HasStdExtZalasr
+
+let Predicates = [HasStdExtZalasr, IsRV64] in {
+  def : PatLAQ<acquiring_load<atomic_load_64>, LD_AQ_AQ>;
+  def : PatLAQ<seq_cst_load<atomic_load_64>, LD_AQ_AQ_RL>;
+
+  def : PatSRL<releasing_store<atomic_store_64>, SD_RL_RL>;
+  def : PatSRL<seq_cst_store<atomic_store_64>, SD_RL_AQ_RL>;
+} // Predicates HasStdExtZalasr, IsRV64