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[AArch64][FMV] Fix name mangling.
Put features into function version name in increasing priority order. Differential Revision: https://reviews.llvm.org/D150800
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5 files changed

+34
-23
lines changed

5 files changed

+34
-23
lines changed

‎clang/lib/CodeGen/CodeGenModule.cpp‎

Lines changed: 12 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1362,8 +1362,13 @@ static void AppendTargetVersionMangling(const CodeGenModule &CGM,
13621362
if (Attr->isDefaultVersion())
13631363
return;
13641364
Out << "._";
1365+
const TargetInfo &TI = CGM.getTarget();
13651366
llvm::SmallVector<StringRef, 8> Feats;
13661367
Attr->getFeatures(Feats);
1368+
llvm::stable_sort(Feats, [&TI](const StringRef FeatL, const StringRef FeatR) {
1369+
return TI.multiVersionSortPriority(FeatL) <
1370+
TI.multiVersionSortPriority(FeatR);
1371+
});
13671372
for (const auto &Feat : Feats) {
13681373
Out << 'M';
13691374
Out << Feat;
@@ -1415,13 +1420,19 @@ static void AppendTargetClonesMangling(const CodeGenModule &CGM,
14151420
const TargetClonesAttr *Attr,
14161421
unsigned VersionIndex,
14171422
raw_ostream &Out) {
1418-
if (CGM.getTarget().getTriple().isAArch64()) {
1423+
const TargetInfo &TI = CGM.getTarget();
1424+
if (TI.getTriple().isAArch64()) {
14191425
StringRef FeatureStr = Attr->getFeatureStr(VersionIndex);
14201426
if (FeatureStr == "default")
14211427
return;
14221428
Out << "._";
14231429
SmallVector<StringRef, 8> Features;
14241430
FeatureStr.split(Features, "+");
1431+
llvm::stable_sort(Features,
1432+
[&TI](const StringRef FeatL, const StringRef FeatR) {
1433+
return TI.multiVersionSortPriority(FeatL) <
1434+
TI.multiVersionSortPriority(FeatR);
1435+
});
14251436
for (auto &Feat : Features) {
14261437
Out << 'M';
14271438
Out << Feat;

‎clang/test/CodeGen/attr-target-clones-aarch64.c‎

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -32,7 +32,7 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))
3232
// CHECK: @ftc_inline3.ifunc = weak_odr ifunc i32 (), ptr @ftc_inline3.resolver
3333

3434
// CHECK: Function Attrs: noinline nounwind optnone
35-
// CHECK-LABEL: @ftc._MaesMlse(
35+
// CHECK-LABEL: @ftc._MlseMaes(
3636
// CHECK-NEXT: entry:
3737
// CHECK-NEXT: ret i32 0
3838
// CHECK: Function Attrs: noinline nounwind optnone
@@ -52,7 +52,7 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))
5252
// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
5353
// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
5454
// CHECK: resolver_return:
55-
// CHECK-NEXT: ret ptr @ftc._MaesMlse
55+
// CHECK-NEXT: ret ptr @ftc._MlseMaes
5656
// CHECK: resolver_else:
5757
// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
5858
// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 68719476736
@@ -68,7 +68,7 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))
6868
// CHECK-NEXT: entry:
6969
// CHECK-NEXT: ret i32 1
7070
// CHECK: Function Attrs: noinline nounwind optnone
71-
// CHECK-LABEL: @ftc_def._Mmemtag2Msha2(
71+
// CHECK-LABEL: @ftc_def._Msha2Mmemtag2(
7272
// CHECK-NEXT: entry:
7373
// CHECK-NEXT: ret i32 1
7474
// CHECK: Function Attrs: noinline nounwind optnone
@@ -84,7 +84,7 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))
8484
// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
8585
// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
8686
// CHECK: resolver_return:
87-
// CHECK-NEXT: ret ptr @ftc_def._Mmemtag2Msha2
87+
// CHECK-NEXT: ret ptr @ftc_def._Msha2Mmemtag2
8888
// CHECK: resolver_else:
8989
// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
9090
// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 4096
@@ -120,7 +120,7 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))
120120
// CHECK-NEXT: entry:
121121
// CHECK-NEXT: ret i32 3
122122
// CHECK: Function Attrs: noinline nounwind optnone
123-
// CHECK-LABEL: @ftc_dup2._McrcMdotprod(
123+
// CHECK-LABEL: @ftc_dup2._MdotprodMcrc(
124124
// CHECK-NEXT: entry:
125125
// CHECK-NEXT: ret i32 3
126126
// CHECK: Function Attrs: noinline nounwind optnone
@@ -136,7 +136,7 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))
136136
// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
137137
// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
138138
// CHECK: resolver_return:
139-
// CHECK-NEXT: ret ptr @ftc_dup2._McrcMdotprod
139+
// CHECK-NEXT: ret ptr @ftc_dup2._MdotprodMcrc
140140
// CHECK: resolver_else:
141141
// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
142142
// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 256
@@ -192,7 +192,7 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))
192192
// CHECK-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]]
193193
// CHECK-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
194194
// CHECK: resolver_return1:
195-
// CHECK-NEXT: ret ptr @ftc_inline1._MpredresMrcpc
195+
// CHECK-NEXT: ret ptr @ftc_inline1._MrcpcMpredres
196196
// CHECK: resolver_else2:
197197
// CHECK-NEXT: [[TMP8:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
198198
// CHECK-NEXT: [[TMP9:%.*]] = and i64 [[TMP8]], 513
@@ -232,7 +232,7 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))
232232
// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
233233
// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
234234
// CHECK: resolver_return:
235-
// CHECK-NEXT: ret ptr @ftc_inline3._MsbMsve
235+
// CHECK-NEXT: ret ptr @ftc_inline3._MsveMsb
236236
// CHECK: resolver_else:
237237
// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
238238
// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 1125899906842624
@@ -248,7 +248,7 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))
248248
// CHECK-NEXT: entry:
249249
// CHECK-NEXT: ret i32 1
250250
// CHECK: Function Attrs: noinline nounwind optnone
251-
// CHECK-LABEL: @ftc_inline1._MpredresMrcpc(
251+
// CHECK-LABEL: @ftc_inline1._MrcpcMpredres(
252252
// CHECK-NEXT: entry:
253253
// CHECK-NEXT: ret i32 1
254254
// CHECK: Function Attrs: noinline nounwind optnone
@@ -276,7 +276,7 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))
276276
// CHECK-NEXT: entry:
277277
// CHECK-NEXT: ret i32 3
278278
// CHECK: Function Attrs: noinline nounwind optnone
279-
// CHECK-LABEL: @ftc_inline3._MsbMsve(
279+
// CHECK-LABEL: @ftc_inline3._MsveMsb(
280280
// CHECK-NEXT: entry:
281281
// CHECK-NEXT: ret i32 3
282282
// CHECK: Function Attrs: noinline nounwind optnone

‎clang/test/CodeGen/attr-target-version.c‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -119,7 +119,7 @@ int hoo(void) {
119119
// CHECK-LABEL: @fmv(
120120
// CHECK-NEXT: entry:
121121
// CHECK-NEXT: ret i32 0
122-
// CHECK-LABEL: @fmv_one._Mls64Msimd(
122+
// CHECK-LABEL: @fmv_one._MsimdMls64(
123123
// CHECK-NEXT: entry:
124124
// CHECK-NEXT: ret i32 1
125125
// CHECK-LABEL: @fmv_one._Mdpb(
@@ -137,7 +137,7 @@ int hoo(void) {
137137
// CHECK-LABEL: @fmv_two._Mdgh(
138138
// CHECK-NEXT: entry:
139139
// CHECK-NEXT: ret i32 3
140-
// CHECK-LABEL: @fmv_two._Mfp16Msimd(
140+
// CHECK-LABEL: @fmv_two._MsimdMfp16(
141141
// CHECK-NEXT: entry:
142142
// CHECK-NEXT: ret i32 4
143143
// CHECK-LABEL: @fmv_two(
@@ -229,10 +229,10 @@ int hoo(void) {
229229
// CHECK-NEXT: ret ptr @fmv
230230
// CHECK-LABEL: @fmv_one.resolver(
231231
// CHECK-NEXT: resolver_entry:
232-
// CHECK-NEXT: ret ptr @fmv_one._Mls64Msimd
232+
// CHECK-NEXT: ret ptr @fmv_one._MsimdMls64
233233
// CHECK-LABEL: @fmv_two.resolver(
234234
// CHECK-NEXT: resolver_entry:
235-
// CHECK-NEXT: ret ptr @fmv_two._Mfp16Msimd
235+
// CHECK-NEXT: ret ptr @fmv_two._MsimdMfp16
236236
// CHECK-LABEL: @fmv_e(
237237
// CHECK-NEXT: entry:
238238
// CHECK-NEXT: ret i32 20
@@ -262,7 +262,7 @@ int hoo(void) {
262262
// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
263263
// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
264264
// CHECK: resolver_return:
265-
// CHECK-NEXT: ret ptr @fmv_inline._Mfp16MfcmaMsmeMfp16
265+
// CHECK-NEXT: ret ptr @fmv_inline._Mfp16Mfp16MfcmaMsme
266266
// CHECK: resolver_else:
267267
// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
268268
// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 893353197568
@@ -407,7 +407,7 @@ int hoo(void) {
407407
// CHECK-LABEL: @fmv_inline._Msha1MpmullMf64mm(
408408
// CHECK-NEXT: entry:
409409
// CHECK-NEXT: ret i32 1
410-
// CHECK-LABEL: @fmv_inline._Mfp16MfcmaMsmeMfp16(
410+
// CHECK-LABEL: @fmv_inline._Mfp16Mfp16MfcmaMsme(
411411
// CHECK-NEXT: entry:
412412
// CHECK-NEXT: ret i32 2
413413
// CHECK-LABEL: @fmv_inline._Msha3Mi8mmMf32mm(

‎clang/test/CodeGenCXX/attr-target-clones-aarch64.cpp‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -108,7 +108,7 @@ void run_foo_tml() {
108108
// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
109109
// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
110110
// CHECK: resolver_return:
111-
// CHECK-NEXT: ret ptr @_ZN7MyClassIssE7foo_tmlEv._Msme-f64f64Mssbs
111+
// CHECK-NEXT: ret ptr @_ZN7MyClassIssE7foo_tmlEv._MssbsMsme-f64f64
112112
// CHECK: resolver_else:
113113
// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
114114
// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 16777216
@@ -128,7 +128,7 @@ void run_foo_tml() {
128128
// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
129129
// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
130130
// CHECK: resolver_return:
131-
// CHECK-NEXT: ret ptr @_ZN7MyClassIisE7foo_tmlEv._Msme-f64f64Mssbs
131+
// CHECK-NEXT: ret ptr @_ZN7MyClassIisE7foo_tmlEv._MssbsMsme-f64f64
132132
// CHECK: resolver_else:
133133
// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
134134
// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 16777216
@@ -157,7 +157,7 @@ void run_foo_tml() {
157157
// CHECK-NEXT: store ptr [[THIS:%.*]], ptr [[THIS_ADDR]], align 8
158158
// CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
159159
// CHECK-NEXT: ret i32 1
160-
// CHECK-LABEL: @_ZN7MyClassIssE7foo_tmlEv._Msme-f64f64Mssbs(
160+
// CHECK-LABEL: @_ZN7MyClassIssE7foo_tmlEv._MssbsMsme-f64f64(
161161
// CHECK-NEXT: entry:
162162
// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
163163
// CHECK-NEXT: store ptr [[THIS:%.*]], ptr [[THIS_ADDR]], align 8
@@ -175,7 +175,7 @@ void run_foo_tml() {
175175
// CHECK-NEXT: store ptr [[THIS:%.*]], ptr [[THIS_ADDR]], align 8
176176
// CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
177177
// CHECK-NEXT: ret i32 2
178-
// CHECK-LABEL: @_ZN7MyClassIisE7foo_tmlEv._Msme-f64f64Mssbs(
178+
// CHECK-LABEL: @_ZN7MyClassIisE7foo_tmlEv._MssbsMsme-f64f64(
179179
// CHECK-NEXT: entry:
180180
// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
181181
// CHECK-NEXT: store ptr [[THIS:%.*]], ptr [[THIS_ADDR]], align 8

‎clang/test/CodeGenCXX/attr-target-version.cpp‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -27,7 +27,7 @@ int bar() {
2727
// CHECK: @_Z3fooi.ifunc = weak_odr ifunc i32 (i32), ptr @_Z3fooi.resolver
2828
// CHECK: @_Z3foov.ifunc = weak_odr ifunc i32 (), ptr @_Z3foov.resolver
2929

30-
// CHECK-LABEL: @_Z3fooi._Msme-f64f64Mbf16(
30+
// CHECK-LABEL: @_Z3fooi._Mbf16Msme-f64f64(
3131
// CHECK-NEXT: entry:
3232
// CHECK-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4
3333
// CHECK-NEXT: store i32 [[TMP0:%.*]], ptr [[DOTADDR]], align 4
@@ -105,7 +105,7 @@ int bar() {
105105
// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
106106
// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
107107
// CHECK: resolver_return:
108-
// CHECK-NEXT: ret ptr @_Z3fooi._Msme-f64f64Mbf16
108+
// CHECK-NEXT: ret ptr @_Z3fooi._Mbf16Msme-f64f64
109109
// CHECK: resolver_else:
110110
// CHECK-NEXT: ret ptr @_Z3fooi
111111
// CHECK-LABEL: @_Z3foov.resolver(

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