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FantasqueXlanza
FantasqueX
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lanza
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[CIR] Add syncscope to AtomicCmpXchgOp (#1419)
I noticed that `AtomicFenceOp` doesn't use `OptionalAttr` like mlir llvmir. As a result, `getLLVMSyncScope` does't return `std::optional`. Should I use `Arg` instead?
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8 files changed

+74
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lines changed

‎clang/include/clang/CIR/Dialect/IR/CIROps.td‎

Lines changed: 14 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -5518,6 +5518,18 @@ def AtomicXchg : CIR_Op<"atomic.xchg", [AllTypesMatch<["result", "val"]>]> {
55185518
let hasVerifier = 0;
55195519
}
55205520

5521+
def MemScope_SingleThread : I32EnumAttrCase<"MemScope_SingleThread",
5522+
0, "single_thread">;
5523+
def MemScope_System : I32EnumAttrCase<"MemScope_System",
5524+
1, "system">;
5525+
5526+
def MemScopeKind : I32EnumAttr<
5527+
"MemScopeKind",
5528+
"Memory Scope Enumeration",
5529+
[MemScope_SingleThread, MemScope_System]> {
5530+
let cppNamespace = "::cir";
5531+
}
5532+
55215533
def AtomicCmpXchg : CIR_Op<"atomic.cmp_xchg",
55225534
[AllTypesMatch<["old", "expected", "desired"]>]> {
55235535
let summary = "Atomic compare exchange";
@@ -5540,6 +5552,7 @@ def AtomicCmpXchg : CIR_Op<"atomic.cmp_xchg",
55405552
CIR_AnyType:$desired,
55415553
Arg<MemOrder, "success memory order">:$succ_order,
55425554
Arg<MemOrder, "failure memory order">:$fail_order,
5555+
OptionalAttr<MemScopeKind>:$syncscope,
55435556
OptionalAttr<I64Attr>:$alignment,
55445557
UnitAttr:$weak,
55455558
UnitAttr:$is_volatile);
@@ -5552,6 +5565,7 @@ def AtomicCmpXchg : CIR_Op<"atomic.cmp_xchg",
55525565
`success` `=` $succ_order `,`
55535566
`failure` `=` $fail_order
55545567
`)`
5568+
(`syncscope` `(` $syncscope^ `)`)?
55555569
(`align` `(` $alignment^ `)`)?
55565570
(`weak` $weak^)?
55575571
(`volatile` $is_volatile^)?
@@ -5561,18 +5575,6 @@ def AtomicCmpXchg : CIR_Op<"atomic.cmp_xchg",
55615575
let hasVerifier = 0;
55625576
}
55635577

5564-
def MemScope_SingleThread : I32EnumAttrCase<"MemScope_SingleThread",
5565-
0, "single_thread">;
5566-
def MemScope_System : I32EnumAttrCase<"MemScope_System",
5567-
1, "system">;
5568-
5569-
def MemScopeKind : I32EnumAttr<
5570-
"MemScopeKind",
5571-
"Memory Scope Enumeration",
5572-
[MemScope_SingleThread, MemScope_System]> {
5573-
let cppNamespace = "::cir";
5574-
}
5575-
55765578
def AtomicFence : CIR_Op<"atomic.fence"> {
55775579
let summary = "Atomic thread fence";
55785580
let description = [{

‎clang/lib/CIR/CodeGen/CIRGenAtomic.cpp‎

Lines changed: 6 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -415,7 +415,7 @@ static void emitAtomicCmpXchg(CIRGenFunction &CGF, AtomicExpr *E, bool IsWeak,
415415
Address Val2, uint64_t Size,
416416
cir::MemOrder SuccessOrder,
417417
cir::MemOrder FailureOrder,
418-
llvm::SyncScope::ID Scope) {
418+
cir::MemScopeKind Scope) {
419419
auto &builder = CGF.getBuilder();
420420
auto loc = CGF.getLoc(E->getSourceRange());
421421
auto Expected = builder.createLoad(loc, Val1);
@@ -425,6 +425,7 @@ static void emitAtomicCmpXchg(CIRGenFunction &CGF, AtomicExpr *E, bool IsWeak,
425425
loc, Expected.getType(), boolTy, Ptr.getPointer(), Expected, Desired,
426426
cir::MemOrderAttr::get(&CGF.getMLIRContext(), SuccessOrder),
427427
cir::MemOrderAttr::get(&CGF.getMLIRContext(), FailureOrder),
428+
cir::MemScopeKindAttr::get(&CGF.getMLIRContext(), Scope),
428429
builder.getI64IntegerAttr(Ptr.getAlignment().getAsAlign().value()));
429430
cmpxchg.setIsVolatile(E->isVolatile());
430431
cmpxchg.setWeak(IsWeak);
@@ -452,7 +453,7 @@ static void emitAtomicCmpXchg(CIRGenFunction &CGF, AtomicExpr *E, bool IsWeak,
452453
static void emitAtomicCmpXchgFailureSet(
453454
CIRGenFunction &CGF, AtomicExpr *E, bool IsWeak, Address Dest, Address Ptr,
454455
Address Val1, Address Val2, mlir::Value FailureOrderVal, uint64_t Size,
455-
cir::MemOrder SuccessOrder, llvm::SyncScope::ID Scope) {
456+
cir::MemOrder SuccessOrder, cir::MemScopeKind Scope) {
456457

457458
cir::MemOrder FailureOrder;
458459
if (auto ordAttr = getConstOpIntAttr(FailureOrderVal)) {
@@ -541,7 +542,8 @@ static void emitAtomicCmpXchgFailureSet(
541542
static void emitAtomicOp(CIRGenFunction &CGF, AtomicExpr *E, Address Dest,
542543
Address Ptr, Address Val1, Address Val2,
543544
mlir::Value IsWeak, mlir::Value FailureOrder,
544-
uint64_t Size, cir::MemOrder Order, uint8_t Scope) {
545+
uint64_t Size, cir::MemOrder Order,
546+
cir::MemScopeKind Scope) {
545547
assert(!cir::MissingFeatures::syncScopeID());
546548
StringRef Op;
547549

@@ -797,7 +799,7 @@ static void emitAtomicOp(CIRGenFunction &CGF, AtomicExpr *Expr, Address Dest,
797799
if (!ScopeModel) {
798800
assert(!cir::MissingFeatures::syncScopeID());
799801
emitAtomicOp(CGF, Expr, Dest, Ptr, Val1, Val2, IsWeak, FailureOrder, Size,
800-
Order, /*FIXME(cir): LLVM default scope*/ 1);
802+
Order, cir::MemScopeKind::MemScope_System);
801803
return;
802804
}
803805

‎clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp‎

Lines changed: 5 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -318,7 +318,7 @@ static RValue emitBinaryAtomicPost(CIRGenFunction &cgf,
318318
return RValue::get(result);
319319
}
320320

321-
static mlir::Value MakeAtomicCmpXchgValue(CIRGenFunction &cgf,
321+
static mlir::Value makeAtomicCmpXchgValue(CIRGenFunction &cgf,
322322
const CallExpr *expr,
323323
bool returnBool) {
324324
QualType typ = returnBool ? expr->getArg(1)->getType() : expr->getType();
@@ -341,6 +341,8 @@ static mlir::Value MakeAtomicCmpXchgValue(CIRGenFunction &cgf,
341341
cir::MemOrder::SequentiallyConsistent),
342342
MemOrderAttr::get(&cgf.getMLIRContext(),
343343
cir::MemOrder::SequentiallyConsistent),
344+
MemScopeKindAttr::get(&cgf.getMLIRContext(),
345+
cir::MemScopeKind::MemScope_System),
344346
builder.getI64IntegerAttr(destAddr.getAlignment().getAsAlign().value()));
345347

346348
return returnBool ? op.getResult(1) : op.getResult(0);
@@ -1854,14 +1856,14 @@ RValue CIRGenFunction::emitBuiltinExpr(const GlobalDecl GD, unsigned BuiltinID,
18541856
case Builtin::BI__sync_val_compare_and_swap_4:
18551857
case Builtin::BI__sync_val_compare_and_swap_8:
18561858
case Builtin::BI__sync_val_compare_and_swap_16:
1857-
return RValue::get(MakeAtomicCmpXchgValue(*this, E, false));
1859+
return RValue::get(makeAtomicCmpXchgValue(*this, E, false));
18581860

18591861
case Builtin::BI__sync_bool_compare_and_swap_1:
18601862
case Builtin::BI__sync_bool_compare_and_swap_2:
18611863
case Builtin::BI__sync_bool_compare_and_swap_4:
18621864
case Builtin::BI__sync_bool_compare_and_swap_8:
18631865
case Builtin::BI__sync_bool_compare_and_swap_16:
1864-
return RValue::get(MakeAtomicCmpXchgValue(*this, E, true));
1866+
return RValue::get(makeAtomicCmpXchgValue(*this, E, true));
18651867

18661868
case Builtin::BI__sync_swap_1:
18671869
case Builtin::BI__sync_swap_2:

‎clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3210,11 +3210,12 @@ mlir::LogicalResult CIRToLLVMAtomicCmpXchgLowering::matchAndRewrite(
32103210
auto expected = adaptor.getExpected();
32113211
auto desired = adaptor.getDesired();
32123212

3213-
// FIXME: add syncscope.
32143213
auto cmpxchg = rewriter.create<mlir::LLVM::AtomicCmpXchgOp>(
32153214
op.getLoc(), adaptor.getPtr(), expected, desired,
32163215
getLLVMAtomicOrder(adaptor.getSuccOrder()),
32173216
getLLVMAtomicOrder(adaptor.getFailOrder()));
3217+
if (const auto ss = adaptor.getSyncscope(); ss.has_value())
3218+
cmpxchg.setSyncscope(getLLVMSyncScope(ss.value()));
32183219
cmpxchg.setAlignment(adaptor.getAlignment());
32193220
cmpxchg.setWeak(adaptor.getWeak());
32203221
cmpxchg.setVolatile_(adaptor.getIsVolatile());

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