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lanzalanza
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[CIR][Lowering] Support zexting all supported cmpops
I only did this previously for ne. Extend this to the rest.
1 parent 963d2c7 commit e18418d

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+44
-23
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1 file changed

+44
-23
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‎clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp‎

Lines changed: 44 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -163,7 +163,6 @@ class CIRIfLowering : public mlir::OpConversionPattern<mlir::cir::IfOp> {
163163
}
164164
};
165165

166-
167166
class CIRScopeOpLowering
168167
: public mlir::OpConversionPattern<mlir::cir::ScopeOp> {
169168
public:
@@ -513,18 +512,22 @@ class CIRCmpOpLowering : public mlir::OpConversionPattern<mlir::cir::CmpOp> {
513512
if (!type.isSignlessInteger())
514513
llvm_unreachable("integer type not supported in CIR yet");
515514
cmpIType = mlir::LLVM::ICmpPredicate::ugt;
516-
rewriter.replaceOpWithNewOp<mlir::LLVM::ICmpOp>(
517-
cmpOp, i1Type,
515+
auto cmp = rewriter.create<mlir::LLVM::ICmpOp>(
516+
cmpOp.getLoc(), i1Type,
518517
mlir::LLVM::ICmpPredicateAttr::get(getContext(), cmpIType),
519518
adaptor.getLhs(), adaptor.getRhs());
519+
rewriter.replaceOpWithNewOp<mlir::LLVM::ZExtOp>(cmpOp, i8Type,
520+
cmp.getRes());
520521
} else if (type.isa<mlir::FloatType>()) {
521-
rewriter.replaceOpWithNewOp<mlir::LLVM::FCmpOp>(
522-
cmpOp, i1Type,
522+
auto cmp = rewriter.create<mlir::LLVM::FCmpOp>(
523+
cmpOp.getLoc(), i1Type,
523524
mlir::LLVM::FCmpPredicateAttr::get(getContext(),
524525
mlir::LLVM::FCmpPredicate::ugt),
525526
adaptor.getLhs(), adaptor.getRhs(),
526527
// TODO(CIR): These fastmath flags need to not be defaulted.
527528
mlir::LLVM::FastmathFlagsAttr::get(cmpOp.getContext(), {}));
529+
rewriter.replaceOpWithNewOp<mlir::LLVM::ZExtOp>(cmpOp, i8Type,
530+
cmp.getRes());
528531
} else {
529532
llvm_unreachable("Unknown Operand Type");
530533
}
@@ -536,17 +539,21 @@ class CIRCmpOpLowering : public mlir::OpConversionPattern<mlir::cir::CmpOp> {
536539
if (!type.isSignlessInteger())
537540
llvm_unreachable("integer type not supported in CIR yet");
538541
cmpIType = mlir::LLVM::ICmpPredicate::uge;
539-
rewriter.replaceOpWithNewOp<mlir::LLVM::ICmpOp>(
540-
cmpOp, i1Type,
542+
auto cmp = rewriter.create<mlir::LLVM::ICmpOp>(
543+
cmpOp.getLoc(), i1Type,
541544
mlir::LLVM::ICmpPredicateAttr::get(getContext(), cmpIType),
542545
adaptor.getLhs(), adaptor.getRhs());
546+
rewriter.replaceOpWithNewOp<mlir::LLVM::ZExtOp>(cmpOp, i8Type,
547+
cmp.getRes());
543548
} else if (type.isa<mlir::FloatType>()) {
544-
rewriter.replaceOpWithNewOp<mlir::LLVM::FCmpOp>(
545-
cmpOp, i1Type,
549+
auto cmp = rewriter.create<mlir::LLVM::FCmpOp>(
550+
cmpOp.getLoc(), i1Type,
546551
mlir::LLVM::FCmpPredicateAttr::get(getContext(),
547552
mlir::LLVM::FCmpPredicate::uge),
548553
adaptor.getLhs(), adaptor.getRhs(),
549554
mlir::LLVM::FastmathFlagsAttr::get(cmpOp.getContext(), {}));
555+
rewriter.replaceOpWithNewOp<mlir::LLVM::ZExtOp>(cmpOp, i8Type,
556+
cmp.getRes());
550557
} else {
551558
llvm_unreachable("Unknown Operand Type");
552559
}
@@ -558,17 +565,21 @@ class CIRCmpOpLowering : public mlir::OpConversionPattern<mlir::cir::CmpOp> {
558565
if (!type.isSignlessInteger())
559566
llvm_unreachable("integer type not supported in CIR yet");
560567
cmpIType = mlir::LLVM::ICmpPredicate::ult;
561-
rewriter.replaceOpWithNewOp<mlir::LLVM::ICmpOp>(
562-
cmpOp, i1Type,
568+
auto cmp = rewriter.create<mlir::LLVM::ICmpOp>(
569+
cmpOp.getLoc(), i1Type,
563570
mlir::LLVM::ICmpPredicateAttr::get(getContext(), cmpIType),
564571
adaptor.getLhs(), adaptor.getRhs());
572+
rewriter.replaceOpWithNewOp<mlir::LLVM::ZExtOp>(cmpOp, i8Type,
573+
cmp.getRes());
565574
} else if (type.isa<mlir::FloatType>()) {
566-
rewriter.replaceOpWithNewOp<mlir::LLVM::FCmpOp>(
567-
cmpOp, i1Type,
575+
auto cmp = rewriter.create<mlir::LLVM::FCmpOp>(
576+
cmpOp.getLoc(), i1Type,
568577
mlir::LLVM::FCmpPredicateAttr::get(getContext(),
569578
mlir::LLVM::FCmpPredicate::ult),
570579
adaptor.getLhs(), adaptor.getRhs(),
571580
mlir::LLVM::FastmathFlagsAttr::get(cmpOp.getContext(), {}));
581+
rewriter.replaceOpWithNewOp<mlir::LLVM::ZExtOp>(cmpOp, i8Type,
582+
cmp.getRes());
572583
} else {
573584
llvm_unreachable("Unknown Operand Type");
574585
}
@@ -580,36 +591,44 @@ class CIRCmpOpLowering : public mlir::OpConversionPattern<mlir::cir::CmpOp> {
580591
if (!type.isSignlessInteger())
581592
llvm_unreachable("integer type not supported in CIR yet");
582593
cmpIType = mlir::LLVM::ICmpPredicate::ule;
583-
rewriter.replaceOpWithNewOp<mlir::LLVM::ICmpOp>(
584-
cmpOp, i1Type,
594+
auto cmp = rewriter.create<mlir::LLVM::ICmpOp>(
595+
cmpOp.getLoc(), i1Type,
585596
mlir::LLVM::ICmpPredicateAttr::get(getContext(), cmpIType),
586597
adaptor.getLhs(), adaptor.getRhs());
598+
rewriter.replaceOpWithNewOp<mlir::LLVM::ZExtOp>(cmpOp, i8Type,
599+
cmp.getRes());
587600
} else if (type.isa<mlir::FloatType>()) {
588-
rewriter.replaceOpWithNewOp<mlir::LLVM::FCmpOp>(
589-
cmpOp, i1Type,
601+
auto cmp = rewriter.create<mlir::LLVM::FCmpOp>(
602+
cmpOp.getLoc(), i1Type,
590603
mlir::LLVM::FCmpPredicateAttr::get(getContext(),
591604
mlir::LLVM::FCmpPredicate::ule),
592605
adaptor.getLhs(), adaptor.getRhs(),
593606
mlir::LLVM::FastmathFlagsAttr::get(cmpOp.getContext(), {}));
607+
rewriter.replaceOpWithNewOp<mlir::LLVM::ZExtOp>(cmpOp, i8Type,
608+
cmp.getRes());
594609
} else {
595610
llvm_unreachable("Unknown Operand Type");
596611
}
597612
break;
598613
}
599614
case mlir::cir::CmpOpKind::eq: {
600615
if (type.isa<mlir::IntegerType>()) {
601-
rewriter.replaceOpWithNewOp<mlir::LLVM::ICmpOp>(
602-
cmpOp, i1Type,
616+
auto cmp = rewriter.create<mlir::LLVM::ICmpOp>(
617+
cmpOp.getLoc(), i1Type,
603618
mlir::LLVM::ICmpPredicateAttr::get(getContext(),
604619
mlir::LLVM::ICmpPredicate::eq),
605620
adaptor.getLhs(), adaptor.getRhs());
621+
rewriter.replaceOpWithNewOp<mlir::LLVM::ZExtOp>(cmpOp, i8Type,
622+
cmp.getRes());
606623
} else if (type.isa<mlir::FloatType>()) {
607-
rewriter.replaceOpWithNewOp<mlir::LLVM::FCmpOp>(
608-
cmpOp, i1Type,
624+
auto cmp = rewriter.create<mlir::LLVM::FCmpOp>(
625+
cmpOp.getLoc(), i1Type,
609626
mlir::LLVM::FCmpPredicateAttr::get(getContext(),
610627
mlir::LLVM::FCmpPredicate::ueq),
611628
adaptor.getLhs(), adaptor.getRhs(),
612629
mlir::LLVM::FastmathFlagsAttr::get(cmpOp.getContext(), {}));
630+
rewriter.replaceOpWithNewOp<mlir::LLVM::ZExtOp>(cmpOp, i8Type,
631+
cmp.getRes());
613632
} else {
614633
llvm_unreachable("Unknown Operand Type");
615634
}
@@ -626,12 +645,14 @@ class CIRCmpOpLowering : public mlir::OpConversionPattern<mlir::cir::CmpOp> {
626645
rewriter.replaceOpWithNewOp<mlir::LLVM::ZExtOp>(cmpOp, i8Type,
627646
cmp.getRes());
628647
} else if (type.isa<mlir::FloatType>()) {
629-
rewriter.replaceOpWithNewOp<mlir::LLVM::FCmpOp>(
630-
cmpOp, i1Type,
648+
auto cmp = rewriter.create<mlir::LLVM::FCmpOp>(
649+
cmpOp.getLoc(), i1Type,
631650
mlir::LLVM::FCmpPredicateAttr::get(getContext(),
632651
mlir::LLVM::FCmpPredicate::une),
633652
adaptor.getLhs(), adaptor.getRhs(),
634653
mlir::LLVM::FastmathFlagsAttr::get(cmpOp.getContext(), {}));
654+
rewriter.replaceOpWithNewOp<mlir::LLVM::ZExtOp>(cmpOp, i8Type,
655+
cmp.getRes());
635656
} else {
636657
llvm_unreachable("Unknown Operand Type");
637658
}

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