[CIR][Lowering] Fix inconditional sign extension on vec.cmp

Author: RiverDave

clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp

@@ -2004,8 +2004,15 @@ mlir::LogicalResult CIRToLLVMVecCmpOpLowering::matchAndRewrite(
   } else {
     return op.emitError() << "unsupported type for VecCmpOp: " << elementType;
   }
-  rewriter.replaceOpWithNewOp<mlir::LLVM::SExtOp>(
-      op, typeConverter->convertType(op.getType()), bitResult);
+
+  // Check if the types are the same before generating SExtOp
+  auto targetType = typeConverter->convertType(op.getType());
+  if (bitResult.getType() == targetType) {
+    rewriter.replaceOp(op, bitResult);
+  } else {
+    rewriter.replaceOpWithNewOp<mlir::LLVM::SExtOp>(op, targetType, bitResult);
+  }
+
   return mlir::success();
 }
 

clang/test/CIR/Lowering/vec-cmp.cir

@@ -0,0 +1,17 @@
+// RUN: cir-opt %s -cir-to-llvm -o %t.cir
+// RUN: FileCheck --input-file=%t.cir %s -check-prefix=MLIR
+
+!s16i = !cir.int<s, 16>
+!u16i = !cir.int<u, 16>
+!s1i = !cir.int<s, 1>
+
+cir.func @vec_cmp(%0: !cir.vector<!s16i x 16>, %1: !cir.vector<!s16i x 16>) -> () {
+  %2 = cir.vec.cmp(lt, %0, %1) : !cir.vector<!s16i x 16>, !cir.vector<!cir.int<u, 1> x 16> 
+  %3 = cir.cast(bitcast, %2 : !cir.vector<!cir.int<u, 1> x 16>), !u16i
+  cir.return
+}
+    
+// MLIR: llvm.func @vec_cmp
+// MLIR-NEXT: %{{[0-9]+}} = llvm.icmp "slt" %arg0, %arg1 : vector<16xi16>
+// MLIR-NEXT: %{{[0-9]+}} = llvm.bitcast %{{[0-9]+}} : vector<16xi1> to i16
+// MLIR-NEXT: llvm.return