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sschrinerpgoodmanalessandrogario
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New arch support (#461)
* This branch contains support for new architectures. * Initial start to support for AArch 32 * Progress * Forgot the new files * Added all data Integer processing instructions without S + ADDS and started ANDS * Updated * Finished Integer Data Processing with three registers, added integer data processing with 2 regs + immediate, started MUL instructions * UMULL, UMULLS, UMLAL, UMLALS * Corrected condition for addend or 0 immediate for UMULL/UMLAL + SMULL/SMLAL instructions * Correct ops in Binary.cpp * UMAAL * SMULL, SMULLS, SMLAL, SMLALS + corrected acc was missing shift left in concatination * Updated decoding instructions based on top level encodings * Update returns around kDataProcessingRI and kDataProcessingI with comments to explain the correlation to the instruction rep * Added appropriate inst.category flags to Multiply and accumulate * Load/Store Word, Unsigned Byte (immediate, literal) && start of Logical Arithmetic (three register, immediate shift) * Was missing UMAAL DEF_ISEL in Binary.cpp * AddAddrRegOp * Logical Arithmetic (three register, immediate shift) without accounting for the possible PC jump * Made DecodeA32ExpandImm much much smaller * Replaced some imm ops with AddImmOp calls * Created AddShiftOp * Added interpreter for evaluating new PC value at decoding time to handle direct jumps and conditional jumps * Created EvalPCDest added PC evaluation to Logical Arithmetic Instructions * AddShiftOp -> AddShiftOp, AddShiftThenExtractOp, AddExtractThenShiftOp * Cleaned up some formatting, Renamed DecodeA32ExpandImm to ExpandTo32AddImmAddCarry and added a clarifying comment * Added comment to EvalPCDest for clarity * Cleaned up some things, updated the decoding semantics and semantics for the logical instructions * Shortened kLogArithEvaluators and fixed a bug * Updates from testing instructions * Fixed DEF_ISEL for pre/post index instructions in MEM.cpp * Integer Test and Compare (two register, immediate shift) * Logical Arithmetic (two register and immediate) * Integer Test and Compare (one register and immediate) * Added to the top level encoding infrastructure to handle the Data-processing register (register shift) set of instructions and 3 corresponding subsets * Add structs for the 3 subsets of Data-processing register (register shift) * Code status before refactoring operand types * This branch contains support for new architectures. * Initial start to support for AArch 32 * Progress * Forgot the new files * Added all data Integer processing instructions without S + ADDS and started ANDS * Updated * Finished Integer Data Processing with three registers, added integer data processing with 2 regs + immediate, started MUL instructions * UMULL, UMULLS, UMLAL, UMLALS * Corrected condition for addend or 0 immediate for UMULL/UMLAL + SMULL/SMLAL instructions * Correct ops in Binary.cpp * UMAAL * SMULL, SMULLS, SMLAL, SMLALS + corrected acc was missing shift left in concatination * Updated decoding instructions based on top level encodings * Update returns around kDataProcessingRI and kDataProcessingI with comments to explain the correlation to the instruction rep * Added appropriate inst.category flags to Multiply and accumulate * Load/Store Word, Unsigned Byte (immediate, literal) && start of Logical Arithmetic (three register, immediate shift) * Was missing UMAAL DEF_ISEL in Binary.cpp * AddAddrRegOp * Logical Arithmetic (three register, immediate shift) without accounting for the possible PC jump * Made DecodeA32ExpandImm much much smaller * Replaced some imm ops with AddImmOp calls * Created AddShiftOp * Added interpreter for evaluating new PC value at decoding time to handle direct jumps and conditional jumps * Created EvalPCDest added PC evaluation to Logical Arithmetic Instructions * AddShiftOp -> AddShiftOp, AddShiftThenExtractOp, AddExtractThenShiftOp * Cleaned up some formatting, Renamed DecodeA32ExpandImm to ExpandTo32AddImmAddCarry and added a clarifying comment * Added comment to EvalPCDest for clarity * Cleaned up some things, updated the decoding semantics and semantics for the logical instructions * Shortened kLogArithEvaluators and fixed a bug * Updates from testing instructions * Fixed DEF_ISEL for pre/post index instructions in MEM.cpp * Integer Test and Compare (two register, immediate shift) * Logical Arithmetic (two register and immediate) * Integer Test and Compare (one register and immediate) * Added to the top level encoding infrastructure to handle the Data-processing register (register shift) set of instructions and 3 corresponding subsets * Add structs for the 3 subsets of Data-processing register (register shift) * Code status before refactoring operand types * Finished updates off master * Start of operand refactor * Finished Expression Operand Support * Fix the .gitignore to add AArch32 to lib/Arch && removed all extra rrx ops from semantics * Updated .gitignore again, Added AddShiftRegRegOperand, Updated AddShiftRegImmOperand, Finished Register shift instructions for Integer Test and Compare, Logical Arithmetic, Integer Data Processing * Updated ROR in AddShiftRegRegOperand * Created ExtractAndZExtExpr * Fixed comment formatting in if else statements * Created RORExpr * Small fixes * Small fix in Logical Arithmetic (two register and immediate) * Corrected AddShiftRegRegOperand and cleaned it up. Split the carry op into a separate function. * conditional support + Start of Branch instructions * Created AddExprOp, cleaned up some expressions in reg shifted reg, and updated some occurances of ShiftThenExtractOp with ExtractAndZExtExpr * Updates from testing register shifted by register value inst * Fix to ROR in AddShiftRegCarryOperand * Corrected negation in DecodeCondition * DecodeCondition edit * DecodeCondition and AddShiftRegCarryOperand edits * Updated arch_for_decode to arch * Halfword Multiply and Accumulate * Edits from testing Halfword Multiply and Accumulate * Changed order of operands in Halfword Multiply and Accumulate to better reflect inst format + updated inst errors * Branch (Imm) & BX/BXL * Update aarch32 cmake * cmake update * CLZ * Forgot BITBYTE.cpp * MOVT * Integer Saturating Arithmetic * updated semantics in SMLAWh & SMLAh to use Select for setting PSTATE.Q * Started Load/Store Word, Unsigned Byte (register) & fixed MOV halfword * Load/Store Word, Unsigned Byte (register) * Finished testing load/Store Word, Unsigned Byte (register) * Load/Store Dual, Half, Signed Byte (register) * Rest of Extra load store: Load/Store Dual, Half, Signed Byte (immediate, literal) * Finished testing all the Load/store additions * Signed multiply, Divide * Cleaned up SExt some * Saturate Insts and Start of Load Store Multiple - STMDB and LDM (aliases which support PUSH and POP of multiple regs) * Condensed args in STMDB and LDM semantics * Rest of Multiple Load/Store that do not execute in a different mode * Bitfield Extract * Extend and Add * fix * NOP * Small fix * Simplified the bit reps in TryMoveSpecialRegisterAndHintsI * Moved Bitfield extract semantics out of BINARY and into BITBYTE * Finished correcting S/ZExt and Trunc use * Ran scripts/format-files to format * Smoke Test * Add false delay slot to kCategoryConditionalDirectFunctionCall * CI: Use single packaging job, add changelog support (#491) * CI: Add tag handler (#492) * Delay slot fixes to TraceLifter Co-authored-by: Peter Goodman <peter.goodman@gmail.com> Co-authored-by: Alessandro Gario <5714290+alessandrogario@users.noreply.github.com>
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‎.github/workflows/vcpkg_ci.yml‎

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@@ -63,6 +63,7 @@ jobs:
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run: |
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remill-lift-${{ matrix.llvm }} --arch amd64 --ir_out /dev/stdout --bytes c704ba01000000
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remill-lift-${{ matrix.llvm }} --arch aarch64 --ir_out /dev/stdout --address 0x400544 --bytes FD7BBFA90000009000601891FD030091B7FFFF97E0031F2AFD7BC1A8C0035FD6
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remill-lift-${{ matrix.llvm }} --arch aarch32 -ir_out /dev/stderr --bytes 0cd04de208008de504108de500208de508309de504009de500109de5903122e0c20fa0e110109fe5001091e5002081e5040081e50cd08de21eff2fe14000000000000000
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- name: Locate the packages
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id: package_names
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run: |
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remill-lift-${{ matrix.llvm }} --arch amd64 --ir_out /dev/stdout --bytes c704ba01000000
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remill-lift-${{ matrix.llvm }} --arch aarch64 --ir_out /dev/stdout --address 0x400544 --bytes FD7BBFA90000009000601891FD030091B7FFFF97E0031F2AFD7BC1A8C0035FD6
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remill-lift-${{ matrix.llvm }} --arch aarch32 -ir_out /dev/stderr --bytes 0cd04de208008de504108de500208de508309de504009de500109de5903122e0c20fa0e110109fe5001091e5002081e5040081e50cd08de21eff2fe14000000000000000
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- name: Locate the packages
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id: package_names

‎CMakeLists.txt‎

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@@ -183,6 +183,7 @@ else()
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endif()
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set(REMILL_BUILD_SEMANTICS_DIR_X86 "${CMAKE_CURRENT_BINARY_DIR}/lib/Arch/X86/Runtime")
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set(REMILL_BUILD_SEMANTICS_DIR_AARCH32 "${CMAKE_CURRENT_BINARY_DIR}/lib/Arch/AArch32/Runtime")
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set(REMILL_BUILD_SEMANTICS_DIR_AARCH64 "${CMAKE_CURRENT_BINARY_DIR}/lib/Arch/AArch64/Runtime")
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set(REMILL_BUILD_SEMANTICS_DIR_SPARC32 "${CMAKE_CURRENT_BINARY_DIR}/lib/Arch/SPARC32/Runtime")
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set(REMILL_BUILD_SEMANTICS_DIR_SPARC64 "${CMAKE_CURRENT_BINARY_DIR}/lib/Arch/SPARC64/Runtime")
@@ -265,6 +266,7 @@ endif()
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target_compile_definitions(remill_settings INTERFACE
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"REMILL_INSTALL_SEMANTICS_DIR=\"${REMILL_INSTALL_SEMANTICS_DIR}/\""
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"REMILL_BUILD_SEMANTICS_DIR_X86=\"${REMILL_BUILD_SEMANTICS_DIR_X86}\""
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"REMILL_BUILD_SEMANTICS_DIR_AARCH32=\"${REMILL_BUILD_SEMANTICS_DIR_AARCH32}\""
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"REMILL_BUILD_SEMANTICS_DIR_AARCH64=\"${REMILL_BUILD_SEMANTICS_DIR_AARCH64}\""
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"REMILL_BUILD_SEMANTICS_DIR_SPARC32=\"${REMILL_BUILD_SEMANTICS_DIR_SPARC32}\""
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"REMILL_BUILD_SEMANTICS_DIR_SPARC64=\"${REMILL_BUILD_SEMANTICS_DIR_SPARC64}\""
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set(REMILL_BC_LIBRARY_LOCATION "${REMILL_INSTALL_LIB_DIR}/${static_lib_prefix}remill_bc.${static_lib_extension}")
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set(REMILL_ARCH_LIBRARY_LOCATION "${REMILL_INSTALL_LIB_DIR}/${static_lib_prefix}remill_arch.${static_lib_extension}")
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set(REMILL_ARCH_X86_LIBRARY_LOCATION "${REMILL_INSTALL_LIB_DIR}/${static_lib_prefix}remill_arch_x86.${static_lib_extension}")
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set(REMILL_ARCH_AARCH32_LIBRARY_LOCATION "${REMILL_INSTALL_LIB_DIR}/${static_lib_prefix}remill_arch_aarch32.${static_lib_extension}")
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set(REMILL_ARCH_AARCH64_LIBRARY_LOCATION "${REMILL_INSTALL_LIB_DIR}/${static_lib_prefix}remill_arch_aarch64.${static_lib_extension}")
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set(REMILL_ARCH_SPARC32_LIBRARY_LOCATION "${REMILL_INSTALL_LIB_DIR}/${static_lib_prefix}remill_arch_sparc32.${static_lib_extension}")
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set(REMILL_ARCH_SPARC64_LIBRARY_LOCATION "${REMILL_INSTALL_LIB_DIR}/${static_lib_prefix}remill_arch_sparc64.${static_lib_extension}")

‎CMakeLists_vcpkg.txt‎

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@@ -145,6 +145,7 @@ math(EXPR REMILL_LLVM_VERSION_NUMBER "${LLVM_MAJOR_VERSION} * 100 + ${LLVM_MINOR
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set(REMILL_INSTALL_SEMANTICS_DIR "${CMAKE_INSTALL_PREFIX}/${REMILL_INSTALL_SHARE_DIR}/remill/${REMILL_LLVM_VERSION}/semantics" CACHE PATH "Directory into which semantics are installed")
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set(REMILL_BUILD_SEMANTICS_DIR_X86 "${CMAKE_CURRENT_BINARY_DIR}/lib/Arch/X86/Runtime")
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set(REMILL_BUILD_SEMANTICS_DIR_AARCH32 "${CMAKE_CURRENT_BINARY_DIR}/lib/Arch/AArch32/Runtime")
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set(REMILL_BUILD_SEMANTICS_DIR_AARCH64 "${CMAKE_CURRENT_BINARY_DIR}/lib/Arch/AArch64/Runtime")
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set(REMILL_BUILD_SEMANTICS_DIR_SPARC32 "${CMAKE_CURRENT_BINARY_DIR}/lib/Arch/SPARC32/Runtime")
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set(REMILL_BUILD_SEMANTICS_DIR_SPARC64 "${CMAKE_CURRENT_BINARY_DIR}/lib/Arch/SPARC64/Runtime")
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target_compile_definitions(remill_settings INTERFACE
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"REMILL_INSTALL_SEMANTICS_DIR=\"${REMILL_INSTALL_SEMANTICS_DIR}\""
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"REMILL_BUILD_SEMANTICS_DIR_X86=\"${REMILL_BUILD_SEMANTICS_DIR_X86}\""
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"REMILL_BUILD_SEMANTICS_DIR_AARCH32=\"${REMILL_BUILD_SEMANTICS_DIR_AARCH32}\""
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"REMILL_BUILD_SEMANTICS_DIR_AARCH64=\"${REMILL_BUILD_SEMANTICS_DIR_AARCH64}\""
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"REMILL_BUILD_SEMANTICS_DIR_SPARC32=\"${REMILL_BUILD_SEMANTICS_DIR_SPARC32}\""
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"REMILL_BUILD_SEMANTICS_DIR_SPARC64=\"${REMILL_BUILD_SEMANTICS_DIR_SPARC64}\""

‎cmake/remillConfig.cmake.in‎

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@@ -65,6 +65,9 @@ if(NOT TARGET remill)
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add_library(remill_arch_x86 STATIC IMPORTED)
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set_property(TARGET remill_arch_x86 PROPERTY IMPORTED_LOCATION "@REMILL_ARCH_X86_LIBRARY_LOCATION@")
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add_library(remill_arch_aarch32 STATIC IMPORTED)
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set_property(TARGET remill_arch_aarch32 PROPERTY IMPORTED_LOCATION "@REMILL_ARCH_AARCH32_LIBRARY_LOCATION@")
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add_library(remill_arch_aarch64 STATIC IMPORTED)
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set_property(TARGET remill_arch_aarch64 PROPERTY IMPORTED_LOCATION "@REMILL_ARCH_AARCH64_LIBRARY_LOCATION@")
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@@ -84,6 +87,7 @@ if(NOT TARGET remill)
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remill_os
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remill_arch
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remill_arch_x86
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remill_arch_aarch32
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remill_arch_aarch64
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remill_arch_sparc32
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remill_arch_sparc64

‎include/remill/Arch/AArch32/Runtime/Operators.h‎

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/*
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* Copyright (c) 2017 Trail of Bits, Inc.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
14+
* limitations under the License.
15+
*/
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#pragma once
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19+
namespace {
20+
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// Read a register directly. Sometimes this is needed for suppressed operands.
22+
ALWAYS_INLINE static addr_t _Read(Memory *, Reg reg) {
23+
return reg.aword;
24+
}
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// Write directly to a register. This is sometimes needed for suppressed
27+
// register operands.
28+
ALWAYS_INLINE static void _Write(Memory *, Reg &reg, addr_t val) {
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reg.aword = val;
30+
}
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} // namespace

‎include/remill/Arch/AArch32/Runtime/State.h‎

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/*
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* Copyright (c) 2017 Trail of Bits, Inc.
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*
4+
* Licensed under the Apache License, Version 2.0 (the "License");
5+
* you may not use this file except in compliance with the License.
6+
* You may obtain a copy of the License at
7+
*
8+
* http://www.apache.org/licenses/LICENSE-2.0
9+
*
10+
* Unless required by applicable law or agreed to in writing, software
11+
* distributed under the License is distributed on an "AS IS" BASIS,
12+
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13+
* See the License for the specific language governing permissions and
14+
* limitations under the License.
15+
*/
16+
17+
#pragma once
18+
19+
#pragma clang diagnostic push
20+
#pragma clang diagnostic fatal "-Wpadded"
21+
22+
#include "remill/Arch/Runtime/State.h"
23+
#include "remill/Arch/Runtime/Types.h"
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struct Reg final {
26+
alignas(4) uint32_t dword;
27+
} __attribute__((packed));
28+
29+
static_assert(sizeof(uint32_t) == sizeof(Reg), "Invalid packing of `Reg`.");
30+
static_assert(0 == __builtin_offsetof(Reg, dword),
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"Invalid packing of `Reg::dword`.");
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struct alignas(8) GPR final {
34+
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// Prevents LLVM from casting a `GPR` into an `i64` to access `X0`.
36+
volatile uint32_t _0;
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Reg r0;
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volatile uint32_t _1;
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Reg r1;
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volatile uint32_t _2;
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Reg r2;
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volatile uint32_t _3;
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Reg r3;
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volatile uint32_t _4;
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Reg r4;
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volatile uint32_t _5;
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Reg r5;
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volatile uint32_t _6;
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Reg r6;
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volatile uint32_t _7;
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Reg r7;
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volatile uint32_t _8;
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Reg r8;
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volatile uint32_t _9;
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Reg r9;
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volatile uint32_t _10;
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Reg r10;
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volatile uint32_t _11;
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Reg r11;
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volatile uint32_t _12;
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Reg r12;
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// R13 is SP (stack pointer)
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volatile uint32_t _13;
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Reg r13;
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// R14 is LR (link register)
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volatile uint32_t _14;
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Reg r14;
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// R15 is PC (program counter)
72+
volatile uint32_t _15;
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Reg r15;
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} __attribute__((packed));
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// System registers affecting control and status of the machine.
79+
struct alignas(8) SR final {
80+
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uint8_t _2;
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uint8_t n; // Negative condition flag.
83+
uint8_t _3;
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uint8_t z; // Zero condition flag
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uint8_t _4;
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uint8_t c; // Carry condition flag
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uint8_t _5;
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uint8_t v; // Overflow condition flag
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uint8_t _6;
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uint8_t ixc; // Inexact (cumulative).
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uint8_t _7;
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uint8_t ofc; // Overflow (cumulative).
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uint8_t _8;
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uint8_t ufc; // Underflow (cumulative).
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uint8_t _9;
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uint8_t idc; // Input denormal (cumulative).
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uint8_t _10;
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uint8_t ioc; // Invalid operation (cumulative).
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uint8_t _11;
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uint8_t q; // Sticky overflow bit.
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uint8_t _padding[4];
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} __attribute__((packed));
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struct alignas(16) State final : public ArchState {
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GPR gpr; // 528 bytes.
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SR sr;
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uint64_t _0;
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} __attribute__((packed));
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using AArch32State = State;
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#pragma clang diagnostic pop

‎include/remill/Arch/AArch32/Runtime/Types.h‎

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/*
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* Copyright (c) 2017 Trail of Bits, Inc.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#pragma once
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// We need this for boolean conditions, used in branch instructions.
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typedef RnW<uint8_t> R8W;
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typedef RnW<uint8_t> R8W;
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typedef RnW<uint16_t> R16W;
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// Note: AArch64 zero-extends like x86, but the smallest register size that
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// can be accessed is 32 bits.
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typedef RnW<uint32_t> R32W;
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typedef Rn<uint8_t> R8;
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//typedef Rn<uint16_t> R16;
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typedef Rn<uint32_t> R32;
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typedef Vn<vec8_t> V8;
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typedef Vn<vec16_t> V16;
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typedef Vn<vec32_t> V32;
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typedef Vn<vec64_t> V64;
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typedef Vn<vec128_t> V128;
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typedef VnW<vec128_t> V128W;
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typedef MnW<uint8_t> M8W;
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typedef MnW<uint16_t> M16W;
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typedef MnW<uint32_t> M32W;
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typedef MnW<uint64_t> M64W;
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typedef MVnW<vec8_t> MV8W;
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typedef MVnW<vec16_t> MV16W;
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typedef MVnW<vec32_t> MV32W;
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typedef MVnW<vec64_t> MV64W;
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typedef MVnW<vec128_t> MV128W;
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typedef Mn<uint8_t> M8;
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typedef Mn<uint16_t> M16;
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typedef Mn<uint32_t> M32;
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typedef Mn<uint64_t> M64;
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typedef MVn<vec8_t> MV8;
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typedef MVn<vec16_t> MV16;
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typedef MVn<vec32_t> MV32;
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typedef MVn<vec64_t> MV64;
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typedef MVn<vec128_t> MV128;
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typedef MVn<vec256_t> MV256;
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typedef In<uint8_t> I8;
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typedef In<uint16_t> I16;
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typedef In<uint32_t> I32;
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typedef In<float32_t> F32;
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typedef In<float64_t> F64;
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typedef In<addr_t> PC;
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typedef In<addr_t> ADDR;

‎include/remill/Arch/Arch.h‎

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#include <llvm/IR/DataLayout.h>
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#include <llvm/IR/IRBuilder.h>
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#pragma clang diagnostic pop
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// clang-format on
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#include <functional>
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// Factory method for loading the correct architecture class for a given
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// operating system and architecture class.
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static auto Get(llvm::LLVMContext &context, std::string_view os,
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std::string_view arch_name) -> ArchPtr;
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std::string_view arch_name) -> ArchPtr;
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// Factory method for loading the correct architecture class for a given
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// operating system and architecture class.
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static auto Get(llvm::LLVMContext &context, OSName os,
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ArchName arch_name) -> ArchPtr;
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static auto Get(llvm::LLVMContext &context, OSName os, ArchName arch_name)
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-> ArchPtr;
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// Return the type of the state structure.
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llvm::StructType *StateStructType(void) const;
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bool IsX86(void) const;
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bool IsAMD64(void) const;
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bool IsAArch32(void) const;
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bool IsAArch64(void) const;
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bool IsSPARC32(void) const;
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bool IsSPARC64(void) const;
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llvm::Triple BasicTriple(void) const;
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// Add a register into this
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const Register *AddRegister(const char *reg_name,
282-
llvm::Type *val_type, size_t offset,
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const char *parent_reg_name) const;
283+
const Register *AddRegister(const char *reg_name, llvm::Type *val_type,
284+
size_t offset, const char *parent_reg_name) const;
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private:
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// Defined in `lib/Arch/X86/Arch.cpp`.
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static ArchPtr GetX86(llvm::LLVMContext *context, OSName os,
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ArchName arch_name);
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291+
// Defined in `lib/Arch/AArch32/Arch.cpp`.
292+
static ArchPtr GetAArch32(llvm::LLVMContext *context, OSName os,
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ArchName arch_name);
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// Defined in `lib/Arch/AArch64/Arch.cpp`.
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static ArchPtr GetAArch64(llvm::LLVMContext *context, OSName os,
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ArchName arch_name);
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// Defined in `lib/Arch/SPARC32/Arch.cpp`.
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static ArchPtr GetSPARC(
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llvm::LLVMContext *context, OSName os, ArchName arch_name);
300+
static ArchPtr GetSPARC(llvm::LLVMContext *context, OSName os,
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ArchName arch_name);
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// Defined in `lib/Arch/SPARC64/Arch.cpp`.
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static ArchPtr GetSPARC64(
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llvm::LLVMContext *context, OSName os, ArchName arch_name);
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static ArchPtr GetSPARC64(llvm::LLVMContext *context, OSName os,
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ArchName arch_name);
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mutable std::unique_ptr<ArchImpl> impl;
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