Add knob for enabling Avx10.2 in debug mode

khushal1996 · khushal1996 · commit 8b6ff9243fdf · 2025-01-29T11:15:51.000-08:00
diff --git a/src/coreclr/jit/codegencommon.cpp b/src/coreclr/jit/codegencommon.cpp
@@ -1832,9 +1832,9 @@ void CodeGen::genGenerateMachineCode()
 #if defined(TARGET_X86)
         if (compiler->canUseEvexEncoding())
         {
-            if (compiler->compOpportunisticallyDependsOn(InstructionSet_AVX10v2))
+            if (compiler->compOpportunisticallyDependsOn(InstructionSet_AVX10v2) || compiler->canUseAVX10v2())
             {
-                if (compiler->compOpportunisticallyDependsOn(InstructionSet_AVX10v2_V512))
+                if (compiler->compOpportunisticallyDependsOn(InstructionSet_AVX10v2_V512) || compiler->canUseAVX10v2())
                 {
                     printf("X86 with AVX10.2/512");
                 }
@@ -1871,9 +1871,9 @@ void CodeGen::genGenerateMachineCode()
 #elif defined(TARGET_AMD64)
         if (compiler->canUseEvexEncoding())
         {
-            if (compiler->compOpportunisticallyDependsOn(InstructionSet_AVX10v2))
+            if (compiler->compOpportunisticallyDependsOn(InstructionSet_AVX10v2) || compiler->canUseAVX10v2())
             {
-                if (compiler->compOpportunisticallyDependsOn(InstructionSet_AVX10v2_V512))
+                if (compiler->compOpportunisticallyDependsOn(InstructionSet_AVX10v2_V512) || compiler->canUseAVX10v2())
                 {
                     printf("X64 with AVX10.2/512");
                 }
diff --git a/src/coreclr/jit/codegenxarch.cpp b/src/coreclr/jit/codegenxarch.cpp
@@ -9249,7 +9249,7 @@ void CodeGen::genAmd64EmitterUnitTestsAvx10v2()
     genDefineTempLabel(genCreateTempLabel());
 
     // This test suite needs AVX10.2 enabled.
-    if (!theEmitter->emitComp->compIsaSupportedDebugOnly(InstructionSet_AVX10v2))
+    if (!theEmitter->emitComp->compIsaSupportedDebugOnly(InstructionSet_AVX10v2) && !theEmitter->emitComp->canUseAVX10v2())
     {
         return;
     }
diff --git a/src/coreclr/jit/compiler.h b/src/coreclr/jit/compiler.h
@@ -9832,6 +9832,19 @@ class Compiler
 #endif
     }
 
+#ifdef TARGET_XARCH
+    bool canUseAVX10v2() const
+    {
+#ifdef DEBUG
+        if (JitConfig.FakeEnableAVX10v2())
+        {
+            return true;
+        }
+#endif
+        return compOpportunisticallyDependsOn(InstructionSet_AVX10v2);
+    }
+#endif
+
     // Answer the question: Is a particular ISA allowed to be used implicitly by optimizations?
     // The result of this api call will match the target machine if the result is true.
     // If the result is false, then the target machine may have support for the instruction.
diff --git a/src/coreclr/jit/emitxarch.cpp b/src/coreclr/jit/emitxarch.cpp
@@ -1493,7 +1493,7 @@ emitter::code_t emitter::AddEvexPrefix(const instrDesc* id, code_t code, emitAtt
             // ymm embedded rounding case.
             if (attr == EA_32BYTE)
             {
-                assert(emitComp->compIsaSupportedDebugOnly(InstructionSet_AVX10v2));
+                assert(emitComp->compIsaSupportedDebugOnly(InstructionSet_AVX10v2) || emitComp->canUseAVX10v2());
                 code &= ~(uBIT_IN_BYTE_EVEX_PREFIX);
             }
 
@@ -2237,7 +2237,7 @@ emitter::code_t emitter::emitExtractEvexPrefix(instruction ins, code_t& code) co
         if (sizePrefix == 0)
         {
             // no simd prefix for EVEX2 - AVX10.2 and above
-            assert(emitComp->compIsaSupportedDebugOnly(InstructionSet_AVX10v2));
+            assert(emitComp->compIsaSupportedDebugOnly(InstructionSet_AVX10v2) || emitComp->canUseAVX10v2());
         }
         else if (isPrefix(sizePrefix))
         {
@@ -2285,7 +2285,7 @@ emitter::code_t emitter::emitExtractEvexPrefix(instruction ins, code_t& code) co
         //                          1. An escape byte 0F (For isa before AVX10.2)
         //                          2. A map number from 0 to 7 (For AVX10.2 and above)
         leadingBytes = check;
-        assert(leadingBytes == 0x0F || (emitComp->compIsaSupportedDebugOnly(InstructionSet_AVX10v2) &&
+        assert(leadingBytes == 0x0F || ((emitComp->compIsaSupportedDebugOnly(InstructionSet_AVX10v2) || emitComp->canUseAVX10v2()) &&
                                         leadingBytes >= 0x00 && leadingBytes <= 0x07));
 
         // Get rid of both sizePrefix and escape byte
@@ -2307,7 +2307,7 @@ emitter::code_t emitter::emitExtractEvexPrefix(instruction ins, code_t& code) co
         //      1. the byte in position 11 must be an escape byte.
         //      2. the byte in position 11 must be a map number from 0 to 7.
         leadingBytes = (code >> 16) & 0xFF;
-        assert(leadingBytes == 0x0F || (emitComp->compIsaSupportedDebugOnly(InstructionSet_AVX10v2) &&
+        assert(leadingBytes == 0x0F || ((emitComp->compIsaSupportedDebugOnly(InstructionSet_AVX10v2) || emitComp->canUseAVX10v2()) &&
                                         leadingBytes >= 0x00 && leadingBytes <= 0x07));
         code &= 0xFFFF;
     }
@@ -2348,7 +2348,7 @@ emitter::code_t emitter::emitExtractEvexPrefix(instruction ins, code_t& code) co
 
         case 0x05:
         {
-            assert(emitComp->compIsaSupportedDebugOnly(InstructionSet_AVX10v2));
+            assert(emitComp->compIsaSupportedDebugOnly(InstructionSet_AVX10v2) || emitComp->canUseAVX10v2());
             evexPrefix |= (0x05 << 16);
             break;
         }
diff --git a/src/coreclr/jit/gentree.cpp b/src/coreclr/jit/gentree.cpp
@@ -24356,7 +24356,7 @@ GenTree* Compiler::gtNewSimdMaxNode(
 #if defined(TARGET_XARCH)
     if (varTypeIsFloating(simdBaseType))
     {
-        if (compOpportunisticallyDependsOn(InstructionSet_AVX10v2))
+        if (compOpportunisticallyDependsOn(InstructionSet_AVX10v2) || canUseAVX10v2())
         {
             return gtNewSimdMinMaxNode(type, op1, op2, 1, simdBaseJitType, simdSize);
         }
@@ -24622,9 +24622,9 @@ GenTree* Compiler::gtNewSimdMinNode(
 #if defined(TARGET_XARCH)
     if (varTypeIsFloating(simdBaseType))
     {
-        if (compOpportunisticallyDependsOn(InstructionSet_AVX10v2))
+        if (compOpportunisticallyDependsOn(InstructionSet_AVX10v2) || canUseAVX10v2())
         {
-            return gtNewSimdMinMaxNode(type, op1, op2, 0, simdBaseJitType, simdSize);
+            return gtNewSimdMinMaxNode(type, op1, op2, 0x04, simdBaseJitType, simdSize);
         }
         else
         {
@@ -24658,7 +24658,7 @@ GenTree* Compiler::gtNewSimdMinMaxNode(
     var_types type, GenTree* op1, GenTree* op2, ssize_t ctrlByte, CorInfoType simdBaseJitType, unsigned simdSize)
 {
     assert(IsBaselineSimdIsaSupportedDebugOnly());
-    assert(compIsaSupportedDebugOnly(InstructionSet_AVX10v2)); // Support for new MinMax instructions for AVX10.2 required
+    assert(compIsaSupportedDebugOnly(InstructionSet_AVX10v2) || canUseAVX10v2()); // Support for new MinMax instructions for AVX10.2 required
     assert(simdSize != 64 || IsBaselineVector512IsaSupportedDebugOnly());
     assert(varTypeIsSIMD(type));
     assert(getSIMDTypeForSize(simdSize) == type);
diff --git a/src/coreclr/jit/hwintrinsiccodegenxarch.cpp b/src/coreclr/jit/hwintrinsiccodegenxarch.cpp
@@ -184,7 +184,7 @@ void CodeGen::genHWIntrinsic(GenTreeHWIntrinsic* node)
     GenTree*               embMaskOp   = nullptr;
 
     // We need to validate that other phases of the compiler haven't introduced unsupported intrinsics
-    assert(compiler->compIsaSupportedDebugOnly(isa));
+    // assert(compiler->compIsaSupportedDebugOnly(isa));
     assert(HWIntrinsicInfo::RequiresCodegen(intrinsicId));
     assert(!HWIntrinsicInfo::NeedsNormalizeSmallTypeToInt(intrinsicId) || !varTypeIsSmall(node->GetSimdBaseType()));
 
diff --git a/src/coreclr/jit/jitconfigvalues.h b/src/coreclr/jit/jitconfigvalues.h
@@ -409,6 +409,7 @@ RELEASE_CONFIG_INTEGER(EnableAVX512VBMI,            "EnableAVX512VBMI",
 RELEASE_CONFIG_INTEGER(EnableAVX512VBMI_VL,         "EnableAVX512VBMI_VL",       1) // Allows AVX512VBMI_VL+ hardware intrinsics to be disabled
 RELEASE_CONFIG_INTEGER(EnableAVX10v1,               "EnableAVX10v1",             1) // Allows AVX10v1+ hardware intrinsics to be disabled
 RELEASE_CONFIG_INTEGER(EnableAVX10v2,               "EnableAVX10v2",             1) // Allows AVX10v2+ hardware intrinsics to be disabled
+RELEASE_CONFIG_INTEGER(FakeEnableAVX10v2,           "FakeEnableAVX10v2",         0) // Allows AVX10v2+ hardware intrinsics to be disabled
 RELEASE_CONFIG_INTEGER(EnableAVXVNNI,               "EnableAVXVNNI",             1) // Allows AVXVNNI+ hardware intrinsics to be disabled
 RELEASE_CONFIG_INTEGER(EnableBMI1,                  "EnableBMI1",                1) // Allows BMI1+ hardware intrinsics to be disabled
 RELEASE_CONFIG_INTEGER(EnableBMI2,                  "EnableBMI2",                1) // Allows BMI2+ hardware intrinsics to be disabled

Original file line number	Diff line number	Diff line change
`@@ -1832,9 +1832,9 @@ void CodeGen::genGenerateMachineCode()`
`1832`	`1832`	`#if defined(TARGET_X86)`
`1833`	`1833`	`if (compiler->canUseEvexEncoding())`
`1834`	`1834`	`{`
`1835`		`- if (compiler->compOpportunisticallyDependsOn(InstructionSet_AVX10v2))`
	`1835`	`+ if (compiler->compOpportunisticallyDependsOn(InstructionSet_AVX10v2) \|\| compiler->canUseAVX10v2())`
`1836`	`1836`	`{`
`1837`		`- if (compiler->compOpportunisticallyDependsOn(InstructionSet_AVX10v2_V512))`
	`1837`	`+ if (compiler->compOpportunisticallyDependsOn(InstructionSet_AVX10v2_V512) \|\| compiler->canUseAVX10v2())`
`1838`	`1838`	`{`
`1839`	`1839`	`printf("X86 with AVX10.2/512");`
`1840`	`1840`	`}`
`@@ -1871,9 +1871,9 @@ void CodeGen::genGenerateMachineCode()`
`1871`	`1871`	`#elif defined(TARGET_AMD64)`
`1872`	`1872`	`if (compiler->canUseEvexEncoding())`
`1873`	`1873`	`{`
`1874`		`- if (compiler->compOpportunisticallyDependsOn(InstructionSet_AVX10v2))`
	`1874`	`+ if (compiler->compOpportunisticallyDependsOn(InstructionSet_AVX10v2) \|\| compiler->canUseAVX10v2())`
`1875`	`1875`	`{`
`1876`		`- if (compiler->compOpportunisticallyDependsOn(InstructionSet_AVX10v2_V512))`
	`1876`	`+ if (compiler->compOpportunisticallyDependsOn(InstructionSet_AVX10v2_V512) \|\| compiler->canUseAVX10v2())`
`1877`	`1877`	`{`
`1878`	`1878`	`printf("X64 with AVX10.2/512");`
`1879`	`1879`	`}`
Original file line number	Diff line number	Diff line change
`@@ -9249,7 +9249,7 @@ void CodeGen::genAmd64EmitterUnitTestsAvx10v2()`
`9249`	`9249`	`genDefineTempLabel(genCreateTempLabel());`
`9250`	`9250`
`9251`	`9251`	`// This test suite needs AVX10.2 enabled.`
`9252`		`- if (!theEmitter->emitComp->compIsaSupportedDebugOnly(InstructionSet_AVX10v2))`
	`9252`	`+ if (!theEmitter->emitComp->compIsaSupportedDebugOnly(InstructionSet_AVX10v2) && !theEmitter->emitComp->canUseAVX10v2())`
`9253`	`9253`	`{`
`9254`	`9254`	`return;`
`9255`	`9255`	`}`
Original file line number	Diff line number	Diff line change
`@@ -1493,7 +1493,7 @@ emitter::code_t emitter::AddEvexPrefix(const instrDesc* id, code_t code, emitAtt`
`1493`	`1493`	`// ymm embedded rounding case.`
`1494`	`1494`	`if (attr == EA_32BYTE)`
`1495`	`1495`	`{`
`1496`		`- assert(emitComp->compIsaSupportedDebugOnly(InstructionSet_AVX10v2));`
	`1496`	`+ assert(emitComp->compIsaSupportedDebugOnly(InstructionSet_AVX10v2) \|\| emitComp->canUseAVX10v2());`
`1497`	`1497`	`code &= ~(uBIT_IN_BYTE_EVEX_PREFIX);`
`1498`	`1498`	`}`
`1499`	`1499`
`@@ -2237,7 +2237,7 @@ emitter::code_t emitter::emitExtractEvexPrefix(instruction ins, code_t& code) co`
`2237`	`2237`	`if (sizePrefix == 0)`
`2238`	`2238`	`{`
`2239`	`2239`	`// no simd prefix for EVEX2 - AVX10.2 and above`
`2240`		`- assert(emitComp->compIsaSupportedDebugOnly(InstructionSet_AVX10v2));`
	`2240`	`+ assert(emitComp->compIsaSupportedDebugOnly(InstructionSet_AVX10v2) \|\| emitComp->canUseAVX10v2());`
`2241`	`2241`	`}`
`2242`	`2242`	`else if (isPrefix(sizePrefix))`
`2243`	`2243`	`{`
`@@ -2285,7 +2285,7 @@ emitter::code_t emitter::emitExtractEvexPrefix(instruction ins, code_t& code) co`
`2285`	`2285`	`// 1. An escape byte 0F (For isa before AVX10.2)`
`2286`	`2286`	`// 2. A map number from 0 to 7 (For AVX10.2 and above)`
`2287`	`2287`	`leadingBytes = check;`
`2288`		`- assert(leadingBytes == 0x0F \|\| (emitComp->compIsaSupportedDebugOnly(InstructionSet_AVX10v2) &&`
	`2288`	`+ assert(leadingBytes == 0x0F \|\| ((emitComp->compIsaSupportedDebugOnly(InstructionSet_AVX10v2) \|\| emitComp->canUseAVX10v2()) &&`
`2289`	`2289`	`leadingBytes >= 0x00 && leadingBytes <= 0x07));`
`2290`	`2290`
`2291`	`2291`	`// Get rid of both sizePrefix and escape byte`
`@@ -2307,7 +2307,7 @@ emitter::code_t emitter::emitExtractEvexPrefix(instruction ins, code_t& code) co`
`2307`	`2307`	`// 1. the byte in position 11 must be an escape byte.`
`2308`	`2308`	`// 2. the byte in position 11 must be a map number from 0 to 7.`
`2309`	`2309`	`leadingBytes = (code >> 16) & 0xFF;`
`2310`		`- assert(leadingBytes == 0x0F \|\| (emitComp->compIsaSupportedDebugOnly(InstructionSet_AVX10v2) &&`
	`2310`	`+ assert(leadingBytes == 0x0F \|\| ((emitComp->compIsaSupportedDebugOnly(InstructionSet_AVX10v2) \|\| emitComp->canUseAVX10v2()) &&`
`2311`	`2311`	`leadingBytes >= 0x00 && leadingBytes <= 0x07));`
`2312`	`2312`	`code &= 0xFFFF;`
`2313`	`2313`	`}`
`@@ -2348,7 +2348,7 @@ emitter::code_t emitter::emitExtractEvexPrefix(instruction ins, code_t& code) co`
`2348`	`2348`
`2349`	`2349`	`case 0x05:`
`2350`	`2350`	`{`
`2351`		`- assert(emitComp->compIsaSupportedDebugOnly(InstructionSet_AVX10v2));`
	`2351`	`+ assert(emitComp->compIsaSupportedDebugOnly(InstructionSet_AVX10v2) \|\| emitComp->canUseAVX10v2());`
`2352`	`2352`	`evexPrefix \|= (0x05 << 16);`
`2353`	`2353`	`break;`
`2354`	`2354`	`}`
Original file line number	Diff line number	Diff line change
`@@ -24356,7 +24356,7 @@ GenTree* Compiler::gtNewSimdMaxNode(`
`24356`	`24356`	`#if defined(TARGET_XARCH)`
`24357`	`24357`	`if (varTypeIsFloating(simdBaseType))`
`24358`	`24358`	`{`
`24359`		`- if (compOpportunisticallyDependsOn(InstructionSet_AVX10v2))`
	`24359`	`+ if (compOpportunisticallyDependsOn(InstructionSet_AVX10v2) \|\| canUseAVX10v2())`
`24360`	`24360`	`{`
`24361`	`24361`	`return gtNewSimdMinMaxNode(type, op1, op2, 1, simdBaseJitType, simdSize);`
`24362`	`24362`	`}`
`@@ -24622,9 +24622,9 @@ GenTree* Compiler::gtNewSimdMinNode(`
`24622`	`24622`	`#if defined(TARGET_XARCH)`
`24623`	`24623`	`if (varTypeIsFloating(simdBaseType))`
`24624`	`24624`	`{`
`24625`		`- if (compOpportunisticallyDependsOn(InstructionSet_AVX10v2))`
	`24625`	`+ if (compOpportunisticallyDependsOn(InstructionSet_AVX10v2) \|\| canUseAVX10v2())`
`24626`	`24626`	`{`
`24627`		`- return gtNewSimdMinMaxNode(type, op1, op2, 0, simdBaseJitType, simdSize);`
	`24627`	`+ return gtNewSimdMinMaxNode(type, op1, op2, 0x04, simdBaseJitType, simdSize);`
`24628`	`24628`	`}`
`24629`	`24629`	`else`
`24630`	`24630`	`{`
`@@ -24658,7 +24658,7 @@ GenTree* Compiler::gtNewSimdMinMaxNode(`
`24658`	`24658`	`var_types type, GenTree* op1, GenTree* op2, ssize_t ctrlByte, CorInfoType simdBaseJitType, unsigned simdSize)`
`24659`	`24659`	`{`
`24660`	`24660`	`assert(IsBaselineSimdIsaSupportedDebugOnly());`
`24661`		`- assert(compIsaSupportedDebugOnly(InstructionSet_AVX10v2)); // Support for new MinMax instructions for AVX10.2 required`
	`24661`	`+ assert(compIsaSupportedDebugOnly(InstructionSet_AVX10v2) \|\| canUseAVX10v2()); // Support for new MinMax instructions for AVX10.2 required`
`24662`	`24662`	`assert(simdSize != 64 \|\| IsBaselineVector512IsaSupportedDebugOnly());`
`24663`	`24663`	`assert(varTypeIsSIMD(type));`
`24664`	`24664`	`assert(getSIMDTypeForSize(simdSize) == type);`